Digital and Hybrid Control Systems

Industrial Engineering and Management

Introduction

Pietro Tesi
ENTEG
University of Groningen

Pietro Tesi – p. 1/20

Process control

d
❄
u y Physical entity whose satisfactory
✲ Process ✲ response requires a control action

u - control input
d - disturbance input (uncontrolled)
y - process output (measurable)

 CONTROL GOALS: output regulation/disturbance rejection

Pietro Tesi – p. 2/20

Ex. Hard disk drive servo systems

y− head radial position

d− gravitational force, vibrations

...........
........... θ u− corrections to the head position
.........
........ (via voice-coil motors)
...........
.....

GOAL: regulate the read/write head over a desired track

(tolerance less than one micrometer)

Pietro Tesi – p. 3/20

Ex. Hot rolling mills
✲
Flow y− thickness
d− material asperities
u− rolling forces

GOAL: roll steel

slabs 8-9 inches thick
into strips as thin as
❄❄ ✻✻ ❄❄ ✻✻ 1/16 inches
Control Control
✻ ✻
❄ ❄ Bus
Pietro Tesi – p. 4/20
Process automation

Optimiz.
Large scale
Managem. Coordin.
Refineries subsystems
specifications
Steel plants

Medium scale Data Safety

Heating records Process devices
Production lines

Start-up Alarms
Small scale Shut-down
Vehicles
Automatic pilots Control

Pietro Tesi – p. 5/20

Hierarchy
Management
3 Coordination of subsystems PC/WS

✻ ✻
❄ ❄
Optimization Optimization
2 Data-Logging Data-Logging
PC

✻ ✻
❄ ❄
Control Control
1 Monitoring Monitoring DCS/PLC/PC
Safety Safety
✻ ✻
❄ ❄
✲ Physical
0 Process 1 ✛ Process 2 process

Pietro Tesi – p. 6/20

Continuous-time signals and systems

Continuous-time (CT) signal: the variable of time is continuous

CT system: receives continuous-time input signals and
generate continuous-time output signals

Physical quantities such as temperature, pressure, etc. are generally

continuous signals

u(t)
✻ Physical systems
are typically continuous-time
✲
time

Pietro Tesi – p. 7/20

Analog controllers

Reference Error Input Dist. Output

❄
r(t) e(t) u(t) y(t)
✲+ ✲ Controller ✲ Act. ✲ Process ✲ Sens. ✲
✻
Plant

Analog control system

Resistors, inductors and capacitors

Pietro Tesi – p. 8/20

Discrete-time signals and systems

Discrete-time (DT) signal: the variable of time is discrete

DT system: receives discrete-time input signals and generate
discrete-time output signals

u(k)
Digital systems are DT systems
✻
They are also called processors,
elaborators, filters
✲
time

Pietro Tesi – p. 9/20

Digital controllers
Reference Error Input Output
Program
❄ ✻
r(t)
✲+
e(t) ✲ A/D e(k)✲ u(k)
✲ D/A
u(t)
✲ Plant
y(t)
✲
Processor
✻
✻ ✻ ✻
Clock

Digital control system

Digital processor + interface units

Pietro Tesi – p. 10/20

e(k)
✻
Analog-to-digital (A/D) converter

✲
steps (t/T )
e∗ (t)
✻ e(t) e∗ (t)
✲ ✲ a/d ✲
✻ A/D e(k)
✲ Clock
time kT k = 0, 1, ....
e(t)
✻
convert analog inputs to
machine readable digital format
✲ every sampling time T
time
clock (quantization effects
✻ ✲δ✛ due to A/D conversion)

✲
T 2T kT time Pietro Tesi – p. 11/20
Quantization

✻
Bit

..
... ... ✲
.
.
✲.. ..✛
. ∆
. Volt
... ...

The digital format can take on only a finite set of values.

Ex. A/D resolution 8 bit, maximum voltage 5 Volt.

Then ∆ = 258 = 0.02 Volt. All values within [0, 0.02) generate 0.

Pietro Tesi – p. 12/20

Discrete vs digital

DT signal: the variable of time is discrete

Digital signal: DT signal with a finite set of values

Ex. Sampled signal u(kT ), k = 0, 1, . . .

Ex. Digital signal = sampled + quantized signal u(kT ), k = 0, 1, . . .

u(k) In control theory, it is common

✻ to not distinguish between DT
and digital signals
✲ It is also common to let u(kT ) = u(k)
time

Pietro Tesi – p. 13/20

Digital processor
Program
✻ ❄
...., e(2), e(1), e(0) ...., u(2), u(1), u(0)
✲ Processor ✲

✻
Clock
#define t system_clock;
#define T sampling_time;
t:=0; k:=0

1. wait_until(t==kT)
read(e(k));
u(k):=g(k,e(k),e(k-1),....,u(k-1),u(k-2),.....);
send(u(k));
k:=k+1;
goto 1.

Pietro Tesi – p. 14/20

Digital-to-analog (D/A) converter

u(k) u∗ (t) u(t)

✲ ✲ d/a ✲ Holder ✲

✻ D/A

Clock
kT + Tc

After processing (Tc = computation time), the D/A unit

reconstructs a CT signal
Typical choice: Zero-order holder (ZOH)

Pietro Tesi – p. 15/20

Zero-order holder

Pietro Tesi – p. 16/20

Analog vs. digital control

Digital control systems:

Cheap
Flexible
Scalable
Reliable

However,
the interaction of continuous (process) and digital (controller)
components makes the overall system hybrid

Pietro Tesi – p. 17/20

Learning goals

Analysis

Discrete-time systems
Properties of discrete-time systems
Sampled-data systems

Design

Control system specifications

Design by emulation
Direct design

Pietro Tesi – p. 18/20

Course schedule

Lectures
L1. Course overview (4/2)
L2. Discrete-time and sampled-data systems (8/2)
L3. Time-domain representations and Z-transform (11/2)
L4. Z-domain representations (15/2)
L5. Heaviside’s expansion method (18/2)
L6. Stability of discrete-time systems (22/2)
L7. Systems response to inputs (25/2)
L10. Control specifications: part I (8/3)
L11. Control specifications: part II (11/3)
L12. Design by emulation: part I (15/3)
L13. Design by emulation: part II (18/3)
L14. Direct design: part I (22/3)
L15. Direct design: part II (25/3)

note: Instead of L8 and L16 we will have two tests, one for L1-L7 (on 1/3), one for L10-15 (on 29/3).
On 4/3 (L9), we will discuss the first test and have a Q&A session for the first part of the course.
The tests do not count for the grading.
Pietro Tesi – p. 19/20
Course schedule

Tutorials
T1. Recap from other courses (6/2, 7/2)
T2. Covers L2 (13/2,14/2)
T3. Covers L3-L4 (20/2, 21/2)
T4. Covers L5-L6 (27/2, 28/2)
T5. Covers L7 (6/3, 7/3)
T6. Covers L10-L11 (13/3, 14/3)
T7. Covers L12-L13 (20/3, 21/3)
T8. Covers L14-L15 (27/3, 28/3)

note: In addition to the tutorials, exercises with solutions will be posted on Nestor.

Exams. Final Q&A session on 1/4. Written exams on 5/4 and 27/6. The exam is open book.
Reference textbook
G.F. Franklin, J.D. Powell, and M. Workman. Digital Control of Dynamic Systems, 3rd Edition.
Ellis-Kagle Press.

note: The course is self-contained. The book is meant for further readings.

Pietro Tesi – p. 20/20