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dsPIC33FJ16GP304
Data Sheet
High-Performance,
16-bit Digital Signal Controllers
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
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• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
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10-Bit/12-Bit ADC
External Interrupts(2)
Packages
Input Capture
Remappable
16-bit Timer
(Kbyte)
Std. PWM
I2C™
RAM
Pins
UART
Device
Pins
SPI
dsPIC33FJ32GP202 28 32 2 16 3(1) 4 2 1 3 1 1 ADC, 1 21 SDIP
10 ch SOIC
QFN-S
dsPIC33FJ32GP204 44 32 2 26 3(1) 4 2 1 3 1 1 ADC, 1 35 QFN
13 ch TQFP
dsPIC33FJ16GP304 44 16 2 26 3(1) 4 2 1 3 1 1 ADC, 1 35 QFN
13 ch TQFP
Note 1: Only two out of three timers are remappable.
2: Only two out of three interrupts are remappable.
Pin Diagrams
28-Pin SDIP, SOIC = Pins are up to 5V tolerant
MCLR 1 28 AVDD
AN0/VREF+/CN2/RA0 2 27 AVSS
AN1/VREF-/CN3/RA1 3 26 AN9/RP15(1)/CN11/RB15
dsPIC33FJ32GP202
PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 4 25 AN10/RP14(1)/CN12/RB14
PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 5 24 AN11/RP13(1)/CN13/RB13
AN4/RP2(1)/CN6/RB2 6 23 AN12/RP12(1)/CN14/RB12
AN5/RP3(1)/CN7/RB3 7 22 PGEC2/TMS/RP11(1)/CN15/RB11
VSS 8 21 PGED2/TDI/RP10(1)/CN16/RB10
OSC1/CLKI/CN30/RA2 9 20 VCAP/VDDCORE
OSC2/CLKO/CN29/RA3 10 19 VSS
SOSCI/RP4(1)/CN1/RB4 11 18 TDO/SDA1/RP9(1)/CN21/RB9
SOSCO/T1CK/CN0/RA4 12 17 TCK/SCL1/RP8(1)/CN22/RB8
VDD 13 16 INT0/RP7/CN23/RB7
PGED3/ASDA1/RP5(1)/CN27/RB5 14 15 PGEC3/ASCL1/RP6(1)/CN24/RB6
28-Pin QFN-S(2)
= Pins are up to 5V tolerant
AN10/RP14(1)/CN12/RB14
AN9/RP15(1)/CN11/RB15
AN0/VREF+/CN2/RA0
AN1/VREF-/CN3/RA1
MCLR
AVDD
AVSS
28 27 26 25 24 23 22
PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 1 21 AN11/RP13(1)/CN13/RB13
PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 2 20 AN12/RP12(1)/CN14/RB12
AN4/RP2(1)/CN6/RB2 3 19 PGEC2/TMS/RP11(1)(1)/CN15/RB11
AN5/RP3(1)/CN7/RB3 4
dsPIC33FJ32GP202 18 PGED2/TDI/RP10/CN16/RB10
VSS 5 17 VCAP/VDDCORE
OSC1/CLKI/CN30/RA2 6 16 Vss
OSC2/CLKO/CN29/RA3 7 15 TDO/SDA1/RP9(1)/CN21/RB9
8 9 10 11 12 13 14
SOSCI/RP4/CN1/RB4
SOSCO/T1CK/CN0/RA4
VDD
PGED3/ASDA1/RP5(1)/CN27/RB5
PGEC3/ASCL1/RP6/CN24/RB6
INT0/RP7(1(1))/CN23/RB7
TCK/SCL1/RP8(1)/CN22/RB8
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available
peripherals.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to
be connected to VSS externally.
44-Pin QFN(2)
= Pins are up to 5V tolerant
PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1
PGED1/AN2/C2IN-/RP0(1)/CN4/RB0
AN10/RP14(1)/CN12/RB14
AN9/RP15(1)/CN11/RB15
AN0/VREF+/CN2/RA0
AN1/VREF-/CN3/RA1
TMS/RA10
TCK/RA7
MCLR
AVDD
AVSS
21 AN11/RP13(1)/CN13/RB13
20
AN4/RP2(1)/CN6/RB2
22
19
18
17
16
15
14
13
12
23 11
AN5/RP3(1)/CN7/RB3 24 10 AN12/RP12(1)/CN14/RB12
AN6/RP16(1)/CN8/RC0 25 9 PGEC2/RP11(1)/CN15/RB11
AN7/RP17(1)/CN9/RC1 26 8 PGED2/RP10(1)/CN16/RB10
AN8/RP18(1)/CN10/RC2 27 7 VCAP/VDDCORE
dsPIC33FJ32GP204
VDD 28 6 VSS
dsPIC33FJ16GP304
VSS 29 5 RP25(1)/CN19/RC9
OSC1/CLKI/CN30/RA2 30 4 RP24(1)/CN20/RC8
OSC2/CLKO/CN29/RA3 31 3 RP23(1)/CN17/RC7
TDO/RA8 32 2 RP22(1)/CN18/RC6
SOSCI/RP4(1)/CN1/RB4 SDA1/RP9(1)/CN21/RB9
41
34
35
36
37
38
39
40
42
43
44
33 1
SOSCO/T1CK/CN0/RA4
TDI/RA9
RP19(1)/CN28/RC3
RP20(1)/CN25/RC4
RP21(1)/CN26/RC5
VDD
PGED3/ASDA1/RP5(1)/CN27/RB5
PGEC3/ASCL1/RP6(1)/CN24/RB6
INT0/RP7(1)/CN23/RB7
SCL1/RP8(1)/CN22/RB8
VSS
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available
peripherals.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to
be connected to Vss externally.
PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1
PGED1/AN2/C2IN-/RP0(1)/CN4/RB0
AN10/RP14(1)/CN12/RB14
AN9/RP15(1)/CN11/RB15
AN0/VREF+/CN2/RA0
AN1/VREF-/CN3/RA1
TMS/RA10
TCK/RA7
MCLR
AVDD
AVSS
22
21
20
19
18
17
16
15
14
13
12
AN4/RP2(1)/CN6/RB2 23 11 AN11/RP13(1)/CN13/RB13
AN5/RP3(1)/CN7/RB3 24 10 AN12/RP12(1)/CN14/RB12
AN6/RP16(1)/CN8/RC0 25 9 PGEC2/RP11(1)/CN15/RB11
AN7/RP17(1)/CN9/RC1 26 8 PGED2/RP10(1)/CN16/RB10
AN8/RP18(1)/CN10/RC2 27 7 VCAP/VDDCORE
VDD
dsPIC33FJ32GP204 6 VSS
28
VSS 29
dsPIC33FJ16GP304 5 RP25(1)/CN19/RC9
OSC1/CLKI/CN30/RA2 30 4 RP24(1)/CN20/RC8
OSC2/CLKO/CN29/RA3 31 3 RP23(1)/CN17/RC7
TDO/RA8 32 2 RP22/CN18/RC6
SOSCI/RP4(1)/CN1/RB4 33 1 SDA1(1)/RP9(1)/CN21/RB9
34
35
36
37
39
40
41
42
43
44
38
SOSCO/T1CK/CN0/RA4
TDI/RA9
RP19(1)/CN28/RC3
RP20(1)/CN25/RC4
RP21(1)/CN26/RC5
VDD
PGED3/ASDA1/RP5(1)/CN27/RB5
PGEC3/ASCL1/RP6(1)/CN24/RB6
INT0/ RP7(1)/CN23/RB7
SCL1/RP8(1)/CN22/RB8
VSS
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available
peripherals.
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 11
2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......................................................................................... 15
3.0 CPU............................................................................................................................................................................................ 19
4.0 Memory Organization ................................................................................................................................................................. 31
5.0 Flash Program Memory.............................................................................................................................................................. 57
6.0 Resets ....................................................................................................................................................................................... 63
7.0 Interrupt Controller ..................................................................................................................................................................... 71
8.0 Oscillator Configuration .............................................................................................................................................................. 99
9.0 Power-Saving Features............................................................................................................................................................ 109
10.0 I/O Ports ................................................................................................................................................................................... 113
11.0 Timer1 ...................................................................................................................................................................................... 135
12.0 Timer2/3 Feature...................................................................................................................................................................... 137
13.0 Input Capture............................................................................................................................................................................ 143
14.0 Output Compare....................................................................................................................................................................... 145
15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 149
16.0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 155
17.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 163
18.0 10-bit/12-bit Analog-to-Digital Converter (ADC) ....................................................................................................................... 169
19.0 Special Features ...................................................................................................................................................................... 183
20.0 Instruction Set Summary .......................................................................................................................................................... 191
21.0 Development Support............................................................................................................................................................... 199
22.0 Electrical Characteristics .......................................................................................................................................................... 203
23.0 High Temperature Electrical Characteristics ............................................................................................................................ 237
24.0 Packaging Information.............................................................................................................................................................. 247
Appendix A: Revision History............................................................................................................................................................. 257
Index .................................................................................................................................................................................................. 263
The Microchip Web Site ..................................................................................................................................................................... 267
Customer Change Notification Service .............................................................................................................................................. 267
Customer Support .............................................................................................................................................................................. 267
Reader Response .............................................................................................................................................................................. 268
Product Identification System ............................................................................................................................................................ 269
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
NOTES:
16
8 16 16 16
23 PORTC
16 16
Remappable
Program Memory Pins
EA MUX
Instruction
Decode and
Control Instruction Reg
16
Control Signals
to Various Blocks DSP Engine
16 x 16
OSC2/CLKO Timing Power-up W Register Array
OSC1/CLKI Generation Timer Divide Support
16
Oscillator
FRC/LPRC Start-up Timer
Oscillators
Power-on
Reset
Precision
16-bit ALU
Band Gap Watchdog
Reference Timer
16
Brown-out
Voltage Reset
Regulator
Timers OC/
UART1 ADC1
1-3 PWM1-2
Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins
and features present on each device.
VSS
VDD
R
R1
resistance and capacitance that can be added to the
MCLR pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
C specific voltage levels (VIH and VIL) and fast signal
dsPIC33F transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
VSS VDD
based on the application and PCB requirements.
VDD VSS For example, as shown in Figure 2-2, it is
0.1 µF 0.1 µF
AVDD
AVSS
VSS
Ceramic Ceramic
MCLR pin during programming and debugging
operations.
0.1 µF 0.1 µF
10 Ceramic Ceramic Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
16 16 16
8 16
Program Memory
EA MUX
Instruction
Decode and
Control Instruction Reg
Control Signals
to Various Blocks 16
DSP Engine
16 x 16
W Register Array
Divide Support 16
16-bit ALU
16
To Peripheral Modules
PC22 PC0
0 Program Counter
7 0
TBLPAG Data Table Page Address
7 0
PSVPAG Program Space Visibility Page Address
15 0
RCOUNT REPEAT Loop Counter
15 0
DCOUNT DO Loop Counter
22 0
DOSTART DO Loop Start Address
22
DOEND DO Loop End Address
15 0
CORCON Core Configuration Register
SRH SRL
Legend:
C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’
S = Set only bit W = Writable bit -n = Value at POR
‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
S
40 a
40-bit Accumulator A
40 Round t 16
40-bit Accumulator B u
Logic r
Carry/Borrow Out a
Saturate t
e
Carry/Borrow In Adder
Negate
40 40 40
Barrel
16
Shifter
X Data Bus
40
Sign-Extend
Y Data Bus
32 16
Zero Backfill
33 32
17-bit
Multiplier/Scaler
16 16
To/From W Array
The SA and SB bits are modified each time data into data space memory. The write is performed across
passes through the adder/subtracter, but can only be the X bus into combined X and Y address space. The
cleared by the user application. When set, they indicate following addressing modes are supported:
that the accumulator has overflowed its maximum • W13, Register Direct:
range (bit 31 for 32-bit saturation or bit 39 for 40-bit The rounded contents of the non-target
saturation) and will be saturated (if saturation is accumulator are written into W13 as a
enabled). When saturation is not enabled, SA and SB 1.15 fraction.
default to bit 39 overflow and thus indicate that a
• [W13]+ = 2, Register Indirect with Post-Increment:
catastrophic overflow has occurred. If the COVTE bit in
The rounded contents of the non-target
the INTCON1 register is set, SA and SB bits will
accumulator are written into the address pointed
generate an arithmetic warning trap when saturation is
to by W13 as a 1.15 fraction. W13 is then
disabled.
incremented by 2 (for a word write).
The Overflow and Saturation Status bits can optionally
be viewed in the STATUS Register (SR) as the logical 3.6.2.3 Round Logic
OR of OA and OB (in bit OAB) and the logical OR of SA
The round logic is a combinational block that performs
and SB (in bit SAB). Programs can check one bit in the
a conventional (biased) or convergent (unbiased)
STATUS register to determine if either accumulator has
round function during an accumulator write (store). The
overflowed, or one bit to determine if either
Round mode is determined by the state of the RND bit
accumulator has saturated. This is useful for complex
in the CORCON register. It generates a 16-bit, 1.15
number arithmetic, which typically uses both
data value that is passed to the data space write
accumulators.
saturation logic. If rounding is not indicated by the
The device supports three Saturation and Overflow instruction, a truncated 1.15 data value is stored and
modes: the least significant word (lsw) is simply discarded.
• Bit 39 Overflow and Saturation: Conventional rounding zero-extends bit 15 of the
When bit 39 overflow and saturation occurs, the accumulator and adds it to the ACCxH word (bits 16
saturation logic loads the maximally positive 9.31 through 31 of the accumulator).
(0x7FFFFFFFFF) or maximally negative 9.31 value
• If the ACCxL word (bits 0 through 15 of the
(0x8000000000) into the target accumulator. The
accumulator) is between 0x8000 and 0xFFFF
SA or SB bit is set and remains set until cleared by
(0x8000 included), ACCxH is incremented.
the user application. This condition is referred to as
‘super saturation’ and provides protection against • If ACCxL is between 0x0000 and 0x7FFF, ACCxH
erroneous data or unexpected algorithm problems is left unchanged.
(such as gain calculations). A consequence of this algorithm is that over a
• Bit 31 Overflow and Saturation: succession of random rounding operations, the value
When bit 31 overflow and saturation occurs, the tends to be biased slightly positive.
saturation logic then loads the maximally positive Convergent (or unbiased) rounding operates in the
1.31 value (0x007FFFFFFF) or maximally same manner as conventional rounding, except when
negative 1.31 value (0x0080000000) into the ACCxL equals 0x8000. In this case, the Least
target accumulator. The SA or SB bit is set and Significant bit (bit 16 of the accumulator) of ACCxH is
remains set until cleared by the user application. examined.
When this Saturation mode is in effect, the guard
• If it is ‘1’, ACCxH is incremented.
bits are not used, so the OA, OB or OAB bits are
never set. • If it is ‘0’, ACCxH is not modified. Assuming that
bit 16 is effectively random in nature, this scheme
• Bit 39 Catastrophic Overflow:
removes any rounding bias that may accumulate.
The bit 39 Overflow Status bit from the adder is
used to set the SA or SB bit, which remains set The SAC and SAC.R instructions store either a
until cleared by the user application. No saturation truncated (SAC), or rounded (SAC.R) version of the
operation is performed and the accumulator is contents of the target accumulator to data memory via
allowed to overflow, destroying its sign. If the the X bus, subject to data saturation (see
COVTE bit in the INTCON1 register is set, a Section 3.6.2.4 “Data Space Write Saturation”). For
catastrophic overflow can initiate a trap exception. the MAC class of instructions, the accumulator
write-back operation functions in the same manner,
3.6.2.2 Accumulator ‘Write Back’ addressing combined MCU (X and Y) data space
The MAC class of instructions (with the exception of though the X bus. For this class of instructions, the data
MPY, MPY.N, ED and EDAC) can optionally write a is always subject to rounding.
rounded version of the high word (bits 31 through 16)
of the accumulator that is not targeted by the instruction
NOTES:
dsPIC33FJ32GP202/204 dsPIC33FJ16GP304
GOTO Instruction 0x000000 GOTO Instruction 0x000000
0x000002 0x000002
Reset Address 0x000004 Reset Address 0x000004
Interrupt Vector Table 0x0000FE Interrupt Vector Table 0x0000FE
Reserved 0x000100 Reserved 0x000100
0x000104 0x000104
Alternate Vector Table 0x0001FE Alternate Vector Table 0x0001FE
0x000200 0x000200
User Program User Program
Flash Memory Flash Memory
User Memory Space
Unimplemented Unimplemented
(Read ‘0’s) (Read ‘0’s)
0x7FFFFE 0x7FFFFE
0x800000 0x800000
Reserved Reserved
Configuration Memory Space
0xF7FFFE 0xF7FFFE
Device Configuration 0xF80000 Device Configuration 0xF80000
Registers 0xF80017 Registers 0xF80017
0xF80018 0xF80018
Reserved Reserved
0xFEFFFE 0xFEFFFE
0xFF0000 0xFF0000
DEVID (2) 0xFFFFFE
DEVID (2) 0xFFFFFE
4.2 Data Address Space All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
The dsPIC33FJ32GP202/204 and care must be taken when mixing byte and word
dsPIC33FJ16GP304 CPU has a separate 16-bit-wide operations, or translating from 8-bit MCU code. If a
data memory space. The data space is accessed using misaligned read or write is attempted, an address error
separate Address Generation Units (AGUs) for read trap is generated. If the error occurred on a read, the
and write operations. The data memory maps is shown instruction underway is completed. If the instruction
in Figure 4-3. occurred on a write, the instruction is executed but the
All Effective Addresses (EAs) in the data memory space write does not occur. In either case, a trap is then
are 16 bits wide and point to bytes within the data space. executed, allowing the system and/or user application
This arrangement gives a data space address range of to examine the machine state prior to execution of the
64 Kbytes or 32K words. The lower half of the data address Fault.
memory space (that is, when EA<15> = 0) is used for All byte loads into any W register are loaded into the
implemented memory addresses, while the upper half Least Significant Byte. The Most Significant Byte is not
(EA<15> = 1) is reserved for the Program Space modified.
Visibility area (see Section 4.6.3 “Reading Data from
Program Memory Using Program Space Visibility”). A sign-extend instruction (SE) is provided to allow
users to translate 8-bit signed data to 16-bit signed
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 values. Alternatively, for 16-bit unsigned data, user
devices implement up to 30 Kbytes of data memory. applications can clear the MSB of any W register by
Should an EA point to a location outside of this area, an executing a zero-extend (ZE) instruction on the
all-zero word or byte will be returned. appropriate address.
4.2.1 DATA SPACE WIDTH 4.2.3 SFR SPACE
The data memory space is organized in byte The first 2 Kbytes of the Near Data Space, from 0x0000
addressable, 16-bit-wide blocks. Data is aligned in data to 0x07FF, is primarily occupied by Special Function
memory and registers as 16-bit words, but all data Registers (SFRs). These are used by the
space EAs resolve to bytes. The Least Significant dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
Bytes (LSBs) of each word have even addresses, while core and peripheral modules for controlling the
the Most Significant Bytes (MSBs) have odd operation of the device.
addresses.
SFRs are distributed among the modules that they
4.2.2 DATA MEMORY ORGANIZATION control, and are generally grouped together by module.
AND ALIGNMENT Much of the SFR space contains unused addresses;
these are read as ‘0’. A complete listing of implemented
To maintain backward compatibility with PIC® MCU SFRs, including their addresses, is shown in Table 4-1
devices and improve data space memory usage through Table 4-22.
efficiency, the dsPIC33FJ32GP202/204 and
dsPIC33FJ16GP304 instruction set supports both Note: The actual set of peripheral features and
word and byte operations. As a consequence of byte interrupts varies by the device. Refer to
accessibility, all effective address calculations are the corresponding device tables and
internally scaled to step through word-aligned memory. pinout diagrams for device-specific
For example, the core recognizes that Post-Modified information.
Register Indirect Addressing mode [Ws++] will result in
a value of Ws + 1 for byte operations and Ws + 2 for 4.2.4 NEAR DATA SPACE
word operations. The 8 Kbyte area between 0x0000 and 0x1FFF is
Data byte reads will read the complete word that referred to as the Near Data Space. Locations in this
contains the byte, using the LSB of any EA to space are directly addressable via a 13-bit absolute
determine which byte to select. The selected byte is address field within all memory direct instructions.
placed onto the LSB of the data path. That is, data Additionally, the whole data space is addressable using
memory and registers are organized as two parallel MOV instructions, which support Memory Direct
byte-wide entities with shared (word) address decode Addressing mode with a 16-bit address field, or by
but separate write lines. Data byte writes only write to using Indirect Addressing mode using a working
the corresponding side of the array or register that register as an address pointer.
matches the byte address.
MSB LSB
Address 16 bits Address
MSb LSb
0x0001 0x0000
2 Kbyte
SFR Space
SFR Space 0x07FE
0x07FF
0x0801 0x0800
X Data RAM (X)
0x0BFF 0x0BFE
2 Kbyte 0x0001 0x0C00 8 Kbyte
Y Data RAM (Y) Near data space
SRAM Space 0x0FFF 0x0FFE
0x1001 0x1000
0x1FFF 0x1FFE
0x2001 0x2000
0x8001 0x8000
X Data
Optionally Unimplemented (X)
Mapped
into Program
Memory
0xFFFF 0xFFFE
4.2.5 X AND Y DATA SPACES The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
The core has two data spaces, X and Y. These data
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide
spaces can be considered either separate (for some
two concurrent data read paths.
DSP instructions), or as one unified linear address
range (for MCU instructions). The data spaces are Both the X and Y data spaces support Modulo
accessed using two Address Generation Units (AGUs) Addressing mode for all instructions, subject to
and separate data paths. This feature allows certain addressing mode restrictions. Bit-Reversed Addressing
instructions to concurrently fetch two words from RAM, mode is only supported for writes to X data space.
thereby enabling efficient execution of DSP algorithms All data memory writes, including in DSP instructions,
such as Finite Impulse Response (FIR) filtering and view data space as combined X and Y address space.
Fast Fourier Transform (FFT). The boundary between the X and Y data spaces is
The X data space is used by all instructions and device-dependent and is not user-programmable.
supports all addressing modes. X data space has All effective addresses are 16 bits wide and point to
separate read and write data buses. The X read data bytes within the data space. Therefore, the data space
bus is the read data path for all instructions that view address range is 64 Kbytes, or 32K words, though the
data space as combined X and Y address space. It is implemented memory locations vary by device.
also the X data prefetch path for the dual operand DSP
instructions (MAC class).
SFR All
SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Addr Resets
XMODSRT 0048 XS<15:1> 0 xxxx
XMODEND 004A XE<15:1> 1 xxxx
CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE —- — — CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000
CNEN2 0062 — CN30IE CN29IE — CN27IE — — CN24IE CN23IE CN22IE CN21IE — — — — CN16IE 0000
CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE — — — CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000
CNPU2 006A — CN30PUE CN29PUE — CN27PUE — — CN24PUE CN23PUE CN22PUE CN21PUE — — — — CN16PUE 0000
Preliminary
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32GP204 AND dsPIC33FJ16GP304
SFR SFR All
Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Addr Resets
CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000
CNEN2 0062 — CN30IE CN29IE CN28IE CN27IE CN26IE CN25IE CN24IE CN23IE CN22IE CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE 0000
CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000
CNPU2 006A — CN30PUE CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS70290F-page 37
DS70290F-page 38
INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL — 0000
INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000
IFS0 0084 — — AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000
IFS1 0086 — — INT2IF — — — — — IC8IF IC7IF — INT1IF CNIF — MI2C1IF SI2C1IF 0000
IFS4 008C — — — — — — — — — — — — — — U1EIF — 0000
IEC0 0094 — — AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000
IEC1 0096 — — INT2IE — — — — — IC8IE IC7IE — INT1IE CNIE — MI2C1IE SI2C1IE 0000
IEC4 009C — — — — — — — — — — — — — — U1EIE — 0000
IPC0 00A4 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444
IPC1 00A6 — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — — — — 4440
IPC2 00A8 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444
IPC3 00AA — — — — — — — — — AD1IP<2:0> — U1TXIP<2:0> 0044
IPC4 00AC — CNIP<2:0> — — — — — MI2C1IP<2:0> — SI2C1IP<2:0> 4044
IPC5 00AE — IC8IP<2:0> — IC7IP<2:0> — — — — — INT1IP<2:0> 4404
IPC7 00B2 — — — — — — — — — INT2IP<2:0> — — — — 0040
Preliminary
SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Addr Resets
U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL 0000
U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
Preliminary
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2009 Microchip Technology Inc.
TABLE 4-12: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ32GP202
File All
Preliminary
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Resets
xxxx
ADC1BUFD 031A ADC Data Buffer 13 xxxx
ADC1BUFE 031C ADC Data Buffer 14 xxxx
ADC1BUFF 031E ADC Data Buffer 15 xxxx
AD1CON1 0320 ADON — ADSIDL — — AD12B FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP DONE 0000
AD1CON2 0322 VCFG<2:0> — — CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000
AD1CON3 0324 ADRC — — SAMC<4:0> ADCS<7:0> 0000
AD1CHS123 0326 — — — — — CH123NB<1:0> CH123SB — — — — — CH123NA<1:0> CH123SA 0000
AD1CHS0 0328 CH0NB — — CH0SB<4:0> CH0NA — — CH0SA<4:0> 0000
AD1PCFGL 032C — — — PCFG12 PCFG11 PCFG10 PCFG9 — — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000
AD1CSSL 0330 — — — CSS12 CSS11 CSS10 CSS9 — — — CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2009 Microchip Technology Inc.
2009 Microchip Technology Inc.
TRISA 02C0 — — — — — TRISA10 TRISA9 TRISA8 TRISA7 — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 079F
PORTA 02C2 — — — — — RA10 RA9 RA8 RA7 — — RA4 RA3 RA2 RA1 RA0 xxxx
LATA 02C4 — — — — — LATA10 LATA9 LATA8 LATA7 — — LATA4 LATA3 LATA2 LATA1 LATA0 xxxx
ODCA 02C6 — — — — — ODCA10 ODCA9 ODCA8 ODCA7 — — ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Preliminary
TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF
PORTB 02CA RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx
LATB 02CC LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx
ODCB 02CE ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TRISC 02D0 — — — — — — TRISC9 TRISC8 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 03FF
PORTC 02D2 — — — — — — RC9 RC8 RC7 RC6 RC5 RC4 RC4 RC2 RC1 RC0 xxxx
LATC 02D4 — — — — — — LATC9 LATC8 LATC7 LATC6 LATC5 LATC4 LATC4 LATC2 LATC1 LATC0 xxxx
DS70290F-page 45
ODCC 02D6 — — — — — — ODCC9 ODCC8 ODCC7 ODCC6 ODCC5 ODCC4 ODCC4 ODCC2 ODCC1 ODCC0 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS70290F-page 46
RCON 0740 TRAPR IOPUWR — — — — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR xxxx(1)
OSCCON 0742 — COSC<2:0> — NOSC<2:0> CLKLOCK IOLOCK LOCK — CF — LPOSCEN OSWEN 0300(2)
CLKDIV 0744 ROI DOZE<2:0> DOZEN FRCDIV<2:0> PLLPOST<1:0> — PLLPRE<4:0> 3040
PLLFBD 0746 — — — — — — — PLLDIV<8:0> 0030
OSCTUN 0748 — — — — — — — — — — TUN<5:0> 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: RCON register Reset values dependent on type of Reset.
2: OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
PMD1 0770 — — T3MD T2MD T1MD — — — I2C1MD — U1MD — SPI1MD — — AD1MD 0000
PMD2 0772 IC8MD IC7MD — — — — IC2MD IC1MD — — — — — — OC2MD OC1MD 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2009 Microchip Technology Inc.
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
• Register Direct
PC<15:0> W15 (before CALL) • Register Indirect
000000000 PC<22:16> • Register Indirect Post-Modified
<Free Word> W15 (after CALL) • Register Indirect Pre-Modified
• 5-bit or 10-bit Literal
POP : [--W15]
PUSH : [W15++] Note: Not all instructions support all the
addressing modes given above. Individual
instructions can support different subsets
of these addressing modes.
4.3.3 MOVE AND ACCUMULATOR The two-source operand prefetch registers must be
INSTRUCTIONS members of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 are always directed to the X RAGU,
Move instructions and the DSP accumulator class of
and W10 and W11 are always directed to the Y AGU.
instructions provide a greater degree of addressing
The effective addresses generated (before and after
flexibility than other instructions. In addition to the
modification) must, therefore, be valid addresses within
Addressing modes supported by most MCU
X data space for W8 and W9 and Y data space for W10
instructions, move and accumulator instructions also
and W11.
support Register Indirect with Register Offset
Addressing mode, also referred to as Register Indexed Note: Register Indirect with Register Offset
mode. Addressing mode is available only for W9
(in X space) and W11 (in Y space).
Note: For the MOV instructions, the addressing
mode specified in the instruction can differ In summary, the following addressing modes are
for the source and destination EA. supported by the MAC class of instructions:
However, the 4-bit Wb (Register Offset) • Register Indirect
field is shared by both source and
• Register Indirect Post-Modified by 2
destination (but typically only used by
one). • Register Indirect Post-Modified by 4
• Register Indirect Post-Modified by 6
In summary, the following addressing modes are
supported by move and accumulator instructions: • Register Indirect with Register Offset (Indexed)
Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0
Pivot Point
XB = 0x0008 for a 16-Word Bit-Reversed Buffer
A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal
0 0 0 0 0 0 0 0 0 0
0 0 0 1 1 1 0 0 0 8
0 0 1 0 2 0 1 0 0 4
0 0 1 1 3 1 1 0 0 12
0 1 0 0 4 0 0 1 0 2
0 1 0 1 5 1 0 1 0 10
0 1 1 0 6 0 1 1 0 6
0 1 1 1 7 1 1 1 0 14
1 0 0 0 8 0 0 0 1 1
1 0 0 1 9 1 0 0 1 9
1 0 1 0 10 0 1 0 1 5
1 0 1 1 11 1 1 0 1 13
1 1 0 0 12 0 0 1 1 3
1 1 0 1 13 1 0 1 1 11
1 1 1 0 14 0 1 1 1 7
1 1 1 1 15 1 1 1 1 15
23 bits
EA 1/0
8 bits 16 bits
24 bits
Select
1 EA 0
Program Space Visibility(1)
(Remapping)
0 PSVPAG
8 bits 15 bits
23 bits
Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain
word alignment of data in the program and data spaces.
2: Table operations are not required to be word-aligned. Table read operations are permitted in
the configuration memory space.
4.6.2 DATA ACCESS FROM PROGRAM In Byte mode, either the upper or lower byte of the
MEMORY USING TABLE lower program word is mapped to the lower byte of
INSTRUCTIONS a data address. The upper byte is selected when
Byte Select is ‘1’; the lower byte is selected when
The TBLRDL and TBLWTL instructions offer a direct it is ‘0’.
method of reading or writing the lower word of any
address within the program space without going • TBLRDH (Table Read High): In Word mode, this
through data space. The TBLRDH and TBLWTH instruction maps the entire upper word of a program
instructions are the only method to read or write the address (P<23:16>) to a data address. Note that
upper 8 bits of a program space word as data. D<15:8>, the ‘phantom byte’, will always be ‘0’.
The PC is incremented by two for each successive In Byte mode, this instruction maps the upper or
24-bit program word. This allows program memory lower byte of the program word to D<7:0> of the
addresses to directly map to data space addresses. data address, as in the TBLRDL instruction. Note
Program memory can thus be regarded as two that the data will always be ‘0’ when the upper
16-bit-wide word address spaces, residing side by side, ‘phantom’ byte is selected (Byte Select = 1).
each with the same address range. TBLRDL and In a similar fashion, two table instructions, TBLWTH
TBLWTL access the space that contains the least and TBLWTL, are used to write individual bytes or
significant data word. TBLRDH and TBLWTH access the words to a program space address. The details of
space that contains the upper data byte. their operation are explained in Section 5.0 “Flash
Two table instructions are provided to move byte or Program Memory”.
word sized (16-bit) data to and from program space. For all table operations, the area of program memory
Both function as either byte or word operations. space to be accessed is determined by the Table Page
• TBLRDL (Table Read Low): In Word mode, this register (TBLPAG). TBLPAG covers the entire program
instruction maps the lower word of the program memory space of the device, including user and
space location (P<15:0>) to a data address configuration spaces. When TBLPAG<7> = 0, the table
(D<15:0>). page is located in the user memory space. When
TBLPAG<7> = 1, the page is located in configuration
space.
‘Phantom’ Byte
TBLRDH.B (Wn<0> = 0)
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
4.6.3 READING DATA FROM PROGRAM 24-bit program word are used to contain the data. The
MEMORY USING PROGRAM SPACE upper 8 bits of any program space location used as
VISIBILITY data should be programmed with ‘1111 1111’ or
‘0000 0000’ to force a NOP. This prevents possible
The upper 32 Kbytes of data space may optionally be issues should the area of code ever be accidentally
mapped into any 16K word page of the program space. executed.
This option provides transparent access to stored
constant data from the data space without the need to Note: PSV access is temporarily disabled during
use special instructions (such as TBLRDL/H). table reads/writes.
Program space access through the data space occurs For operations that use PSV and are executed outside
if the Most Significant bit of the data space EA is ‘1’ and a REPEAT loop, the MOV and MOV.D instructions
program space visibility is enabled by setting the PSV require one instruction cycle in addition to the specified
bit in the Core Control register (CORCON<2>). The execution time. All other instructions require two
location of the program memory space to be mapped instruction cycles in addition to the specified execution
into the data space is determined by the Program time.
Space Visibility Page register (PSVPAG). This 8-bit For operations that use PSV, and are executed inside
register defines any one of 256 possible pages of a REPEAT loop, these instances require two instruction
16K words in program space. In effect, PSVPAG cycles in addition to the specified execution time of the
functions as the upper 8 bits of the program memory instruction:
address, with the 15 bits of the EA functioning as the
lower bits. By incrementing the PC by 2 for each • Execution in the first iteration
program memory word, the lower 15 bits of data space • Execution in the last iteration
addresses directly map to the lower 15 bits in the • Execution prior to exiting the loop due to an
corresponding program space addresses. interrupt
Data reads to this area add a cycle to the instruction • Execution upon re-entering the loop after an
being executed, since two program memory fetches interrupt is serviced
are required. Any other iteration of the REPEAT loop will allow the
Although each data space address 8000h and higher instruction using PSV to access data to execute in a
maps directly into a corresponding program memory single cycle.
address (see Figure 4-9), only the lower 16 bits of the
PSV Area
...while the lower 15 bits
of the EA specify an
exact address within
0xFFFF the PSV area. This
corresponds exactly to
the same lower 15 bits
of the actual program
space address.
0x800000
NOTES:
5.0 FLASH PROGRAM MEMORY ground (VSS) and Master Clear (MCLR). This allows
customers to manufacture boards with unprogrammed
Note 1: This data sheet summarizes the features devices and then program the digital signal controller
of the dsPIC33FJ32GP202/204 and just before shipping the product. This also allows the
dsPIC33FJ16GP304 family of devices. It most recent firmware or a custom firmware to be pro-
is not intended to be a comprehensive grammed.
reference source. To complement the RTSP is accomplished using TBLRD (table read) and
information in this data sheet, refer to TBLWT (table write) instructions. With RTSP, the user
Section 5. “Flash Programming” application can write program memory data either in
(DS70191) of the “dsPIC33F/PIC24H blocks or ‘rows’ of 64 instructions (192 bytes) at a time
Family Reference Manual”, which is avail- or a single program memory word, and erase program
able from the Microchip website memory in blocks or ‘pages’ of 512 instructions (1536
(www.microchip.com). bytes) at a time.
2: Some registers and associated bits
described in this section may not be avail- 5.1 Table Instructions and Flash
able on all devices. Refer to Section 4.0 Programming
“Memory Organization” in this data
sheet for device-specific register and bit Regardless of the method used, all programming of
information. Flash memory is done with the table read and table
write instructions. These allow direct read and write
The dsPIC33FJ32GP202/204 and
access to the program memory space from the data
dsPIC33FJ16GP304 devices contain internal Flash
memory while the device is in normal operating mode.
program memory for storing and executing application
The 24-bit target address in the program memory is
code. The memory is readable, writable and erasable
formed using bits <7:0> of the TBLPAG register and the
during normal operation over the entire VDD range.
Effective Address (EA) from a W register specified in
Flash memory can be programmed in two ways: the table instruction, as shown in Figure 5-1.
• In-Circuit Serial Programming™ (ICSP™) The TBLRDL and the TBLWTL instructions are used to
programming capability read or write to bits<15:0> of program memory.
• Run-Time Self-Programming (RTSP) TBLRDL and TBLWTL can access program memory in
both Word and Byte modes.
ICSP allows a dsPIC33FJ32GP202/204 and
dsPIC33FJ16GP304 device to be serially programmed The TBLRDH and TBLWTH instructions are used to read
while in the end application circuit. This is done with or write to bits<23:16> of program memory. TBLRDH
two lines for programming clock and programming data and TBLWTH can also access program memory in Word
(one of the alternate programming pin pairs: or Byte mode.
PGECx/PGEDx), and three other lines for power (VDD),
24 bits
Using
0 Program Counter 0
Program Counter
Working Reg EA
Using
1/0 TBLPAG Reg
Table Instruction
8 bits 16 bits
User/Configuration Byte
Space Select 24-bit EA Select
11064 Cycles
T RW = ---------------------------------------------------------------------------------------------- = 1.586ms
7.37 MHz 1 – 0.05 1 – 0.00375
If ERASE = 0:
1111 = No operation
1101 = No operation
1100 = No operation
0011 = Memory word program operation
0010 = No operation
0001 = Memory row program operation
0000 = Program a single Configuration register byte
5.4.1 PROGRAMMING ALGORITHM FOR 4. Write the first 64 instructions from data RAM into
FLASH PROGRAM MEMORY the program memory buffers (see Example 5-2).
Programmers can program one row of program Flash 5. Write the program block to Flash memory:
memory at a time. To do this, it is necessary to erase a) Set the NVMOP bits to ‘0001’ to configure
the 8-row erase page that contains the desired row. for row programming. Clear the ERASE bit
The general process is: and set the WREN bit.
1. Read eight rows of program memory b) Write 0x55 to NVMKEY.
(512 instructions) and store in data RAM. c) Write 0xAA to NVMKEY.
2. Update the program data in RAM with the d) Set the WR bit. The programming cycle
desired new data. begins and the CPU stalls for the duration of
3. Erase the block (see Example 5-1): the write cycle. When the write to Flash
memory is done, the WR bit is cleared
a) Set the NVMOP bits (NVMCON<3:0>) to
automatically.
‘0010’ to configure for block erase. Set the
ERASE (NVMCON<6>) and WREN 6. Repeat steps 4 and 5, using the next available
(NVMCON<14>) bits. 64 instructions from the block in data RAM by
incrementing the value in TBLPAG, until all
b) Write the starting address of the page to be
512 instructions are written back to Flash memory.
erased into the TBLPAG and W registers.
c) Write 0x55 to NVMKEY. For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
d) Write 0xAA to NVMKEY.
any erase or program operation to proceed. After the
e) Set the WR bit (NVMCON<15>). The erase programming command has been executed, the user
cycle begins and the CPU stalls for the application must wait for the programming time until
duration of the erase cycle. When the erase is programming is complete. The two instructions
done, the WR bit is cleared automatically. following the start of the programming sequence
should be NOPs, as shown in Example 5-3.
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
BOR
Internal
Regulator SYSRST
VDD
Trap Conflict
Illegal Opcode
Uninitialized W Register
Configuration Mismatch
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
6.1 System Reset 2. BOR Reset: The on-chip voltage regulator has
a BOR circuit that keeps the device in Reset
The dsPIC33FJ32GP202/204 and until VDD crosses the VBOR threshold and the
dsPIC33FJ16GP304 family of devices have two types delay TBOR has elapsed. The delay TBOR
of Reset: ensures that the voltage regulator output
• Cold Reset becomes stable.
• Warm Reset 3. PWRT Timer: The programmable power-up
timer continues to hold the processor in Reset
A cold Reset is the result of a Power-on Reset (POR)
for a specific period of time (TPWRT) after a
or a Brown-out Reset (BOR). On a cold Reset, the
BOR. The delay TPWRT ensures that the system
FNOSC configuration bits in the FOSC device
power supplies have stabilized at the
configuration register selects the device clock source.
appropriate level for full-speed operation. After
A warm Reset is the result of all other reset sources, the delay TPWRT has elapsed, the SYSRST
including the RESET instruction. On warm Reset, the becomes inactive, which in turn enables the
device will continue to operate from the current clock selected oscillator to start generating clock
source as indicated by the Current Oscillator Selection cycles.
(COSC<2:0>) bits in the Oscillator Control 4. Oscillator Delay: The total delay for the clock to
(OSCCON<14:12>) register. be ready for various clock source selections is
The device is kept in a Reset state until the system given in Table 6-1. Refer to Section 8.0
power supplies have stabilized at appropriate levels “Oscillator Configuration” for more
and the oscillator clock is ready. The sequence in information.
which this occurs is detailed below and is shown in 5. When the oscillator clock is ready, the processor
Figure 6-2. begins execution from location 0x000000. The
1. POR Reset: A POR circuit holds the device in user application programs a GOTO instruction at
Reset when the power supply is turned on. The the reset address, which redirects program
POR circuit is active until VDD crosses the VPOR execution to the appropriate start-up routine.
threshold and the delay TPOR has elapsed. 6. The Fail-Safe Clock Monitor (FSCM), if enabled,
begins to monitor the system clock when the
system clock is ready and the delay TFSCM
elapsed.
Vbor
VBOR
VPOR
VDD
TPOR
1
POR Reset TBOR
2
BOR Reset 3
TPWRT
SYSRST
4
Oscillator Clock
TOSCD TOST TLOCK
6
TFSCM
FSCM
5
Time
Note 1: POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is
active until VDD crosses the VPOR threshold and the delay TPOR has elapsed.
2: BOR Reset: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses
the VBOR threshold and the delay TBOR has elapsed. The delay TBOR ensures the voltage regulator output
becomes stable.
3: PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific
period of time (TPWRT) after a BOR. The delay TPWRT ensures that the system power supplies have stabilized
at the appropriate level for full-speed operation. After the delay TPWRT has elapsed, the SYSRST becomes
inactive, which in turn enables the selected oscillator to start generating clock cycles.
4: Oscillator Delay: The total delay for the clock to be ready for various clock source selections are given in
Table 6-1. Refer to Section 8.0 “Oscillator Configuration” for more information.
5: When the oscillator clock is ready, the processor begins execution from location 0x000000. The user
application programs a GOTO instruction at the reset address, which redirects program execution to the
appropriate start-up routine.
6: The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock
is ready and the delay TFSCM elapsed.
VBOR
TBOR + TPWRT
SYSRST
VDD
VBOR
TBOR + TPWRT
SYSRST
VDD
VBOR
TBOR + TPWRT
SYSRST
6.3 External Reset (EXTR) The Software Reset (Instruction) Flag (SWR) bit in the
Reset Control (RCON<6>) register is set to indicate
The external Reset is generated by driving the MCLR the software Reset.
pin low. The MCLR pin is a Schmitt trigger input with an
additional glitch filter. Reset pulses that are longer than
6.5 Watchdog Time-out Reset (WDTO)
the minimum pulse-width will generate a Reset. Refer
to Section 22.0 “Electrical Characteristics” for Whenever a Watchdog time-out occurs, the device will
minimum pulse-width specifications. The External asynchronously assert SYSRST. The clock source will
Reset (MCLR) Pin (EXTR) bit in the Reset Control remain unchanged. A WDT time-out during Sleep or
(RCON) register is set to indicate the MCLR Reset. Idle mode will wake-up the processor, but will not reset
the processor.
6.3.1 EXTERNAL SUPERVISORY CIRCUIT
The Watchdog Timer Time-out Flag (WDTO) bit in the
Many systems have external supervisory circuits that Reset Control (RCON<4>) register is set to indicate
generate reset signals to Reset multiple devices in the the Watchdog Reset. Refer to Section 19.4
system. This external Reset signal can be directly “Watchdog Timer (WDT)” for more information on
connected to the MCLR pin to Reset the device when Watchdog Reset.
the rest of system is Reset.
6.6 Trap Conflict Reset
6.3.2 INTERNAL SUPERVISORY CIRCUIT
If a lower-priority hard trap occurs while a
When using the internal power supervisory circuit to higher-priority trap is being processed, a hard trap
Reset the device, the external reset pin (MCLR) should conflict Reset occurs. The hard traps include
be tied directly or resistively to VDD. In this case, the exceptions of priority level 13 through level 15, inclu-
MCLR pin will not be used to generate a Reset. The sive. The address error (level 13) and oscillator error
external reset pin (MCLR) does not have an internal (level 14) traps fall into this category.
pull-up and must not be left unconnected.
The Trap Reset Flag (TRAPR) bit in the Reset Control
(RCON<15>) register is set to indicate the Trap Conflict
6.4 Software RESET Instruction (SWR)
Reset. Refer to Section 7.0 “Interrupt Controller” for
Whenever the RESET instruction is executed, the more information on trap conflict Resets.
device will assert SYSRST, placing the device in a
special Reset state. This Reset state will not
re-initialize the clock. The clock source in effect prior to
the RESET instruction will remain. SYSRST is released
at the next instruction cycle, and the reset vector fetch
will commence.
6.7 Configuration Mismatch Reset each program memory section to store the data values.
The upper 8 bits should be programmed with 3Fh,
To maintain the integrity of the peripheral pin select which is an illegal opcode value.
control registers, they are constantly monitored with
shadow registers in hardware. If an unexpected 6.8.2 UNINITIALIZED W REGISTER
change in any of the registers occur (such as cell RESET
disturbances caused by ESD or other external events),
a configuration mismatch Reset occurs. Any attempts to use the uninitialized W register as an
address pointer will Reset the device. The W register
The Configuration Mismatch Flag (CM) bit in the array (with the exception of W15) is cleared during all
Reset Control (RCON<9>) register is set to indicate resets and is considered uninitialized until written to.
the configuration mismatch Reset. Refer to
Section 10.0 “I/O Ports” for more information on the 6.8.3 SECURITY RESET
configuration mismatch Reset.
If a Program Flow Change (PFC) or Vector Flow
Note: The configuration mismatch feature and Change (VFC) targets a restricted location in a
associated reset flag is not available on all protected segment (Boot and Secure Segment), that
devices. operation will cause a security Reset.
The PFC occurs when the Program Counter is
6.8 Illegal Condition Device Reset reloaded as a result of a Call, Jump, Computed Jump,
Return, Return from Subroutine, or other form of
An illegal condition device Reset occurs due to the branch instruction.
following sources:
The VFC occurs when the Program Counter is
• Illegal Opcode Reset reloaded with an Interrupt or Trap vector.
• Uninitialized W Register Reset
Refer to Section 19.6 “Code Protection and
• Security Reset CodeGuard™ Security” for more information on
The Illegal Opcode or Uninitialized W Access Reset Security Reset.
Flag (IOPUWR) bit in the Reset Control (RCON<14>)
register is set to indicate the illegal condition device 6.9 Using the RCON Status Bits
Reset.
The user application can read the Reset Control
6.8.1 ILLEGAL OPCODE RESET (RCON) register after any device Reset to determine
the cause of the reset.
A device Reset is generated if the device attempts to
execute an illegal opcode value that is fetched from Note: The status bits in the RCON register
program memory. should be cleared after they are read so
The illegal opcode Reset function can prevent the that the next RCON register value after a
device from executing program memory sections that device Reset will be meaningful.
are used to store constant data. To take advantage of Table 6-3 provides a summary of the reset flag bit
the illegal opcode Reset, use only the lower 16 bits of operation.
Note 1: See Table 7-1 for the list of implemented interrupt vectors.
Legend:
C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’
S = Set only bit W = Writable bit -n = Value at POR
‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: For complete register details, see Register 3-1: “SR: CPU Status Register”.
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
Note 1: For complete register details, see Register 3-2: “CORCON: CORE Control Register”.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
NOTES:
DOZE
(1) S1/S3
S1 PLL
OSC2
POSCMD<1:0>
FP
FRCDIV
FRC FRCDIVN ÷ 2
Oscillator S7
FOSC
FRCDIV<2:0>
TUN<5:0> FRCDIV16 S6
÷ 16
FRC S0
LPRC LPRC
S5
Oscillator
Secondary Oscillator
SOSC
SOSCO S4
LPOSCEN
SOSCI Clock Fail Clock Switch Reset
S7 NOSC<2:0> FNOSC<2:0>
WDT, PWRT,
FSCM
Timer 1
For a primary oscillator or FRC oscillator, output ‘FIN’, • If PLLDIV<8:0> = 0x1E, then M = 32. This yields a
The PLL output ‘FOSC’ is given by: VCO output of 5 x 32 = 160 MHz, which is within
the 100-200 MHz ranged needed.
EQUATION 8-2: FOSC CALCULATION • If PLLPOST<1:0> = 0, then N2 = 2. This provides
a Fosc of 160/2 = 80 MHz. The resultant device
F OSC = F IN -------------------
M operating speed is 80/2 = 40 MIPS.
N1 N2
EQUATION 8-3: XT WITH PLL MODE
For example, suppose a 10 MHz crystal is being used, EXAMPLE
with “XT with PLL” being the selected oscillator mode.
1 10000000 32
• If PLLPRE<4:0> = 0, then N1 = 2. This yields a F CY = ------------- = --- ---------------------------------- = 40 MIPS
F OSC
VCO input of 10/2 = 5 MHz, which is within the 2 2 22
acceptable range of 0.8-8 MHz.
FVCO
0.8-8.0 MHz 12.5-80 MHz
100-200 MHz
Here(1) Here(1)
Here(1)
PLLDIV
N1 N2
Divide by Divide by
2-33 M 2, 4, 8
Divide by
2-513
Legend: y = Value set from Configuration bits on POR C = Clear only bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: Writes to this register require an unlock sequence. Refer to Section 7. “Oscillator” (DS70186) in the
“dsPIC33F/PIC24H Family Reference Manual” (available from the Microchip website) for details.
2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC mode
as a transition clock source between the two PLL modes.
Note 1: Writes to this register require an unlock sequence. Refer to Section 7. “Oscillator” (DS70186) in the
“dsPIC33F/PIC24H Family Reference Manual” (available from the Microchip website) for details.
2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC mode
as a transition clock source between the two PLL modes.
Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither
characterized nor tested.
8.2 Clock Switching Operation case, the OSWEN bit is cleared automatically
and the clock switch is aborted.
Applications are free to switch among any of the four
2. If a valid clock switch has been initiated, the
clock sources (Primary, LP, FRC and LPRC) under
LOCK (OSCCON<5>) and the CF
software control at any time. To limit the possible side
(OSCCON<3>) status bits are cleared.
effects of this flexibility, dsPIC33FJ32GP202/204 and
dsPIC33FJ16GP304 devices have a safeguard lock 3. The new oscillator is turned on by the hardware
built into the switch process. if it is not currently running. If a crystal oscillator
must be turned on, the hardware waits until the
Note: Primary Oscillator mode has three different Oscillator Start-up Timer (OST) expires. If the
submodes (XT, HS and EC), which are new source is using the PLL, the hardware waits
determined by the POSCMD<1:0> until a PLL lock is detected (LOCK = 1).
Configuration bits. While an application 4. The hardware waits for 10 clock cycles from the
can switch to and from Primary Oscillator new clock source and then performs the clock
mode in software, it cannot switch among switch.
the different primary submodes without
5. The hardware clears the OSWEN bit to indicate a
reprogramming the device.
successful clock transition. In addition, the NOSC
bit values are transferred to the COSC status bits.
8.2.1 ENABLING CLOCK SWITCHING
6. The old clock source is turned off at this time,
To enable clock switching, the FCKSM1 Configuration with the exception of LPRC (if WDT or FSCM
bit in the Configuration register must be programmed to are enabled) or LP (if LPOSCEN remains set).
‘0’. (Refer to Section 19.1 “Configuration Bits” for
further details.) If the FCKSM1 Configuration bit is Note 1: The processor continues to execute code
unprogrammed (‘1’), the clock switching function and throughout the clock switching sequence.
Fail-Safe Clock Monitor function are disabled. This is Timing-sensitive code should not be
the default setting. executed during this time.
The NOSC control bits (OSCCON<10:8>) do not 2: Direct clock switches between any primary
control the clock selection when clock switching is oscillator mode with PLL and FRCPLL
disabled. However, the COSC bits (OSCCON<14:12>) mode are not permitted. This applies to
reflect the clock source selected by the FNOSC clock switches in either direction. In these
Configuration bits. instances, the application must switch to
FRC mode as a transition clock source
The OSWEN control bit (OSCCON<0>) has no effect between the two PLL modes.
when clock switching is disabled. It is held at ‘0’ at all 3: Refer to Section 7. “Oscillator”
times. (DS70186) in the “dsPIC33F/PIC24H
Family Reference Manual” for details.
8.2.2 OSCILLATOR SWITCHING
SEQUENCE
8.3 Fail-Safe Clock Monitor (FSCM)
Performing a clock switch requires this basic
sequence: The Fail-Safe Clock Monitor (FSCM) allows the device
1. If desired, read the COSC bits to continue to operate even in the event of an oscillator
(OSCCON<14:12>) to determine the current failure. The FSCM function is enabled by programming.
oscillator source. If the FSCM function is enabled, the LPRC internal
oscillator runs at all times (except during Sleep mode)
2. Perform the unlock sequence to allow a write to
and is not subject to control by the Watchdog Timer.
the OSCCON register high byte.
3. Write the appropriate value to the NOSC control In the event of an oscillator failure, the FSCM
bits (OSCCON<10:8>) for the new oscillator generates a clock failure trap event and switches the
source. system clock over to the FRC oscillator. Then the
application program can either attempt to restart the
4. Perform the unlock sequence to allow a write to
oscillator or execute a controlled shutdown. The trap
the OSCCON register low byte.
can be treated as a warm Reset by simply loading the
5. Set the OSWEN bit to initiate the oscillator Reset address into the oscillator fail trap vector.
switch.
If the PLL multiplier is used to scale the system clock,
Once the basic sequence is completed, the system the internal FRC is also multiplied by the same factor
clock hardware responds automatically as follows: on clock failure. Essentially, the device switches to
1. The clock switching hardware compares the FRC with PLL on a clock failure.
COSC status bits with the new value of the
NOSC control bits. If they are the same, the
clock switch is a redundant operation. In this
NOTES:
9.2.2 IDLE MODE Doze mode is enabled by setting the DOZEN bit
(CLKDIV<11>). The ratio between peripheral and core
The following occur in Idle mode:
clock speed is determined by the DOZE<2:0> bits
• The CPU stops executing instructions. (CLKDIV<14:12>). There are eight possible
• The WDT is automatically cleared. configurations, from 1:1 to 1:128, with 1:1 being the
• The system clock source remains active. By default setting.
default, all peripheral modules continue to operate Programs can use Doze mode to selectively reduce
normally from the system clock source, but can power consumption in event-driven applications. This
also be selectively disabled (see Section 9.4 allows clock-sensitive functions, such as synchronous
“Peripheral Module Disable”). communications, to continue without interruption while
• If the WDT or FSCM is enabled, the LPRC also the CPU idles, waiting for something to invoke an
remains active. interrupt routine. An automatic return to full-speed CPU
The device will wake from Idle mode on any of these operation on interrupts can be enabled by setting the
events: ROI bit (CLKDIV<15>). By default, interrupt events
have no effect on Doze mode operation.
• Any interrupt that is individually enabled.
For example, suppose the device is operating at
• Any device Reset
20 MIPS and the CAN module has been configured for
• A WDT time-out 500 kbps based on this device operating speed. If the
On wake-up from Idle mode, the clock is reapplied to device is placed in Doze mode with a clock frequency
the CPU and instruction execution will begin (2-4 ratio of 1:4, the CAN module continues to communicate
cycles later), starting with the instruction following the at the required bit rate of 500 kbps, but the CPU now
PWRSAV instruction, or the first instruction in the ISR. starts executing instructions at a frequency of 5 MIPS.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: PCFGx bits have no effect if the ADC module is disabled by setting this bit. In this case, all port pins
multiplexed with ANx will be in Digital mode.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
10.0 I/O PORTS the I/O pin. The logic also prevents “loop through”, in
which a port’s digital output can drive the input of a
Note 1: This data sheet summarizes the features peripheral that shares the same pin. Figure 10-1 shows
of the dsPIC33FJ32GP202/204 and how ports are shared with other peripherals and the
dsPIC33FJ16GP304 family of devices. It associated I/O pin to which they are connected.
is not intended to be a comprehensive When a peripheral is enabled and the peripheral is
reference source. To complement the
actively driving an associated pin, the use of the pin as
information in this data sheet, refer to
a general purpose output pin is disabled. The I/O pin
Section 10. “I/O Ports” (DS70193) of
can be read, but the output driver for the parallel port bit
the “dsPIC33F/PIC24H Family Reference
is disabled. If a peripheral is enabled, but the peripheral
Manual”, which is available from the
is not actively driving a pin, that pin can be driven by a
Microchip website (www.microchip.com).
port.
2: Some registers and associated bits
described in this section may not be avail- All port pins have three registers directly associated
able on all devices. Refer to Section 4.0 with their operation as digital I/O. The data direction
“Memory Organization” in this data register (TRISx) determines whether the pin is an input
sheet for device-specific register and bit or an output. If the data direction bit is a ‘1’, then the pin
information. is an input. All port pins are defined as inputs after a
Reset. Reads from the latch (LATx) read the latch.
All of the device pins (except VDD, VSS, MCLR and Writes to the latch, write the latch. Reads from the port
OSC1/CLKI) are shared among the peripherals and the (PORTx) read the port pins, while writes to the port pins
parallel I/O ports. All I/O input ports feature Schmitt write the latch.
Trigger inputs for improved noise immunity.
Any bit and its associated data and control registers
that are not valid for a particular device will be
10.1 Parallel I/O (PIO) Ports disabled. That means the corresponding LATx and
A parallel I/O port that shares a pin with a peripheral is TRISx registers and the port pin will read as zeros.
generally subservient to the peripheral. The When a pin is shared with another peripheral or
peripheral’s output buffer data and control signals are function that is defined as an input only, it is
provided to a pair of multiplexers. The multiplexers nevertheless regarded as a dedicated port because
select whether the peripheral or the associated port there is no other competing source of outputs.
has ownership of the output data and control signals of
PIO Module
1
Read TRIS Output Data
0
Data Bus D Q
I/O Pin
WR TRIS CK
TRIS Latch
D Q
WR LAT +
WR Port CK
Data Latch
Read LAT
Input Data
Read Port
The AD1PCFG and TRIS registers control the Four control registers are associated with the CN
operation of the analog-to-digital (A/D) port pins. The module. The CNEN1 and CNEN2 registers contain the
port pins that are desired as analog inputs must have interrupt enable control bits for each of the CN input
their corresponding TRIS bit set (input). If the TRIS bit pins. Setting any of these bits enables a CN interrupt
is cleared (output), the digital output level (VOH or VOL) for the corresponding pins.
will be converted. Each CN pin also has a weak pull-up connected to it.
The AD1PCFGL register has a default value of 0x0000; The pull-ups act as a current source connected to the
therefore, all pins that share ANx functions are analog pin, and eliminate the need for external resistors when
(not digital) by default. push button or keypad devices are connected. The
pull-ups are enabled separately using the CNPU1 and
When the PORT register is read, all pins configured as CNPU2 registers, which contain the control bits for
analog input channels will read as cleared (a low level). each of the CN pins. Setting any of the control bits
Pins configured as digital inputs will not convert an enables the weak pull-ups for the corresponding pins.
analog input. Analog levels on any pin that is defined as
Note: Pull-ups on change notification pins
a digital input (including the ANx pins) can cause the
should always be disabled when the port
input buffer to consume current that exceeds the
pin is configured as a digital output.
device specifications.
10.6 Peripheral Pin Select peripheral’s bit field with an appropriate 5-bit value
maps the RPn pin with that value to that peripheral. For
A major challenge in general-purpose devices is any given device, the valid range of values for any bit
providing the largest possible set of peripheral features field corresponds to the maximum number of peripheral
while minimizing the conflict of features on I/O pins. pin selections supported by the device.
The challenge is even greater on low-pin count
devices. In an application where more than one Figure 10-2 Illustrates remappable pin selection for
peripheral must be assigned to a single pin, U1RX input.
inconvenient workarounds in application code or a Note: For input mapping only, the Peripheral Pin
complete redesign may be the only option. Select (PPS) functionality does not have
Peripheral pin select configuration enables peripheral priority over the TRISx settings. Therefore,
set selection and placement on a wide range of I/O when configuring the RPn pin for input, the
pins. By increasing the pinout options available on a corresponding bit in the TRISx register
particular device, programmers can better tailor the must also be configured for input (i.e., set
microcontroller to their entire application, rather than to ‘1’).
trimming the application to fit the device.
The peripheral pin select configuration feature FIGURE 10-2: REMAPPABLE MUX
operates over a fixed subset of digital I/O pins. INPUT FOR U1RX
Programmers can independently map the input and/or U1RXR<4:0>
output of most digital peripherals to any one of these
I/O pins. Peripheral pin select is performed in software,
and generally does not require the device to be 0
reprogrammed. Hardware safeguards are included that RP0
prevent accidental or spurious changes to the
peripheral mapping, once it has been established. 1
RP1
10.6.1 AVAILABLE PINS U1RX input
to peripheral
The peripheral pin select feature is used with a range 2
of up to 26 pins. The number of available pins depends RP2
on the particular device and its pin count. Pins that
support the peripheral pin select feature include the
designation “RPn” in their full pin designation, where
“RP” designates a remappable peripheral and “n” is the
remappable pin number. 25
Default
0
U1TX Output
3
U1RTS Output 4
RPn
Output Data
OC1 Output
18
OC2 Output
19
10.6.3 CONTROLLING CONFIGURATION Unlike the similar sequence with the oscillator’s LOCK
CHANGES bit, IOLOCK remains in one state until changed. This
allows all of the peripheral pin selects to be configured
Because peripheral remapping can be changed during
with a single unlock sequence followed by an update to
run time, some restrictions on peripheral remapping
all control registers, then locked with a second lock
are needed to prevent accidental configuration
sequence.
changes. dsPIC33F devices include three features to
prevent alterations to the peripheral map: 10.6.3.2 Continuous State Monitoring
• Control register lock sequence In addition to being protected from direct writes, the
• Continuous state monitoring contents of the RPINRx and RPORx registers are
• Configuration bit pin select lock constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
10.6.3.1 Control Register Lock (such as cell disturbances caused by ESD or other
Under normal operation, writes to the RPINRx and external events), a configuration mismatch Reset will
RPORx registers are not allowed. Attempted writes be triggered.
appear to execute normally, but the contents of the
registers remain unchanged. To change these 10.6.3.3 Configuration Bit Pin Select Lock
registers, they must be unlocked in hardware. The As an additional level of safety, the device can be
register lock is controlled by the IOLOCK bit configured to prevent more than one write session to
(OSCCON<6>). Setting IOLOCK prevents writes to the the RPINRx and RPORx registers. The IOL1WAY
control registers; clearing IOLOCK allows writes. (FOSC<IOL1WAY>) configuration bit blocks the
To set or clear IOLOCK, a specific command sequence IOLOCK bit from being cleared after it has been set
must be executed: once.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2: Some registers and associated bits 1. Set the TON bit (= 1) in the T1CON register.
described in this section may not be avail- 2. Select the timer prescaler ratio using the
able on all devices. Refer to Section 4.0 TCKPS<1:0> bits in the T1CON register.
Memory Organization in this data sheet 3. Set the Clock and Gating modes using the TCS
for device-specific register and bit infor- and TGATE bits in the T1CON register.
mation. 4. Set or clear the TSYNC bit in T1CON to select
The Timer1 module is a 16-bit timer, which can serve synchronous or asynchronous operation.
as the time counter for the real-time clock, or operate 5. Load the timer period value into the PR1
as a free-running interval timer/counter. Timer1 can register.
operate in three modes: 6. If interrupts are required, set the interrupt enable
• 16-bit Timer bit, T1IE. Use the priority bits, T1IP<2:0>, to set
the interrupt priority.
• 16-bit Synchronous Counter
• 16-bit Asynchronous Counter
TCKPS<1:0>
SOSCO/ TON 2
1x
T1CK
Gate Prescaler
SOSCEN Sync 01 1, 8, 64, 256
SOSCI
TCY 00
TGATE
TGATE TCS
1 Q D
Set T1IF
0 Q CK
0
Reset
TMR1
1 Sync
Comparator TSYNC
Equal
PR1
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
TCKPS<1:0>
TON 2
T2CK 1x
Gate Prescaler
Sync 01 1, 8, 64, 256
TCY 00
TGATE TGATE
TCS
1 Q D
Set T3IF
Q CK
0
PR3 PR2
MSb LSb
16
Read TMR2
Write TMR2
16
16
TMR3HLD
16
Data Bus<15:0>
Note 1: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective
to the T2CON register.
2: The ADC event trigger is available only on Timer2/3.
TCKPS<1:0>
TON 2
T2CK 1x
Gate Prescaler
Sync 01 1, 8, 64, 256
TGATE 00
TCY TCS
1 Q D TGATE
Set T2IF Q CK
0
Reset
TMR2 Sync
Comparator
Equal
PR2
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (T2CON<3>), the TSIDL bit
must be cleared to operate the 32-bit timer in Idle mode.
2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control (T2CON<3>) register, these bits
have no effect.
NOTES:
16 16
ICTMR
1 0
(ICxCON<7>)
Prescaler Edge Detection Logic FIFO
Counter and R/W
(1, 4, 16) Clock Synchronizer Logic
ICx Pin
ICM<2:0> (ICxCON<2:0>)
3 Mode Select
FIFO
System Bus
Set Flag ICxIF
(in IFSn Register)
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
OCxRS
OCxR Output S Q
OCx
Logic R
3 Output Enable
OCM<2:0>
Mode Select OCFA
Comparator
0 1 OCTSEL 0 1
16 16
14.1 Output Compare Modes application must disable the associated timer when
writing to the output compare control registers to avoid
Configure the Output Compare modes by setting the malfunctions.
appropriate Output Compare Mode (OCM<2:0>) bits in
the Output Compare Control (OCxCON<2:0>) register. Note: See Section 13. “Output Compare” in
Table 14-1 lists the different bit settings for the Output the “dsPIC33F/PIC24H Family Reference
Compare modes. Figure 14-2 illustrates the output Manual” (DS70209) for OCxR and OCxRS
compare operation for various modes. The user register restrictions.
OCxRS
TMRy
OCxR
Active-Low One-Shot
(OCM = 001)
Active-High One-Shot
(OCM = 010)
Toggle Mode
(OCM = 011)
Delayed One-Shot
(OCM = 100)
PWM Mode
(OCM = 110 or 111)
NOTES:
Transfer Transfer
SPIxRXB SPIxTXB
SPIxBUF
16
Internal Data Bus
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes
(FRMEN = 1).
2: This bit must be cleared when FRMEN = 1.
3: Do not set both Primary and Secondary prescalers to a value of 1:1.
Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes
(FRMEN = 1).
2: This bit must be cleared when FRMEN = 1.
3: Do not set both Primary and Secondary prescalers to a value of 1:1.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
NOTES:
Internal
Data Bus
I2CxRCV
Read
Shift
SCLx Clock
I2CxRSR
LSb
I2CxMSK
Write Read
I2CxADD
Read
Read
Collision Write
Detect
I2CxCON
Acknowledge
Generation Read
Clock
Stretching
Write
I2CxTRN
LSb
Shift Clock Read
Reload
Control
Write
Read
TCY/2
R/C-0 HS R/C-0 HS R-0 HSC R/C-0 HSC R/C-0 HSC R-0 HSC R-0 HSC R-0 HSC
IWCOL I2COV D_A P S R_W RBF TBF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
NOTES:
17.0 UNIVERSAL ASYNCHRONOUS The primary features of the UART module are:
RECEIVER TRANSMITTER • Full-Duplex, 8- or 9-bit Data Transmission through
(UART) the UxTX and UxRX pins
• Even, odd or no parity options (for 8-bit data)
Note 1: This data sheet summarizes the features • One or two stop bits
of the dsPIC33FJ32GP202/204 and • Hardware Flow Control Option with UxCTS and
dsPIC33FJ16GP304 family of devices. It UxRTS pins
is not intended to be a comprehensive
• Fully Integrated Baud Rate Generator with 16-bit
reference source. To complement the
prescaler
information in this data sheet, refer to
Section 17. “UART” (DS70188) of the • Baud rates ranging from 10 Mbps to 38 bps at 40
“dsPIC33F/PIC24H Family Reference MIPS
Manual”, which is available on the • 4-deep first-in-first-out (FIFO) Transmit Data Buf-
Microchip website (www.microchip.com). fer
2: Some registers and associated bits • 4-Deep FIFO Receive Data Buffer
described in this section may not be avail- • Parity, framing and buffer overrun error detection
able on all devices. Refer to Section 4.0 • Support for 9-bit mode with Address Detect
“Memory Organization” in this data (9th bit = 1)
sheet for device-specific register and bit • Transmit and Receive interrupts
information.
• A separate interrupt for all UART error conditions
The Universal Asynchronous Receiver Transmitter • Loopback mode for diagnostic support
(UART) module is one of the serial I/O modules • Support for Sync and Break characters
available in the dsPIC33FJ32GP202/204 and • Support for automatic baud rate detection
dsPIC33FJ16GP304 device family. The UART is a
• IrDA® encoder and decoder logic
full-duplex asynchronous system that can
communicate with peripheral devices, such as • 16x baud clock output for IrDA® support
personal computers, LIN, RS-232 and RS-485 A simplified block diagram of the UART module is
interfaces. The module also supports a hardware flow shown in Figure 17-1. The UART module consists of
control option with the UxCTS and UxRTS pins and these key hardware elements:
also includes an IrDA® encoder and decoder.
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
IrDA® BCLK
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for infor-
mation on enabling the UART module for receive or transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for infor-
mation on enabling the UART module for receive or transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for infor-
mation on enabling the UART module for transmit operation.
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for infor-
mation on enabling the UART module for transmit operation.
NOTES:
18.0 10-BIT/12-BIT The 12-bit ADC configuration supports all the above
features, except:
ANALOG-TO-DIGITAL
CONVERTER (ADC) • In the 12-bit configuration, conversion speeds of
up to 500 ksps are supported.
Note 1: This data sheet summarizes the features • There is only one sample-and-hold amplifier in the
of the dsPIC33FJ32GP202/204 and 12-bit configuration, so simultaneous sampling of
dsPIC33FJ16GP304 family of devices. It multiple channels is not supported.
is not intended to be a comprehensive Depending on the particular device pinout, the ADC
reference source. To complement the can have up to 13 analog input pins, designated AN0
information in this data sheet, refer to through AN12. In addition, there are two analog input
Section 28. “Analog-to-Digital Con- pins for external voltage reference connections. These
verter (ADC) without DMA” (DS70210) voltage reference inputs can be shared with other ana-
of the “dsPIC33F/PIC24H Family Refer- log input pins.
ence Manual”, which is available on the
Microchip website (www.microchip.com). The actual number of analog input pins and external
voltage reference input configuration will depend on the
2: Some registers and associated bits specific device. Refer to the device data sheet for
described in this section may not be avail- further details.
able on all devices. Refer to Section 4.0
“Memory Organization” in this data A block diagram of the ADC for the
sheet for device-specific register and bit dsPIC33FJ16GP304 and dsPIC33FJ32GP204 devices
information. is shown in Figure 18-1. A block diagram of the ADC for
the dsPIC33FJ32GP202 device is shown in
The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Figure 18-2.
devices have up to 13 Analog-to-Digital Conversion
(ADC) module input channels. 18.2 ADC Initialization
The AD12B bit (AD1CON1<10>) allows each of the
ADC modules to be configured as either a 10-bit, To configure the ADC module:
4-sample-and-hold ADC (default configuration) or a 1. Select port pins as analog inputs
12-bit, 1-sample-and-hold ADC. (AD1PCFGH<15:0> or AD1PCFGL<15:0>).
Note: The ADC module must be disabled before 2. Select voltage reference source to match
the AD12B bit can be modified. expected range on analog inputs
(AD1CON2<15:13>).
18.1 Key Features 3. Select the analog conversion clock to match
desired data rate with processor clock
The 10-bit ADC configuration has the following key (AD1CON3<7:0>).
features: 4. Determine how many sample-and-hold
• Successive Approximation (SAR) conversion channels will be used (AD1CON2<9:8> and
• Conversion speeds of up to 1.1 Msps AD1PCFGH<15:0> or AD1PCFGL<15:0>).
• Up to 13 analog input pins 5. Select the appropriate sample/conversion
sequence (AD1CON1<7:5> and
• External voltage reference input pins
AD1CON3<12:8>).
• Simultaneous sampling of up to four analog input
6. Select the way conversion results are presented
pins
in the buffer (AD1CON1<9:8>).
• Automatic Channel Scan mode
e) Turn on the ADC module (AD1CON1<15>).
• Selectable conversion trigger source
7. Configure ADC interrupt (if required):
• Selectable Buffer Fill modes
a) Clear the AD1IF bit.
• Four result alignment options (signed/unsigned,
b) Select ADC interrupt priority.
fractional/integer)
• Operation during CPU Sleep and Idle modes
• 16-word conversion result buffer
AN0
AN12
S/H0
CHANNEL
SCAN +
CH0SB<4:0>
CH0SA<4:0> -
CH0 CSCNA
AN1
VREF-
CH0NA CH0NB
AN0
VREF+(1) AVDD VREF -(1) AVSS
AN3 S/H1
+
CH123SA CH123SB -
CH1(2)
AN6
AN9
VCFG<2:0> ADC1BUF0
VREFL-
ADC1BUF1
ADC1BUF2
VREFH VREFL
CH123NA CH123NB
SAR ADC
AN1
AN4
S/H2
+ ADC1BUFE
CH123SA CH123SB - ADC1BUFF
CH2(2) AN7
AN10
VREFL-
CH123NA CH123NB
AN2
AN5
S/H3
+
CH123SA CH123SB
-
CH3(2)
AN8
AN11
VREF-
CH123NA CH123NB
Alternate
Input Selection
Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs.
2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.
AN0
AN12
S/H0
CHANNEL
SCAN +
CH0SB<4:0>
CH0SA<4:0> -
CH0 CSCNA
AN1
VREFL-
CH0NA CH0NB
AN0
VREF+(1) AVDD VREF -(1) AVSS
AN3 S/H1
+
CH123SA CH123SB -
CH1(2)
AN9
VCFG<2:0> ADC1BUF0
VREFL-
ADC1BUF1
ADC1BUF2
VREFH VREFL
CH123NA CH123NB
SAR ADC
AN1
AN4
S/H2
+ ADC1BUFE
CH123SA CH123SB - ADC1BUFF
(2)
CH2
AN10
VREFL-
CH123NA CH123NB
AN2
AN5
S/H3
+
CH123SA CH123SB
-
CH3(2)
AN11
VREFL-
CH123NA CH123NB
Alternate
Input Selection
Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs.
2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.
AD1CON3<15>
ADC Internal
RC Clock(2) 0
TAD
AD1CON3<5:0> 1
ADC Conversion
TCY Clock Multiplier
TOSC(1) X2
1, 2, 3, 4, 5,..., 64
Note 1: Refer to Figure 8-2 for the derivation of FOSC when the PLL is enabled. If the PLL is not used, FOSC is equal
to the clock frequency. TOSC = 1/FOSC.
2: See the ADC Electrical Characteristics for the exact RC clock value.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
ADREF+ ADREF-
000 AVDD AVSS
001 External VREF+ AVSS
010 AVDD External VREF-
011 External VREF+ External VREF-
1xx AVDD Avss
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
If AD12B = 0:
11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11
10 = Reserved
01 = CH1, CH2, CH3 negative input is VREF-
00 = CH1, CH2, CH3 negative input is VREF-
If AD12B = 0:
11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11
10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8
01 = CH1, CH2, CH3 negative input is VREF-
00 = CH1, CH2, CH3 negative input is VREF-
bit 8 CH123SB: Channel 1, 2, 3 Positive Input Select for Sample B bit
If AD12B = 1:
1 = Reserved
0 = Reserved
If AD12B = 0:
1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
bit 7-3 Unimplemented: Read as ‘0’
If AD12B = 0:
11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11
10 = Reserved
01 = CH1, CH2, CH3 negative input is VREF-
00 = CH1, CH2, CH3 negative input is VREF-
If AD12B = 0:
11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11
10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8
01 = CH1, CH2, CH3 negative input is VREF-
00 = CH1, CH2, CH3 negative input is VREF-
bit 0 CH123SA: Channel 1, 2, 3 Positive Input Select for Sample A bit
If AD12B = 1:
1 = Reserved
0 = Reserved
If AD12B = 0:
1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: On devices without 13 analog inputs, all AD1CSSL bits can be selected by the user application. However,
inputs selected for scan without a corresponding input on device converts VREFL.
2: CSSx = ANx, where x = 0 through 12.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: On devices without 13 analog inputs, all PCFG bits are R/W by user software. However, the PCFG bits are
ignored on ports without a corresponding input on device.
2: PCFGx = ANx, where x = 0 through 12.
3: The PCFGx bits have no effect if the ADC module is disabled by setting ADxMD bit in the PMDx Register.
In this case, all port pins multiplexed with ANx will be in Digital mode.
NOTES:
3.3V
dsPIC33F
VDD
VCAP/VDDCORE
CEFC
VSS
Sleep/Idle
WDTPRE WDTPOST<3:0>
SWDTEN WDT
FWDTEN Wake-up
RS RS 1
Prescaler Postscaler
LPRC Clock (divide by N1) (divide by N2) WDT
0 Reset
CLRWDT Instruction
19.5 JTAG Interface peripherals) on a single chip. This feature helps protect
individual Intellectual Property in collaborative system
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 designs.
devices implement a JTAG interface, which supports
boundary scan device testing, as well as in-circuit When coupled with software encryption libraries, Code-
programming. Detailed information on this interface will Guard™ Security can be used to securely update Flash
be provided in future revisions of the document. even when multiple IPs reside on the single chip.
The code protection features are controlled by the
19.6 Code Protection and Configuration registers: FBS and FGS. The Secure
CodeGuard™ Security segment and RAM is not implemented.
Note: Refer to “CodeGuard™ Security
The dsPIC33FJ32GP202/204 and
Reference Manual” (DS70180) for further
dsPIC33FJ16GP304 product families offer the
information on usage, configuration and
intermediate implementation of CodeGuard™ Security.
operation of CodeGuard Security.
CodeGuard Security enables multiple parties to
securely share resources (memory, interrupts and
TABLE 19-3: CODE FLASH SECURITY TABLE 19-4: CODE FLASH SECURITY
SEGMENT SIZES FOR SEGMENT SIZES FOR
32 KBYTE DEVICES 16 KBYTE DEVICES
CONFIG BITS CONFIG BITS
000000h 000000h
VS = 256 IW 0001FEh VS = 256 IW 0001FEh
000200h 000200h
BSS<2:0> = x11 0007FEh BSS<2:0> = x11 0007FEh
000800h 000800h
001FFEh 001FFEh
0K 002000h 0K 002000h
GS = 11008 IW 003FFEh GS = 5376 IW
004000h
0057FEh 002BFEh
000000h 000000h
VS = 256 IW 0001FEh VS = 256 IW 0001FEh
000200h 000200h
BS = 768 IW 0007FEh BS = 768 IW 0007FEh
BSS<2:0> = x10 000800h BSS<2:0> = x10 000800h
001FFEh 001FFEh
002000h 002000h
256 003FFEh 256
004000h
GS = 10240 IW GS = 4608 IW
0057FEh 002BFEh
000000h 000000h
VS = 256 IW 0001FEh VS = 256 IW 0001FEh
000200h 000200h
BSS<2:0> = x01 BS = 3840 IW 0007FEh BSS<2:0> = x01 BS = 3840 IW 0007FEh
000800h 000800h
001FFEh 001FFEh
768 002000h 768 002000h
003FFEh
004000h
GS = 7168 IW GS = 1536 IW
0057FEh 002BFEh
000000h 000000h
VS = 256 IW 0001FEh VS = 256 IW 0001FEh
000200h 000200h
BS = 7936 IW 0007FEh BS = 5376 IW 0007FEh
BSS<2:0> = x00 000800h BSS<2:0> = x00 000800h
001FFEh 001FFEh
1792 002000h 1792 002000h
003FFEh
004000h
GS = 3072 IW
0057FEh 002BFEh
NOTES:
Most instructions are a single word. Certain (unconditional/computed branch), indirect CALL/GOTO,
double-word instructions are designed to provide all of all table reads and writes and RETURN/RETFIE
the required information in these 48 bits. In the second instructions, which are single-word instructions but take
word, the 8 MSbs are ‘0’s. If this second word is two or three cycles. Certain instructions that involve skip-
executed as an instruction (by itself), it will execute as ping over the subsequent instruction require either two
a NOP. The double-word instructions execute in two or three cycles if the skip is performed, depending on
instruction cycles. whether the instruction being skipped is a single-word or
Most single-word instructions are executed in a single two-word instruction. Moreover, double-word moves
instruction cycle, unless a conditional test is true, or the require two cycles.
program counter is changed as a result of the Note: For more details on the instruction set,
instruction. In these cases, the execution takes two refer to the “dsPIC30F/33F Programmer’s
instruction cycles with the additional instruction cycle(s) Reference Manual” (DS70157).
executed as a NOP. Notable exceptions are the BRA
Wm*Wm Multiplicand and Multiplier working register pair for Square instructions
{W4 * W4,W5 * W5,W6 * W6,W7 * W7}
Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions
{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}
Wn One of 16 working registers {W0..W15}
Wnd One of 16 destination working registers {W0...W15}
Wns One of 16 source working registers {W0...W15}
WREG W0 (working register used in file register instructions)
Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso Source W register
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx X data space prefetch address register for DSP instructions
{[W8]+ = 6, [W8]+ = 4, [W8]+ = 2, [W8], [W8]- = 6, [W8]- = 4, [W8]- = 2,
[W9]+ = 6, [W9]+ = 4, [W9]+ = 2, [W9], [W9]- = 6, [W9]- = 4, [W9]- = 2,
[W9 + W12], none}
Wxd X data space prefetch destination register for DSP instructions {W4...W7}
Wy Y data space prefetch address register for DSP instructions
{[W10]+ = 6, [W10]+ = 4, [W10]+ = 2, [W10], [W10]- = 6, [W10]- = 4, [W10]- = 2,
[W11]+ = 6, [W11]+ = 4, [W11]+ = 2, [W11], [W11]- = 6, [W11]- = 4, [W11]- = 2,
[W11 + W12], none}
Wyd Y data space prefetch destination register for DSP instructions {W4...W7}
21.7 MPLAB SIM Software Simulator 21.9 MPLAB ICD 3 In-Circuit Debugger
The MPLAB SIM Software Simulator allows code
System
development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro-
ing the PIC MCUs and dsPIC® DSCs on an instruction chip's most cost effective high-speed hardware
level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig-
examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU)
a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon-
logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet easy-
buffer and logic analyzer display extend the power of to-use graphical user interface of MPLAB Integrated
the simulator to record and track program execution, Development Environment (IDE).
actions on I/O, most peripherals and internal registers.
The MPLAB ICD 3 In-Circuit Debugger probe is con-
The MPLAB SIM Software Simulator fully supports nected to the design engineer's PC using a high-speed
symbolic debugging using the MPLAB C Compilers, USB 2.0 interface and is connected to the target with a
and the MPASM and MPLAB Assemblers. The soft- connector compatible with the MPLAB ICD 2 or MPLAB
ware simulator offers the flexibility to develop and REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
debug code outside of the hardware laboratory envi- MPLAB ICD 2 headers.
ronment, making it an excellent, economical software
development tool. 21.10 PICkit 3 In-Circuit Debugger/
Programmer and
21.8 MPLAB REAL ICE In-Circuit
PICkit 3 Debug Express
Emulator System
The MPLAB PICkit 3 allows debugging and program-
MPLAB REAL ICE In-Circuit Emulator System is ming of PIC® and dsPIC® Flash microcontrollers at a
Microchip’s next generation high-speed emulator for most affordable price point using the powerful graphical
Microchip Flash DSC and MCU devices. It debugs and user interface of the MPLAB Integrated Development
programs PIC® Flash MCUs and dsPIC® Flash DSCs Environment (IDE). The MPLAB PICkit 3 is connected
with the easy-to-use, powerful graphical user interface of to the design engineer's PC using a full speed USB
the MPLAB Integrated Development Environment (IDE), interface and can be connected to the target via an
included with each kit. Microchip debug (RJ-11) connector (compatible with
The emulator is connected to the design engineer’s PC MPLAB ICD 3 and MPLAB REAL ICE). The connector
using a high-speed USB 2.0 interface and is connected uses two device I/O pins and the reset line to imple-
to the target with either a connector compatible with in- ment in-circuit debugging and In-Circuit Serial Pro-
circuit debugger systems (RJ11) or with the new high- gramming™.
speed, noise tolerant, Low-Voltage Differential Signal The PICkit 3 Debug Express include the PICkit 3, demo
(LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM
The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and
downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software.
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers signifi-
cant advantages over competitive emulators including
low-cost, full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, a rugge-
dized probe interface and long (up to three meters) inter-
connection cables.
Note 1: Stresses above those listed under “Absolute Maximum Ratings” can cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods can affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 22-2).
3: Exceptions are CLKOUT, which is able to sink/source 25 mA, and the VREF+, VREF-, SCLx, SDAx, PGECx
and PGEDx pins, which are able to sink/source 12 mA.
4: Refer to the “Pin Diagrams” section for 5V tolerant pins.
22.1 DC Characteristics
Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2
VDD/2
RL Pin CL
VSS
CL
Pin RL = 464
CL = 50 pF for all pins except OSC2
VSS 15 pF for OSC2 output
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
OS20
OS30 OS30 OS31 OS31
OS25
CLKO
OS41 OS40
I/O Pin
(Input)
DI35
DI40
FIGURE 22-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING CHARACTERISTICS
VDD SY12
MCLR
Internal SY10
POR
SY11
PWRT
Time-out
SY30
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
SY20
SY13
SY13
I/O Pins
SY35
FSCM
Delay
TABLE 22-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
Symbol Characteristic Min Typ(2) Max Units Conditions
No.
SY10 TMCL MCLR Pulse-Width (low)(1) 2 — — s -40°C to +85°C
SY11 TPWRT Power-up Timer Period — 2 — ms -40°C to +85°C
4 User programmable
8
16
32
64
128
SY12 TPOR Power-on Reset Delay(3) 3 10 30 s -40°C to +85°C
SY13 TIOZ I/O High-Impedance from 0.68 0.72 1.2 s —
MCLR Low or Watchdog
Timer Reset(1)
SY20 TWDT1 Watchdog Timer Time-out — — — ms See Section 19.4 “Watchdog
Period(1) Timer (WDT)” and LPRC parameter
F21a (Table 22-19).
SY30 TOST Oscillator Start-up Time — 1024 — — TOSC = OSC1 period
TOSC
SY35 TFSCM Fail-Safe Clock Monitor — 500 900 s -40°C to +85°C
Delay(1)
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: These parameters are characterized, but are not tested in manufacturing.
TxCK
Tx10 Tx11
Tx15 Tx20
OS60
TMRx
ICx
IC10 IC11
IC15
OCx
(Output Compare
or PWM Mode) OC11 OC10
OC20
OCFA/OCFB
OC15
OCx
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SP31 SP30
SP40 SP41
SCKX
(CKP = 1)
SP35
SP20 SP21
SP40 SP30,SP31
SP41
SSX
SP50 SP52
SCKX
(CKP = 0)
SP71 SP70
SP73 SP72
SCKX
(CKP = 1)
SP72 SP73
SP35
SP30,SP31 SP51
SP41
SP40
Note: Refer to Figure 22-1 for load conditions.
SP50 SP52
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SP35
SP72 SP73
SP30,SP31 SP51
SDIx
SDI
MSb In Bit 14 - - - -1 LSb In
SP41
SP40
FIGURE 22-13: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31 IM34
IM30 IM33
SDAx
Start Stop
Condition Condition
SDAx
Out
FIGURE 22-15: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS31 IS34
IS30 IS33
SDAx
Start Stop
Condition Condition
SDAx
Out
AD50
ADCLK
Instruction
Execution Set SAMP Clear SAMP
SAMP
AD61
AD60
TSAMP AD55
DONE
AD1IF
1 2 3 4 5 6 7 8 9
AD50
ADCLK
Instruction
Execution Set SAMP Clear SAMP
SAMP
AD61
AD60
DONE
AD1IF
Buffer(0)
Buffer(1)
1 2 3 4 5 6 7 8 5 6 7 8
FIGURE 22-19: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01,
SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)
AD50
ADCLK
Instruction
Set ADON
Execution
SAMP
TSAMP AD55 AD55 TSAMP AD55
AD1IF
DONE
1 2 3 4 5 6 7 3 4 5 6 8
2 – Sampling starts after discharge period. TSAMP is described in 6 – One TAD for end of conversion.
Section 28. “10/12-bit ADC without DMA” in the
“dsPIC33F/PIC24H Family Reference Manual”. 7 – Begin conversion of next channel.
4 – Convert bit 8.
Note 1: Stresses above those listed under “Absolute Maximum Ratings” can cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods can affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 23-2).
3: Unlike devices at 125°C and below, the specifications in this section also apply to the CLKOUT, VREF+,
VREF-, SCLx, SDAx, PGCx, and PGDx pins.
4: AEC-Q100 reliability testing for devices intended to operate at 150°C is 1,000 hours. Any design in which
the total operating time from 125°C to 150°C will be greater than 1,000 hours is not warranted without prior
written approval from Microchip Technology Inc.
5: Refer to the “Pin Diagrams” section for 5V tolerant pins.
Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2
VDD/2
RL Pin CL
VSS
CL
Pin RL = 464
CL = 50 pF for all pins except OSC2
VSS 15 pF for OSC2 output
Param
Symbol Characteristic Min Typ Max Units Conditions
No.
HOS53 DCLK CLKO Stability (Jitter)(1) -5 0.5 5 % Measured over 100 ms
period
Note 1: These parameters are characterized, but are not tested in manufacturing.
Param
Symbol Characteristic(1) Min Typ Max Units Conditions
No.
HSP35 TscH2doV, SDOx Data Output Valid after — 10 25 ns —
TscL2doV SCKx Edge
HSP40 TdiV2scH, Setup Time of SDIx Data Input 28 — — ns —
TdiV2scL to SCKx Edge
HSP41 TscH2diL, Hold Time of SDIx Data Input 35 — — ns —
TscL2diL to SCKx Edge
Note 1: These parameters are characterized but not tested in manufacturing.
Param
Symbol Characteristic(1) Min Typ Max Units Conditions
No.
HSP35 TscH2doV, SDOx Data Output Valid after — 10 25 ns —
TscL2doV SCKx Edge
HSP36 TdoV2sc, SDOx Data Output Setup to 35 — — ns —
TdoV2scL First SCKx Edge
HSP40 TdiV2scH, Setup Time of SDIx Data Input 28 — — ns —
TdiV2scL to SCKx Edge
HSP41 TscH2diL, Hold Time of SDIx Data Input 35 — — ns —
TscL2diL to SCKx Edge
Note 1: These parameters are characterized but not tested in manufacturing.
Param
Symbol Characteristic(1) Min Typ Max Units Conditions
No.
HSP35 TscH2doV, SDOx Data Output Valid after — — 35 ns —
TscL2doV SCKx Edge
HSP40 TdiV2scH, Setup Time of SDIx Data Input 25 — — ns —
TdiV2scL to SCKx Edge
HSP41 TscH2diL, Hold Time of SDIx Data Input to 25 — — ns —
TscL2diL SCKx Edge
HSP51 TssH2doZ SSx to SDOx Output 15 — 55 ns See Note 2
High-Impedance
Note 1: These parameters are characterized but not tested in manufacturing.
2: Assumes 50 pF load on all SPIx pins.
Param
Symbol Characteristic(1) Min Typ Max Units Conditions
No.
HSP35 TscH2doV, SDOx Data Output Valid after — — 35 ns —
TscL2doV SCKx Edge
HSP40 TdiV2scH, Setup Time of SDIx Data Input 25 — — ns —
TdiV2scL to SCKx Edge
HSP41 TscH2diL, Hold Time of SDIx Data Input 25 — — ns —
TscL2diL to SCKx Edge
HSP51 TssH2doZ SSx to SDOX Output 15 — 55 ns See Note 2
High-Impedance
HSP60 TssL2doV SDOx Data Output Valid after — — 55 ns —
SSx Edge
Note 1: These parameters are characterized but not tested in manufacturing.
2: Assumes 50 pF load on all SPIx pins.
Param
Symbol Characteristic Min Typ Max Units Conditions
No.
Reference Inputs
HAD08 IREF Current Drain — 250 600 A ADC operating, See Note 1
— — 50 A ADC off, See Note 1
Note 1: These parameters are not characterized or tested in manufacturing.
2: These parameters are characterized, but are not tested in manufacturing.
Param
Symbol Characteristic Min Typ Max Units Conditions
No.
ADC Accuracy (12-bit Mode) – Measurements with External VREF+/VREF-(1)
HAD20a Nr Resolution 12 data bits bits —
HAD21a INL Integral Nonlinearity -2 — +2 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
HAD22a DNL Differential Nonlinearity > -1 — <1 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
HAD23a GERR Gain Error -2 — 10 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
HAD24a EOFF Offset Error -3 — 5 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
ADC Accuracy (12-bit Mode) – Measurements with Internal VREF+/VREF-(1)
HAD20a Nr Resolution 12 data bits bits —
HAD21a INL Integral Nonlinearity -2 — +2 LSb VINL = AVSS = 0V, AVDD = 3.6V
HAD22a DNL Differential Nonlinearity > -1 — <1 LSb VINL = AVSS = 0V, AVDD = 3.6V
HAD23a GERR Gain Error 2 — 20 LSb VINL = AVSS = 0V, AVDD = 3.6V
HAD24a EOFF Offset Error 2 — 10 LSb VINL = AVSS = 0V, AVDD = 3.6V
Dynamic Performance (12-bit Mode)(2)
HAD33a FNYQ Input Signal Bandwidth — — 200 kHz —
Note 1: These parameters are characterized, but are tested at 20 ksps only.
2: These parameters are characterized by similarity, but are not tested in manufacturing.
Param
Symbol Characteristic Min Typ Max Units Conditions
No.
ADC Accuracy (10-bit Mode) – Measurements with External VREF+/VREF-(1)
HAD20b Nr Resolution 10 data bits bits —
HAD21b INL Integral Nonlinearity -3 — 3 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
HAD22b DNL Differential Nonlinearity > -1 — <1 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
HAD23b GERR Gain Error -5 — 6 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
HAD24b EOFF Offset Error -1 — 5 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
ADC Accuracy (10-bit Mode) – Measurements with Internal VREF+/VREF-(1)
HAD20b Nr Resolution 10 data bits bits —
HAD21b INL Integral Nonlinearity -2 — 2 LSb VINL = AVSS = 0V, AVDD = 3.6V
HAD22b DNL Differential Nonlinearity > -1 — <1 LSb VINL = AVSS = 0V, AVDD = 3.6V
HAD23b GERR Gain Error -5 — 15 LSb VINL = AVSS = 0V, AVDD = 3.6V
HAD24b EOFF Offset Error -1.5 — 7 LSb VINL = AVSS = 0V, AVDD = 3.6V
Dynamic Performance (10-bit Mode)(2)
HAD33b FNYQ Input Signal Bandwidth — — 400 kHz —
Note 1: These parameters are characterized, but are tested at 20 ksps only.
2: These parameters are characterized by similarity, but are not tested in manufacturing.
Param
Symbol Characteristic Min Typ Max Units Conditions
No.
Clock Parameters
HAD50 TAD ADC Clock Period(1) 147 — — ns —
Conversion Rate
HAD56 FCNV Throughput Rate(1) — — 400 Ksps —
Note 1: These parameters are characterized but not tested in manufacturing.
Param
Symbol Characteristic Min Typ Max Units Conditions
No.
Clock Parameters
HAD50 TAD ADC Clock Period(1) 104 — — ns —
Conversion Rate
HAD56 FCNV Throughput Rate(1) — — 800 Ksps —
Note 1: These parameters are characterized but not tested in manufacturing.
NOTES:
XXXXXXXXXXXXXXXXXXXX dsPIC33FJ32GP
XXXXXXXXXXXXXXXXXXXX 202-E/SO e3
XXXXXXXXXXXXXXXXXXXX 0730235
YYWWNNN
XXXXXXXX 33FJ32GP
XXXXXXXX 202E/MM e3
YYWWNNN 0730235
XXXXXXXXXX dsPIC33FJGP
XXXXXXXXXX MC204-E/ML e3
XXXXXXXXXX 0730235
YYWWNNN
XXXXXXXXXX dsPIC33FJ
XXXXXXXXXX 32GP204
XXXXXXXXXX -E/PT e3
YYWWNNN 0730235
Note: If the full Microchip part number cannot be marked on one line, it is carried over to the next
line, thus limiting the number of available characters for customer-specific information.
28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
NOTE 1
E1
1 2 3
A A2
L c
A1 b1
b e eB
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 28
Pitch e .100 BSC
Top to Seating Plane A – – .200
Molded Package Thickness A2 .120 .135 .150
Base to Seating Plane A1 .015 – –
Shoulder to Shoulder Width E .290 .310 .335
Molded Package Width E1 .240 .285 .295
Overall Length D 1.345 1.365 1.400
Tip to Seating Plane L .110 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .050 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB – – .430
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
D
N
E
E1
NOTE 1
1 2 3
e
b
h
α
h
φ c
A A2
L
A1 L1 β
Units MILLMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 28
Pitch e 1.27 BSC
Overall Height A – – 2.65
Molded Package Thickness A2 2.05 – –
Standoff § A1 0.10 – 0.30
Overall Width E 10.30 BSC
Molded Package Width E1 7.50 BSC
Overall Length D 17.90 BSC
Chamfer (optional) h 0.25 – 0.75
Foot Length L 0.40 – 1.27
Footprint L1 1.40 REF
Foot Angle Top φ 0° – 8°
Lead Thickness c 0.18 – 0.33
Lead Width b 0.31 – 0.51
Mold Draft Angle Top α 5° – 15°
Mold Draft Angle Bottom β 5° – 15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-052B
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PAD
E2
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2 2
1 1 K
N N
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NOTE 1 BOTTOM VIEW
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A3 A1
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44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D D2
EXPOSED
PAD
E2
b
2 2
1 1
N N K
NOTE 1 L
A3 A1
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 44
Pitch e 0.65 BSC
Overall Height A 0.80 0.90 1.00
Standoff A1 0.00 0.02 0.05
Contact Thickness A3 0.20 REF
Overall Width E 8.00 BSC
Exposed Pad Width E2 6.30 6.45 6.80
Overall Length D 8.00 BSC
Exposed Pad Length D2 6.30 6.45 6.80
Contact Width b 0.25 0.30 0.38
Contact Length L 0.30 0.40 0.50
Contact-to-Exposed Pad K 0.20 – –
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
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44-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
E
e
E1
N
b
NOTE 1 1 2 3
NOTE 2
A α
c φ
β A1 A2
L L1
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Leads N 44
Lead Pitch e 0.80 BSC
Overall Height A – – 1.20
Molded Package Thickness A2 0.95 1.00 1.05
Standoff A1 0.05 – 0.15
Foot Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle φ 0° 3.5° 7°
Overall Width E 12.00 BSC
Overall Length D 12.00 BSC
Molded Package Width E1 10.00 BSC
Molded Package Length D1 10.00 BSC
Lead Thickness c 0.09 – 0.20
Lead Width b 0.30 0.37 0.45
Mold Draft Angle Top α 11° 12° 13°
Mold Draft Angle Bottom β 11° 12° 13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-076B
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NOTES:
Added Note 1 to all pin diagrams, which references RPn pin usage by
remappable peripherals (see “Pin Diagrams”).
Section 1.0 “Device Overview” Changed PORTA pin name from RA15 to RA10 (see Table 1-1).
Section 3.0 “Memory Organization” Added SFR definitions (ACCAL, ACCAH, ACCAU, ACCBL, ACCBH, and
ACCBU) to the CPU Core Register Map (see Table 3-1).
Updated Reset values for the following SFRs: IPC1, IPC3-IPC5, IPC7,
IPC16 and INTTREG (see Table 3-4).
Updated the Reset value for CLKDIV in the System Control Register Map
(see Table 3-20).
Section 6.0 “Resets” Entire section was replaced to maintain consistency with other dsPIC33F
data sheets.
Section 7.0 “Oscillator Removed the first sentence of the third clock source item (External Clock) in
Configuration” Section 7.1.1.2 “Primary”.
Updated the default bit values for DOZE and FRCDIV in the Clock Divisor
Register (see Register 7-2).
Added the center frequency in the OSCTUN register for the FRC Tuning bits
(TUN<5:0>) value 011111 and updated the center frequency for bits value
011110 (see Register 7-4).
Section 8.0 “Power-Saving Added the following two registers:
Features” • PMD1: Peripheral Module Disable Control Register 1
• PMD2: Peripheral Module Disable Control Register 2
Section 9.0 “I/O Ports” Added paragraph and Table 9-1 to Section 9.1.1 “Open-Drain
Configuration”, which provides details on I/O pins and their functionality.
Removed the following sections, which are now available in the related
section of the dsPIC33F/PIC24H Family Reference Manual:
• 9.4.2 “Available Peripherals”
• 9.4.3.3 “Mapping”
• 9.4.5 “Considerations for Peripheral Pin Selection”
Section 13.0 “Output Compare” Replaced sections 13.1, 13.2 and 13.3 and related figures and tables with
entirely new content.
Removed IrDA references and Note 1, and updated the bit and bit value
descriptions for UTXINV (UxSTA<14>) in the UARTx Status and Control
Register (see Register 16-2).
Section 17.0 “10-bit/12-bit Analog- Removed Equation 17-1: ADC Conversion Clock Period and Figure 17-2:
to-Digital Converter (ADC)” ADC Transfer Function (10-Bit Example).
Added Note 2 to Figure 17-3: ADC Conversion Clock Period Block Diagram.
Added FICD register content (BKBUG, COE, JTAGEN, and ICS<1:0> to the
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Configuration Bits
Description (see Table 18-2).
Removed the words “if enabled” from the second sentence in the fifth
paragraph of Section 18.3 “BOR: Brown-Out Reset”.
Section 21.0 “Electrical Updated Max MIPS value for -40ºC to +125ºC temperature range in
Characteristics” Operating MIPS vs. Voltage (see Table 21-1).
Added Note 4 (reference to new table containing digital-only and analog pin
information to I/O Pin Input Specifications (see Table 21-9).
Updated Typ, Min, and Max values for Program Memory parameters D136,
D137, and D138 (see Table 21-12).
Updated Max value for Internal RC Accuracy parameter F21 for -40°C TA
+125°C condition and added Note 2 (see Table 21-19).
Removed all values for Reset, Watchdog Timer, Oscillator Start-up Timer,
and Power-up Timer parameter SY20 and updated conditions, which now
refers to Section 18.4 “Watchdog Timer (WDT)” and LPRC parameter
F21a (see Table 21-21).
Updated Min and Typ values for parameters AD60, AD61, AD62 and AD63
and removed Note 3 (see Table 21-37).
Updated Min and Typ values for parameters AD60, AD61, AD62 and AD63
and removed Note 3 (see Table 21-38).
Updated typical values for Operating Current (IDD) and added Note 3 in
Table 22-5.
Updated typical and maximum values for Idle Current (IIDLE): Core OFF
Clock ON Base Current and added Note 3 in Table 22-6.
Updated typical and maximum values for Power Down Current (IPD) and
added Note 5 in Table 22-7.
Updated typical and maximum values for Doze Current (IDOZE) and added
Note 2 in Table 22-8.
Updated typical value for parameter AD08 (ADC in operation) and added
Notes 2 and 3 in Table 22-34.
Updated the Min value for parameter DI35 (see Table 22-20).
INDEX
A CPU Clocking System ...................................................... 100
Options ..................................................................... 100
A/D Converter ................................................................... 169
Initialization ............................................................... 169 Selection................................................................... 100
Key Features............................................................. 169 Customer Change Notification Service............................. 267
Customer Notification Service .......................................... 267
AC Characteristics .................................................... 212, 240
ADC Module.............................................................. 243 Customer Support............................................................. 267
ADC Module (10-bit Mode) ....................................... 244 D
ADC Module (12-bit Mode) ....................................... 243
Data Accumulators and Adder/Subtractor .......................... 27
Internal RC Accuracy ................................................ 214
Data Space Write Saturation ...................................... 29
Load Conditions ................................................ 212, 240
Overflow and Saturation ............................................. 27
ADC Module
Round Logic ............................................................... 28
ADC11 Register Map ...................................... 41, 43, 44
Write Back .................................................................. 28
Alternate.............................................................................. 71
Data Address Space........................................................... 33
Alternate Interrupt Vector Table .......................................... 71
Alignment.................................................................... 33
Alternate Interrupt Vector Table (AIVT) .............................. 71
Memory Map for dsPIC33F Devices with 8 KBs RAM 34
Arithmetic Logic Unit (ALU)................................................. 25
Near Data Space ........................................................ 33
Assembler
Software Stack ........................................................... 47
MPASM Assembler................................................... 200
Width .......................................................................... 33
B DC Characteristics............................................................ 204
Doze Current (IDOZE)................................................ 239
Barrel Shifter ....................................................................... 29
High Temperature..................................................... 238
Bit-Reversed Addressing .................................................... 50
I/O Pin Input Specifications ...................................... 209
Example ...................................................................... 51
I/O Pin Output........................................................... 239
Implementation ........................................................... 50
I/O Pin Output Specifications.................................... 210
Sequence Table (16-Entry)......................................... 51
Idle Current (IDOZE) .................................................. 208
Block Diagrams
Idle Current (IIDLE) .................................................... 207
16-bit Timer1 Module ................................................ 135
Operating Current (IDD) ............................................ 206
A/D Module ....................................................... 170, 171
Operating MIPS vs. Voltage ..................................... 238
Connections for On-Chip Voltage Regulator............. 186
Power-Down Current (IPD)........................................ 208
Device Clock ....................................................... 99, 101
Power-down Current (IPD) ........................................ 238
DSP Engine ................................................................ 26
Program Memory.............................................. 211, 239
dsPIC33F .................................................................... 12
Temperature and Voltage......................................... 238
dsPIC33F CPU Core................................................... 20
Temperature and Voltage Specifications.................. 205
Input Capture ............................................................ 143
Thermal Operating Conditions.................................. 238
Output Compare ....................................................... 145
Development Support ....................................................... 199
PLL............................................................................ 101
DSP Engine ........................................................................ 25
Reset System.............................................................. 63
Multiplier ..................................................................... 27
Shared Port Structure ............................................... 113
SPI ............................................................................ 149 E
Timer2 (16-bit) .......................................................... 139
Electrical Characteristics .................................................. 203
Timer2/3 (32-bit) ....................................................... 138
AC..................................................................... 212, 240
UART ........................................................................ 163
Equations
Watchdog Timer (WDT) ............................................ 187
Device Operating Frequency.................................... 100
C Errata .................................................................................... 9
C Compilers F
MPLAB C18 .............................................................. 200
Flash Program Memory ...................................................... 57
Clock Switching................................................................. 107
Control Registers........................................................ 58
Enabling .................................................................... 107
Operations .................................................................. 58
Sequence.................................................................. 107
Programming Algorithm .............................................. 61
Code Examples
RTSP Operation ......................................................... 58
Erasing a Program Memory Page............................... 61
Table Instructions ....................................................... 57
Initiating a Programming Sequence............................ 62
Flexible Configuration ....................................................... 183
Loading Write Buffers ................................................. 62
Port Write/Read ........................................................ 114 H
PWRSAV Instruction Syntax..................................... 109
High Temperature Electrical Characteristics .................... 237
Code Protection ........................................................ 183, 188
Configuration Bits.............................................................. 183 I
Description (Table).................................................... 184 I/O Ports ........................................................................... 113
Configuration Register Map .............................................. 183 Parallel I/O (PIO) ...................................................... 113
Configuring Analog Port Pins ............................................ 114 Write/Read Timing.................................................... 114
CPU I2C
Control Register .......................................................... 22 Operating Modes ...................................................... 155
OSCCON (Oscillator Control) ................................... 102 Timer1, 2, 3, 4, 5, 6, 7, 8, 9 External Clock .............. 218
OSCTUN (FRC Oscillator Tuning) ............................ 106 Timing Requirements
PLLFBD (PLL Feedback Divisor).............................. 105 ADC Conversion (10-bit mode) ................................ 245
PMD1 (Peripheral Module Disable Control Register 1) .. ADC Conversion (12-bit Mode) ................................ 245
111 CLKO and I/O ........................................................... 215
PMD2 (Peripheral Module Disable Control Register 2) .. External Clock .......................................................... 213
112 Input Capture............................................................ 220
RCON (Reset Control) ................................................ 64 SPIx Master Mode (CKE = 0) ................................... 241
SPIxCON1 (SPIx Control 1)...................................... 151 SPIx Module Master Mode (CKE = 1) ...................... 241
SPIxCON2 (SPIx Control 2)...................................... 153 SPIx Module Slave Mode (CKE = 0) ........................ 242
SPIxSTAT (SPIx Status and Control) ....................... 150 SPIx Module Slave Mode (CKE = 1) ........................ 242
SR (CPU Status)................................................... 22, 76 Timing Specifications
T1CON (Timer1 Control)........................................... 136 10-bit A/D Conversion Requirements ....................... 236
TxCON (T2CON, T4CON, T6CON or T8CON Control) .. 12-bit A/D Conversion Requirements ....................... 234
140 I2Cx Bus Data Requirements (Master Mode)........... 228
TyCON (T3CON, T5CON, T7CON or T9CON Control) .. I2Cx Bus Data Requirements (Slave Mode)............. 230
141 Output Compare Requirements................................ 220
UxMODE (UARTx Mode).......................................... 164 PLL Clock ......................................................... 214, 240
UxSTA (UARTx Status and Control)......................... 166 Reset, Watchdog Timer, Oscillator Start-up Timer, Pow-
Reset er-up Timer and Brown-out Reset Requirements...
Illegal Opcode ....................................................... 63, 70 217
Trap Conflict.......................................................... 69, 70 Simple OC/PWM Mode Requirements ..................... 221
Uninitialized W Register........................................ 63, 70 SPIx Master Mode (CKE = 0) Requirements............ 222
Reset Sequence ................................................................. 71 SPIx Master Mode (CKE = 1) Requirements............ 223
Resets ................................................................................. 63 SPIx Slave Mode (CKE = 0) Requirements.............. 224
SPIx Slave Mode (CKE = 1) Requirements.............. 226
S Timer1 External Clock Requirements ....................... 218
Serial Peripheral Interface (SPI) ....................................... 149 Timer2, Timer4, Timer6 and Timer8 External Clock Re-
Software Reset Instruction (SWR) ...................................... 69 quirements........................................................ 219
Software Simulator (MPLAB SIM)..................................... 201 Timer3, Timer5, Timer7 and Timer9 External Clock Re-
Software Stack Pointer, Frame Pointer quirements........................................................ 219
CALL Stack Frame...................................................... 47
Special Features of the CPU ............................................ 183 U
SPI Module UART Module
SPI1 Register Map...................................................... 40 UART1 Register Map ................................................. 40
Symbols Used in Opcode Descriptions............................. 192 Using the RCON Status Bits............................................... 70
System Control
Register Map............................................................... 46 V
Voltage Regulator (On-Chip) ............................................ 186
T
Temperature and Voltage Specifications W
AC ..................................................................... 212, 240 Watchdog Time-out Reset (WDTR).................................... 69
Timer1 ............................................................................... 135 Watchdog Timer (WDT)............................................ 183, 187
Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ..................... 137 Programming Considerations ................................... 187
Timing Characteristics WWW Address ................................................................. 267
CLKO and I/O ........................................................... 215 WWW, On-Line Support ....................................................... 9
Timing Diagrams
10-bit A/D Conversion............................................... 235
10-bit A/D Conversion (CHPS = 01, SIMSAM = 0, ASAM
= 0, SSRC = 000) ............................................. 235
12-bit A/D Conversion (ASAM = 0, SSRC = 000) ..... 234
Brown-out Situations................................................... 69
External Clock........................................................... 213
I2Cx Bus Data (Master Mode) .................................. 227
I2Cx Bus Data (Slave Mode) .................................... 229
I2Cx Bus Start/Stop Bits (Master Mode) ................... 227
I2Cx Bus Start/Stop Bits (Slave Mode) ..................... 229
Input Capture (CAPx)................................................ 220
OC/PWM................................................................... 221
Output Compare (OCx)............................................. 220
Reset, Watchdog Timer, Oscillator Start-up Timer and
Power-up Timer ................................................ 216
SPIx Master Mode (CKE = 0) ................................... 222
SPIx Master Mode (CKE = 1) ................................... 223
SPIx Slave Mode (CKE = 0) ..................................... 224
SPIx Slave Mode (CKE = 1) ..................................... 225
NOTES:
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