AMITY UNIVERSITY RAJASTHAN

Name of School: ASET

EVEN SEMESTER
2013-2014

Course Handout

Program : B.Tech (ECE)

Course Code : BTE 401

Course Title : Digital Circuits and Systems-I

Faculty-in-charge : Archek Praveen Kumar

Credits : 4

Course Details

(a) Course Objectives:

1. To introduce the basic principles of digital electronics such as logic gates, Boolean
algebra, number systems and simplification of digital circuits.

2. To give the sufficient information about design and operation of basic Sequential
and Combinational circuits.

3. To have the elementary knowledge of different logic families and data converters.

(b) Learning Outcomes:

After successful completion, students will be able to:

1. Identify the fundamentals of computers including number systems, logic gates,

logic and arithmetic subsystems, and integrated circuits.

2. Apply the knowledge to work with digital circuits through problem solving and
hands on laboratory experience with logic gates, encoders, flip-flops, counters,
shift registers etc.
3. Analyze and design simple logic circuits using tools such as Boolean algebra and
Karnaugh Mapping.

(c) Prerequisites:
 Analog Electronics-I
 Circuits and Systems
(d) Pedagogy/ Instruction Methodology:
  Lecture
 Quiz
 Home Assignment
 Viva

(e) Text Books:

 Anand Kumar, Fundamentals of Digital Circuits, 2nd ed. (2010), PHI Learning Pvt. Ltd.
 Ronald J. Tocci, “Digital systems principles and applications”, 10th ed. (2009), pearson
publications

Reference Books/Journals/Other Study Material:

 R. P. Jain, “Modern Digital Electronics”, 4th ed. (2010), Tata McGraw Hill.
 Floyd & Jain, “Digital Fundamentals”, Pearsons education.,2nd Ed. 2007

(f). Tentative Delivery Schedule:

Suggested reading
Lecture Module Learning from Text Book
Topics to be covered
No. No Outcome (Section/Chapter
No.)
1. Analog & digital signals, AND, OR, NOT, I 1
NAND, NOR , XOR & XNOR gates

2. Boolean algebra I 1

3. De Morgan’s theorems I 1

4. Implementation of logical functions using I 1

only NAND/NOR gates

5. 1`s complement and 2`s complement I 1

6. BCD to Gray and Gray to BCD code I 1

conversion

7. Standard representation of logical I 1

functions: SOP and POS forms

8. K-map representation and simplification I 1

of logical functions up to five variables

9. Don’t care condition, XOR & XNOR I 1

simplifications of K-maps
10. Tabulation method I 1

11. Tutorial 1 I 1

12. Adders, Subtractors II 1,2

13. Implementation of full adder using half II 1,2

adder and full subtractor using half
subtractor

14. Multiplexer , De-multiplexer II 1,2

15. 1 & 2 bit comparators II 1,2

16. Code converters II 1,2

17. Decoder, Encoder II 1,2

18. BCD to seven segment decoder/encoder II 1,2

19. Implementation of logic functions using II 1,2

multiplexer/de-multiplexer and decoder

20. Implementation of 16×1 MUX using 4×1 II 1,2

MUX

21. Implementation of 4×16 decoder using II 1,2

3×8 decoder

22. Logic implementations using PROM, PLA II 1,2

& PAL

23. Tutorial 2 II 1,2

24. Difference between combinational and III 1,2,3

sequential circuits

25. Latch, Flip-flops: SR III 1,2,3

26. Flip-flops: JK III 1,2,3

27. Flip-flops: D III 1,2,3

28. Flip-flops: T III 1,2,3

29. Conversion of flip-flops III 1,2,3

30. Set up and hold time, race around III 1,2,3

 condition

31. Master Slave flip flop III 1,2,3

32. Shift registers: SIPO, PISO, PIPO, SIPO, Bi- III 1,2,3
directional, 4-bit universal shift register

33. Counters 1: Asynchronous/ripple & III 1,2,3

synchronous counters

34. Counters 2:up/down, Ring counter, III 1,2,3

sequence detector

35. Tutorial 3 III 1,2,3

36. Logic families: Special characteristics fan IV 1,2,3

out, power dissipation, propagation
delay, noise margin

37. Working of RTL, DTL, TTL, ECL and CMOS IV 1,2,3

families

38. Working of DTL IV 1,2,3

39. Working of TTL IV 1,2,3

40. Working of ECL IV 1,2,3

41. Working of CMOS IV 1,2,3

42. ADC– Successive approximation, Linear IV 1,2,3

ramp, Dual slope

43. DAC - Binary Weighted, R-2R ladder type IV 1,2,3

44. Tutorial 4 IV 1,2,3

Evaluation Scheme:

S.
Evaluation Component Weightage % Remarks
N.
1 Mid Term/Class Test 15 Closed Book
Continuous Evaluation Closed Book/
2 10
(Tests/Quizzes/Assignments/Viva) Open Book
3 Attendance 05
4 Final Examination 70 Closed Book
Total 100
Name of Faculty-in-charge : Archek Praveen Kumar

Mobile : 8233028344

Email : apkumar@jpr.amity.edu

Chamber Consultation Hours : Wednesday and Thursday (3:15-5:10pm)

(Signature of the Faculty-in-charge)