The Role of ISA

CS2600: Computer Organization and Architecture I Specifies the functionality of the processor
Instruction Set Architecture1
I Provides the interface between the compilers and hardware

C  program   Java  program   FORTRAN90  program  

Compiled to Compiled to Compiled to

ISA program ISA program ISA program
Madhu Mutyam
PACE Laboratory ISA  Level  
Department of Computer Science and Engineering
Indian Institute of Technology Madras
  ISA program executed by
microprogram or hardware

Jan 23-29, 2019

Hardware  

1 Chapters 12 and 13 of W. Stallings, Computer Organization and Architecture, 10th

Edition.  

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Classification of ISA Memory Addressing

I General-purpose
I Register-memory architecture
register architecture
I Memory can be accessed as part of any
instruction
Processor Processor
I 2-operand ALU instructions
I No separate load instruction to access data
from memory I 80x86 and ARM use byte addressing
I CPI vary based on operand location
I Provide access for bytes, half-words (2 bytes), words (4 bytes), and
ALU ALU I Example: 80x86
double words (8 bytes)
I Register-register (or load-store) architecture
I Memory is accessed through load/store I Two important issues: Endianness and Alignment
instructions
I 3-operand ALU instructions
I Same type of ALU instructions take
similar number of cycles
I Instruction count is higher than
Memory Memory register-memory architecture
Register-Memory Register-Register I Example: ARM
Architecture Architecture    

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Endianness Alignment
I An access to an object of size s bytes at byte address A is aligned if A
I Big Endian: The most significant byte is stored in the smallest address
mod s = 0
I Little Endian: The least significant byte is stored in the smallest address I Example showing the addresses at which an access is aligned (indicated
I 80x86 – Little Endian; Motorola 6800 – Big Endian; ARM – switchable with "Y") or misaligned (indicated with "N")
endianness Width  of  object  
1  byte  
0  
Y  
1  
Y  
2  
Y  
3  
Y  
4  
Y  
5  
Y  
6  
Y  
7  
Y  
Byte Byte 2  bytes   Y   Y   Y   Y  
11   12   13   14                   11   12   13   14  
address address 2  bytes   N   N   N   N  
struct{ 00 00   01   02   03   04   05   06   07   07   06   05   04   03   02   01   00   00
4  bytes   Y   Y  
int a; // 0x11121314 21   22   23   24   25   26   27   28   21   22   23   24   25   26   27   28  
4  bytes   N   N  
int b; 08 08   09   0A   0B   0C   0D   0E   0F   0F   0E   0D   0C   0B   0A   09   08   08 4  bytes   N   N  
double c; // 0x21222324252627
char* d; //0x31323334 31   32   33   34   ‘A’   ‘B’   ‘C’   ‘D’   ‘D’   ‘C’   ‘B’   ‘A’   31   32   33   34   4  bytes   N   N  
char e[7]; //‘A’, ‘B’, ‘C’, ‘D’, ‘E’, ‘F’, ‘G’ 10 10   11   12   13   14   15   16   17   17   16   15   14   13   12   11   10   10 8  bytes   Y  
short f; //0x5152 ‘E’   ‘F’   ‘G’     51   52           51   52     ‘G’   ‘F’   ‘E’   8  bytes   N  
} 18 18   19   1A   1B   1C   1D   1E   1F   1F   1E   1D   1C   1B   1A   19   18   18 8  bytes   N  
8  bytes   N  
Big Endian Address Mapping Little Endian Address Mapping
8  bytes   N  

I Endianness does not affect the ordering of data items within a structure2
8  bytes   N  
8  bytes   N  
8  bytes   N  

I Creates problem when exchanging data among computers with different

I Misaligned operations may take multiple aligned memory references
ordering
I Supporting multi-byte accesses requires an alignment to align bytes,
I Registers do not care about endianness
half-words, and words in 64-bit registers
2 Example is taken from William Stallings book on Computer Organization & Architecture.  
I 80x86 does not require alignment while ARM requires it  

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Registers Addressing Modes
I Special-purpose registers I Specify the way in which operands of an instruction are stored
I Program counter, stack pointer, etc.
Instruction Instruction
I Some special-purpose registers available in kernal mode (used only by the Instruction A   A  
OS) to control caches, memory, I/O, etc. Operand  
Register Register
I General-purpose registers Register
File Memory
File Memory File Memory

I To hold local variables and intermediate results.

B Operand
I In Core i7, though EDX is a general purpose register, it also receives half
the product in a multiplication and holds half the dividend in a division. A Operand A B
I Control register, i.e., Program Status Word or Flag Register
I To hold condition codes, set on every ALU operation and reflect the status (b) Direct Addressing (c) Memory Indirect
(a) Immediate Addressing
of the result of the most recent operation. ADD R1, Operand
ADD R1, A ADD R1, (A)

I Typical condition codes: I Used for accessing I Used for pointer

I Used for constants
N Set when the result was Negative Z Set when the result was Zero static data manipulations
I No memory
V Set when the result caused an P Set when the result had even I Only one memory I Large address
oVerflow Parity reference
reference space
C Set when the result caused a A Set when there was a carry I Limited operand
I Limited address I Two memory
Carry out of the leftmost bit out of bit 3 (Auxiliary carry) magnitude
 

space references
 

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Addressing Modes Uses of Displacement Addressing Mode

Instruction Instruction
R   R   Instruction
R   A  
Register Register
I Relative addressing
File Memory File Memory Register
File Memory I Displacement is relative to the address of the instruction
Operand R A R
I PC-relative addressing
R
I Used for control-transfer instructions
A Operand

Operand
I Base-Register addressing
(d) Register Addressing
I Reference register contains a memory address
(e) Register Indirect
ADD R1, R ADD R1, (R)
(f) Displacement I Address field contains a displacement from the memory address
ADD R1, A(R) I Used for implementing segmentation
I Used for values I Used for pointer
I direct + register I Indexed addressing
stored in registers manipulations
indirect addressing I Address field contains a memory address
I No memory I Large address I Reference register contains a displacement from the memory address
I Flexibility
reference space I Used for performing iterative operations
I Complex
I Limited address I One memory
implementation
space reference
   

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Addressing Modes Summary Machine Instruction Characteristics

I A simple instruction format:

I Instruction count can be reduced with some addressing modes, but CPI
may increase Opcode Destination Operand Source Operand1 Source Operand2
I 80x86 supports register, immediate, and displacement with zero, one, I Operation code (Opcode) – specifies the operation to be performed.
and two registers I Opcodes are represented by abbreviations, called mnemonics.
I ADD, SUB, MUL, DIV, LOAD, STORE
I ARM supports register, immediate, displacement with one and two
registers, PC-relative, auto-increment, and auto-decrement I Source and destination operands can be from main or virtual memory,
I The addressing modes any new ISA need to have are displacement, processor registers, I/O devices, or instruction itself.
immediate, and register indirect I Instruction types:
I Data processing – arithmetic and logic instructions
I Choosing the displacement field sizes and the immediate field sizes are I Data storage – movement of data into/out of register and/or memory
very important I Data movement – I/O instructions
I Control – test and branch instructions

   

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 A−B
Machine Instruction Characteristics (Contd) Program to Execute Y = C+(D×E)

I Number of Operands: Instruction Comment

I Virtually, all arithmetic and logic operations are either unary or binary.
SUB Y, A, B Y← A - B
I Three-operand instruction MUL T, D, E T← D × E
Instruction Comment
I Two-operand instruction – one operand acts as both source and destination ADD T, T, C T← T + C
LOAD D AC← D
I One-operand instruction – second operand must be implicit, coming from DIV Y, Y, T Y← Y ÷ T
MUL E AC← AC × E
accumulator (AC) register Three-operand instructions
I Zero-operand instruction – applicable to stack ADD C AC← AC + C
STORE Y Y← AC
Instruction Comment
Number of Operands Symbolic Representation Interpretation LOAD A AC← A
MOV Y, A Y← A
3 OP A, B, C A← B OP C SUB B AC← AC - B
SUB Y, B Y← Y - B
2 OP A, B A← A OP B DIV Y AC← AC ÷ Y
MOV T, D T← D
1 OP A AC← AC OP A STORE Y Y← AC
MUL T, E T← T × E
0 OP T← (T-1) OP T One-operand instructions
ADD T, C T← T + C
DIV Y, T Y← Y ÷ T
(T-1): second element of stack
Two-operand instructions
   

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Type and Size of Operands Common Instruction Operations

I Arithmetic/Logical: Integer ALU operations
I Common operand types I ADD, SUB, DIV, AND, OR, ...
I Character (8 bits), half-word (16 bits), word (32 bits), single-precision FP I Load/Stores: Data transfer between memory and registers
(1 word), double-precision FP (2 words) I LOAD, STORE, MOVE
I Integers are represented as 2’s complement binary number I Control: Instructions to change the flow of instruction execution
I Conditional branches, jumps, procedure calls, procedure returns
I Characters are represented in ASCII
I PC-relative – the target address is known at compile time
I 16-bit unicode is gaining popularity
I Register indirect – the target address is not known at compile time
I IEEE standard 754 is used for FP numbers I Condition codes are used to specify branch conditions
I Single-precision: Sign(1):Exponent(8):Mantissa(23) I Procedure call places the return address in a register (ARM) or on a stack
I Double-precision: Sign(1):Exponent(11):Mantissa(52) in memory (80x86)
I Consider biased exponent and normalised mantissa I BEQZ, BNEQ, JMP, CALL, RETURN, TRAP
I BCD format can also be needed I System: OS instructions, virtual memory management instructions
I Calculations that are exact in decimal can be inexact in binary I INT
I Floating-point: FP operations
 
I FADD, FMULT, ...  

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Encoding An Instruction Set CISC Vs RISC

I The number of registers and the number of addressing modes have an I Complex Instruction Set Computer (CISC) Architecture uses multi-word
instructions
impact on the size of instructions
I The primary goal is to complete a task in as few lines of assembly as
I Fixed Length Encoding: possible
Opera&on   Address   Address   Address   I supporting the operations and data structures used by the high-level
field  1   field  2   field  3   language
I Supporting a large variety of memory addressing modes
I The operation and the addressing mode are encoded into the opcode I Results in variable length instructions
I Instruction decoding is simple I Example ISA: x86
I Example ISA: ARM
I Reduced Instruction Set Computer (RISC) Architecture uses one-word
I Variable Length Encoding: instructions
Opera&on  and   Address   Address   Address   Address   I Uses processor registers extensively
no.  of  operands   specifier  1   field  1   specifier  n   field  n   I Operands must be from registers only
I Load-store architecture
I Separate address specifier is needed for each operand I Register-based addressing is used
I Takes less space I Memory addressing modes are used only for loads/stores
I Example ISA: 80x86 I Example ISA: ARM
   

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 Thank You

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