S7300Instr PDF

S7-300 Instruction List
CPU 312 IFM, 314 IFM,

313, 314, 315, 315-2 DP, 316-2 DP,
318-2
6ES7 398-8AA03-8BN0
Edition 1
Contents Contents
Contents Comparison Instructions with Integers (16 Bits) . . .

Comparison Instructions with Integers (32 Bits) . . .
122
124
Comparison Instructions with Real Numbers
(32 Bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
! ! Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Accumulator Transfer Instructions, Incrementing
#! and Decrementing . . . . . . . . . . . . . . . . . . . . . . . . 134
Program Display and Null Operation Instructions . . 136
! Data Type Conversion Instructions . . . . . . . . . . . . . 138
Forming the Ones and Twos Complements . . . . . . . 142
Block Call Instructions . . . . . . . . . . . . . . . . . . . . . . 144
% Block End Instructions . . . . . . . . . . . . . . . . . . . . . . . 148

Exchanging Shared Data Block and Instance Data
%"! $! ! Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Instructions for the Master Control Relay (MCR) . . 160
! !"!
Bit Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . 28
Bit Logic Instructions with Parenthetical ! % !"!
Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
ORing of AND Operations . . . . . . . . . . . . . . . . . . . 38 Convention:
Logic Instructions with Timers and Counters . . . . . 40
Word Logic Instructions with the Contents of In the following, the CPU 312 IFM is called CPU 312*.
Accumulator 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Evaluating Conditions Using AND, OR and In the following, the CPU 314 IFM is called CPU 314*.
EXCLUSIVE OR . . . . . . . . . . . . . . . . . . . . . . . . 46
Edge-Triggered Instructions . . . . . . . . . . . . . . . . . . 60 In the following, the CPU 315-2 DP is called CPU 315-2.
Setting/Resetting Bit Addresses . . . . . . . . . . . . . . . . 64 In the following, the CPU 316-2 DP is called CPU 316-2.
Instructions Directly Affecting the RLO . . . . . . . . . 70
Timer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Counter Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 76
Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Load Instructions for Timers and Counters . . . . . . . 88
Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . 90
Load and Transfer Instructions for Address
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Load and Transfer Instructions for the Status Word 102
Load Instructions for DB Number and DB Length . 104
Integer Math (16 Bits) . . . . . . . . . . . . . . . . . . . . . . . 106
Integer Math (32 Bits) . . . . . . . . . . . . . . . . . . . . . . . 108
Floating-Point Math (32 Bits) . . . . . . . . . . . . . . . . . 110
Square Root and Square Instructions (32 Bits) . . . . 112
Logarithmic Function (32 Bits) . . . . . . . . . . . . . . . . 114
Trigonometrical Functions (32 Bits) . . . . . . . . . . . . 116
Adding Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Adding Using Address Registers . . . . . . . . . . . . . . . 120
S7-300 Instruction List S7-300 Instruction List

0 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 1
Addresses Identifiers and Parameter Ranges Addresses Identifiers and Parameter Ranges
Address Identifiers and Parameter

Ranges
Parameter Ranges
Addr. Description
D i ti
312* 313 314 314* 315/315–2/ 318-2
ID
316–2
Q 0.0 to 31.7 0.0 to 127.7 0.0 to 123.7 0.0 to 127.7 0.0 to 2047.71 Output bit (in PIQ)
124.7 to – 124.0 to – – ... integrated outputs
127.7 127.7
QB
Q 0 to 31 0 to 127 0 to 123 0 to 127 0 to 20471 Output byte (in PIQ)
124 to 127 – 124 to 127 – – ... integrated outputs
QW
Q 0 to 30 0 to 126 0 to 122 0 to 126 0 to 20461 Output word in (PIQ)
124 to 126 – 124 to 126 – – ... integrated outputs
QD
Q 0 to 28 0 to 124 0 to 120 0 to 124 0 to 20441 Output double word (in PIQ)
124 – 124 – – ... integrated outputs
B – – – Byte with general register-
indirect addressing
W – – – Word with general register-
indirect addressing
D – – – Double word with general
register-indirect addressing
DBX 0.0 to 8191.7 0.0 to 8191.7 0.0 to Data bit in data block
65533.7
DB 1 to 63 1 to 127 1 to 127 0 to 2047 Data block
DBB 0 to 6143 0 to 8191 0 to 8191 0 to 65533 Data byte in DB
DBW 0 to 6142 0 to 8190 0 to 8190 0 to 65532 Data word in DB
DBD 0 to 6140 0 to 8188 0 to 8188 0 to 65530 Data double word in DB
1 PIQ is preset to 256 byte

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Parameter Ranges
Addr.
312* 313 314 314* 315/315-2/ 318-2 Description
ID
316-2
DIX 0.0 to 8191.7 0.0 to 0.0 to Data bit in instance DB
8191.7 65533.7
DI 1 to 63 1 to 127 1 to 127 1 to 2047 Instance data block
DIB 0 to 6143 0 to 8191 0 to 8191 0 to 65533 Data byte in instance DB
DIW 0 to 6142 0 to 8190 0 to 8190 0 to 65532 Data word in instance DB
DID 0 to 6140 0 to 8188 0 to 8188 0 to 65530 Data double word in instance DB
I 0.0 to 31.7 0.0 to 127.7 0.0 to 123.7 0.0 to 127.7 0.0 to Input bit (in PII)
2047.7 1
124.0 to – 124.0 to – – ... integrated inputs
127.7 127.7
IB 0 to 31 0 to 127 0 to 123 0 to 127 0 to 2047 1 Input byte (in PII)
124 to 127 – 124 to 127 – – ... integrated inputs
IW 0 to 30 0 to 127 0 to 122 0 to 126 0 to 2046 1 Input word (in PII)
124 to 126 – 124 to 126 – – ... integrated inputs
ID 0 to 28 0 to 124 0 to 120 0 to 124 0 to 2044 1 Input double word (in PII)
124 – 124 – – ... integrated inputs
L 0.0 to 255.7 0.0 to 255.7 0.0 to Local data bit
8191.7 2
LB 0 to 255 0 to 255 0 to 8191 2 Local data byte
LW 0 to 254 0 to 254 0 to 8190 2 Local data word
LD 0 to 252 0 to 252 0 to 8188 2 Local data double word
1 PII is preset to 256 byte

2 Local data area is preset to 4096 byte

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Parameter Ranges
Addr.
312* 313 314 314* 315/315-2/ 318-2 Description
ID
316-2
M 0.0 to 127.7 0.0 to 255.7 0.0 to 255.7 0.0 to Bit memory bit
1023.0
MB 0 to 127 0 to 255 0 to 255 0 to 1023 Bit memory byte
MW 0 to 126 0 to 254 0 to 254 0 to 1022 Bit memory word
MD 0 to 124 0 to 252 0 to 252 0 to 1020 Bit memory double word

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Parameter Ranges
Addr. ID 312* 313 314 314* 315 315-2/ 318–2 Description
316–2
PQB
Q 0 to 31 0 to 31 0 to 767 0 to 751 0 to 767 0 to 1023 0 to 8191 Peripheral
p output
p byte
y
(direct I/O access)
124
256 to 383 256 to 383
PQW 0 to 30 0 to 30 0 to 766 0 to 750 0 to 766 0 to 1022 0 to 8190 Peripheral output
word (direct I/O ac-
256 to 382 256 to 382 cess)
PQD 0 to 28 0 to 28 0 to 764 0 to 748 0 to 764 0 to 1020 0 to 8188 Peripheral output
double word (direct
256 to 380 256 to 380 I/O access)
PIB 0 to 31 0 to 31 0 to 767 0 to 751 0 to 767 0 to 1023 0 to 8191 Peripheral
p input
p byte
y
(direct I/O access)
124 to 125
256 to 383 256 to 383
PIW 0 to 30 0 to 30 0 to 766 0 to 750 0 to 766 0 to 1022 0 to 8190 Peripheral
p input
p word
(direct I/O access)
124
256 to 382 256 to 382
PID 0 to 28 0 to 28 0 to 764 0 to 748 0 to 764 0 to 1020 0 to 8188 Peripheral input
double word
256 to 380 256 to 380 (direct I/O access)
T 0 to 63 0 to 127 0 to 127 0 to 511 Timer
Z 0 to 31 0 to 35 0 to 63 0 to 63 0 to 511 Counter
Parame- – – Instruction addressed
ter via parameter
B#16# – – Byte
W#16# Word
DW#16# Double word
hexadecimal

8 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 9
Parameter Ranges
Addr.
312* 313 314 314* 315/315–2, 318-2 Description
ID
316
D# – – IEC data constant
L# – – 32-bit integer constant
P# – – Pointer constant
S5T# – – S5 time constant (16 bits) 1
T# – 2 2 Time constant (16/32 bits)
TOD# – – IEC time constant
C# – – Counter constant (BCD–codiert)
2# – – Binary constant
B – – Constant, 2 or 4 Byte
(b1,b2)
B
(b1,b2,
b3,b4)
1 for loading of S5 timers

2 T#1D_5H_3M_1S_2MS

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Abbreviations and Mnemonics Abbreviations and Mnemonics
Abbreviations and Mnemonics

The following abbreviations and mnemonics are used in the
Instruction List:
Abbre- Description Example Abbre- Description Example
viations viations
k8 8-bit constant 32 f Timer–/Zähler–Nr. 5
k16 16-bit constant 62 531 g Operandenbereich IB, QB, PIB, MB, LB,
DBB, DIB
k32 32-bit constant 127 624
h Operandenbereich IW, QW, PIW, MW, LW,
i8 8-bit integer –155 DBW, DIW
i16 16-bit integer +6523 i Operandenbereich ID, QD, PID, MD, LD,
i32 32-bit integer –2 222 222 DBD, DID
r Baustein–Nr. 10
m P#x.y (pointer) P#240.3
n Binary constant 1001 1100
p Hexadecimal constant EA12
q Real number (32-bit 12.34567E+5
floating-point number)
LABEL Symbolic jump address DEST
(max. 4 characters)
a Byteadresse 2
b Bitadresse x.1
c Operandenbereich I, Q, M, L, DBX, DIX

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Registers Registers
Registers
ACCU1 and ACCU2 (32 Bits) Area-internal address
00000000 00000bbb bbbbbbbb bbbbbxxx
The accumulators are registers for processing bytes, words or
double words. The operands are loaded into the accumulators, Area-crossing address
where they are logically gated. The result of the logic operation
10000yyy 00000bbb bbbbbbbb bbbbbxxx
(RLO) is in ACCU1.
Legend: b Byte address
CPU 318–2: also ACCU3 and ACCU4.
x Bit number
Accumulator designations: y Area identifier
(see section “Examples of Addressing”)
ACCU Bits
ACCUx (x = 1 to 4) Bits 0 to 31 Status Word (16 Bits)
ACCUx-L Bits 0 to 15
The status word bits are evaluated or set by the instructions.
ACCUx-H Bits 16 to 31
The status word is 16 bits long.
ACCUx-LL Bits 0 to 7
Bit Assignment Description
ACCUx-LH Bits 8 to 15
0 FC First check bit *
ACCUx-HL Bits 16 to 23
1 RLO Result of (previous) logic operation
ACCUx-HH Bits 24 to 31
2 STA Status *
3 OR Or *
Address Registers AR1 and AR2 (32 Bits) 4 OS Stored overflow
The address registers contain the area-internal or area-crossing ad- 5 OV Overflow

dresses for instructions using indirect addressing. The address regis- 6 CC 0 Condition code
ters are 32 bits long.
7 CC 1 Condition code
The area-internal and/or area-crossing addresses have the following
syntax: 8 BR Binary result
9 ... 15 Unassigned –
* Bit cannot be evaluated in the user program with the L STW

instruction since it is not updated at program runtime.

14 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 15
Examples of Addressing Examples of Addressing
Examples of Addressing
Addressing Examples Description Addressing Examples Description
Direct Addressing Direct Addressing
L +27 Load 16-bit integer constant A I 0.0 ANDing of input bit 0.0
“27” into ACCU1
L IB 1 Load input byte 1 into ACCU1
L L#–1 Load 32-bit integer constant
“–1” into ACCU1 L IW 0 Load input word 0 into
ACCU1
L 2#1010101010101010 Load binary constant into
ACCU1 L ID 0 Load input double word 0 into
ACCU1
L DW#16#A0F0_BCFD Load hexadecimal constant into
ACCU1 Indirect Addressing of Timers/Counters
L ’END’ Load ASCII character into SP T [LW 8] Start timer; the timer number is
ACCU1 in local word 8
L T#500 ms Load time value into ACCU1 CU C [LW 10] Start counter; the counter num-
ber is in local data word 10
L C#100 Load count value into ACCU1
Area-Internal Memory-Indirect Addressing
L B#(100,12) Load 2-byte constant
A I [LD 12] AND operation: The address of
L B#(100,12,50,8) Load 4-byte constant Example: L P#22.2 the input is in local data double
T LD 12 word 12 as pointer
L P#10.0 Load area-internal pointer into A I [LD 12]
ACCU1
A I [DBD 1] AND operation: The address of
L P#E20.6 Load area-crossing pointer into the input is in data double
ACCU1 word 1 of the DB as pointer
L –2.5 Load real number into ACCU1 A Q [DID 12] AND operation: The address of
L D#1995–01–20 Load date the output is in data double
word 12 of the instance DB as
L TOD#13:20:33.125 Load time of day pointer
A Q [MD 12] AND operation: The address of
the output is in memory marker
double word 12 of the instance
DB as pointer

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Examples of Addressing Examples of Addressing
Addressing Examples Description Addressing Examples Description

Area-Internal Register-Indirect Addressing Addressing Via Parameters
A I [AR1,P#12.2] AND operation: The address of A Parameter Addressing via parameters
the input is calculated from the
“pointer value in AR1+
P#12.2”
Area-Crossing Register-Indirect Addressing Examples of how to calculate the pointer
For area-crossing register-indirect addressing, bits 24 to 26 of the Example for sum of bit addresses 7:
address must also contain an area identifier. The address is in the
address register. LAR1 P#8.2
A I [AR1,P#10.2]
Area Coding Area
identifier (binary) hex. Result: Input 18.4 is addressed (by adding the byte and bit
P 1000 0000 80 I/O area addresses)
I 1000 0001 81 Input area
Q 1000 0010 82 Output area Example for sum of bit addresses7:
M 1000 0011 83 Bit memory area L MD 0 Random pointer, e.g. P#10.5
DB 1000 0100 84 Data area LAR1
DI 1000 0101 85 Instance data area A I [AR1,P#10.7]
L 1000 0110 86 Local data area
VL 1000 0111 87 Predecessor local data Result: Input 21.4 is addressed (by adding the byte and bit
(access to local data of addresses with carry)
invoking block see
page 15)
L B [AR1,P#8.0] Load byte into ACCU1: The
address is calculated from the
“pointer value in AR1+ P#8.0”
A [AR1,P#32.3] AND operation: The address of
the operand is calculated from
the “pointer value in AR1+
P#32.3”

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Execution Times with Indirect Addressing Execution Times with Indirect Addressing
Execution Times with Indirect

Addressing
You must calculate the execution times when using indirect addres- The execution time for loading the address of the instruction from
sing. This chapter shows you how. the various areas is shown in the following table. You will also find
this table on the fold-out part of the cover.
Two-Part Statement You do not have to change the page when calculating the execution
time.
A statement with indirectly addressed instructions consists of two Execution Time in s
parts:
Address is in ... 312*/ 314/ 315/315-2/ 318–2
Part 1: Load the address of the instruction 313 314* 316-2
Part 2: Execute the instruction Bit memory area M
Word 1.7 0.7 0.8 0.2
In other words, you must calculate the execution time of a state- Double word 3.5 2.3 2.1 0.3
ment with indirectly addressed instructions from these two parts.
Data block DB/DX
Word 5.2 2.8 3.0 0.2
Double word 6.7 3.9 4.1 0.3
Calculating the Execution Time
Local data area L
Word 2.0 0.8 0.9 0.2
Double word 3.7 2.6 2.2 0.3
The total execution time is calculated as follows:
AR1/AR2 (area-internal) 3.0 1.9 1.7 0.0
Time required for loading the address
+ execution time of the instruction AR1/AR2 (area-crossing) 4.9 3.9 3.2 0 .0
= Total execution time of the instruction Parameter (word) ... for: 4.0 2.5 2.1 0.2
Timers
Counters
The execution times listed in the chapter entitled “List of Instruc- Block calls
tions” apply to the execution times of the second part of an instruc- Parameter (double word) 7.3 5.3 4.3 0.3
tion, i.e. for the actual execution of an instruction. ... for
You must then add the time required for loading the address of the Bits, bytes,
words and
instruction to this execution time (see Table on following page).
double words
The pages that follow contain examples for calculating the instruc-
tion run time for the various indirectly addressed instructions.

20 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 21
Examples of Calculations (for the CPU 314) Step 2: AND the input addressed in this way (you will find
the execution time in the tables in the chapter entitled
You will find a few examples here for calculating the execution “List of Instructions”)
times for the various methods of indirect addressing. Execution
times are calculated for the CPU 314. Typical Execution Time in s
Direct Addressing Indirect Addressing

Calculating the Execution Times for Area-Internal
Memory-Indirect Addressing 0.2 Time for 2.0+
: AI :
Example: A I [DBD 12]
Step 1: Load the contents of DBD 12 (time required is listed
Total execution time:
in the table on page 21)
3.9 s
+ 2.0 s
Address is in ... Execution Time in s
= 5.9 s
Bit memory area M
Word 0.7
Double word 2.3
Data block DB/DI
Word 2.8
Double word 3.9

22 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 23
Calculating the Execution Time for Area-Internal Calculating the Execution Time for Area-Crossing
Register-Indirect Addressing Memory-Indirect Addressing
Example: A I [AR1, P#34.3] Example: A [AR1, P#23.1] ... with I 1.0 in AR1
Step 1: Load the contents of AR1, and increment it by the Step 1: Load the contents of AR1, and increment them by
offset 34.3 (the time required is listed in the table on the offset 23.1 (the time required is in the table on
page 21) page 21)
Address is in ... Execution Time in s Address is in ... Execution Time in s

: : : :
AR1/AR2 (area-internal) 1.9 AR1/AR2 (area-crossing) 3.9
: : : :
Step 2: AND the input addressed in this way (you will find Step 2: AND the input addressed in this way (you will find
the execution time in the tables in the chapter entitled the execution time in the tables in the chapter entitled
“List of Instructions”) “List of Instructions”)
Typical Execution Time in s Typical Execution Time in s
Direct Addressing Indirect Addressing Direct Addressing Indirect Addressing
0.2 Time for 2.0+ 0.2 Time for 2.0+

: AI : : AI :
Total execution time: Total execution time:

1.9 s 3.9 s
+ 2.0 s + 2.0 s
= 3.9 s = 5.9 s

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Execution times with Indirect Addressing Execution times with Indirect Addressing
Execution Time for Addressing Via Parameters
Example: A Parameter ... with I 0.5 in the block parameter list

Step 1: Load input I 0.5 addressed via the parameter (the
time required is in the table on page 21).
Address is in ... Execution Time in s

: :
: :
Parameter (double word) 5.3
Step 2: AND the input addressed in this way (you will find
the execution time in the tables in the chapter entitled
“List of Instructions”)
Typical Execution Time in s
Direct Addressing Indirect Addressing
0.2 Time for 2.0+

: AI :
Total execution time:

5.3 s
+ 2.0 s
= 7.3 s

26 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 27
List of Instructions List of Instructions
List of Instructions page 16), you must add the time required for loading the address of
the particular instruction to the execution times listed (see page 21).
This chapter contains the complete list of S7-300 instructions. The
descriptions have been kept as concise as possible. You will find a Bit Logic Instructions
detailed functional description in the various STEP 7 reference
manuals. Examining the signal state of the addressed instruction and gating
Please note that, in the case of indirect addressing (examples see the result with the RLO according to the appropriate logic function.
In-
In Length
g Typical Execution Time in s
struc- Address Description in
Words Direct Addressing Indirect Addressing 1
tion Identifier
315 315
312* 314 312* 314
315-2 318-2 315-2 318-2
313 314* 313 314*
316-2 316-2
A AND
I/Q a.b Input/output 1 2/2 0.7 0.2 0.3 0.1+ 2.5+ 2.0+ 1.6+ 0.1+
M a.b Bit memory 1 2/2 1.5 0.6 0.6 0.1+ 2.7+ 2.2+ 1.7+ 0.1+
L a.b Local data bit 2 2.2 0.8 0.9 0.1+ 3.0+ 2.2+ 1.8+ 0.1+
DBX a.b Data bit 2 5.2 2.7 2.8 0.1+ 4.2+ 2.8+ 2.5+ 0.1+
DIX a.b Instance data bit 2 5.2 2.7 2.8 0.1+ 4.2+ 2.8+ 2.5+ 0.1+
c[AR1,m] Register–ind., area–internal (AR1) 2 – – – – + + + +
[AR1,m] Area-crossing via (AR1) 2 – – – – + + + +
Parameter Via parameter 2 – – – – + + + +
Status word for: A BR CC 1 CC 0 OV OS OR STA RLO FC
Instruction depends on: – – – – – Yes – Yes Yes
Instruction affects: – – – – – Yes Yes Yes 1
1 Plus time required for loading the address of the instruction

(see page 21)
2 With direct instruction addressing
Adress area 0 to 127

28 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 29
In-
In Length Typical Execution Time in s
Direct Addressing Indirect Addressing 1
tion Identifier Words
315 315
312* 314 312* 314
315-2 318-2 315-2 318-2
313 314* 313 314*
316-2 316-2
AN AND NOT 0.4
I/Q a.b Input/output 1 2/2 0.7 1.4 0.5 0.5 0.1 2.9+ 2.2+ 1.9+ 0.1+
M a.b Bit memory 1 2/2 0.9 1.9 0.7 0.8 0.1 3.1+ 2.4+ 2.1+ 0.1+
L a.b Local data bit 2 3.6 2.5 0.9 1.0 0.1 3.4+ 2.4+ 2.2+ 0.1+
DBX a.b Data bit 2 5.5 3.0 3.1 0.1 4.6+ 2.9+ 2.8+ 0.1+
DIX a.b Instance data bit 2 5.5 3.0 3.1 0.1 4.6+ 2.9+ 2.8+ 0.1+
Status word for: AN BR CC 1 CC 0 OV OS OR STA RLO FC

(see page 21)
Adress area 0 to 127

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In-
315 315
312* 314 312* 314
315-2 318-2 315-2 318-2
313 314* 313 314*
316-2 316-2
O OR
I/Q a.b Input/output 1 2/2 0.7 0.2 0.3 0.1 2.5+ 2.0+ 1.6+ 0.1+
M a.b Bit memory 1 2/2 1.5 0.6 0.7 0.1 2.7+ 2.2+ 1.7+ 0.1+
L a.b Local data bit 2 2.2 0.8 0.9 0.1 3.0+ 2.2+ 1.8+ 0.1+
DBX a.b Data bit 2 5.2 2.7 2.9 0.1 4.2+ 2.8+ 2.5+ 0.1+
ON OR NOT
I/Q a.b Input/output 13/2 1.4 0.5 0.5 0.1 2.9+ 2.2+ 1.6+ 0.1+
M a.b Bit memory 12/2 1.9 0.7 0.8 0.1 3.1+ 2.4+ 2.0+ 0.1+
DBX a.b Data bit 2 5.5 3.0 3.1 0.1 4.6+ 2.9+ 2.8+ 0.1+
Status word for: O, ON BR CC 1 CC 0 OV OS OR STA RLO FC
Instruction depends on: – – – – – – – Yes Yes
Instruction affects: – – – – – 0 Yes Yes 1
(see page 21)

32 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 33
In-
315 315
312* 314 312* 314
315-2 318-2 315-2 318-2
313 314* 313 314*
316-2 316-2
X EXCLUSIVE OR
I/Q a.b Input/output 2 0.7 0.2 0.3 0.1 2.5+ 1.9+ 1.6+ 0.1+
M a.b Bit memory 2 1.5 0.6 0.7 0.1 2.7+ 2.1+ 1.7+ 0.1+
DBX a.b Data bit 2 5.2 2.8 2.9 0.1 4.2+ 2.6+ 2.5+ 0.1+
XN EXCLUSIVE OR NOT
I/Q a.b Input/output 2 1.4 0.5 0.5 0.1 2.9+ 2.2+ 1.9+ 0.1+
M a.b Bit memory 2 1.9 0.7 0.8 0.1 3.1+ 2.4+ 2.0+ 0.1+
DBX a.b Data bit 2 5.5 3.0 3.1 0.1 4.6+ 2.9+ 2.8+ 0.1+
Status word for: X, XN BR CC 1 CC 0 OV OS OR STA RLO FC
(see page 21)

34 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 35
Bit Logic Instructions with Parenthetical

Expressions
Saving the BR, RLO and OR bits and a function identifier

(A, AN, ...) to the nesting stack. Seven nesting levels are possible
per block.
In- Length
Address
struc- Description in Typical Execution Time in s
Identifier
tion Words
315/315-2
312*/313 314/314* 318-2
316-2
A( AND left parenthesis 1 2.9 1.7 1.7 0.1
AN( AND NOT left parenthesis 1 2.9 1.7 1.7 0.1
O( OR left parenthesis 1 2.9 1.4 1.7 0.1
ON( OR NOT left parenthesis 1 2.9 1.4 1.7 0.1
X( EXCLUSIVE OR 1 2.9 1.4 1.7 0.1
left parenthesis
XN( EXCLUSIVE OR NOT 1 2.9 1.4 1.7 0.1
left parenthesis
Status word for: A(, AN(, O(, ON(, X(, BR CC 1 CC 0 OV OS OR STA RLO FC
XN(
Instruction depends on: Yes – – – – Yes – Yes Yes
Instruction affects: – – – – – 0 1 – 0
) Right parenthesis, popping an 1 3.3 1.7 1.9 0.1
entry off the nesting stack, gat-
ing the RLO with the current
RLO in the processor
Status word for: ) BR CC 1 CC 0 OV OS OR STA RLO FC
Instruction depends on: – – – – – – – Yes –
Instruction affects: Yes – – – – Yes 1 Yes 1

36 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 37
ORing of AND Operations
The ORing of AND operations is implemented according to the

rule: AND before OR.
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
O ORing of AND operations 1 1.4 0.3 0.5 0.1
according to the rule:
AND before OR
Status word for: O BR CC 1 CC 0 OV OS OR STA RLO FC
Instruction affects: – – – – – Yes 1 – Yes

38 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 39
Logic Instructions with Timers and

Counters
Examining the signal state of the addressed timer/counter and

gating the result with the RLO according to the appropriate
logic function.
In
In- Length Typical Execution Time in s
tion Identifier
315 315
312* 314 312* 314
315-2 318-2 315-2 318-2
313 314* 313 314*
316-2 316-2
A AND
T Timer 1 2/2 2.4 0.8 0.9 0.1 3.3+ 2.2+ 2.1+ 0.1+
C Counter 1 2/2 1.7 0.6 0.6 0.1 3.0+ 1.9+ 1.8+ 0.1+
Timer para. Timer/counter 2 – – – – + + + +
Counter p. (addressed via parameter) – – – – + + + +
AN AND NOT
T Timer 13/2 3.0 1.0 1.1 0.1 3.7+ 2.4+ 2.3+ 0.1+
C Counter 1 2/2 2.4 0.8 0.9 0.1 3.3+ 2.2+ 2.1+ 0.1+
Timer para. Timer/counter 2 – – – – + + + +

(see page 21)

40 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 41
In- Length
struc- Address Description i
in
tion Identifier
315 315
312*/ 314/ 312*/ 314/
315-2 318-2 315-2 318-2
313 314* 313 314*
316-2 316-2
O T OR timer 1 2/2 2.4 0.8 0.9 0.1 3.3+ 2.2+ 2.1+ 0.1+
C OR counter 13/2 1.7 0.6 0.6 0.1 3.0+ 1.9+ 1.8+ 0.1+
Timerpara. OR timer/counter 2 – – – – + + + +
ON T OR NOT timer 14/2 3.0 1.0 1.1 0.1 3.7+ 2.4+ 2.3+ 0.1+
C OR NOT counter 15/2 2.4 0.8 0.9 0.1 3.3+ 2.2+ 2.1+ 0.1+
Timerpara. OR NOT timer/counter 2 – – – – + + + +
X T EXCLUSIVE OR timer 2 2.4 0.8 0.9 0.1 3.3+ 2.2+ 2.1+ 0.1+
C EXCLUSIVE OR counter 2 1.7 0.6 0.6 0.1 3.0+ 1.9+ 1.8+ 0.1+
Timerpara. EXCLUSIVE OR timer/counter 2 – – – – + + + +
Counter p. (addressed via parameter) 2 – – – – + + + +
XN T EXCLUSIVE OR NOT timer 2 3.0 1.0 1.1 0.1 3.7+ 2.4+ 2.3+ 0.1+
C EXCLUSIVE OR NOT counter 2 2.4 1.0 0.9 0.1 3.3+ 1.2+ 2.1+ 0.1+
Timerpara. EXCLUSIVE OR NOT 2 – – – – + + + +
Counter p. timer/counter (addressed via – – – – + + + +
parameter)
Status word for: O, ON, X, XN BR CC 1 CC 0 OV OS OR STA RLO FC

(see page 21)

42 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 43
Word Logic Instructions with the

Contents of Accumulator 1
Gating the contents of ACCU1 and/or ACCU1-L with a word or double word is either a constant in the instruction or in ACCU2.
double word according to the appropriate function. The word or The result is in ACCU1 and/or ACCU1-L.
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
AW AND ACCU2-L 1 1.7 0.5 0.6 0.1
AW k16 AND 16-bit constant 2 2.3 0.7 0.9 0.1
OW OR ACCU2-L 1 1.7 0.5 0.6 0.1
OW k16 OR 16-bit constant 2 2.3 0.7 0.9 0.1
XOW EXCLUSIVE OR ACCU2-L 1 1.7 0.5 0.6 0.1
XOW k16 EXCLUSIVE OR 16-bit 2 2.3 0.7 0.9 0.1
constant
AD AND ACCU2 1 3.4 1.9 2.0 0.1
AD k32 AND 32-bit constant 3 4.1 2.1 2.3 0.15
OD OR ACCU2 1 3.4 1.9 2.0 0.1
OD k32 OR 32-bit constant 3 4.1 2.1 2.3 0.15
XOD EXCLUSIVE OR ACCU2 1 3.4 1.9 2.0 0.1
XOD k32 EXCLUSIVE OR 32-bit 3 4.1 2.1 2.3 0.15
constant
Status word for: AW, OW, XOW, AD, BR CC 1 CC 0 OV OS OR STA RLO FC
OD, XOD
Instruction depends on: – – – – – – – – –
Instruction affects: – Yes 0 0 – – – – –

44 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 45
Evaluating Conditions Using AND, OR

and EXCLUSIVE OR
Examining the specified conditions for their signal status, and gat-
ing the result with the RLO according to the appropriate function.
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
A AND 1 1.5 0.5 0.6 0.1
==0 Result=0
(CC 1=0) and (CC 0=0)
>0 Result>0 1 2.3 0.7 0.9 0.1
(CC 1=1) and (CC 0=0)
<0 Result<0 1 2.3 0.7 0.9 0.1
(CC 1=0) and (CC 0=1)
<>0 Result0 1 1.5 0.5 0.6 0.1
((CC 1=0) and (CC 0=1) or
(CC 1=1) and (CC 0=0))
<=0 Result<=0 1 1.5 0.5 0.6 0.1
((CC 1=0) and (CC 0=1) or
(CC 1=0) and (CC 0=0))
>=0 Result>=0 1 1.5 0.5 0.6 0.1
((CC 1=1) and (CC 0=0) or
(CC 1=0) and (CC 0=0))
Instruction depends on: Yes Yes Yes Yes Yes Yes – Yes Yes

46 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 47
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
A AND 1 1.5 0.5 0.6 0.1
UO unordered math instruction
(CC 1=1) and (CC 0=1)
OS AND OS=1 1 0.7 0.2 0.3 0.1
BR AND BR=1 1 0.7 0.2 0.3 0.1
OV AND OV=1 1 0.7 0.2 0.3 0.1

48 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 49
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
AN ==0 AND NOT 1 1.5 0.5 0.6 0.1
Result=0
(CC 1=0) and (CC 0=0)
>0 Result>0 1 2.3 0.7 0.9 0.1
(CC 1=1) and (CC 0=0)
<0 Result<0 1 2.3 0.7 0.9 0.1
(CC 1=0) and (CC 0=1)
<>0 Result0 1 2.3 0.7 0.9 0.1
((CC 1=0) and (CC 0=1) or
(CC 1=1) and (CC 0=0))
<=0 Result<=0 1 0.7 0.2 0.3 0.1
((CC 1=0) and (CC 0=1) or
(CC 1=0) and (CC 0=0))
>=0 Result>=0 1 0.7 0.7 0.3 0.1
((CC 1=1) and (CC 0=0) or
(CC 1=0) and (CC 0=0))
UO unordered math instruction 1 2.3 0.7 0.9 0.1
(CC 1=1) and (CC 0=1)
OS OS=1 1 1.5 0.5 0.6 0.1
BR BR=1 1 1.5 0.5 0.6 0.1
OV OV=1 1 1.5 0.5 0.6 0.1

50 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 51
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
O ==0 OR 1 1.5 0.5 0.6 0.1
Result=0
(CC 1=0) and (CC 0=0)
>0 Result>0 1 2.3 0.7 0.9 0.1
(CC 1=1) and (CC 0=0)
<0 Result<0 1 2.3 0.7 0.9 0.1
(CC 1=0) and (CC 0=1)
<>0 Result0 1 1.5 0.5 0.6 0.1
((CC 1=0) and (CC 0=1) or
(CC 1=1) and (CC 0=0))
<=0 Result<=0 1 1.5 0.5 0.6 0.1
((CC 1=0) and (CC 0=1) or
(CC 1=0) and (CC 0=0))
>=0 Result>=0 1 1.5 0.5 0.6 0.1
((CC 1=1) and (CC 0=0) or
(CC 1=0) and (CC 0=0))
(CC 1=1) and (CC 0=1)
OS OS=1 1 0.7 0.2 0.3 0.1
BR BR=1 1 0.7 0.2 0.3 0.1
OV OV=1 1 0.7 0.2 0.3 0.1
Status word for: O BR CC 1 CC 0 OV OS OR STA RLO FC
Instruction depends on: Yes Yes Yes Yes Yes – – Yes Yes

52 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 53
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
ON ==0 OR NOT 1 1.5 0.5 0.6 0.1
Result=0
(CC 1=0) and (CC 0=0)
>0 Result>0 1 2.3 0.7 0.9 0.1
(CC 1=1) and (CC 0=0)
<0 Result<0 1 2.3 0.7 0.9 0.1
(CC 1=0) and (CC 0=1)
<>0 Result0 1 2.3 0.7 0.9 0.1
((CC 1=0) and (CC 0=1) or
(CC 1=1) and (CC 0=0))
<=0 Result<=0 1 0.7 0.2 0.3 0.1
((CC 1=0) and (CC 0=1) or
(CC 1=0) and (CC 0=0))
>=0 Result>=0 1 0.7 0.7 0.3 0.1
((CC 1=1) and (CC 0=0) or
(CC 1=0) and (CC 0=0))
(CC 1=1) and (CC 0=1)
OS OS=1 1 1.5 0.5 0.6 0.1
BR BR=1 1 1.5 0.5 0.6 0.1
OV OV=1 1 1.5 0.5 0.6 0.1
Status word for: ON BR CC 1 CC 0 OV OS OR STA RLO FC

54 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 55
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
X ==0 EXCLUSIVE OR 1 1.5 0.5 0.6 0.1
Result=0
(CC 1=0) and (CC 0=0)
>0 Result>0 1 2.3 0.7 0.9 0.1
(CC 1=1) and (CC 0=0)
<0 Result<0 1 2.3 0.7 0.9 0.1
(CC 1=0) and (CC 0=1)
<>0 Result0 1 1.5 0.5 0.6 0.1
((CC 1=0) and (CC 0=1) or
(CC 1=1) and (CC 0=0))
<=0 Result<=0 1 1.5 0.5 0.6 0.1
((CC 1=0) and (CC 0=1) or
(CC 1=0) and (CC 0=0))
>=0 Result>=0 1 1.5 0.5 0.6 0.1
((CC 1=1) and (CC 0=0) or
(CC 1=0) and (CC 0=0))
(CC 1=1) and (CC 0=1)
OS OS=1 1 0.7 0.2 0.3 0.1
BR BR=1 1 0.7 0.2 0.3 0.1
OV OV=1 1 0.7 0.2 0.3 0.1
Status word for: X BR CC 1 CC 0 OV OS OR STA RLO FC

56 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 57
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
XN ==0 EXCLUSIVE OR NOT 1 1.5 0.5 0.6 0.1
Result=0
(CC 1=0) and (CC 0=0)
>0 Result>0 1 2.3 0.7 0.9 0.1
(CC 1=1) and (CC 0=0)
<0 Result<0 1 2.3 0.7 0.9 0.1
(CC 1=0) and (CC 0=1)
<>0 Result0 1 2.3 0.7 0.9 0.1
((CC 1=0) and (CC 0=1) or
(CC 1=1) and (CC 0=0))
<=0 Result<=0 1 0.7 0.2 0.3 0.1
((CC 1=0) and (CC 0=1) or
(CC 1=0) and (CC 0=0))
>=0 Result>=0 1 0.7 0.7 0.3 0.1
((CC 1=1) and (CC 0=0) or
(CC 1=0) and (CC 0=0))
(CC 1=1) and (CC 0=1)
OS OS=1 1 1.5 0.5 0.6 0.1
BR BR=1 1 1.5 0.5 0.6 0.1
OV OV=1 1 1.5 0.5 0.6 0.1
Status word for: XN BR CC 1 CC 0 OV OS OR STA RLO FC

58 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 59
Edge-Triggered Instructions
Detection of an edge change. The current signal state of the RLO is

compared with the signal state of the instruction or “edge bit
memory”. FP detects a change in the RLO from “0” to “1”; FN
detects a change in the RLO from “1” to “0”.
In
tion Identifier
315 315
312* 314 312* 314
315-2 318-2 315-2 318-2
313 314* 313 314*
316-2 316-2
FP I/Q a.b Detecting the positive edge in 2 2.0 0.7 0.8 0.2 3.6+ 2.7+ 2.4+ 0.2+
M a.b the RLO. The bit addressed in 2 3.5 1.4 1.5 0.2 3.9+ 2.9+ 2.7+ 0.2+
L a.b
ab the instruction is the auxiliary 2 38
3.8 15
1.5 16
1.6 02
0.2 4 1+
4.1+ 2 9+
2.9+ 2 7+
2.7+ 0 2+
0.2+
DBX a.b edge bit memory. 2 6.7 2.0 4.0 0.2 5.7+ 3.7+ 3.6+ 0.2+
DIX a.b 2 6.7 2.0 4.0 0.2 5.7+ 3.7+ 3.6+ 0.2+
c[AR1,m] 2 – – – – + + + +
c[AR2,m] 2 – – – – + + + +
[AR1,m] 2 – – – – + + + +
[AR2,m] 2 – – – – + + + +
Parameter 2 – – – – + + + +
Status word for: FP BR CC 1 CC 0 OV OS OR STA RLO FC

(see page 21)

60 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 61
In-
tion Identifier
315 315
312* 314 312* 314
315-2 318-2 315-2 318-2
313 314* 313 314*
316-2 316-2
FN I/Q a.b Detecting the negtive edge in 2 2.6 0.9 1.0 0.2 3.8+ 2.9+ 2.6+ 0.2+
M a.b the RLO. The bit addressed in 2 3.8 1.6 1.6 0.2 4.1+ 3.1+ 2.8+ 0.2+
L a.b the intruction is the auxiliary 2 4.2 1.7 1.7 0.2 4.3+ 3.1+ 2.8+ 0.2+
DBX a.b edge bit memory. 2 6.8 2.2 4.1 0.2 5.8+ 4.0+ 3.7+ 0.2+
DIX a.b 2 6.8 2.2 4.1 0.2 5.8+ 4.0+ 3.7+ 0.2+
c[AR1,m] 2 – – – – + + + +
c[AR2,m] 2 – – – – + + + +
[AR1,m] 2 – – – – + + + +
[AR2,m] 2 – – – – + + + +
Parameter 2 – – – – + + + +
Status word for: FN BR CC 1 CC 0 OV OS OR STA RLO FC

(see page 21)

62 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 63
Setting/Resetting Bit Addresses
Assigning the value “1” or “0” or the RLO o the addressed instruc-
tion. The instructions can be dependent on the MCR.
In
In- Length
in
tion Identifier
315 315
312* 314 312* 314
315-2 318-2 315-2 318-2
313 314* 313 314*
316-2 316-2
S I/Q a.b Set input/output to “1” 1 2/2 0.7 0.3 0.3 0.2 3.3+ 2.2+ 2.2+ 0.2+
(MCR-dependent) 1.4 1.4 0.5 0.2 4.4+ 3.4+ 2.9+ 0.2+
M a.b Set bit memory to “1” 12/2 1.9 0.8 0.8 0.2 3.7+ 2.4+ 2.5+ 0.2+
(MCR-dependent) 3.9 3.0 2.3 0.2 4.4+ 3.6+ 3.0+ 0.2+
L a.b Set local data bit to “1” 2 3.0 1.2 1.3 0.2 3.8+ 2.4+ 2.5+ 0.2+
(MCR-dependent) 4.9 3.1 2.9 0.2 3.9+ 3.6+ 2.5+ 0.2+
DBX a.b Set data bit to “1” 2 6.2 3.3 3.7 0.2 5.5+ 3.3+ 3.5+ 0.2+
(MCR-dependent) 7.3 4.5 4.3 0.2 6.6+ 4.4+ 4.1+ 0.2+
DIX a.b Set instance data bit to “1” 2 6.2 3.3 3.7 0.2 5.5+ 3.3+ 3.5+ 0.2+
(MCR-dependent) 7.3 4.5 4.3 0.2 6.6+ 4.4+ 4.1+ 0.2+
c[AR1,m] Register–ind., area–internal 2 – – – – + + + +
c[AR2,m] (AR1) 2 – – – – + + + +
[AR1,m] Register–ind., area–internal 2 – – – – + + + +
[AR2,m] (AR2) 2 – – – – + + + +
Parameter Area-crossing via (AR1) 2 – – – – + + + +
Area-crossing via (AR2)
Via parameter
Status word for: S BR CC 1 CC 0 OV OS OR STA RLO FC
Instruction affects: – – – – – 0 Yes – 0

(see page 21)

64 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 65
In-
In Length
in
Word Direct Addressing Indirect Addressing 1
tion Identifier
315 315
312* 314 312* 314
315-2 318-2 315-2 318-2
313 314* 313 314*
316-2 316-2
R I/Q a.b Reset input/output to “0” 1 2/2 1.0 0.4 0.4 0.2 3.5+ 2.4+ 2.3+ 0.2+
(MCR-dependent) 1.4 1.4 0.5 0.2 4.6+ 3.5+ 3.0+ 0.2+
M a.b Set bit memory to “0” 1 2/2 2.2 0.9 0.9 0.2 3.8+ 2.5+ 2.6+ 0.2+
(MCR-dependent) 4.1 3.1 2.4 0.2 4.6+ 3.7+ 3.2+ 0.2+
L a.b Set local data bit to“ 0” 2 3.0 1.2 1.3 0.2 4.0+ 2.5+ 2.6+ 0.2+
(MCR-dependent) 5.1 3.2 3.0 0.2 4.1+ 3.7+ 2.7+ 0.2+
DBX a.b Set data bit to “0” 2 6.4 3.5 3.8 0.2 5.7+ 3.4+ 3.6+ 0.2+
(MCR-dependent) 7.3 4.6 4.3 0.2 6.7+ 4.5+ 4.3+ 0.2+
DIX a.b Set instance data bit to “0” 2 6.4 3.5 3.8 0.2 5.7+ 3.4+ 3.6+ 0.2+
(MCR-dependent) 7.3 4.6 4.3 0.2 6.7+ 4.5+ 4.3+ 0.2+
c[AR1,m] Register–ind., area–internal 2 – – – – + + + +
c[AR2,m] (AR1) 2 – – – – + + + +
[AR1,m] Register–ind., area–internal 2 – – – – + + + +
[AR2,m] (AR2) 2 – – – – + + + +
Via parameter
Status word for: R BR CC 1 CC 0 OV OS OR STA RLO FC

(see page 21)

66 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 67
In-
In Length
in
tion Identifier
315 315
312* 314 312* 314
315-2 318-2 315-2 318-2
313 314* 313 314*
316-2 316-2
= I/Q a.b Assign RLO to input/output 1 2/2 0.7 0.2 0.3 0.2 3.3+ 2.2+ 2.2+ 0.2+
(MCR-dependent) 1.4 1.4 0.5 0.2 4.4+ 3.4+ 2.9+ 0.2+
M a.b Assign RLO to bit memory 1 2/2 2.2 0.9 0.9 0.2 3.7+ 2.4+ 2.5+ 0.2+
(MCR-dependent) 3.9 3.0 2.3 0.2 4.4+ 3.6+ 3.0+ 0.2+
L a.b Assign RLO to local data bit 2 2.7 1.0 1.1 0.2 3.8+ 2.4+ 2.5+ 0.2+
(MCR-dependent) 4.6 3.1 2.6 0.2 3.6+ 3.6+ 2.3+ 0.2+
DBX a.b Assign RLO to data bit 2 6.4 3.3 3.8 0.2 5.7+ 3.3+ 3.6+ 0.2+
(MCR-dependent) 7.5 5.3 4.4 0.2 6.7+ 5.3+ 4.3+ 0.2+
DIX a.b Assign RLO to instance data bit 2 6.4 3.3 3.8 0.2 5.7+ 3.3+ 3.6+ 0.2+
(MCR-dependent) 7.5 5.3 4.4 0.2 6.7+ 5.3+ 4.3+ 0.2+
c[AR1,m] Register–ind., area–inter- 2 – – – – + + + +
c[AR2,m] nal(AR1) 2 – – – – + + + +
[AR1,m] Register–ind., area–inter- 2 – – – – + + + +
[AR2,m] nal(AR2) 2 – – – – + + + +
Via parameter
Status word for: = BR CC 1 CC 0 OV OS OR STA RLO FC

(see page 21)

68 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 69
Instructions Directly Affecting the RLO
The following instructions have a direct effect on the RLO.
In- Length
Address
Identifier Words
tion
312*/313 314/314* 315/315/316 318-2
CLR Set RLO to ”0” 1 0.7 0.2 0.3 0.1
Status word for: CLR BR CC 1 CC 0 OV OS OR STA RLO FC
Instruction affects: – – – – – 0 0 0 0
SET Set RLO to ”1” 1 0.7 0.2 0.3 0.1
Status word for: SET BR CC 1 CC 0 OV OS OR STA RLO FC
NOT Negate RLO 1 0.7 0.2 0.3 0.1
Status word for: NOT BR CC 1 CC 0 OV OS OR STA RLO FC
Instruction depends on: – – – – – Yes – Yes –
Instruction affects: – – – – – – 1 Yes –
SAVE Save RLO to the BR bit 1 0.7 0.2 0.3 0.1
Status word for: SAVE BR CC 1 CC 0 OV OS OR STA RLO FC
Instruction affects: Yes – – – – – – – –

70 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 71
Timer Instructions
Starting or resetting a timer (addressed directly or via a parameter).

The time value must be in ACCU1-L.
In-
In Length
in
tion Identifier
315 315
312* 314 312* 314
315-2 318-2 315-2 318-2
313 314* 313 314*
316-2 316-2
SP Tf Start timer as pulse
p on edge
g 1 2/2 14.0 8.4 9.2 0.2 14.3+ 8.8+ 9.7+ 0.2+
change from “0” to “1”
Timer para. 2 – – – – + + + +
SE Tf Start timer as exded ppulse on 1 2/2 14.0 8.4 9.2 0.2 14.3+ 8.8+ 9.7+ 0.2+
edge change from “0” to “1”
Timer para. 2 – – – – + + + +
SD Tf Start timer as ON delayy on edge
g 1 2/2 14.7 9.0 9.7 0.2 15.0+ 9.4+ 10.2+ 0.2+
Timer para 2 – – – – + + + +
SS Tf Start timer as retive ON delay
y 1 2/2 14.7 9.0 9.7 0.2 15.0+ 9.4+ 10.2+ 0.2+
on edge change from “0” to “1”
Timer para. 2 – – – – + + + +
SF Tf Start timer as OFF delayy on 1 2/2 15.0 9.2 10.0 0.2 15.4+ 9.6+ 10.5+ 0.2+
Timer para. 2 – – – – + + + +
Status word for: SP, SE, SD, SS, SF BR CC 1 CC 0 OV OS OR STA RLO FC
Instruction affects: – – – – – 0 – – 0

(see page 21)

72 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 73
In-
In Length
in
tion Identifier
315 315
312* 314 312* 314
315-2 318-2 315-2 318-2
313 314* 313 314*
316-2 316-2
FR Tf Enable timer for restarting on 1 2/2 3.9 2.0 2.1 0.2 4.3+ 2.5+ 2.7+ 0.2+
edge change from “0”
0 to “1”1
Timer para. (
(reset edge bit memory for 2 – – – – + + + +
starting timer)
R Tf Reset timer 1 2/2 3.5 1.8 1.8 0.2 3.8+ 2.2+ 2.4+ 0.2+
Timer para. 2 – – – – + + + +
Status word for: FR, R BR CC 1 CC 0 OV OS OR STA RLO FC

(see page 21)

74 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 75
Counter Instructions
The count value is in ACCU1-L or in the address transferred as

parameter.
In
In- Length
in
tion Identifier
315 315
312* 314 312* 314
315-2 318-2 315-2 318-2
313 314* 313 314*
316-2 316-2
S Cf Presetting
g of counter on edge
g 1 2/2 9.8 6.0 6.6 0.2 10.2+ 6.4+ 7.1+ 0.2+
Counter p. 2 – – – – + + + +
R Cf Reset counter to “0” 1 2/2 3.4 1.7 1.8 0.2 3.8+ 2.2+ 2.3+ 0.2+
Counter p. 2 – – – – + + + +
CU Cf Increment counter byy 1 on edge
g 1 2/2 4.8 2.6 2.8 0.2 5.2+ 3.1+ 3.4+ 0.2+
Counter p. 2 – – – – + + + +
CD Cf Decrement counter byy 1 on 1 2/2 5.1 2.8 3.0 0.2 5.3+ 3.2+ 3.5+ 0.2+
Counter p. 2 – – – – + + + +
FR Cf Enable counter on edge change 1 2/2 4.0 2.1 2.2 0.2 4.3+ 2.5+ 2.7 0.2+
from “0” 1 (reset edge bit
0 to “1”
Counter p. memory for up and down 2 – – – – + + + +
counting)
Status word for: S, R, CU, CD, FR BR CC 1 CC 0 OV OS OR STA RLO FC

(see page 21)

76 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 77
Load Instructions
Loading address identifiers into ACCU1. The conts of ACCU1 and

ACCU2 are saved first. The status word is not affected.
In-
In Length
in
tion Identifier
315 315
312* 314 312* 314
315-2 318-2 315-2 318-2
313 314* 313 314*
316-2 316-2
L Load ...
IB a Input byte 1 2/2 1.7 0.6 0.6 0.1 2.7+ 2.2+ 1.7+ 0.1+
QB a Output byte 1 2/2 1.7 0.6 0.6 0.1 2.7+ 2.2+ 1.7+ 0.1+
PIB a Peripheral input byte 2 < 30/ < 24/ <24 0.1 < 40/ 26+/ < 27 0.1+
< 21 3 < 533 < 30 3 <58 3/
/< 88 <92 4
4
MB a Bit memory byte 1 2/2 1.9 0.7 0.8 0.1 2.8+ 2.2+ 1.8+ 0.1+
LB a Local data byte 2 2.9 1.0 1.1 0.1 3.2+ 2.2+ 2.0+ 0.1+
DBB a Data byte 2 50
5.0 28
2.8 28
2.8 01
0.1 4 3+
4.3+ 2 8+
2.8+ 2 6+
2.6+ 0 1+
0.1+
DIB a Instance data byte 2 6.8 2.8 2.8 0.1 4.3+ 2.8+ 2.6+ 0.1+
... into ACCU1 2
g[AR1,m] Register–ind., area–internal (AR1) 2 – – – – + + + +
g[AR2,m] Register–ind., area–internal (AR2) 2 – – – – + + + +
B[AR1,m] Area-crossing (AR1) 2 – – – – + + + +
B[AR2,m] Area-crossing (AR2) 2 – – – – + + + +

(see page 21)
3 Integrated digital I/O for CPU 312* and 314*
4 Integrated analog I/O for CPU 314*

78 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 79
In-
In Length
in
tion Identifier
315 315
312* 314 312* 314
315-2 318-2 315-2 318-2
313 314* 313 314*
316-2 316-2
L Load ...
IW a Input word 1 2/2 2.4 0.8 0.9 0.1 2.9+ 2.1+ 1.9+ 0.1+
QW a Output word 1 2/2 2.4 0.8 0.9 0.1 2.9+ 2.1+ 1.9+ 0.1+
PIW a Peripheral input word < 40 < 29/ < 30 0.1 < 46/ 30+/ < 32 0.1+
<533/ < 30 3 <583/
<884 <92 4
MW a Bit memory word 2 2.7 1.0 1.1 0.1 3.2+ 2.4+ 2.1+ 0.1+
LW a Local data word 2 3.0 1.1 1.3 0.1 3.7+ 2.8+ 2.3+ 0.1+
DBW a Data word 1 2/2 57
5.7 33
3.3 33
3.3 01
0.1 5 2+
5.2+ 3 7+
3.7+ 3 2+
3.2+ 0 1+
0.1+
DIW a Instance data word 1 2/2 5.7 3.3 3.3 0.1 5.2+ 3.7+ 3.2+ 0.1+
... into ACCU1
h[AR1,m] Register–ind., area–internal (AR1) 2 – – – – + + + +
h[AR2,m] Register–ind., area–internal (AR2) 2 – – – – + + + +
W[AR1,m] Area-crossing via (AR1) 2 – – – – + + + +
W[AR2,m] Area-crossing via (AR2) 2 – – – – + + + +

(see page 21)

80 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 81
In-
In Length
in
tion Identifier
315 315
312* 314 312* 314
315-2 318-2 315-2 318-2
313 314* 313 314*
316-2 316-2
L Load ...
ID a Input double word 1 2/2 2.9 0.9 1.1 0.2 3.2+ 2.4+ 2.1+ 0.2+
QD a Output double word 1 2/2 2.9 0.9 1.1 0.2 3.2+ 2.4+ 2.1+ 0.2+
PID a Peripheral input double word 2 < 45 37/ < 40 0.2 < 65 39+/ < 42 0.2+
<1903 <2003
MD a Bit memory double word 1 2/2 3.4 1.4 1.5 0.2 3.7+ 2.7+ 2.5+ 0.2+
LD a Local data double word 2 3.7 1.5 1.6 0.2 4.2+ 3.1+ 2.7+ 0.2+
DBD a Data double word 2 70
7.0 44
4.4 43
4.3 02
0.2 6 5+
6.5+ 4 7+
4.7+ 4 2+
4.2+ 0 2+
0.2+
DID a Instance data double word 2 7.0 4.4 4.3 0.2 6.5+ 4.7+ 4.2+ 0.2+
... into ACCU1
i[AR1.m] Register–ind., area–internal (AR1) 2 – – – – + + + +
i[AR2,m] Register–ind., area–internal (AR2) 2 – – – – + + + +
D[AR1.m] Area-crossing via (AR1) 2 – – – – + + + +
D[AR2,m] Area-crossing via (AR2) 2 – – – – + + + +

(see page 21)

82 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 83
In-
In Length
in
tion Identifier
315 315
312* 314 312* 314
315-2 318-2 315-2 318-2
313 314* 313 314*
316-2 316-2
L Load ...
k8 8-bit constant into ACCU1-LL 1 1.7 0.6 0.6 0.1 – – – –
k16 16-bit constant into ACCU1-L 2 1.7 0.6 0.6 0.1 – – – –
k32 32-bit constant into ACCU1 3 2.0 0.7 0.8 0.15 – – – –
Parameter Load constant into ACCU1 2 – – – – + + + +
(addressed via parameter)
L 2#n Load 16-bit binary constant into 2 1.7 0.6 0.6 0.1 – – – –
ACCU1-L
Load 32-bit binary constant into 3 2.0 0.7 0.7 0.15 – – – –
ACCU1
L B#8#p Load 8-bit hexadecimal constant into 1 1.7 0.6 0.6 0.1 – – – –
ACCU1-L
W#16#p Load 16-bit hexadecimal constant 2 1.7 0.6 0.6 0.1 – – – –
into ACCU1-L
DW#16#p Load 32-bit hexadecimal constant 3 2.0 0.7 0.7 0.15 – – – –
into ACCU1-L

(see page 21)

84 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 85
In-
In Length
g
in Typical Execution Time in s
tion Words
Identifier
315/315-2/
312*/313 314/314* 318-2
316-2
L ’x’ Load 1 characters 1.2 0.6 0.7 0.1
L ’xx’ Load 2 characters 2 1.2 0.6 0.7 0.1
L ’xxx’ Load 3 characters 1.4 0.7 0.88 0.15
L ’xxxx’ Load 4 characters 3 1.4 0.7 0.88 0.15
L D# date Load IEC date (BCD) 3 1.2 0.6 0.8 0.15
L S5T# time Load S5 time constant (16 bits) 2 1.2 0.6 0.8 0.1
value
L TOD# time Load 32-bit time constant 3 1.4 0.93 0.88 0.15
value IEC time of day
L T# time Load 16-bit timer constant 2 1.2 0.7 0.88 0.1
value
al e
Load 32-bit timer constant 3 1.4 0.6 0.88 0.15
L C# count Load 16-bit counter constant 2 1.2 0.6 0.88 0.1
value
L P# bit Load bit pointer 3 1.4 0.7 0.88 0.15
pointer
L L# integer Load 32 bit integer constant 3 1.4 0.7 0.88 0.15
L Real num- Load real number 3 1.4 0.93 0.88 0.15
ber

86 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 87
Load Instructions for Timers and

Counters
Loading a time value or count value into ACCU1. The contents of

ACCU1 are first saved to ACCU2. The bits of the status word are
not affected.
In-
In Length
in
tion Identifier
315 315
312* 314 312* 314
315-2 318-2 315-2 318-2
313 314* 313 314*
316-2 316-2
L Tf Load time value 1 2/2 3.1 1.6 1.7 0.1 5.2+ 0.8+ 2.1+ 0.1+
Timer para. Load time value (addressed via 2 – – – – + + + +
parameter)
L Cf Load count value 1 2/2 2.9 1.6 1.5 0.1 5.2+ 0.8+ 2.1+ 0.1+
Counter Load count value (addressed via 2 – – – – + + + +
para. parameter)
LD Tf Load time value in BCD 1 2/2 8.1 5.4 5.4 0.3 15.6+ 4.6+ 5.9+ 0.3+
Timer para. Load time value in BCD 2 – – – – + + + +
(addressed via parameter)
LD Cf Load count value in BCD 1 2/2 7.4 5.0 4.9 0.3 14.2+ 4.2+ 5.4+ 0.3+
Counter Load count value (addressed via 2 – – – – + + + +
para. parameter)

(see page 21)

88 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 89
Transfer Instructions
Transferring the contents of ACCU1 to the addressed Inrand. The

status word is not affected. Remember that some transfer instruc-
tions depend on the MCR.
In
In- Length
in
tion Identifier
315 315
312* 314 312* 314
315-2 318-2 315-2 318-2
313 314* 313 314*
316 316
T Transfer contents of
ACCU1-LL to ...
IB a input byte 1 2/2 0.7 0.2 0.3 0.1 2.0+ 1.6+ 1.2+ 0.1+
(MCR-dependent) 2.6 1.3 1.4 0.1 2.5+ 2.0+ 1.6+ 0.1+
QB a output byte 1 2/2 0.7 0.2 0.3 0.1 2.0+ 1.6+ 1.2+ 0.1+
(MCR-dependent) 2.6 1.3 1.4 0.1 2.5+ 2.0+ 1.6+ 0.1+
PQB a peripheral output byte 1 3/2 < 30 24/ < 24 0.1 <35.5/ 25+/ < 27 0.1+
<404/ < 19 4 <45 4/
<475 < 50 5
(MCR-dependent) < 32 25/ < 25 0.1 <36.5/ 26+/ < 28 0.1+
<414/ < 20 4 < 46 4
<485 < 51 5

(see page 21)
3 Direct addressing with PQB 0 to 255

90 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 91
In-
In Length
in
tion Identifier
315 315
312* 314 312* 314
315-2 318-2 315-2 318-2
313 314* 313 314*
316 316
T MB a bit memory byte 1 2/2 0.9 0.4 0.4 0.1 2.2+ 1.7+ 1.3+ 0.1+
(MCR-dependent) 2.7 1.8 1.5 0.1 2.7+ 2.2+ 1.7+ 0.1+
LB a local data byte 2 1.5 0.6 0.6 0.1 2.5+ 1.8+ 1.5+ 0.1+
(MCR-dependent) 3.1 2.2 1.8 0.1 3.3+ 2.4+ 2.0 0.1+
DBB a data byte 2 4.6 2.9 2.5 0.1 3.9+ 2.7+ 2.3+ 0.1+
(MCR-dependent) 5.4 3.5 3.0 0.1 4.7+ 3.3+ 2.8+ 0.1+
DIB a instance data byte 2 4.6 2.9 2.5 0.1 3.9+ 2.7+ 2.3+ 0.1+
(MCR-dependent) 5.4 3.5 3.0 0.1 4.7+ 3.3+ 2.8+ 0.1+
T g[AR1.m] Register–ind., area–internal 2 – – – – + + + +
(AR1)
g[AR2,m] Register–ind., area–internal 2 – – – – + + + +
(AR2)
B[AR1.m] Area–crossing (AR1) 2 – – – – + + + +
B[AR2,m] Area–crossing (AR2) 2 – – – – + + + +

(see page 21)

92 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 93
In-
In Length
in
tion Identifier
315 315
312* 314 312* 314
315-2 318-2 315-2 318-2
313 314* 313 314*
316 316
ACCU1-L to ...
IW input word 1 2/2 1.4 0.5 0.5 0.1 2.3+ 1.8+ 1.5+ 0.1+
(MCR-dependent) 2.7 1.4 1.5 0.1 2.8+ 2.2+ 1.8+ 0.1+
QW output word 1 2/2 1.4 0.5 0.5 0.1 2.3+ 1.8+ 1.5+ 0.1+
(MCR-dependent) 2.7 1.4 1.5 0.1 2.8+ 2.2+ 1.8+ 0.1+
PQW peripheral output word 1 3/2 < 34 <27/ < 27 0.1 <40 29+/ < 31 0.1+
<42 4/ <46 4/
< 50 5 <53 5
(MCR-dependent) < 36 <28/ < 28 0.1 < 42 <30+/ < 32 0.1+
<44 4/ <48 4/
< 52 5 <55 5
MW bit memory word 1 2/2 1.7 0.7 0.8 0.1 2.7+ 2.1+ 1.7+ 0.1+
(MCR-dependent) 3.0 2.0 1.8 0.1 3.2+ 2.6+ 2.1+ 0.1+
LW local data word 2 2.0 0.8 0.9 0.1 3.0+ 2.2+ 1.8+ 0.1+
(MCR-dependent) 3.4 2.4 2.0 0.1 3.8+ 2.8+ 2.3+ 0.1+
DBW data word 2 5.2 3.6 3.0 0.1 4.7+ 3.5+ 2.9+ 0.1+
(MCR-dependent) 6.1 4.2 3.5 0.1 5.6+ 4.1+ 3.4+ 0.1+
DIW instance data word 2 5.2 3.6 3.0 0.1 4.7+ 3.5+ 2.9+ 0.1+
(MCR-dependent) 6.1 4.2 3.5 0.1 5.6+ 4.1+ 3.4+ 0.1+
T h[AR1.m] Register–ind., area–internal(AR1) 2 – – – – + + + +
h[AR2,m] Register–ind., area–internal(AR2) 2 – – – – + + + +
W[AR1.m] Area–crossing (AR1) 2 – – – – + + + +
W[AR2,m] Area–crossing (AR2) 2 – – – – + + + +
(see page 21)
3 Direct addressing with PQW 0 to 254
4 Integrated digital I/O for CPU 314*

94 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 95
In-
In Length
in
tion Identifier
315 315
312* 314 312* 314
315-2 318-2 315-2 318-2
313 314* 313 314*
316 316
ACCU1 to ...
ID input double word 1 2/2 2.0 0.7 0.8 0.2 2.7+ 2.0+ 1.7+ 0.2+
(MCR-dependent) 3.0 1.7 1.8 0.2 3.2+ 2.4+ 2.1+ 0.2+
QD output double word 1 2/2 2.0 0.7 0.8 0.2 2.7+ 2.0+ 1.7+ 0.2+
(MCR-dependent) 3.0 1.7 1.8 0.2 3.2+ 2.4+ 2.1+ 0.2+
PQD peripheral output double word 1 2/2 < 38 < 31 < 31 0.2 < 42 < 32+ < 34 0.2+
(MCR-dependent) < 39 < 32 < 32 0.2 < 43 < 35+ < 35 0.2+
MD bit memory double word 1 2/2 2.7 1.2 1.3 0.2 3.3+ 2.7+ 2.2+ 0.2+
(MCR-dependent) 3.7 2.0 2.3 0.2 3.8+ 3.2+ 2.6+ 0.2+
LD local data double word 2 3.0 1.2 1.4 0.2 5.3+ 3.3+ 3.0+ 0.2+
(MCR-dependent) 4.1 2.2 2.6 0.2 6.2+ 3.9+ 3.5+ 0.2+
DBD data double word 2 6.7 4.9 4.1 0.2 6.2+ 4.9+ 4.0+ 0.2+
(MCR-dependent) 7.6 5.5 4.6 0.2 7.1+ 5.5+ 4.5+ 0.2+
DID instance data double word 2 6.7 4.9 4.1 0.2 6.2+ 4.9+ 4.0+ 0.2+
(MCR-dependent) 7.6 5.5 4.6 0.2 7.2+ 5.5+ 4.5+ 0.2+
T i[AR1.m] Register–ind., area–internal 2 – – – – + + + +
(AR1)
i[AR2,m] Register–ind., area–internal 2 – – – – + + + +
(AR2)
D[AR1.m] Area–crossing (AR1) 2 – – – – + + + +
D[AR2,m] Area–crossing (AR2) 2 – – – – + + + +

(see page 21)

96 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 97
Load and Transfer Instructions for

Address Registers
Loading a double word from a memory area or register into AR1 or

AR2.
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
LAR1 Load contents from ...
– ACCU1 1 0.7 0.2 0.3 0.2
AR2 Address register 2 1 0.7 0.2 0.3 0.2
DBD a Data double word 2 6.3 4.0 3.8 0.3
DID a Instance data double word 2 6.3 4.0 3.8 0.3
m 32-bit constant as pointer 3 1.4 0.4 0.5 0.2
LD a Local data double word 2 3.4 1.4 1.5 0.3
MD a Bit memory double word 2 3.0 1.2 1.4 0.3
... into AR1
LAR2 Load contents from ...
– ACCU1 1 0.7 0.2 0.3 0.2
MD a Bit memory double word 2 3.0 1.2 1.4 0.3
... into AR2

98 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 99
Transferring a double word from AR1 or AR2 to a memory area or

register. The status word is not affected.
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
CAR1 Transfer contents of AR1 to ...
– ACCU1 1 1.7 0.4 0.7 0.1
AR2 Address register 2 1 0.7 0.2 0.3 0.2
MD a Bit memory double word 2
CAR2 Transfer contents of AR2 to ...
– ACCU1 1 1.7 0.4 0.7 0.1
MD a Bit memory double word 2
CAR – Exchange the contents of AR1 1 1.4 0.7 0.5 0.4
and AR2

100 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 101
Load and Transfer Instructions for the

Status Word
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
L STW Load status word 1 into ACCU1 2.4 1.4 1.5 0.1
Status word for: L STW BR CC 1 CC 0 OV OS OR STA RLO FC
Instruction depends on: Yes Yes Yes Yes Yes 0 0 Yes 0
Instruction affects: – – – – – – – – –
T STW Transfer ACCU1 (bits 0 to 8) to 2.2 1.5 1.4 0.1
the status word1
Status word for: T STW BR CC 1 CC 0 OV OS OR STA RLO FC
Instruction affects: Yes Yes Yes Yes Yes – – Yes –
1 For the structure of the status word see page 15

102 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 103
Load Instructions for DB Number and

DB Length
Loading the number/length of a data block into ACCU1. The old

contents of ACCU1 are saved to ACCU2. The condition code bits
are not affected.
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
L DBNO Load number of data block 1 5.1 3.1 3.3 0.1
L DINO Load number of instance data 1 5.1 3.1 3.3 0.1
block
L DBLG Load length of data block into 1 1.7 0.6 0.6 0.1
byte
L DILG Load length of instance data 1 1.7 0.6 0.6 0.1
block into byte

104 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 105
Integer Math (16 Bits) CPU 318–2: ACCU3 and ACCU4 are then transferred to ACCU2
and ACCU3.
Math instructions on two 16-bit words. The result is in ACCU1 and
ACCU1-L, resp.
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
+I – Add 2 integers (16 bits) 1 2.4 1.5 1.5 0.1
(ACCU1-L)=(ACCU1-L)+
(ACCU2-L)
–I – Subtract 1 integer from another 1 2.6 1.8 1.6 0.1
(16 bits)
(ACCU1-L)=(ACCU2-L)–
(ACCU1-L)
*I – Multiply 1 integer by another 1 3.6 2.1 2.4 0.8

(16 bits)
(ACCU1)=(ACCU2-L)*
(ACCU1-L)
/I – Divide 1 integer by another 1 5.0 3.2 3.4 0.8
(16 bits)
(ACCU1-L)=
(ACCU2-L):(ACCU1-L)
The remainder is in ACCU1-H
Status word for: +I, –I,*I, /I BR CC 1 CC 0 OV OS OR STA RLO FC
Instruction affects: – Yes Yes Yes Yes – – – –

106 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 107
Integer Math (32 Bits) CPU 318–2: ACCU3 and ACCU4 are then transferred to ACCU2
and ACCU3.
Math instructions on two 32-bit words. The result is in ACCU1.
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
+D – Add 2 integers (32 bits) 1 3.1 1.8 2.0 0.1
(ACCU1)=(ACCU2)+
(ACCU1)
–D – Subtract 1 integer from another 1 4.0 2.3 2.7 0.1
(32 bits)
(ACCU1)=(ACCU2)–
(ACCU1)
*D – Multiply 1 integer by another 1 13.5 8.2 9.9 1.3

(32 bits)
(ACCU1)=(ACCU2)*
(ACCU1)
/D – Divide 1 integer by another 1 14.8 6.5 10.8 1.3
(32 bits)
(ACCU1)=(ACCU2):
(ACCU1)
MOD – Divide 1 integer by another 1 15.5 6.4 11.3 1.3
(32 bits) and load the remainder
into ACCU1:
(ACCU1)=remainder of
[(ACCU2):(ACCU1)]
Status word for: +D, –D,*D, /D, MOD BR CC 1 CC 0 OV OS OR STA RLO FC

108 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 109
Floating-Point Math (32 Bits) CPU 318–2: ACCU3 and ACCU4 are then transferred to ACCU2
and ACCU3.
The result of the math instruction is in ACCU1. The execution time
of the instruction depends on the value to be calculated.
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
+R – Add 2 real numbers (32 bits) 1 < 60 < 50 < 35 0.6
(ACCU1)= (ACCU2)+(ACCU1)
–R – Subtract 1 real number from 1 < 60 < 50 < 35 0.6
another (32 bits)
(ACCU1)= (ACCU2)–(ACCU1)
*R – Multiply 1 real number by another 1 < 60 < 50 < 35 1.4
(32 bits)
(ACCU1)=(ACCU2)*(ACCU1)
/R – Divide 1 real number by another 1 < 60 < 50 < 40 2.1
(32 bits)
(ACCU1)=(ACCU2):(ACCU1)
Status word for: +R, –R, *R, /R BR CC 1 CC 0 OV OS OR STA RLO FC
NEGR – Negate the real number in ACCU1 1 0.7 1.0 0.3 0.1
ABS – Form the absolute value of the real 1 0.7 0.4 0.3 0.1
number in ACCU1
Status word for: NEGR, ABS BR CC 1 CC 0 OV OS OR STA RLO FC

110 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 111
Square Root and Square Instructions

(32 Bits)
The result of the instruction is in ACCU1. The instructions can be

interrupted.
In- Length
Address
Identifier
tion Words
315/315-2/
312* 313/314/314* 318-2
316-2
SQRT – Calculate the square root of a real 1 – < 1000 < 1000 40
number in ACCCU1
SQR – Form the square of a real number 1 – < 300 < 300 1,4
in ACCU1
Status word for: SQRT, SQR BR CC 1 CC 0 OV OS OR STA RLO FC

112 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 113
Logarithmic Function (32 Bits)
The result of the logarithmic function is in ACCU1. The instruc-

tions can be interrupted.
In- Length
Address
Identifier
tion Words
315/315-2/
312* 313/314/314* 318-2
316-2
LN – Form the natural logarithm of a 1 – < 650 < 650 < 35
real number in ACCU1
EXP – Calculate the exponential value 1 – < 1500 < 1500 < 35
of a real number in ACCU1 to
the base e (= 2.71828)
Status word for: LN, EXP BR CC 1 CC 0 OV OS OR STA RLO FC

114 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 115
Trigonometrical Functions (32 Bits)
The result of the instruction is in ACCU1. The instructions can be

interrupted.
In- Length
Address
Identifier
tion Words
315/315-2/
312* 313/314/314* 318-2
316-2
SIN – Calculate the sine of a real number 1 – < 900 < 900 31
ASIN – Calculate the arcsine of a real 1 – < 2500 < 2500 74
number
COS – Calculate the cosine of a real num- 1 – < 900 < 900 32
ber
ACOS – Calculate the arccosine of a real 1 – < 2500 < 2500 77
number
TAN – Calculate the tangent of a real 1 – < 900 < 900 35
number
ATAN – Calculate the arctangent of a real 1 – < 900 < 900 32
number
Status word for: SIN, ASIN, COS, BR CC 1 CC 0 OV OS OR STA RLO FC
ACOS, TAN, ATAN

116 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 117
Adding Constants
Adding integer constants and storing the result in ACCU1. The

condition code bits are not affected.
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
+ i8 Add an 8-bit integer constant 1 0.7 0.2 0.3 0.1
+ i16 Add a 16-bit integer constant 2 0.7 0.2 0.3 0.1
+ i32 Add a 32-bit integer constant 3 1.5 0.4 0.6 0.15

118 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 119
Adding Using Address Registers
Adding a 16-bit integer to the contents of the address register. The

value is in the instruction or in ACCU1-L. The condition code bits
are not affected.
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
+AR1 – Add the contents of ACCU1-L 1 0.7 0.3 0.3 0.2
to those of AR1
+AR1 m Add a pointer constant to the 2 0.7 0.6 0.3 0.2
contents of AR1
+AR2 – Add the contents of ACCU1-L 1 0.7 0.3 0.3 0.2
to those of AR2
+AR2 m Add pointer constant to the con- 2 0.7 0.6 0.3 0.2
tents of AR2

120 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 121
Comparison Instructions with Integers

(16 Bits)
Comparing the 16-bit integers in ACCU1-L and ACCU2-L.

RLO = 1 if the condition is satisfied.
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
==I – ACCU2-L=ACCU1-L 1 2.3 1.4 1.4 0.1
<>I – ACCU2-LACCU1-L 1 2.4 1.6 1.5 0.1
<I – ACCU2-L<ACCU1-L 1 2.4 1.6 1.5 0.1
<=I – ACCU2-L<=ACCU1-L 1 2.3 1.4 1.4 0.1
>I – ACCU2-L>ACCU1-L 1 2.4 1.3 1.5 0.1
>=I – ACCU2-L>=ACCU1-L 1 2.3 1.4 1.4 0.1
Status word for: ==I, <>I, <I, <=I, >I, BR CC 1 CC 0 OV OS OR STA RLO FC
>=I
Instruction affects: – Yes Yes 0 – 0 Yes Yes 1

122 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 123
Comparison Instructions with Integers

(32 Bits)
Comparing the 32-bit integers in ACCU1 and ACCU2.

RLO = 1 if the condition is satisfied.
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
==D – ACCU2=ACCU1 1 3.1 1.9 2.0 0.1
<>D – ACCU2ACCU1 1 3.1 1.9 2.0 0.1
<D – ACCU2<ACCU1 1 3.1 1.9 2.0 0.1
<=D – ACCU2<=ACCU1 1 3.1 1.9 2.0 0.1
>D – ACCU2>ACCU1 1 3.1 1.9 2.0 0.1
>=D – ACCU2>=ACCU1 1 3.1 1.9 2.0 0.1
Status word for: ==D,< >D, <D, <=D, >D, BR CC 1 CC 0 OV OS OR STA RLO FC
>=D
Instruction affects: – Yes Yes 0 – 0 Yes Yes 1

124 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 125
Comparison Instructions with Real

Numbers (32 Bits)
Comparing the 32-bit real numbers in ACCU1 and ACCU2.

RLO = 1 if the condition is satisfied. The execution time of the
instruction depends on the value to be compared.
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
==R – ACCU2=ACCU1 1 < 70 < 50 < 45 0.4
<>R – ACCU2ACCU1 1 < 70 < 50 < 45 0.4
<R – ACCU2<ACCU1 1 < 70 < 50 < 45 0.4
<=R – ACCU2<=ACCU1 1 < 70 < 50 < 45 0.4
>R – ACCU2>ACCU1 1 < 70 < 50 < 45 0.4
>=R – ACCU2>=ACCU1 1 < 70 < 50 < 45 0.4
Status word for: ==R, <>R, <R, <=R, BR CC 1 CC 0 OV OS OR STA RLO FC
>R, >=R
Instruction affects: – Yes Yes Yes Yes 0 Yes Yes 1

126 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 127
Shift Instructions
Shifting the contents of ACCU1 and ACCU1-L to the left or right

by the specified number of places. If no address identifier is
specified, shift the number of places into ACCU2-LL. Any posi-
tions that become free are padded with zeros or the sign. The last
bit shifted is in condition code bit CC 1.
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
SLW – Shift the contents of ACCU1-L to 1 3.0 1.5 2.0 0.1
the left
left. Positions that become free
SLW 0 ... 15 are provided with zeros. 1.8 0.6 0.7 0.1
SLD – Shift the contents of ACCU1 to the 1 4.5 1.7 3.1 0.1
left Positions that become free are
left.
SLD 0 ... 32 provided with zeros. 4.9 2.9 3.1 0.1
SRW – Shift the contents of ACCU1-L to 1 3.0 1.5 2.0 0.1
right Positions that become
the right.Positions
SRW 0 ... 15 free are provided with zeros. 1.8 0.6 0.7 0.1
SRD – Shift the contents of ACCU1 to the 1 4.5 1.7 3.1 0.1
right Positions that become free are
right.Positions
SRD 0 ... 32 provided with zeros. 4.9 2.9 3.2 0.1
SSI – Shift the contents of ACCU1-L 1 2.9 1.6 1.8 0.1
with sign to the right.Positions that
SSI 0 ... 15 b
become ffree are provided
id d with
i h the
h 1.8 0.6
6 0.7 0.1
sign (bit 15).
Status word for: SLW, SLD, SRW, SRD, BR CC 1 CC 0 OV OS OR STA RLO FC
SSI
Instruction affects: – Yes Yes Yes – – – – –

128 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 129
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
SSD – Shift the contents of ACCU1 with 1 4.5 1.7 3.1 0.1
sign to the right 49
4.9 29
2.9 32
3.2 01
0.1
SSD 0 ... 32
Status word for: SSD BR CC 1 CC 0 OV OS OR STA RLO FC

130 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 131
Rotate Instructions
Rotate the contents of ACCU1 to the left or right by the specified

number of places. If no address identifier is specified, rotate the
number of places into ACCU2-LL.
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
RLD – Rotate the contents of ACCU1 1 4.8 3.3 3.3 0.1
to the left 53
5.3 34
3.4 34
3.4 01
0.1
RLD 0 ... 32
RRD – Rotate the contents of ACCU1 1 5.0 3.3 3.5 0.1
to the right 54
5.4 34
3.4 35
3.5 01
0.1
RRD 0 ... 32
Status word for: RLD, RRD BR CC 1 CC 0 OV OS OR STA RLO FC
RLDA – Rotate the contents of ACCU1 2.9 1.9 1.9 0.1
one bit position to the left
through condition code bit
CC 1
RRDA – Rotate the contents of ACCU1 2.9 1.9 1.9 0.1
one bit position to the right
through condition code bit
CC 1
Status word for: RLDA, RRDA BR CC 1 CC 0 OV OS OR STA RLO FC
Instruction affects: – Yes 0 0 – – – – –

132 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 133
Accumulator Transfer Instructions,

Incrementing and Decrementing
The status word is not affected.
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
CAW – Reverse the order of the bytes in 1 0.7 0.2 0.3 0.1
ACCU1-L.
LL, LH becomes LH, LL.
CAD – Reverse the order of the bytes in 1 1.7 0.6 0.6 0.1
ACCU1.
LL, LH, HL, AA becomes HH,
HL, LH, LL.
TAK – Swap the contents of ACCU1 1 2.0 0.7 0.8 0.1
and ACCU2
ENT – The contents of ACCU2 and 1 – – – 0.1
ACCU3 are transferred to
ACCU3 and ACCU4.
LEAVE – The contents of ACCU3 and 1 – – – 0.1
ACCU4 are transferred to
ACCU2 and ACCU3.
PUSH – The contents of ACCU1 are 1 0.7 0.2 0.3 0.1
transferred to ACCU2
CPU 318–2: The contents of
ACCU1, ACCU2 and ACCU3
are transferred to ACCU2,
ACCU3 and ACCU4.

134 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 135
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
POP – The contents of ACCU2 are 1 0.7 0.2 0.3 0.1
transferred to ACCU1
CPU 318–2: The contents of
ACCU2, ACCU3 and ACCU4
are transferred to ACCU1,
ACCU2 and ACCU3.
INC 0 ... 255 Increment ACCU1-LL 1 0.7 0.2 0.3 0.1
DEC 0 ... 255 Decrement ACCU1-LL 1 0.7 0.2 0.3 0.1
Program Display and Null Operation

Instructions
The status word is not affected.
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
BLD 0 ... 255 Program display instruction: 1 0.7 0.2 0.3 0.1
Is treated by the CPU like a null
operation instruction.
NOP 0 Null Operation instruction: 1 0.7 0.2 0.3 0.1
1 0.7 0.2 0.3 0.1

136 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 137
Data Type Conversion Instructions
The results of the conversion are in ACCU1. When converting real

numbers, the execution time depends on the value.
Ad- Description Length

In-
dress i
in
struc- 315/315-2/
Identi- Words 312*/313 314/314* 318-2
tion 316-2
fier
BTI – Conv. cont. of ACCU1 from BCD 1 6.6 4.5 4.7 0.2
to integer (16 bits) (BCD To Int)
BTD – Conv. cont. of ACCU1 from BCD 1 15.7 10.4 11.5 0.2
to double int. (32 bits) (BCD To
Doubleint)
DTR – Convert contents of ACCU1 from 1 < 26 < 20 < 15 0.3
double integer to real (32 bits)
(Doubleint To Real)
ITD – Convert contents of ACCU1 from 1 0.7 0.2 0.1 0.1
integer (16 bits) to double int. (32
bits) (Int To Doubleint)
Status word for: BTI, BTD, DTR, ITD BR CC 1 CC 0 OV OS OR STA RLO FC
ITB – Conv. cont. of ACCU1 from int. (16 1 7.2 5.2 5.1 0.2
bits) to BCD from 0 to
+/– 999 (Int To BCD)
DTB – Conv. cont. of ACCU1 f. double 1 16.1 4.1 11.8 0.2
int. (32 bits) t. BCD f. 0 to
+/–9 999 999 (Doubleint To BCD)
Status word for: ITB, DTB BR CC 1 CC 0 OV OS OR STA RLO FC
Instruction affects: – – – Yes Yes – – – –

138 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 139
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
RND – Convert a real number into a 1 < 35 < 28 < 20 0.4
32-bit integer.
RND– – Convert a real number into a 1 < 35 < 28 < 20 0.4
32-bit integer. The number is
rounded to the next whole num-
ber.
RND+ – Convert a real number into a 1 < 35 < 28 < 20 0.4
32-bit integer. The number is
rounded to the next whole num-
ber.
TRUNC – Convert a real number into a 1 < 35 < 28 < 20 0.4
32-bit integer. The places after
the decimal point are truncated.
Status word for: RND, RND–, RND+, BR CC 1 CC 0 OV OS OR STA RLO FC
TRUNC
Instruction affects: – – – Yes Yes – – – –

140 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 141
Forming the Ones and Twos Complements
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
INVI – Form the ones complement of 1 0.7 0.2 0.3 0.1
ACCU1-L
INVD – Form the ones complement of 1 0.7 0.2 0.3 0.1
ACCU1
Status word for: INVI, INVD BR CC 1 CC 0 OV OS OR STA RLO FC
NEGI – Form the twos complement of 1 2.3 1.6 1.5 0.1
ACCU1-L (integer)
NEGD – Form the twos complement of 1 3.1 1.8 2.0 0.1
ACCU1 (double integer)
Status word for: NEGI, NEGD BR CC 1 CC 0 OV OS OR STA RLO FC

142 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 143
Block Call Instructions

tion Identifier
315 315
312* 314 312* 314
315-2 315-2
313 314* 318-2 313 314* 318-2
316-2 316-2
CALL FB q, Unconditional call of an FB, 1 9.2 7.7 5.3 – – – –
DB q with parameter transfer
CALL SFB q, Unconditional call of an SFB, 2 2 See 7.7 – – – – – –
DB q with parameter transfer ? execu-
tion
time
for
SFB 2
CALL FC q Unconditional call of a func- 1 9.2 7.7 5.3 – – – –
tion, with parameter transfer
CALL SFC q Unconditional call of an SFC, 2 See execution time for –
with parameter transfer SFCs2
UC FB q Unconditional call of blocks 13 9.2 7.7 5.3 1.4 9.8+ 8.5+ 6.1+ 1.4+
FC q without parameter transfer 14
1.4 1 4+
1.4+
Parameter FB/FC call via parameter 1.4 1.4+
CC FB q Conditional call of blocks 13 9.2 7.7 5.3 1.4 9.8+ 8.5+ 6.1+ 1.4+
FC q without parameter transfer 14
1.4 1 4+
1.4+
Parameter FB/FC call via parameter 1.4 1.4+
Status word for: CALL, UC, CC BR CC 1 CC 0 OV OS OR STA RLO FC
Instruction affects: – – – – 0 0 1 – 0

(see page 21)
2 In the S7-300 Hardware and Installation Manual

144 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 145

tion Identifier
315 315
312* 314 312* 314
315-2 315-2
313 314* 318-2 313 314* 318-2
316-2 316-2
OPN Open:
DB q Data block 1/22 2.9 1.6 1.5 0.3 4.0+ 1.4+ 2.6+ 0.3+
DI q Instance data block 2
Parameter Data block using parameters 2
Status word for: OPN BR CC 1 CC 0 OV OS OR STA RLO FC

(see page 21)
2 With direct instruction addressing Block No. > 255

146 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 147
Block End Instructions
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
BE – End block 1 4.9 4.1 2.8 2.0
BEU – End block unconditionally 1 – – – –
Status word for: BE, BEU BR CC 1 CC 0 OV OS OR STA RLO FC
Instruction affects: – – – – 0 0 1 – 0
BEC – End block conditionally if 5.9 4.4 3.2 2.2
RLO = “1”
Status word for: BEC BR CC 1 CC 0 OV OS OR STA RLO FC
Instruction affects: – – – – Yes 0 1 1 0

148 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 149
Exchanging Shared Data Block and

Instance Data Block
Exchanging the two current data blocks. The current shared data
block becomes the current instance data block, and vice versa. The
condition code bits are not affected.
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
CDB – Exchange shared data block and 1 1.0 0.3 0.4
instance data block

150 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 151
Jump Instructions Note:

Please note for S7–300 CPU programs that the jump destination
always (not for 318–2) forms the beginning of a Boolean logic
Jumping as a function of conditions. With 8–bit operands the jump string in the case of jump instructions. The jump destination must
width is between –128 and +127. In the case of 16–bit operands, not be included in the logic string.
the jump width lies between –32768 and –129 (+128 and +32767).
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
JU LABEL Jump unconditionally 1 1/2 1.8 1.7 1.8 0.5
Status word for: JU BR CC 1 CC 0 OV OS OR STA RLO FC
JC LABEL Jump if RLO = “1” 1 1/2 2.3 2.0 1.5 0.5
JCN LABEL Jump if RLO = “0” 2 2.6 2.3 1.6 0.5
Status word for: JC, JCN BR CC 1 CC 0 OV OS OR STA RLO FC
JCB LABEL Jump if RLO = “1”. 2 2.9 2.2 1.8 0.5
Save the RLO in the BR bit
JNB LABEL Jump if RLO = “0”. 2 2.9 2.4 1.8 0.5
Save the RLO in the BR bit
Status word for: JCB, JNB BR CC 1 CC 0 OV OS OR STA RLO FC
Instruction affects: Yes – – – – 0 1 1 0
1 1 word long for jump widths between –128 and +127

152 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 153
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
JBI LABEL Jump if BR = “1” 2 2.3 2.1 1.5 0.5
JNBI LABEL Jump if BR = “0” 2 2.3 2.1 1.5 0.5
Status word for: JBI, JNBI BR CC 1 CC 0 OV OS OR STA RLO FC
Instruction depends on: Yes – – – – – – – –
JO LABEL Jump on stored overflow 1 1/2 2.3 2.1 1.5 0.5
(OV = “1”)
Status word for: JO BR CC 1 CC 0 OV OS OR STA RLO FC
Instruction depends on: – – – Yes – – – – –
JOS LABEL Jump on stored overflow 2 2.6 2.2 1.6 0.5
(OS = “1”)
Status word for: JOS BR CC 1 CC 0 OV OS OR STA RLO FC
Instruction depends on: – – – – Yes – – – –
Instruction affects: – – – – 0 – – – –

154 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 155
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
JUO LABEL Jump if “unordered instruction” 2 2.8 2.3 1.8 0.5
(CC 1=1 and CC 0=1)
JZ LABEL Jump if result=0 1 1/2 2.7 2.2 1.7 0.5
(CC 1=0 and CC 0=0)
JP LABEL Jump if result>0 1 1/2 2.7 2.4 1.8 0.5
(CC 1=1 and CC 0=0)
JM LABEL Jump if result<0 1 1/2 3.0 2.4 1.8 0.5
(CC 1=0 and CC 0=1)
JN LABEL Jump if result00 1 1/2 2.8 2.3 1.8 0.5
(CC 1=1 and CC 0=0) or
(CC 1=0) and (CC 0=1)
JMZ LABEL Jump if resultv0 2 2.4 2.1 1.5 0.5
(CC 1=0 and CC 0=0)
JPZ LABEL Jump if resultw0 2 2.4 2.2 1.6 0.5
(CC 1=0) and (CC 0=0)
Status word for: JUO, JZ, JP, JM, BR CC 1 CC 0 OV OS OR STA RLO FC
JN, JMZ, JPZ
Instruction depends on: – Yes Yes – – – – – –

156 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 157
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
JL LABEL Jump distributor 2 3.2 3.9 2.7 0.7
This instruction is followed by a
list of jump instructions.
The operand is a jump label to
subsequent instructions in this
list.
ACCU1-L contains the number
of the jump instruction to be
executed.
LOOP LABEL Decrement ACCU1-L and jump 2 2.4 1.7 1.6 0.5
if ACCU1-L0
(loop programming)
Status word for: JL, LOOP BR CC 1 CC 0 OV OS OR STA RLO FC

158 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 159
Instructions for the Master Control Relay MCR=1MCR is deactivated

MCR=0MCR is activated; “T” and “=” instructions write “0” to
(MCR) the corresponding address identifiers; “S” and “R” instructions
leave the memory contents unchanged.
In- Length
Address
Identifier
tion Words
315/315-2/
312*/313 314/314* 318-2
316-2
MCR( Open an MCR zone. 1 3.0 1.6 1.7 0.1
Save the RLO to the MCR
stack.
Status word for: MCR( BR CC 1 CC 0 OV OS OR STA RLO FC
)MCR Close an MCR zone. 1 2.8 1.5 1.6 0.1
Pop an entry off the MCR stack.
Status word for: )MCR BR CC 1 CC 0 OV OS OR STA RLO FC
MCRA Activate the MCR 1 0.7 0.2 0.3 0.1
MCRD Deactivate the MCR 1 0.7 0.2 0.3 0.1
Status word for: MCRA, MCRD BR CC 1 CC 0 OV OS OR STA RLO FC

160 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 161
Alphabetical Index of Instructions Alphabetical Index of Instructions
Alphabetical Index of Instructions

Instruction Page Instruction Page Instruction Page Instruction Page
) 36 <=D 124 AN 30, 40, 50 COS 116
)MCR 160 <=I 122 AN( 36 CU 76
+ 118 <=R 126 ASIN 116 DEC 136
+AR1 120 <D 124 ATAN 116 DTB 138
+AR2 120 <I 122 AW 44 DTR 138
+D 108 <R 126 BE 148 ENT 134
+I 106 <>D 124 BEC 148 EXP 114
+R 110 <>I 122 BEU 148 FN 62
–D 108 <>R 126 BLD 136 FP 60
–I 106 >=D 124 BTD 138 FR 74, 76
–R 110 >=I 122 BTI 138 INC 136
*D 108 >=R 126 CAD 134 INVD 142
*I 106 >D 124 CALL 144 INVI 142
*R 110 >I 122 CAR 100 ITB 138

/D 108 >R 126 CAR1 100 ITD 138
/I 106 A 28, 40, 46, CAR2 100 JBI 154
50
/R 110 CAW 134 JC 152
A( 36
= 68 CC 144 JCB 152
ABS 110
==D 124 CD 76 JCN 152
ACOS 116
==I 122 CDB 150 JL 158
AD 44
==R 126 CLR 70 JM 156

162 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 163
Alphabetical Index of Instructions Alphabetical Index of Instructions
Instruction Page Instruction Page Instruction Page Instruction Page

JMZ 156 MOD 108 RRD 132 TAK 134
JN 156 NEGD 142 RRDA 132 TAN 116
JNB 152 NEGI 142 S 64, 76 TRUNC 140
JNBI 154 NEGR 110 SAVE 70 UC 144
JO 154 NOP 136 SD 72 X 34, 42, 56
JOS 154 NOT 70 SE 72 X( 36
JP 156 O 32, 38, 42, SET 70 XN 34, 42, 58
52
JPZ 156 SF 72 XN( 36
O( 36
JU 152 SIN 116 XOD 44
OD 44
JUO 156 SLD 128 XOW 44
ON 32, 42, 54
JZ 156 SLW 128
ON( 36
L 78– 86, 88, SP 72
102, 104 OPN 146
SQR 112
LAR1 98 OW 44
SQRT 112
LAR2 98 POP 136
SRD 128
LD 88 PUSH 134
SRW 128
LEAVE 134 R 66, 74, 76
SS 72
LN 114 RLD 132
SSD 130
LOOP 158 RLDA 132
SSI 128
MCR( 160 RND 140
T 90–96, 104
MCRA 160 RND+ 140
MCRD 160 RND– 140

164 EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02 165
To
Siemens AG
A&D AS E 82
P. O. Box 1963
D–92209 Amberg
From:
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EWA 4NEB 710 6087-02
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EWA 4NEB 710 6087-02
EWA 4NEB 710 6087-02
EWA 4NEB 710 6087-02
Additional Execution Times for
Indirect Addressing
The following table lists the execution times necessary for loading
the address of the instruction from the various address areas.
Execution time in s
Address is in ... 312*/ 314/ 315/315-2/ 318-2
313 314* 316-2
Bit memory area M
Word 1.7 0.7 0.8 0.2
Double word 3.5 2.3 2.1 0.3
Data block DB/DX
Word 5.2 2.8 3.0 0.2
Double word 6.7 3.9 4.1 0.3
Local data area L
Word 2.0 0.8 0.9 0.2
Double word 3.7 2.6 2.2 0.3
AR1/AR2 (area-inter- 3.0 1.9 1.7 0.0
nal)
AR1/AR2 (area-cros- 4.9 3.9 3.2 0.0
sing)
Parameter (word) ... 4.0 2.5 2.1 0.2
for:
Timers
Counters
Block calls
Parameter (double 7.3 5.3 4.3 0.3
word) ... for
Bit, byte, words
and double words
You will find examples of how to calculate execution times for the
various indirectly-addressed instructions on page 20 ff. in the sec-
tion entitled “Execution Times for Indirect Addressing”.

EWA 4NEB 710 6087-02 EWA 4NEB 710 6087-02

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S7-300 Instruction List

CPU 312 IFM, 314 IFM,

Contents Comparison Instructions with Integers (16 Bits) . . .

%     Block End Instructions . . . . . . . . . . . . . . . . . . . . . . . 148

%"!  $! !    Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

S7-300 Instruction List S7-300 Instruction List

Address Identifiers and Parameter

1 PIQ is preset to 256 byte

S7-300 Instruction List S7-300 Instruction List

1 PII is preset to 256 byte

S7-300 Instruction List S7-300 Instruction List

S7-300 Instruction List S7-300 Instruction List

S7-300 Instruction List S7-300 Instruction List

1 for loading of S5 timers

S7-300 Instruction List S7-300 Instruction List

Abbreviations and Mnemonics

S7-300 Instruction List S7-300 Instruction List

The address registers contain the area-internal or area-crossing ad- 5 OV Overflow

* Bit cannot be evaluated in the user program with the L STW

S7-300 Instruction List S7-300 Instruction List

S7-300 Instruction List S7-300 Instruction List

Addressing Examples Description Addressing Examples Description

S7-300 Instruction List S7-300 Instruction List

Execution Times with Indirect

S7-300 Instruction List S7-300 Instruction List

Direct Addressing Indirect Addressing

S7-300 Instruction List S7-300 Instruction List

Address is in ... Execution Time in s Address is in ... Execution Time in s

Typical Execution Time in s Typical Execution Time in s

Direct Addressing Indirect Addressing Direct Addressing Indirect Addressing

0.2 Time for 2.0+ 0.2 Time for 2.0+

Total execution time: Total execution time:

S7-300 Instruction List S7-300 Instruction List

Execution Time for Addressing Via Parameters

Example: A Parameter ... with I 0.5 in the block parameter list

Address is in ... Execution Time in s

Typical Execution Time in s

Direct Addressing Indirect Addressing

0.2 Time for 2.0+

Total execution time:

S7-300 Instruction List S7-300 Instruction List

1 Plus time required for loading the address of the instruction

S7-300 Instruction List S7-300 Instruction List

1 Plus time required for loading the address of the instruction

S7-300 Instruction List S7-300 Instruction List

S7-300 Instruction List S7-300 Instruction List

S7-300 Instruction List S7-300 Instruction List

Bit Logic Instructions with Parenthetical

Saving the BR, RLO and OR bits and a function identifier

S7-300 Instruction List S7-300 Instruction List

ORing of AND Operations

The ORing of AND operations is implemented according to the

S7-300 Instruction List S7-300 Instruction List

Logic Instructions with Timers and

Examining the signal state of the addressed timer/counter and

1 Plus time required for loading the address of the instruction

S7-300 Instruction List S7-300 Instruction List

1 Plus time required for loading the address of the instruction

S7-300 Instruction List S7-300 Instruction List

Word Logic Instructions with the

S7-300 Instruction List S7-300 Instruction List

Evaluating Conditions Using AND, OR

S7-300 Instruction List S7-300 Instruction List

% Block End Instructions . . . . . . . . . . . . . . . . . . . . . . . 148

%"! $! ! Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150