Interrupt aware queue

implementation for energy

efficient multitasking systems
based on Cortex-M3 architecture
Modern micro-controllers provide enough processing power to benefit from
the advantages of multitasking schedulers or operating systems even in the
area of small, battery based or energy self-sustaining
devices. Interrupt driven software designs provide maximum sleep times
and energy savings in such devices. For a multitasking operating system, a
software technique with minimal resource overhead must be found to
transport data between interrupt service routines and tasks. This paper
describes a queue implementation based on special low-level
synchronization commands provided by the widespread Cortex-M3 micro-
controller architecture. The proposed queue design provides a fast, low
overhead data transport from task to task and between interrupt service
routine and task. The implementation shows slightly lower latency (1%),
higher bandwidth (18%) and has less memory overhead (33%) than the
generic implementation provided by the well known FreeRTOS multitasking
scheduler for embedded systems. It allows the use of multitasking
schedulers even in ultra low energy embedded systems with few kilobytes
of RAM.