Analog Integrated Circuit Design

Lab 3
Layout and Post-layout Simulations

Department of Electrical and Computer Engineering

The University of Texas at Austin

Fall 2007
In this lab, you are introduced to Cadence Virtuoso Layout tools and techniques to do post-layout
simulations.

1. Objectives:

1. To learn layout techniques of analog integrated circuits.

2. To do post-layout simulations in Analog Environment.

2. Tasks:

Draw the layout of the inverter that you designed in Lab 1; and perform DRC (Design Rule Check),
Extraction, LVS (Layout Versus Schematic check), and post-layout simulations.

3. Instructions:

Part I: Layout, DRC, Extraction, and LVS

We will do the layout, DRC (Design Rule Check), extraction, and LVS (Layout Versus Schematic check) of
a simple inverter in AMI 0.6µm CMOS technology. Note that the examples are only for your reference.
Your actual design could be different.
1. In Lab 1 you have learned how to capture a schematic using Schematic Editor in Cadence. In this
example, we will draw the layout of this inverter in Layout Editor. The transistor’s sizes are: NMOS
(w=6um, l=0.6um, m=2) and PMOS (w=6um, l=0.6um, and m=4).
2. From Library Manager, choose “Lab1/Inverter” by clicking “Lab1” in the Library column, and then
“Inverter” in the Cell column. Choose menu “FileÆNewÆCell
View …”, a new window pops up as shown in the right. Fill the text
fields of “Cell Name” and “View Name” as shown in the figure.
Choose “Virtuoso” as the Tool.
3. Click “OK after you confirm that “Library Name”, “Cell Name”, and
“View Name” are correct. Two new windows show up. The first one
is the LSW Window from which you can choose drawing layers. The
second window is the actual drawing area where you will draw the
layout.

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4. Adjust the “Display Options” for the Layout. In the Layout Editor Window, click on “Options Æ
Display” (or press hot key “e”). “Display Options” window appears. Make necessary changes to the
selection buttons and text fields. Your “Display Options” window should be the same as what is
shown below. At the bottom of the window, make sure that “Cellview” is selected as the save-to
target, click “Save To” button. After that you confirm that you have completed all necessary changes
in the form, click “OK”.

5. Now you are ready to draw the layout. In the blank layout editor window, add one NMOS transistor
and one PMOS transistor, by clicking on “Create Æ Instance”. The Library is
“NCSU_TechLib_ami06”, as we are using AMI 0.6µm CMOS technology. You can change the
properties of the transistors when creating the instances. The transistor sizes and multipliers are,

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 NMOS: w=6um, l=0.6um, m=2; and PMOS: w=6um, l=0.6um, and m=4.

You may type the “Library” name “NCSU_TechLib_ami06”, “Cell” name “nmos” or “pmos”, and
“View” name “layout” in the above “Create Instance” window. You can also click “Browse” button at
the upper right corner to pop up the “Library Browser” window. Click “Show Categories” in the
“Library Browser” window if it is not checked. Choose “NCSU_TechLib_ami06” Library,
“layout_macros” Category, “nmos” or “pmos” Cell, and “layout” View. The “Create Instance” window
updates simultaneously when you change the selections in the “Library Browser” window.

6. In case that you did not change the properties of the transistors when the instances were created, you

can change now by typing “q”, or clicking “EditÆEdit Properties…”, or clicking the button in

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the left side tool bar, similar to editing object properties in the schematic editor. The “Edit Instance
Properties” window appears. Click the “parameter” selection button. Make changes of “Bulk node
connection”, “Multiplier”, “Width” (not “Width (grid units)”), and “Length” of the NMOS
transistor, to “vss”, “2”, “6u”, and “600n”, respectively. Similarly, change the “Bulk node
connection”, “Multiplier”, “Width” (not “Width (grid units)”), and “Length” properties of PMOS
transistor, to “vdd”, “4”, “6u”, and “600n”, respectively. Your “Edit Instance Properties” windows
should be the same as what shown below.

If the NMOS or PMOS transistor is not in place, move it to the right location, Similar to what you

did in Lab 1, click menu “Design Æ Move”, or type hot key ‘m’, or click button in the left side
tool bar, the “Move” option window appears. Note that you can change the orientation of the object
by clicking “Rotate”, “Sideways”, and/or “Upside Down” buttons. The “Snap Mode” selection has
options of “anyAngle”, “diagonal”, “orthogonal”, “horizontal”, and “vertical”. If you want to move
your object in any direction, change the “Snap Mode” to “anyAngle”. Keep other buttons and text
fields unchanged, as shown in the follow window. You can pick up the object by clicking the object,
and move it and drop to the right location by a second mouse button click.

<***For information only***> If the “Move” option window does not appear after you click menu

“Design Æ Move”, or type hot key ‘m’, or click button in the left side tool bar, you may need to
check the “User Preferences” window, which can be invoked by selecting menu “Options Æ User
Preferences” from CIW window. Confirm that the “Options Displayed When Commands Starts”

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 button is checked in the “User Preferences” window as shown below.

The layout window should look like the following snapshot.

7. Now you are ready to connect the gate terminals of the transistors. Select “poly” material,

from the LSW Window. Click menu “CreateÆRectangle”, or, click at the left
side tool bar, or, press the hot key “r”, to create a rectangle using the poly layer. Draw two vertical
bars of poly to connect the two gate fingers of NMOS transistor and the center two gate fingers of
the PMOS transistor vertically. Draw a horizontal ploy bar between two transistors to merge the two

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 vertical poly rectangles, and another two vertical poly bars
to extend the right most and left most gate fingers of the
PMOS transistor to the horizontal ploy bar.
Alternatively, you can also create five paths instead of
rectangles with ploy, to merge the gates of NMOS and
PMOS transistors. Paths can be created by clicking menu
“CreateÆPath” or the hotkey “p”.
8. Connect the source and drain fingers of the NMOS multi-
finger transistor. Again, we can create either Rectangles or
Paths for the connections. This time we select “metal1

(dg)”, , as the drawing layer from LSW

window before making any connections. The drains of
NMOS and PMOS are tied together as the inverter output;
the sources of NMOS and PMOS are connected to the negative and positive power supply rails,
respectively. Usually it is important in the layout design to identify critical nodes and minimize
parasitic capacitances at these nodes. In our case, the output terminal of the inverter is a critical
node. Instead, the parasitic capacitances at the source terminals are not a concern. To reduce
parasitic capacitance, we will choose the center fingers (N
diffusion) of the NMOS transistor as drain, and left and right
fingers as the source. Similarly we can choose the drain and
source terminals of the PMOS transistor, and create
Rectangles or Paths with “metal1” layer to connect source
and drain terminals as in the schematic.
9. Make the substrate and well connections. Click on “Create Æ
Instance” and choose “ptap”, as shown in the following
window. You can change the “Rows of contacts” (or
“Columns of contacts”) to more than 1 to create a vertical (or
horizontal) “ptap” bar. Enough number of ptaps or ntaps
should be placed to make good (low impedance) bulk
connections of the transistors. Note that for an NMOS
transistor, we use ptap for the substrate connection; for a
PMOS transistor, we use ntap for the n-well connection. The
ptaps are connected to the source of the NMOS transistor as
the NMOS bulk is connected to the NMOS source in the schematic. Similarly, the ntaps are
connected to the source of the PMOS transistor.

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After the ptaps and ntaps are placed, the layout looks similar to the following figure.

We draw the n-diffusion layer ( “nactive (dg)” in LSW window) to extend the n-

diffusion layer of the ntaps. We also need to draw n-select (“nselect (dg)” ) layer. n-
diffusion layer should be completely covered by n-select layer with an extension of 0.6 µm each
side. The n-well should be re-drawn to extend the n-well layer from the PMOS transistor layout
instance, to satisfy the design rules. N-diffusion, n-select, and n-well rectangles are shown in the
following figure. Note that overlap of geometries of the same layer is permitted by the layout rules,
and will result in merged geometries in the masks for manufacturing. You may need to stretch the
metal1 rectangles of source terminals of the NMOS and PMOS transistors. The layout after this step
looks similar to the following figure (the texts and highlights are added for demonstration only).

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10. Create the pins of Vin, Vout, vdd and vss which are also the pins in the schematic. In the layout
editor window, click “Create Æ Pin” to create pins. Similar to those in schematic, the pins in layout
also have three I/O types: input, output and inputoutput. Make sure to select the same I/O types as
those in the schematic. The “Create Symbolic Pin” window is shown below. All four pins should use
“metal1” in the “Pin Type” in the “Create Symbolic Pin” window.

11. Make sure that your layout has no DRC (Design Rule Check) Errors. To perform DRC, choose

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 menu “Verify Æ DRC” and the following DRC window appears. Click “OK”. Check the CIW
window for any DRC errors. Correct any errors before the next step. It should be helpful to run DRC
check after you have made some major changes in the layout. Otherwise, you might be
overwhelmed by many DRC errors after you complete the entire layout design.

12. After your design passes the DRC check, the next step is to extract the layout for LVS (Layout
Versus Schematic) check. In the layout editor window, click on “Verify Æ Extract”, the following
“Extractor” window appears. Click “Set Switches” button. The “Set Switches” window opens.
Choose “Extract_parasitic_caps” from the “Set Switches” window and click “OK”. The parasitic
capacitances will be extracted for post-layout simulations. The “Extractor” and “Set Switches”
windows are shown below. Click “OK” of the “Extractor” window.

13. A new “extracted” cellview will be created in your library. Open the extracted view from the Library
Manager. The extracted view is shown in the following window.

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14. Now we do LVS check. Select menu “Verify Æ LVS” in the extracted view window. The following
two windows appear. Check “Form Contents” option in the “LVS Form Contents Different”
window, and click “OK”. Both of the “LVS Form Contents Different” and the “LVS” window are
shown as follows.

15. Click “Run” button in the “LVS” window. After a couple of minutes, the following window will
appear if your LVS is successful. Click “OK” in the “Analysis Job Succeeded” window and return to

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 the “LVS” window.

16. Click “Output” button in the LVS window. The content of “si.out” file is displayed in a new window.
showing the netlist comparison between the schematic view and the extracted view. “The net-lists
match” shows that your layout matches the schematic. If the netlists fail to match, modify the layout
or schematic appropriately. Rerun extraction and LVS until the layout and schematic are matched.
Pay attention to the upper/lower cases of the pin names – LVS is sensitive to upper and lower cases.

If you netlists match, you are ready to start the next part: post-layout simulation.

Part II: Post-Layout Simulaitons

Here we will perform post-layout simulation in Cadence Analog Environment with parasitics extracted
from the layout. Before you start the post-layout simulation, complete the LVS (Layout vs. Schematic)

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procedures, as shown in the Part I.
1. Building analog_extracted view for cell Inverter
In the “LVS” window shown below, which can be opened either from the layout view or the extracted view
of cell Inverter by clicking menu “Verify Æ LVS” in the Virtuoso layout editor. Fill out the required
sections in the LVS window as discussed earlier. Make sure that you specified the correct schematic and the
extracted views of your design.

NOTE: This is only an example. Please make sure that you select the right library, cell and view.
Once the “LVS” window is completed as shown above, click the “Build Analog” button. The “Build
analog_extracted View” window opens as shown below. Click on “Include all” to extract all parasitics in
the extracted view. After you press “OK”, the “analog_extracted” view of the cell will be created. Follow
the messages in the CIW (Command Interpreter Window) window to confirm that everything is completed
without any errors. You can see whether the “analog_extracted” view is created in the Library Manager.

2. Create config view for Inverter_tst

Now, we need to work on the test fixture schematic that contains the inverter design along with the sources
and loads. In our example, the cell that contains the test fixture is “inverter_tst”. Next, use the Hierarchy
Editor to create a configuration file that defines the views to simulate your design. In the CIW or Library
Manager, select “File Æ New Æ Cellview”. Then the “Create New File” form appears as shown below.
Fill out library name and the cell name sections properly as shown below and click “OK”. The “Hierarchy
Editor” window opens. A second “New Configuration” window also appears as shown bellow.

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Click “Use Template …”, the following window opens. In the “Name” field, choose “spectreS”, and click
on “OK”. The contents of the “New Configuration” window automatically update, as shown below.

In the “Top Cell” section, make sure that you have updated the Library, Cell and the View correctly. For
example, the View field, change “myView” to “schematic”. In the “Global Bindings” section, change
“myLib” to “Lab1”. The “New Configuration” window should be similar to the following window snapshot.

Click “OK” in the “New Configuration” form. The Hierarchy Editor will display the hierarchy of this

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design. In the “Cell Bindings” section of the “Hierarchy Editor” form, you can locate the entry associated
with the cellview of your design (Inverter in this example), as shown on the following figure.

Note that the “View Found” is set as schematic. To run post-layout simulation, we will use the
“analog_extracted” view instead. Place your cursor in the cell “Inverter” row, “View To Use” column, in
the Hierarchy Editor window, press and hold your right mouse button to activate the Object Sensitive
Popup Menu. Choose “Set Cell View Æ analog_extracted”, as shown in the following figure.

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The “View Found” and “View To Use” fields now change to “analog_extracted” as shown below.

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Click the “Save” button , or select “File Æ Save” to save the configuration file. Click “File Æ Exit” to
quit the “Hierarchy Editor”. Now you have already set up the configuration file to use extracted view for
post-layout simulations.
3. Open Analog Environment window for “config” view
Post-layout simulations can give more realistic understanding on how the circuit performs after the
integrated circuit chip is fabricated. Note that, the toplevel Inverter_tst cell is the stimulus cell that provides
power supplies, bias currents/voltages and signal sources for the cell (in our case, it is “Inverter” cell) that
we have completed layout, DRC, extraction, and LVS.
There are two ways to open the “Analog Environment” to simulate the Inverter_tst cell with Inverter
analog_extract view.
(1) You can open “Analog Environment” window from the schematic (actually “config” view) window.
Open the Inverter_tst cell config view window from Library Manager. Choose the “config” view (not

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“schematic” view) in the Library Manager, and select menu “File Æ Open…” or double click the
“config” view.

The following window will appear.

Keep the setting unchanged, and click “OK”. The following schematic editing window opens. Note that
the window title is “Virtuoso® Schematic Editing … Inverter_tst config”. Make sure that “… config”
appears in the title of the window. Even though the window looks the same as the schematic editing
window, the used view of the “Inverter” cell is “analog_extracted” instead of schematic.

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Open “Analog Environment” window by selecting “Tools Æ Analog Environment”. Confirm that the
View is “config” instead of “schenatic” in the “Design” section (upper left part of the window) of the
Analog Design Environment window.

(2) You can also set the “config” view of the “Inverter_tst” cell as the active design of the Analog
Environment window. In the Analog Environment, choose menu “Setup Æ Design” as shown above,
“Choosing Design” window pops up.

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In the “View Name” item, choose “config” instead of “schematic”, as shown in the above “Choosing
Design” window. Click “OK”. Now check the “Design” section (upper left part of the window) of the
“Analog Environment” window, the View should be “config” instead of “schematic”.

4. Perform post-layout simulations

Then you can follow the same DC and transient simulation procedures as you did in Lab 1 – steps 3 to 8 in
Section 3.8. The post-layout simulation waveforms are shown below.

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If the results of post-layout simulation are not satisfactory, the designer should figure out what is wrong, or
modify some of transistor’s dimension and/or the circuit topology. In order to achieve the desired circuit
performance in "realistic" conditions, we need take into account all of the circuit parasitics. This may
require iterations on the design, until the post-layout simulation results satisfy the original requirements.

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References:

[1] ELEN474 Analog Integrated Circuit Design Lab Manual, Texas A&M University, 1998
[2] Cadence on-line documentation, command “cdsdoc” in UNIX shell.

* This document was written and revised by TAs of EE 338L / EE 382M-14, Nihar Kulkarni, Byung-geun
Lee, and Jingyu Hu, and Prof. Shouli Yan. Other TAs, including, Ashwin Gunashekar, Zhuofan Yang, and
Tongyu Song, also contributed to the revision of the document.

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