3.5.

3 Small Geometry Effects

The basic and original analytical MOSFET models were introduced during the mid-196Os
[22, 23]. These models are relatively simple, and were developed for what are referred to today as
"long, wide" FETs; they form the underlying foundation for all the analytical FET models available in
SPICE.

As device geometries have decreased (channel length and width, and oxide thickness), device
structures have become more complicated (e.g., nonuniform substrate doping), and internal electric
fields have become stronger (due to the reduction in feature sizes proceeding more rapidly than the
reduction of the power supply voltage [24]). Thus, a number of new features have appeared in FET
behavior. New models, extending beyond the original models, are continually being introduced to
account for these additional effects.

This is the basis for all the FET current models that have been developed and introduced into
SPICE. The original long channel FET model is treated as a base, and· the small geometry effects are
added as "corrections." Over time, decreasing device geometries have spawned a growing list of such
effects; this list will be considered in a simple form here. The objective is to quantitatively describe
the physical origin of each effect, and to postpone a detailed discussion of specific descriptions until
the individual SPICE FET models are developed. Often, the same effect is modeled differently in
different FET models. On the other hand, some effects discussed here are not yet included in any of
the SPICE FET models; their description is included for completeness, and, in anticipation of their
addition to future SPICE FET models.

The descriptions to be given here are qualitative, with quantitative discussion postponed until
the inclusion of each effect in a particular SPICE FET model is considered; the intent is to introduce
each small geometry effect in a simple and clear manner. Exhaustive mathematical descriptions of
these effects may be found in two excellent textbooks [14, 25].

1. Depletion Region Overlap:

The basic FET structure combines the depletion regions of two p-n junctions (source-
substrate and drain-substrate) with the depletion region of a MOS capacitor. In a large FET, these
depletion regions can be described by the equations for the corresponding two-terminal structures. In
a smaller FET, the situation is as shown in Figure 3.27. The shaded regions show where the junction
depletion regions overlap the gate depletion region. Thus, the total depletion charge is no longer
simply the sum from the three individual regions; instead, it is reduced from that value. Since,
according to (3.79),

Qs = Qinv + Qdepl, (3.151)

and as Qs merely images the gate charge, a decrease in Qdepl from its expected value implies an
increase in Qinv. The net result is that Qinv will be larger than that predicted by the theory of the simple
two-dimensional MOS capacitor; this must be accounted for in the FET model.
 Figure 3.27 FET depletion regions. The gate-induced depletion region overlaps the source and drain depletion regions.

Figure 3.28 FET depletion regions. showing change sharing between the source and drain.

2. Source-Drain Charge Sharing

As the channel length decreases further, the situation just described becomes even more
complicated. As shown in Figure 3.28a, the source and drain depletion regions can overlap. This is
often referred to as charge sharing between the source and the drain. This further decreases the
depletion charge Qdepl from the value predicted by the two-terminal MOS capacitor model, leading to
a concomitant increase in the inversion charge Qinv above its expected value. In addition, the
application of a drain bias will expand the drain junction depletion region (Figure 3.28b), further
increasing the extent of charge sharing.

3. Depletion Region Spreading-Outside the Channel Width

Consider the cutaway view (across the width of the channel) of an FET shown in Figure 3.29.
In a very wide FET (Figure 3.29a), the gate-induced depletion region is treated as not extending
beyond the gate edge; since the FET width is large, this-approximation is good, and the dep1etion
region is well described by the simple MOS capacitor model. The situation is different in a narrow
device, defined by an isolation oxide "groove," as shown in Figure 3.29b. Here the depletion region
spreading outside the channel region is significant and cannot be ignored. In this case, the depletion
charge Qdepl is larger than
 Figure 3.29 The gate-induced depletion region across the width of the FET; (a) very wide device; (b) simple narrow
device; showing how the depletion region spreads outside the defined channel; (c) dep1etion region spreading in
LOCOS-bounded device; (d) an isolation-trench--bounded structure, in which the isolation prevent the depletion
region from spreading outside the defined channel width.

that predicted by the two-terminal MOS capacitor model, so the inversion charge Qinv is decreased
from the simply predicted value.

The same situation holds in the more complex LOCOS isolation structure. As shown in
Figure 3.29c, LOCOS complicates the shape of the extended depletion region, but the basic result is
the same. Interestingly, more recent (and more complex) oxide-filled trench isolation structures
[26,27] eliminate this problem. As shown in Figure 3.29d, the presence of the isolation trench
prevents the depletion region from spreading outside the width of the defined channel; assuming that
the doping is relatively uniform across the device "pedestal," the depletion region is once again well
described by the simple MOS capacitor model.

4. Mobility Reduction Due to the Gate Field

The mobility, µ, was introduced in (3.116) as a method of relating the carrier velocity to the
lateral field:

ν = µE. (3.152)

This relationship is simple and approximate, but actually describes carrier conduction in a bulk
semiconductor material under low fields. This approach is adequate for large FETs, and (3.152) has
been used effectively with µ as a constant.

However, as gate oxides have become thinner and the vertical field at the silicon surface has
increased, the mobility no longer remains constant. Instead, as shown in Figure 3.30, it decreases with
increasing gate field. Although the physical basis of this mobility reduction is still a matter of some
debate [28-30], it must be included in the FET models.

5. Lateral Mobility Reduction and Velocity Saturation

In addition to the mobility reduction due to the gate field, the simple Ohm’s law relationship
(3.152) does not hold for larger values of the lateral field. Instead, as shown in Figure 3.31, the carrier
velocity departs from its linear relationship with the lateral field and becomes constant; this
phenomenon is known as carrier velocity saturation, and the constant maximum velocity is referred to
as the saturation velocity.

At the most detailed level, since the lateral field varies along the channel, the mobility will
also vary along the channel. However, this makes the situation too complicated for the description by
an analytical model. Instead, velocity saturation and the lateral mobility reduction are linked to the
drain current saturation described by the saturation voltage Vdsat. As detailed earlier, for a constant
gate bias Vgs (Vgs > Vt), the- drain current Ids increases linearly with the applied drain bias until Vds
reaches the saturation voltage Vdsat. For Vds > Vdsat, the drain current remains essentially constant.
However, in short channel FETs, due to the high lateral field, the carriers reach the saturation velocity
before the expected value of Vdsat. As shown in Figure 3.32, the drain current thus saturates at a lower
value.

In short channel FET models, this behavior is accounted for in the following way. Carrier
velocity saturation is used to describe the reduction of the mobility by the high

Figure 3.30 the channel electron mobility versus gate voltage of a thin oxide FET.
 Figure 3.31 the velocity of electrons in silicon versus the applied field. For low fields, the velocity increases linearly
with the field (Ohm’s law regime), while for higher fields the velocity no longer increases.

lateral field. This mobility result is then used to compute a reduced value of the saturation voltage
Vdsat which is used to describe the drain current behavior.

Interestingly, drain current sa1lU'ation and carrier velocity saturation originally described two
separate FET phenomena, the former being an inherent characteristic of any FET, while the latter is a
high field phenomenon in a bulk material. However, it turns

Figure 3.32 Drain current characteristics of an FET with a fixed gate bias (Vgs > Vt). The dashed line shows the
expected behavior (if carrier velocity saturation is ignored), while the solid line shows the effect of velocity saturation.
Note how carrier velocity saturation reduces the saturation voltage Vdsat.

out that the two phenomena are closely related, and in short channel devices the current saturation
characteristics are determined by carrier velocity saturation.

6. Channel Length Modulation

As described earlier in this chapter and just above, for a constant gate bias with Vgs > Vt and
Vds > Vdsat the drain current no longer increases with increasing drain bias. ',: In short channel devices,
this is not exactly the case. As shown in Figure 3.33a, when Vds = Vdsat, the channel pinches off and
the inversion layer no longer reaches the drain. ,', . When Vds > Vdsat, as shown in Figure 3.33b, the
pinch-off point moves away from the drain junction and toward the source. This phenomenon is
negligible in long channe1 devices, but becomes more important in short channel FETs. Since the
lateral voltage at the pinch-off point is always Vdsat if the pinch-off point moves toward the source, the
lateral field along the channel (between the source and the pinch-off point) increases above its value
when Vds = Vdsat. This increased field in turn increases the drain current. This is illustrated in Figure
3.34 for a short channel device; the drain current increases slightly for increasing drain bias when Vds
> Vdsat.
Figure 3.33 Channel length modulation in an FET: (a) Vds = Vdsat; (b) Vds > Vdsat; the pinch-off point has moved away
from the drain junction and toward the source.

Figure 3.34 PET drain current characteristic for a fixed gate bias (Vgs > Vt). Due to channel length modulation, the
drain current increases slightly as Vds increases above Vdsat.

7. Series Resistance

In a long channel FET, the resistance of the channel region is by far the largest resistance in
the source-drain current path. In a short channel device, this is no longer the case, shown in Figure
3.35;the channel resistance has become small enough for the resistance of the source and drain
regions to be come important. A portion of the applied drain-source bias Vds is in fact dropped across
the source and drain resistances, decreasing the drain current from its expected value.

8. Drain-Induced Barrier Lowering (DIBL)

Consider the potential profile along the channel axis of a long channel FET with no biases
applied, as depicted in Figure 3.363. There is a barrier between the diffusions and the channel region
equal to the built-in zero bias junction potential between the diffusions

Figure 3.35 Parasitic source-drain series resistance. These parasitic resistances become important in short channel
device, in which the channel resistance has become small.
 Figure 3.36 channel potential profile of a long channel device; (a) Vds = 0; (b) Vds > 0.

Figure 3.37 Channel potential profile of a short channel device; (a) Vds =0; (b) Vds > 0; the drain bias lowers the
potential barrier at the source end of the channel

and the bulk silicon. When a drain bias is applied (Figure 3.36b), only the immediate region of the
drain is affected, and the channel potential profile is basically unaffected.

Now consider a short channel device. As shown in Figure 3.37a, with no biases applied, the
potential profile is the same as that in the long channel device. However, with a drain bias applied
(Figure 3.37b), the channel potential profile is affected. The drain bias now changes the potential
profile along the entire channel, lowering the barrier at the source-bulk junction; this is referred to as
drain-induced barrier lowering, or DIBL. For a given drain bias, this allows carriers to traverse the
channel at a lower gate bias than would otherwise be expected. It is most common to note the effect
on the threshold voltage, defined by (3.96):

Vt = Vfb + 2φf +γ. (2 φf)1/2 (1.153)

Since carriers are able to traverse the channel for lower than expected gate biases: DIBL is usually
included as a modification to the threshold voltage expression (3.153), as it serves to decrease the
threshold voltage.

9. Punch through

When drain-induced barrier lowering occurs in a short channel FET, the channel potential
barrier is decreased. but still exists; although a drain current will flow at a lower gate bias than would
otherwise be expected, the gate is still able to control the current.

Recall the above discussion of charge sharing between the source and the drain, in which the
drain depletion region expands with increasing drain bias to partially overlap the source depletion
region. A more detailed analysis (31) shows that the extent of the source and drain depletion regions
in the lateral (channel) direction is in fact restricted by the presence of the gate. As shown in Figure
3.38a, under zero bias, the lateral depletion depth is less than the vertical depletion depth. The same
situation holds when a drain bias is applied (Figure 3.38b). However, note that away from the silicon
surface, the depletion region is larger. As the drain bias increases, this "bulge" in the depletion region
can reach the source depletion region (Figure 3.38c). When this occurs, the channel

Figure 3.38 Source-drain depletion regions in a short channel FET; (a) Vds = 0; (b) Vds > 0; note how the lateral
depletion region is larger away from the surface; (c) Vds >> 0; below the surface, the drain depletion region has
contacted the source depletion region, and a punch through current flows.

potential barrier no longer exists in the "contact" region; a large drain current which is not controlled
by the gate begins to flow. This phenomenon is known as punch through, and the current which
ensues is referred to as the punch through current.

Punch through is a failure mechanism witch limits the minimum channel length of a design.
The technology design roles should keep the designer from encountering this problem; its presence in
a design indicates a problem with the silicon process technology.

10. Hot Carrier Effects

During the 1970s, simple scaling rules for MOSFET technology were developed [32]. These
rules stipulated that the power supply voltage should be reduced in proportion to the reduction of FET
feature sizes (the channel length and width, the oxide thickness. etc.). However, a continually
changing power supply voltage is very difficult to accommodate in designs; it is much simpler to
maintain a constant supply voltage for compatibility.

Since constant voltage scaling was chosen over constant field scaling [24], a number of
interesting problems have manifested themselves in FET operation. With feature sizes decreasing
more rapidly than the power supply voltage, field strengths in the FET channel increased. This is
particularly notable at the drain end of a short channel device, where the applied bias Vdd is dropped
over a smaller channel length. Under the simple model described earlier, all carriers have the same
velocity, reaching a maximum at the saturation velocity VSAT. The carrier energy is then simply
computed from

U = 0.5 x m x VSAT2 (3.154)

where m is the carrier effective mass. However, as will be described in Chapter 4, this view is too
simplistic. A detailed simulation shows that the velocity (and thus the energy) of the carriers is i;, fact
a distribution; this distribution becomes more spread out as the field increases. High-energy carriers at
the high end of the distribution cause impact ionization, generating an electron and a hole; in nFETs,
the generated hole is swept away into the bulk, while the electron is injected into the oxide where it
can damage the device, leading to long-term reliability problems [33, 34]. This occurrence is known
as hoc carrier degradation, or by some similar name. The rate of degradation has been
 Figure 3.39 An nFET with lightly doped drain (LDD) extensions to the conventional source and drain.

shown to correlate with the substrate current in nFETs [33], and with the gate current in pFETs [35].

The device fabrication technology was modified to mitigate this problem: The field at the
drain junction can be decreased by increasing the width· of the lateral depletion region between the
pinch-off point and the drain. This is done by adding a lightly doped extension to the drain, as shown
in Figure 3.39. Normal source and drain diffusions are doped at a concentration of 5xlOl9 cm-3 to
lxl020 cm-3, while the lightly doped drain (LDD) regions are doped at a concentration of 4x 1018 cm-3
to 8x1018 cm-3. This reduces the field, and decreases the generation of hot carriers [36]. A penalty is
paid increased series resistance [37], in process complexity, and, as noted more recently, in an
inability to decrease the total device feature size as the effective channel length decreases [38]. Given
these difficulties, there is now strong interest in returning to constant field scaling as a method of
simplifying the FET structure [24, 39].

Although it is a topic of great interest to the device physicist: in general, a circuit designer
does not require a detailed model for hot, carrier degradation. The design rules should include
constraints on the power supply v6ltage and operating temperature that guarantee that difficulties with
hot carrier effects are not encountered.

11. Gate-Induced Drain Leakage

Constant voltage scaling has also led to another interesting problem. Consider an nFET drain region,
where the gate overlaps the drain diffusion (Figure 3.40a). With the gate grounded and the drain
biased, the silicon surface will be depleted, as shown in the band diagram of Figure 3.40b. Since the
silicon is doped n+, the depletion

Figure 3.40 The origins of gate· induced drain leakage; (a) gate overlap of the ˆheavily doped drain diffusion: (b)
band diagram for Vgs = 0 and Vds > O. Due to the high field carriers are generated by bend-to-band tunneling. From
[40]. © 1987 IEEE. Used by permission.
 Figure 3.41 Polysilicon gate fabrication process. Sidewall oxidation can introduce point defects into the silicon just
below the gate edge.

Figure 3.42 Potential profiles in FETs with channel dopant redistribution due to oxidation-enhanced diffusion. In
short channel devices, the change becomes significant.

region is very small, and the band bending is confined to a small spatial region; this implies a very
high field. Electrons can tunnel from the valence band near the surface into the conduction band,
leaving a hole behind. This is a generation mechanism, with the holes swept into the bulk and the
electrons into the drain, where they appear as a leakage current [40]. This leakage mechanism is
referred to as gate-induced drain leakage (GIDL).

12. Threshold Voltage Roll-Up

In most FET fabrication processes, after the polysilicon gate is defined by reactive ion
etching, its sides are oxidized to "clean them up" for further processing, such as spacer formation
(Figure 3.41). Depending on the oxidation process used, mechanical stress at the bottom of the gate
can introduce point defects into the silicon just below the gate edge. As processing proceeds, these
point defects gather impurities from the substrate, a process referred to as oxidation-enhanced
diffusion [41]. The effect on the device behavior is depicted in the potential profiles of Figure 3.42. In
a long channel device (Figure 3.413). The two minor "bumps" in the potential profile are not
significant when the gate bias forms the inversion layer. As the channel length decreases (Figure
3.42b), the increased potential at the ends of the channel becomes more significant, while in a shorter
device (Figure 3042c). the entire channel now has increased surface doping, leading to a larger
channel potential than that found in the longer device: ~ecal1ing (3.96) and (3.153).
 Figure 3.43 Threshold voltage roll-up due 10 oxidation-enhanced diffusion.

indicates that the increased potential manifests itself as an increasing threshold voltage with
decreasing channel length (Figure 3.43); this is known as threshold voltage roll-up [42].

13. Substrate Current-Induced Body Effect (SCBE)

As described above, hot carriers generate electron-hole pairs. In an nFET, the holes are swept
into the bulk and appear as substrate current. If the generation of holes becomes large, the hole
injection current, introducing positive charge into the hulk and charging it, produces an effect similar
to that on a small positive substrate bias Vbs; hence, the effect is known as the substrate current-
induced body effect [43]. The result is a decrease in the effective threshold voltage, and therefore an
increase in the drain current above the expected value. The total drain current also becomes the sum
of the usual drain current and the substrate current, further adding to the observed drain current [44].

14. Comments on Small Geometry Effects

The above list summarizes the various corrections required to model small geometry effects in FETs.
Many of these effects are included in the most popular FET models available in SPICE, and some
have been added more recently. A few have yet to be added, and it is not yet clear if their addition will
be necessary. As FET dimensions decrease further, it is certain that additional effects will arise that
will need to he taken into account.

It is reasonable to ask if the historical and current approach of a "base" long channel model,
continually decorated with a growing list of corrections, is still the best method. This is a topic that
will require considerable rethinking of the traditional approach to FET modeling. However, as all the
present FET models used in SPICE employ this traditional approach, such a discussion will not be
undertaken.
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