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Transfer of Control Operations

CS2600: Computer Organization and Architecture


Instruction Set Architecture - II1
I Branch or Jump
I Conditional or unconditional
I Forward or backword
I Skip 301
I Skips the next instruction. ..
.
Madhu Mutyam I Includes an implied address, so it does not require a 309 ISZ R1
PACE Laboratory
Department of Computer Science and Engineering destination address field. 310 BR 301
Indian Institute of Technology Madras I Ex: Increment-and-skip-if-zero (ISZ) instruction 311
 

I Procedure call
Feb 5 - 6, 2019

1 Chapter 12 of W. Stallings, Computer Organization and Architecture, 10th Edition.


Material for Atomic Instructions is taken from Culler, et. al. Parallel Computer Architecture.  

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Procedure Call Instructions Storing Return Address

I Register:
I A procedure is a self-contained program that is incorporated into a larger
I Call X causes RN ← PC + I and PC ← X
program. I The called procedure saves the contents of RN.
I Procedures provide modularity and reuse of the code. I Start of called procedure:
I Two basic instructions: call and return I Call X causes X ← PC + I and PC ← X+1
I A procedure can be called from more than one location. I The above two approaches complicate the use of reentrant procedures.
I A procedure call can appear in a procedure. I Top of stack:
I Each procedure call is matched by a return in the called program. I The calling procedure stacks both the return address and parameters to be
passed to the called procedure.

   

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Stack Frames Mutual Exclusion


I The entire set of parameters, including return address, that is stored for a
procedure invocation is referred to as a stack frame. I Ensures that only one process enters the critical section
I Simple software lock algorithm:

lock: ld register, location /* copy location to register */


y2 Stack cmp register, #0 /* compare with 0 */
pointer bnz lock /* if not 0, try again */
y1
st location, #1 /* store 1 to mark it locked */
Frame
Old frame pointer
pointer
ret /* return control to caller */
Q: Return point
Stack
unlock: st location, #0 /* write 0 to location */
x2 x2
pointer ret /* return control to caller */
x1 x1
Old frame pointer Frame Old frame pointer
pointer
P: Return point P: Return point
Two processes can enter the critical section
(a) P active (b) P has called Q    

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Atomic Read-Modify-Write Instructions Variants of Read-Modify-Write Instructions

I Hardware primates to implement synchronization


I Atomic test-and-set, swap, fetch-and-increment, etc
I Swap:
I Atomic test & set instruction: I Atomically swaps the values in a memory location and a register
I Value in a memory location is read into a specified register I Fetch & op:
I Constant 1 is stored into the location atomically
I I Atomically reads the current value of a location into a register and writes
Successful if the value loaded into the register is 0
I Other constants could be used instead of 0 and 1 the new value into the location
I fetch&increment; fetch&decrement; fetch&add;
lock: t&s register, location I Compare & swap:
bnz register, lock /* if not 0, try again */ I Three operands: a memory location, register to compare with, register to
ret /* return control to caller */ swap with
I Not commonly supported by RISC instruction sets
unlock: st location, #0 /* write 0 to location */
ret /* return control to caller */

   

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Instruction Sets Offering Hardware Support for x86 SIMD Instructions


Synchronization I Video and audio data are typically composed of small data types.
I In graphics, a single scene consists of an array of pixels, each pixel is
represented with 8-bit data and its color component (RGB) is represented
with another 8 bits.
I x86 has support for multi-media extensions (MMX)
I Same operation performed on multiple data elements at once.
I IBM 370: included atomic compare&swap for multiprogramming
I Each 64 bit data type consists of multiple smaller data fields:
I x86: any instruction can be prefixed with LOCK I Packed byte: Eight bytes packed into 64 bits.
I SPARC: atomic register-memory ops (swap, compare&swap) I Packed word: Four 16-bit words packed into 64 bits.
I Packed double word: Two 32-bit double words packed into 64 bits.
I MIPS, IBM Power: no atomic operations, but pair of instructions
I Saturation arithmetic is considered in MMX instruction set.
(load-locked, store-conditional)
F000h = 1111 0000 0000 0000
F000h = 1111 0000 0000 0000
+3000h = 0011 0000 0000 0000
+3000h = 0011 0000 0000 0000 10010 0000 0000 0000
10010 0000 0000 0000
1111 1111 1111 1111
Normal Arithmetic
 

Saturation Arithmetic  

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Thank You

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