AND GATE

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity and1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end and1;

architecture Behavioral of and1 is

begin
c<= a AND b;

end Behavioral;

VERILOG TEXT FIXTURE

module and2;
reg a;
reg b;
// Outputs
wire c;
// Instantiate the Unit Under Test (UUT)
and1uut (
.a(a),
.b(b),
.c(c)
);
initial begin
// Initialize Inputs
a = 0;b = 0;#100;
a = 0;b = 1;#100;
a = 1;b = 0;#100;
a = 1;b = 1;#100;
end
endmodule
 OR
VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity or1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end or1;

architecture Behavioral of or1 is

begin
c <= a OR b;

end Behavioral;

VERILOG
module or2;
// Inputs
reg a;
reg b;
// Outputs
wire c;
// Instantiate the Unit Under Test (UUT)
or1uut (
.a(a),
.b(b),
.c(c)
);
initial begin
// Initialize Inputs
a = 0;b = 0;#200;
a = 0;b = 1;#200;
a = 1;b = 0;#200;
a = 1;b = 1;#200;
// Add stimulus here
end

endmodule
 NAND GATE

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity and1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end and1;

architecture Behavioral of and1 is

begin
c<= a NAND b;

end Behavioral;

VERILOG TEXT FIXTURE

module and2;
reg a;
reg b;
// Outputs
wire c;
// Instantiate the Unit Under Test (UUT)
and1uut (
.a(a),
.b(b),
.c(c)
);
initial begin
// Initialize Inputs
a = 0;b = 0;#100;
a = 0;b = 1;#100;
a = 1;b = 0;#100;
a = 1;b = 1;#100;
end
endmodule
 AND GATE

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity and1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end and1;

architecture Behavioral of and1 is

begin
c<= a NOR b;

end Behavioral;

VERILOG TEXT FIXTURE

module and2;
reg a;
reg b;
// Outputs
wire c;
// Instantiate the Unit Under Test (UUT)
and1uut (
.a(a),
.b(b),
.c(c)
);
initial begin
// Initialize Inputs
a = 0;b = 0;#100;
a = 0;b = 1;#100;
a = 1;b = 0;#100;
a = 1;b = 1;#100;
end
endmodule
 XOR

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xor1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end xor1;

architecture Behavioral of xor1 is

begin
c <= a XOR b;

end Behavioral;

VERILOG TEXT FIXTURE

module xor2;
// Inputs
reg a;
reg b;
// Outputs
wire c;
// Instantiate the Unit Under Test (UUT)
xor1uut (
.a(a),
.b(b),
.c(c)
);
initial begin
// Initialize Inputs
a = 0;b = 0;#200;
a = 0;b = 1;#200;
a = 1;b = 0;#200;
a = 1;b = 1;#200;
end

endmodule
 XNOR

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xor1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end xor1;

architecture Behavioral of xor1 is

begin
c <= a XNOR b;

end Behavioral;

VERILOG TEXT FIXTURE

module xor2;
// Inputs
reg a;
reg b;
// Outputs
wire c;
// Instantiate the Unit Under Test (UUT)
xor1uut (
.a(a),
.b(b),
.c(c)
);
initial begin
// Initialize Inputs
a = 0;b = 0;#200;
a = 0;b = 1;#200;
a = 1;b = 0;#200;
a = 1;b = 1;#200;
end

endmodule
 BOOLEAN EXPRESSION 1
VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity boolean1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : out STD_LOGIC);
end boolean1;

architecture Behavioral of boolean1 is

begin

d <= ((not a)and b and c)or(a and(b or c))or (a and (not b) and c);

end Behavioral;

TEXT FIXTURE
module boolean_1;

// Inputs
reg a;
reg b;
reg c;

// Outputs
wire d;

// Instantiate the Unit Under Test (UUT)

boolean1 uut (
.a(a),
.b(b),
.c(c),
.d(d)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;
c = 0;

// Wait 100 ns for global reset to finish

#50;
 // Add stimulus here
a = 0;
b = 0;
c = 1;

// Wait 100 ns for global reset to finish

#50;

a = 0;
b = 1;
c = 0;

// Wait 100 ns for global reset to finish

#50;

a = 0;
b = 1;
c = 1;

// Wait 100 ns for global reset to finish

#50;

BOOLEAN EXPRESSION 2
VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity boolean2 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : out STD_LOGIC);
end boolean2;

architecture Behavioral of boolean2 is

begin
d <= ((not a)and (not b)and (not c)) or (b and(a or (not c)));

end Behavioral;

TEXT FIXTURE
module boolean_2;

// Inputs
reg a;
reg b;
reg c;
 // Outputs
wire d;

// Instantiate the Unit Under Test (UUT)

boolean2 uut (
.a(a),
.b(b),
.c(c),
.d(d)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;
c = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

a = 0;
b = 0;
c = 1;

// Wait 100 ns for global reset to finish

#100;

a = 0;
b = 1;
c = 0;

// Wait 100 ns for global reset to finish

#100;

a = 0;
b = 1;
c = 1;

// Wait 100 ns for global reset to finish

#100;

BOOLEAN EXPRESSION 3
VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity boolean3 is
 Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : in STD_LOGIC;
a : out STD_LOGIC);
end boolean3;

architecture Behavioral of boolean3 is

begin
a <= (x and y and (not z)) or ((not x) and y and z) or (x and (not y) and z);

end Behavioral;

TEXT FIXTURE
module boolean_3;

// Inputs
reg x;
reg y;
reg z;

// Outputs
wire a;

// Instantiate the Unit Under Test (UUT)

boolean3 uut (
.x(x),
.y(y),
.z(z),
.a(a)
);

initial begin
// Initialize Inputs
x = 0;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

x = 0;
y = 0;
z = 1;

// Wait 100 ns for global reset to finish

#100;
 x = 0;
y = 1;
z = 0;

// Wait 100 ns for global reset to finish

#100;
x = 0;
y = 1;
z = 1;

// Wait 100 ns for global reset to finish

#100;

HALF ADDER
VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity half1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end half1;

architecture Behavioral of half1 is

begin
s<=a xor b;
c<= a and b;

end Behavioral;

VERILOG TEXT FIXTURE

module half2;
// Inputs
reg a;
reg b;
// Outputs
wire s;
wire c;
// Instantiate the Unit Under Test (UUT)
half1uut (
.a(a),
.b(b),
.s(s),
.c(c)
);
 initial begin
// Initialize Inputs
a = 0;b = 0;#200;
a = 0;b = 1;#200;
a = 1;b = 0;#200;
a = 1;b = 1;#200;
// Add stimulus here
end

endmodule

FULL ADDER
VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FULLADDER1 is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Cout : out STD_LOGIC;
S : out STD_LOGIC);
end FULLADDER1;

architecture Behavioral of FULLADDER1 is

begin
S<=A XOR B XOR Cin;
Cout<=(A AND B) OR (Cin AND A) OR (Cin AND B);

end Behavioral;

VERILOG TEXT FIXTURE

module FULLLADDERR;
// Inputs
reg A;
reg B;
regCin;
// Outputs
wireCout;
wire S;
// Instantiate the Unit Under Test (UUT)
FULLADDER1 uut (
.A(A),
.B(B),
.Cin(Cin),
.Cout(Cout),
.S(S)
);
initial begin
A = 0;B = 0;Cin = 0;#100;
A = 1;B = 0;Cin = 0;#100;
A = 0;B = 1;Cin = 0;#100;
A = 1;B = 1;Cin = 0;#100;
A = 0;B = 0;Cin = 1;#100;
A = 1;B = 0;Cin = 1;#100;
A = 0;B = 1;Cin = 1;#100;
A = 1;B = 1;Cin = 1;#100;
end
endmodule
FULL ADDER USING HALF ADDER
VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fulladder1 is
Port ( a1 : in STD_LOGIC;
b1 : in STD_LOGIC;
cin : in STD_LOGIC;
s1: out STD_LOGIC;
cout : out STD_LOGIC);
end fulladder1;
architecture Behavioral of fulladder1 is

componenthalfadder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end component;
signal s2,x,y: STD_LOGIC;
begin
l1: halfadder port map(a1,b1,s2,x);
l2: halfadder port map(s2,cin,s1,y);
cout<=x or y;

VERILOG TEXT FIXTURE

module bb;
// Inputs
reg a1;
reg b1;
regcin;
// Outputs
wire s1;
wirecout;
 // Instantiate the Unit Under Test (UUT)
fulladder1uut (
.a1(a1),
.b1(b1),
.cin(cin),
.s1(s1),
.cout(cout)
);
initial begin
// Initialize Inputs
A = 0;B = 0;Cin = 0;#100;
A = 1;B = 0;Cin = 0;#100;
A = 0;B = 1;Cin = 0;#100;
A = 1;B = 1;Cin = 0;#100;
A = 0;B = 0;Cin = 1;#100;
A = 1;B = 0;Cin = 1;#100;
A = 0;B = 1;Cin = 1;#100;
A = 1;B = 1;Cin = 1;#100;
end
endmodule

4 BIT ADDER SUBSTRACTOR COMPOSITE UNIT

VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity addersub is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
m : in STD_LOGIC;
c : out STD_LOGIC;
s : out STD_LOGIC_VECTOR (3 downto 0));
end addersub;

architecture Behavioral of addersub is

component fulladder is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end component;
component Xo_gate
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end component;

signal cout : STD_LOGIC_VECTOR (4 downto 0);

signal sum : STD_LOGIC_VECTOR (3 downto 0);

begin

cout(0)<= m;
l1: for I in 3 downto 0 generate
x1: Xo_gate port map (m,b(i),sum(i));
end generate;

l2: for I in 3 downto 0 generate

x2: fulladder port map (sum(i),a(i),cout(i),s(i),cout(i+1));
end generate;

c<=cout(4);

end Behavioral;

VERILOG TEXT FIXTURE

module addder_sub;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg m;
// Outputs
wire c;
wire [3:0] s;
// Instantiate the Unit Under Test (UUT)
addersub uut (
.a(a),
.b(b),
.m(m),
.c(c),
.s(s)
);
initial begin
// Initialize Inputs
a = 4'b 1101;
b = 4'b 1011;
m = 0;
// Wait 100 ns for global reset to finish
#100;

// Add stimulus here

a = 4'b 1101;
b = 4'b 1011;
m = 1;

// Wait 100 ns for global reset to finish

 #100;

end

endmodule

3: 8 DECODER
VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Decoder is
Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC_VECTOR (7 downto 0));
end Decoder;

architecture Behavioral of Decoder is

begin
y<= "10000000" when a="000" else
"01000000" when a="001" else
"00100000" when a="010" else
"00010000" when a="011" else
"00001000" when a="100" else
"00000100" when a="101" else
"00000010" when a="110" else
"00000001" when a="111" ;

end Behavioral;

VERILOG TEXT FIXTURE

module De_coder;
// Inputs
reg [2:0] a;
// Outputs
wire [7:0] y;
// Instantiate the Unit Under Test (UUT)
Decoder uut (
.a(a),
.y(y)
);
initial begin
// Initialize Inputs
a =3'b 000;#50;
a =3'b 001;#50;
a =3'b 010;#50;
a =3'b 011;#50;
end
endmodule
2:1 MUX
VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux2 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : in STD_LOGIC;
m : out STD_LOGIC);
end mux2;

architecture Behavioral of mux2 is

begin
m<= (a and s) or (b and (not s));

end Behavioral;

VERILOG TEXT FIXTURE

module mux_2;

// Inputs
reg a;
reg b;
reg s;

// Outputs
wire m;

// Instantiate the Unit Under Test (UUT)

mux2 uut (
.a(a),
.b(b),
.s(s),
.m(m)
);

initial begin
// Initialize Inputs
a = 0;b = 0;s = 0;#100;
a = 0;b = 1;s = 0;#100;
a = 1;b = 0;s = 0;#100;
a = 1;b = 1;s = 0;#100;
a = 0;b = 0;s = 1;#100;
end
endmodule
 4:1 MUX
VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX_4_1 is
Port ( s : in STD_LOGIC_VECTOR (1 downto 0);
d : in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC);
end MUX_4_1;

architecture Behavioral of MUX_4_1 is

begin
y<= d(0) when s="00" else
d(1) when s="01" else
d(2) when s="10" else
d(3) when s="11" ;

end Behavioral;

VERILOG TEXT FIXTURE

module MUX_41;

// Inputs
reg [1:0] s;
reg [3:0] d;

// Outputs
wire y;

// Instantiate the Unit Under Test (UUT)

MUX_4_1 uut (
.s(s),
.d(d),
.y(y)
);

initial begin
// Initialize Inputs
s = 2'b 00;
d =4'b 0001;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

 s = 2'b 01;
d =4'b 0010;

// Wait 100 ns for global reset to finish

#100;
s = 2'b 10;
d =4'b 0100;

// Wait 100 ns for global reset to finish

#100;
s = 2'b 11;
d = 4'b 1000;

// Wait 100 ns for global reset to finish

#100;

end

endmodule

D FLIP FLOP

VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dff is
Port ( d : in STD_LOGIC;
clk : in STD_LOGIC;
qn : out STD_LOGIC;
q_n : out STD_LOGIC);
end dff;

architecture Behavioral of dff is

begin
process (clk)
variable temp,temp1:STD_LOGIC;
begin
if(clk='1') then
if(d='0') then
temp:='0';
temp1:='1';
else
temp:='1';
temp1:='0';
end if;
end if;
qn<=temp;
q_n<=temp1;
end process;

end Behavioral;

TEXT BENCH
module dff_;

// Inputs
reg d;
reg clk;

// Bidirs
wire qn;
wire q_n;

// Instantiate the Unit Under Test (UUT)

dff uut (
.d(d),
.clk(clk),
.qn(qn),
.q_n(q_n)
);

initial begin
// Initialize Inputs
d = 0;
clk = 1;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

d = 1;
clk = 1;

// Wait 100 ns for global reset to finish

#100;

end
endmodule

4 BIT UP DOWN COUNTER

VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity counter is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
d : in STD_LOGIC;
count : out STD_LOGIC_VECTOR (3 downto 0));
end counter;

architecture Behavioral of counter is

signal s: STD_LOGIC_VECTOR(3 downto 0);

begin
process(clk,rst)
begin
if (rst='1') then
s<="0000";
elsif (clk='1') then
if (d='1') then
s<=s+1;
else
s<=s-1;
end if;
end if;
end process;
count<=s;

end Behavioral;

TEXT BENCH
begin
d<='1';
rst<='0';

-- hold reset state for 100 ns.

wait for 10 ns;

wait for clk_period*10;

d<='0';
rst<='1';

wait for 10 ns;

wait for clk_period*10;

-- insert stimulus here
d<='1';
 rst<='0';

wait for 10 ns;

wait for clk_period*10;

wait;
end process;

4 BIT ALU
VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity ALU4 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
scl : in STD_LOGIC_VECTOR (2 downto 0);
outputs : out STD_LOGIC_VECTOR (3 downto 0));
end ALU4;

architecture Behavioral of ALU4 is

begin
process(a,b,scl)
begin
case scl is
when "000"=>
outputs<=a+b;
when "001" =>
outputs<=a-b;
when "010" =>
outputs<=a - 1;
when "011" =>
outputs<=a + 1;
when "100" =>
outputs<=a and b;
when "101" =>
outputs<=a or b;
when "110" =>
outputs<=not(a) ;
when "111" =>
outputs<=a xor b;
when others =>
outputs<="0000";
end case;
end process;
end Behavioral;

TEST BENCH

initial begin
// Initialize Inputs
a = 4'b1111;
b = 4'b1010;
scl = 000;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

a = 4'b1111;
b = 4'b1010;
scl = 001;

// Wait 100 ns for global reset to finish

#100;
a = 4'b1111;
b = 4'b1010;
scl = 010;

// Wait 100 ns for global reset to finish

#100;
a = 4'b1111;
b = 4'b1010;
scl = 011;
end

endmodule