Neuromorphic Engineering II Lab 6, Spring 2015 1

Lab 6 March 30, 2015

Post-layout simulation

Today you will learn about post-layout simulation, i.e. the differences in electrical behavior
between your (ideal) schematic and the actual drawn circuit. When someone says that
they will do a “post simulation”, they are saying in short that they are doing a post-layout
simulation.

The goals of this lab are to:

• understand how to extract a circuit including parasitics that are “back-annotated”

from the layout.

• Understand how to simulate a post-layout mixed design with schematics and ex-
tracted layout in ADE L.

• Understand AC simulation of your follower-integrator as a frequency-dependent

transmission element.

6.1 Instructions

1. Finish the exercise from last lab, i.e. build a new layout file that instances pads into
a padframe and wires your instanced layout for the delay line to the padframe. Get it
DRC and LVS clean. Get a screenshot for the lab report.

2. Extract a circuit model from the layout of your follower integrator that contains para-
sitic R and C elements. For this, you need to run through the detailed in the attached
document Steps for Calibre PEX (Parasitic Extraction) and Post-Layout simulation
in AMS 0.35um technology.

3. Now we need to incorporate this parasitic circuit into our simulation:

• Create a testbench (schematic) for your follower integrator. Apart from the
regular supplies, hook up a vdc source to your vin, set its dc voltage to 0.9
V and its ac magnitude to 1 V. This setup biases your follow integrator and
references your ac output to a normalized 1 V amplitude.
Neuromorphic Engineering II Lab 6, Spring 2015 2

• Create a new config cell view for the testbench. In the hierarchy editor, select
schematic for the view and your own library for the library list. For the view
list, select schematic spectre cmos sch calibre (Hint: you have to enter calibre
manually). Select spectre for the stop list.
• In the cell bindings, you can see that the hierarchy editor has found spectre
views for your sources and transistors, plus the schematic views for the test-
bench and follower integrator.
• Leave the hierarchy editor open, start ADE L from your testbench.
• In ADE L, select Setup - Design. Select the config view for your testbench.
Now, ADE L will use the hierarchy set up in the config view to simulate your
design. Since the config view at the moment only has Spectre and schematic
views instantiated, this setup is identical to simulating the schematic view (i.e.
what you have been doing so far when simulating).
• Set up an AC simulation from 1 Hz to 10 MHz, plot amplitude and phase dia-
grams.
• To incorporate your parasitic extracted version of the follower integrator, go to
the hierarchy editor cell bindings list. Manually enter calibre in the view to
use for the follower integrator cell, save. Because ADE L simulates based on
this config view, it will now use the parasitic circuit. You can see this from the
additional Spectre elements that were added to the cell bindings list, e.g. the
parasitic presistors.
• Repeat your AC simulation, note and explain the differences (Hint: set plot-
ting mode to append to get both plots in a single waveform window). Get a
screenshot for the lab report.

6.2 Postlab

Using the transistor mismatch AVT number from the lecture (1mv ∗ um/nm Tox), estimate
the random offset in the output voltage from the follower integrator delay line with 3 stages.
Use the value for Tox we derived in lab 3. You can assume that each differential pair and
current mirror transistor contributes equally to the offset voltage.

Does the offset in the biasing transistor also contribute equally? Why or why not?

Is this the only source of offset between input and output, i.e., is there also a source of
systematic offset?

6.3 Next Week

Following Easter holiday, we will start to define the class projects.

Steps for Calibre PEX (Parasitic Extraction) and
Post-Layout simulation in AMS 0.18um
technology
Ning Qiao, 30.3.15

1. in terminal-----: cd ~
2. : gedit calview.cellmap
3. replace all “auLVS” with “symbol” in this file. (the view of auLVS is not good in this PDK,
might cause overlaps of transistors in the schematic view generated by Calibre)
4. in layout window, choose Calibre—PEX to start PEX.
5. in Rules option, check whether you have the right PEX Rules file, if not choose the rule file in :
6. opt/vlsi/designkit/cadence_h18_HK/calibre/cmhv7sf/cacmhv7sfrules_lvs.run
7. in Outputs option, choose extraction type: we choose Transistor Level, R+C+CC, No
Inductance.
8. And in Netlist option, we choose Format: CALIBREVIEW and Use Names From:
SCHEMATIC

9. click Run PEX

10. after running, get the following options:

11. Output Library and Schematic Library should be the library where your layout cell in.
12. Choose the Cellmap file the one you changed before.
13. Choose Calibre View Type: schematic
14. Choose Device Placement : Layout Location
15. Click OK.

16. Go to Library Manager, find your cell for PEX, choose and open the cellview “calibre” which is
just generated by Calibre, open it. Or in step 5, choose “Edit-mode” in option “open Calibre
Cellview”.

17.
18.
You will see the pins, transistors and parasitic caps/resistors .

19. Important.(special step for our PDK)

I am not clear why but there is one parameter (gcon = 1) attached by Calibre which will hinder
the spectre to generate right netlist for simulation.
The way to fix it:
choose one NMOS,
press Q to edit the object Properties,
On the top of the interface, Choose “apply to all” “instance” of “same master ” to choose all NMOS.
Don't need to change anything, just click OK to close the window. (We just re-saved the transistors..)

Do the same thing to PMOS.

“Shift+X” to Check and Save your schematic.
After that, the gcon=1 will disappear:

20. Launch---ADE_L---run post simulations as you want using this schematic including parasitic
caps and resistors.
21. You can also start RVE to open the data svdb generated by PEX. Data is stored in ~/svdb.
Try to find the critical caps/resistors affecting the performance of your circuit.