EE 271 REVISION

Prob1: Design a counter that operates according to the sequence as shown in the table
besides.
A B C a. Draw a timing diagram for such a counter.
0 0 0 b. What is the period of the counter?
0 0 1 c. Give the flip-flop input equations if the counter is to be
0 1 1 implemented using a D flip flop for A, an R-S for B, and a J-K
1 0 1 for C.
1 1 1
1 1 0
1 0 0
0 1 0 1. We wish to have a counter that operates according to the sequence as
shown in the table besides.
A B C
0 0 0
0 0 1
0 1 1
1 0 1
1 1 1
1 1 0
1 0 0
0 1 0
a. Please draw a timing diagram for such a counter.

b. What is the period of the counter ?

c. Please give the flip-flop input equations if the counter is to be implemented using a D
flip flop for A, an R-S for B, and a J-K for C.

What is the period of the counter 8

A B 0 1 C
0 0 a 1
0 1 0 1
1 1 0 b
1 0 0 1
 A B
C

DA = BC+AB+AC

SB = A!B + !BC
RB = B!C + !AB

JC = !A!B
KC = AB

Prob 2: You've just been hired by the Really Fast Design Company to replace an engineer
who designed the following circuit. This circuit is intended to provide an output signal on QC
with a frequency of 500 KHz. However, the signal QC had a frequency of 1 MHz instead.
The flip flops have the following characteristics: dHL = 20ns, dLH = 10ns where dHL and dLH
are the high to low and low to high propagation delays respectively.

QC

Vcc
SET
J Q
C

SET SET
K CLR
Q
D Q J Q
c lo c k
A B
4 M Hz Q K Q
CLR CLR

a. Can you explain why? Please use a timing diagram as necessary for illustration.
b. How would you modify the design to work properly?
c.
a.

d.
b. e.
QC

SET
J Q
C
K CLR
Q
c lo c k

4 M Hz

f.
g.
h.
 i.
j.
k.
l.
m.
n.
o.
p.

Prob 3: A logic circuit has two inputs, Clock and Start, and two outputs, f and g. The
behavior of the circuit is described by the timing diagram in Figure 1. When a pulse is
received on the Start input, the circuit produces pulses on the f and g outputs as shown
in the timing diagram. Design a suitable circuit using only the following components:
a three-bit resettable positive-edge-triggered synchronous counter and basic logic
gates. For your answer assume that the delays through all logic gates and the counter
are negligible. Fig. 1

Prob 4:
As part of a system for locking on to an incoming data stream, we must apply FSM to
design a synchronizer that operates as follows:
- The two outputs of the synchronizer, Z1 and Z2, are normally in the logical 1 state.
- If the synchronizer detects the bit sequence 101 in the input data stream, the output Z1 is
to be asserted low. If the bit sequence 110 is detected, the output Z2 is to be asserted low.
- Data is entered least significant bit first.
- Once either pattern has been detected and Z1 or Z2 has been asserted, the synchronizer is
to enter a lock state where it is to remain, ignoring all further input data, until a restart
signal is received. At that time, the synchronizer must return to its initial state.
- Detection is to be done using a sliding window algorithm.
Prob 5:
Prob 6: You have just developed the most incredible gizwhatzit in the world and only the
time base unit remains to be designed. The time base has 2 inputs: select and clock and 1
output: sync. The unit has the following specifications:
 The input signal clock has a frequency of 1 M Hz.
 When select is a logical 0, the output signal, sync, is a 2 sec wide pulse with a
period of 5 sec. When select is a logical 1, the output signal, sync, is a 2 sec
wide pulse with a period of 7 sec.
a. Please draw a timing diagram for the output signal sync of the time base unit showing
its behavior when select is a logical 0.

sync

s e le c t

c lo c k

b. Please draw a timing diagram for the output signal sync of the time base unit showing
its behaviour when select is a logical 1.

sync

s e le c t

c lo c k

c. How many flip-flops should be used to build the time base? Please explain your
answer.
d. Please give the equations for the flip-flop inputs and the output signal sync if the time
base is to be implemented using D flip-flops.

Prob 7: Design an address decoder for a computing system consisting of a CPU having 15-bit
address bus, 2 RAMs 8KB, 4 RAMs 4KB.

Prob 8: 5. (20)