FPGA Implementation Of SHA Using VHDL Team ID- 48859

“FPGA IMPLEMENTATION OF SECURE HASH

ALGORITHM USING VHDL”

UDP
A PROJECT REPORT

SUBMITTED BY

Jinal Desai (120420111004)

Vandana Jain (120420111008)
Anjali Kapadia (120420111023)
Aysha Patel (120420111025)

Fulfillment for the award of the degree

Of
BACHELOR OF ENGINEERING
In
Electronics & Communication

SARVAJANIK COLLEGE OF ENGINEERING & TECHNOLOGY,SURAT

Gujarat Technological University, Ahmadabad

May-June 2016

Project guide : Prof. Nehal N Shah

Head of the department & Associate Professor
ECED, SCET

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

Sarvajanik Education Society

Sarvajanik College of Engineering & Technology

Surat.

Department of
Electronics & Communication Engineering

CERTIFICATE

This is to certify that Project report entitled “FPGA IMPLEMENTATION OF

SECURE HASH ALGORITHM USING VHDL”is prepared & presented by Jinal
Desai,Vandana Jain,Anjali Kapadia,Aysha Patel of B.E. IVth Electronics and Communication
Engineering department during year 2016.Their work is satisfactory.

Signature of Guide Signature of HOD Signature of Jury

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

UNDERTAKING ABOUT ORIGINALITY OF WORK

We hereby certify that we are the sole authors of this IDP/UDP project report and that neither
any part of this IDP/UDP project report nor the whole of the IDP/UDP Project report has
been submitted for a degree by other student(s) to any other University or Institution.

We certify that, to the best of our knowledge, the current IDP/UDP Project report does not
infringe upon anyone‟s copyright nor violate any proprietary rights and that any ideas,
techniques, quotations or any other material from the work of other people included in our
IDP/UDP Project report, published or otherwise, are fully acknowledged in accordance with
the standard referencing practices. Furthermore, to the extent that we have included
copyrighted material that surpasses the boundary of fair dealing within the meaning of the
Indian Copyright (Amendment) Act 2012, we certify that we have obtained a written
permission from the copyright owner(s) to include such material(s) in the current IDP/UDP
Project report and have included copies of such copyright clearances to our appendix.

We have checked the write up of the present IDP/UDP Project report using anti -plagiarism
database and it is in the allowable limit. In case of any complaints pertaining to plagiarism,
we certify that we shall be solely responsible for the same and we understand that as per
norms, University can even revoke BE degree conferred upon the student(s) submitting this
IDP/UDP Project report, in case it is found to be plagiarized.

Team:

Enrollment No. Name Signature

120420111004 Jinal Desai
120420111008 Vandana Jain
120420111023 Anjali Kapadia
120420111025 Aysha Patel

Place: SCET, Surat Date:

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

Acknowledgement

We would like to express our deep sense of gratitude to our guide Prof.Nehal N Shah for
guiding us throughout to create such an excellent report and also for her full dedication and
devotion of time. It was a blast of report to write.
We would further like to thank our head of department Prof.Nehal N Shah and all the
faculty members to give us this opportunity. And want to thank my god.
Last but not the least, acknowledgement will not be over without mentioning a word of
thanks to all our friends and colleagues who helped us directly or indirectly in all the way
throughout this semester.

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

CONTENTS
ACKNOWLEDGEMENT ................................................................................................................................... 4
CONTENTS .......................................................................................................................................................... 5
LIST OF FIGURES .............................................................................................................................................. 6
1. INTRODUCTION ............................................................................................................................................ 7
1.1 AIM OF THE PROJECT ......................................................................................................................................... 7
1.2 INTRODUCTION ................................................................................................................................................. 7
1.3 LITERATURE SURVEY .............................................................................................................................. 8
1.3.1 FPGA .......................................................................................................................................................... 8
1.3.2 FPGA Architecture ................................................................................................................................ 9
1.3.3 Programmable Logic Block ................................................................................................................... 9
1.3.4 Programmable Interconnect .............................................................................................................. 10
1.3.5 Input Output Blocks (IOB) ................................................................................................................... 11
1.3.6 Specification of FPGA kit .................................................................................................................... 11
1.3.7 Required tools for interfacing............................................................................................................. 13
1.3.8 Flow of FPGA Programming ............................................................................................................... 14
2. DESIGN ........................................................................................................................................................... 15
2.1 CANVAS ........................................................................................................................................................ 15
2.1.1 AEIOU summary Canvas ..................................................................................................................... 15
2.1.2 Empathy summary Canvas ................................................................................................................. 15
2.1.3 Product development Canvas ............................................................................................................. 16
2.1.4 Ideatation Canvas .............................................................................................................................. 16
2.1.5 Business Model Canvas ...................................................................................................................... 17
3. VHDL............................................................................................................................................................... 18
3.1 INTRODUCTION OF VHDL ................................................................................................................................. 18
3.2 COMPARISON ................................................................................................................................................. 20
3.2.1 Comparison of VHDL and Verilog ....................................................................................................... 20
3.2.2 Comparison of CPLD and FPGA .......................................................................................................... 21
4. CRYPTOGRAPHY ........................................................................................................................................ 22
4.1 INTRODUCTION OF CRYPTOGRAPHY .................................................................................................................... 22
5. SECURE HASH ALGORITHM ................................................................................................................... 23
5.1 CLASSIFICATION AND COMPARISON OF SHA ........................................................................................................ 23
5.2 SPECIFICATION OF SHA 1 ................................................................................................................................ 24
5.3 BLOCK DIAGRAM OF SHA ................................................................................................................................. 24
5.4 FLOW OF DESIGN ........................................................................................................................................... 25
5.5 IMPORTANT PROPERTIES .................................................................................................................................. 27
5.6 SHA ALGORITHM .......................................................................................................................................... 27
Step 0: Initialize some variables ................................................................................................................. 27
Step 1: Pick a string .................................................................................................................................... 28
Step 3: Convert characters to ASCII codes ................................................................................................. 28
Step 4: Convert numbers into binary ......................................................................................................... 28
Step 5: Append '1' to the end ..................................................................................................................... 28
Step 6: Append '0's' to the end ................................................................................................................... 29
Step 6.1: Append original message length ................................................................................................ 29
Step 7: 'Chunk' the message....................................................................................................................... 29
Step 9: 'Extend' into 80 words .................................................................................................................... 30
Step 10: Initialize some variables ............................................................................................................... 34
Step 11: The main loop ............................................................................................................................... 34
Step 11.1: Four choices ............................................................................................................................... 34

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Step 11.2: Put them together ..................................................................................................................... 37

Step 12: The end ......................................................................................................................................... 38
6. DESIGN SUMMARY..................................................................................................................................... 39
7. APPLICATION .............................................................................................................................................. 43
8. WORK PLAN ................................................................................................................................................. 44
8.1 WORK DONE IN ODD SEMESTER ........................................................................................................................ 44
8.2 WORK DONE IN EVEN SEMESTER (TILL 8/3/2016) ...................................................................................... 45
9. SUMMARY ..................................................................................................................................................... 45
10. REFERENCES ............................................................................................................................................. 46
11. APPENDIX ................................................................................................................................................... 47
11.1 PERIODIC PROGRESS REPORT (PPR) ......................................................................................................... 47
11.2 PATENT DRAFTING EXERCISE (PDE) .......................................................................................................... 47
11.3 PLAGIARISM REPORT ................................................................................................................................ 47

LIST OF FIGURES

1.Structure of FPGA ................................................................................................................. 9

2.Programmable logic blocks................................................................................................... 10
3.FPGA Interconnection Schematic......................................................................................... 11
4.XC3S400 ............................................................................................................................... 13
5.Device Model ........................................................................................................................ 19
6.Classification of SHA ........................................................................................................... 23
7.Block Diagram ...................................................................................................................... 24
8 Example 1-$cEt ..................................................................................................................... 39
9 Example 2 _(space)@! .......................................................................................................... 41
10 Example 3- SHA ................................................................................................................. 42
11 Example 4- EC16 ................................................................................................................ 42

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1. Introduction

1.1 Aim of the Project

Implementation of the cryptographic algorithm i.e. secure hash algorithm on the FPGA board
using VHDL.

1.2 Introduction

VHDL is an acronym for VHSIC Hardware Description Language (VHSIC is an acronym for
Very High Speed Integrated Circuits). It is a hardware description language that can be used
to model a digital system at many levels of abstraction ranging from the algorithmic level to
the gate level. VHDL is a hardware description language that can be used to model a digital
system. It contains elements that can be used to describe the behavior or structure of the
digital system, with the provision for specifying its timing explicitly.
Cryptography is one of the fundamental components for secure communication of data and
authentication. However, cryptographic algorithms impose tremendous processing power
demands that can be a bottleneck in high-speed networks. The implementation of a
cryptographic algorithm must achieve high processing rate to fully utilize the available
network bandwidth. To follow the variety and the rapid changes in algorithms and standards,
a cryptographic implementation must also support different algorithms and be upgradeable in
field. Otherwise, interoperability among different systems is prohibited and any upgrade
results in excessive cost. The ultimate solution for the problem would be an adaptive
processor that can provide software-like flexibility with hardware-like performance. Efficient
hardware design is essentially a resource allocation problem. The goal is, given the
constraints, to find the optimal balance between required silicon area, operation throughput,
energy consumption and design time to implement a system.

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1.3 Literature Survey

1.3.1 FPGA

A Field Programmable Gate Array is a semiconductor device containing programmable logic

components called "logic blocks", and programmable interconnects. Logic blocks can be
programmed to perform the function of basic logic gates such as AND, and XOR, or more
complex combinational functions such as decoders or mathematical functions. In most
FPGA‟s, the logic blocks also include memory elements, which may be simple flip-flops or
more complete blocks of memory.
Field Programmable means that the FPGA's function is defined by a user's program rather
than by the manufacturer of the device. A typical integrated circuit performs a particular
function defined at the time of manufacture. In contrast, the FPGA's function is defined by a
program written by someone other than the device manufacturer. Depending on the particular
device, the program is either 'burned' in permanently or semi permanently as part of a board
assembly process, or is loaded from an external memory each time the device is powered up.
This user programmability gives the user access to complex integrated designs without the
high engineering costs associated with application specific integrated circuits. Over the past
few years, the density of the average programmable logic device has begun to skyrocket. The
maximum number of gates in an FPGA is currently around 5,00,000 and doubling every 18
months.
FPGAs contain programmable logic components called "logic blocks", and a hierarchy of
reconfigurable interconnects that allow the blocks to be "wired together"-somewhat like a
one-chip programmable breadboard. Logic blocks can be configured to perform complex
combinational functions, or merely simple logic gates like AND and XOR. In most FPGA‟s,
the logic blocks also include memory elements, which may be simple flip-flops or more
complete blocks of memory.
The FPGA industry sprouted from programmable read only memory (PROM) and
programmable logic devices (PLDs). PROMs and PLDs both had the option of being
programmed in batches in a factory or in the field (field programmable), however
programmable logic was hard-wired between logic gates.
Xilinx Co-Founders, Ross Freeman and Bernard Vonder schmitt, invented the first
commercially viable field programmable gate array in 1985 – the XC2064. The XC2064 had
programmable gates and programmable interconnects between gates, the beginnings of a new
technology and market. The XC2064 boasted a mere 64 configurable logic blocks (CLBs),
with two 3-input lookup tables (LUTs). More than 20 years later, Freeman was entered into
the National Inventor‟ss Hall of Fame for his invention.
The 1990s were an explosive period of time for FPGA‟s, both in sophistication and the
volume of production. In the early 1990s, FPGAs were primarily used in telecommunications
and networking. By the end of the decade, FPGAs found their way into consumer,
automotive, and industrial applications.

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1.3.2 FPGA Architecture

The typical FPGA consists of the following components:

1. Programmable Logic blocks
2. Interconnection Resources
3. Input output blocks

1.Structure of FPGA

1.3.3 Programmable Logic Block

The programmable logic block in a typical FPGA consists of Configurable Logic Blocks
(CLB). The CLB can be realized in many ways one of them being the Look up Table (LUT)
based CLB. The LUT is a one bit wide memory location. The memory address lines are the
inputs to the LUT and the one bit output is the LUT output. Thus the LUT with K-inputs acts
as a 2kx1 bit memory and the user can directly implement any k input function by
programming the functions truth table into the LUT. The figure 2.2 shows a generalized CLB
that can be used for implementing any logic function of up to nine inputs; two separate four
input logic functions and many other possibilities. The CLB also has a D-Flip Flop that can
be used to implement sequential logic functions. The CLB has also got features that support
the integration of entire systems. It has also go certain specialized circuitry that enables it
perform arithmetic operations like addition, multiplication etc. in a fast and efficient manner.
Users can also configure the LUT in the CLB as read/write RAM locations. Some FPGA also
allow configuration of their LUT„s as Dual port RAM„s with one write and two read inputs.
The chips also include very wide FPGA vs. ASICs AND planes around the periphery of the
CLB to facilitate implementation of wide decoders.

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2.Programmable logic blocks

1.3.4 Programmable Interconnect

The other most important feature that decides the performance of the FPGA is programmable
interconnects. This is because programmable interconnect allow the implementation of an
entire digital system by providing a means of connecting various individual circuits
(subsystems) that have been implemented on different CLB„s in an FPGA. The
programmable interconnect in typical FPGA can be classified as. 1. General Purpose
Interconnects: Signal between CLBs and Input/output Blocks (IOBs) can be routed through
switch matrices as they travel along the horizontal and vertical interconnect lines. 2. Direct
Interconnects: Adjacent CLBs are interconnected directly. 3. Long Lines: Long lines provide
for high fan out, low-skew distribution of signals that must travel relatively long distances.
They span the entire length or width of the interconnect area. They are typically used for
clock signals. FPGA interconnects are normally unsegmented i.e. each wiring segment spans
only one logic block before it terminates in a switch box. A switch box is a switching matrix
that contains programmable interconnections to all the wiring segments that terminate inside
it. By turning on some of the programmable switches within a switch box, longer paths can
be constructed. Figure 2 shows typical FPGA interconnection scheme.

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3.FPGA Interconnection Schematic

1.3.5 Input Output Blocks (IOB)

The IOB provides the interface between the FPGA and the real world signals. The IOB
consists broadly of I/O pads. The I/O pads connect to one of the pins on the IC package so
that the external signals can be input to or output from the array of logic cells. It also consists
of tristate buffers, which enable the signals to be input to and output from the logic array. Flip
flops are provided so that the input and the output values can be stored within the IOB. Each
IOB has also got a variety of other features like reprogram ability of the input threshold to
respond to either TTL or CMOS logic levels. It also incorporates slew rate control of the
output signal and includes internal pull up resistors to avoid floating inputs.

1.3.6 Specification of FPGA kit

For hardware design we are going to use XC3S400k FPGA kit. In that there is one FPGA of
which supports 400 kilo gate count. In that kit with interface PROM which is used to store our
program initially.FPGA is shown in fig .

1) In FPGA implementation we are going to use XC3S400 FPGA kit. Here XC means Xilinx and
3S means Spartan 3 and 400 means 400 K gate count means it can supports the design of 400 K
gate count.

2) FPGA kit contain total 208 pin out of them more than 100 GPIO (General purpose Input
Output) pins are available for user interface .

3) FPGA must apply +5V dc supply.

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FPGA download cables

FPGA vendors provides many ways to “configure” (i.e. download) their devices. One way is
using a cable that connects from your PC to the FPGA board. The most popular cables
connect to your PC‟s parallel or USB interface.
These cables are sometimes called “JTAG cables”(because they often connect to the JTAG
pins of an FPGA).

FPGA configuration
An FPGA can be into 2 states: “configuration mode” or “user mode”. When the FPGA wakes
up after power-up, it is in configuration mode, sitting idle with all its outputs in active. You
need to configure it. Configuring an FPGA means downloading a stream of 0‟s and 1‟s into it
through some special pins. Once the FPGA is configured, it goes into “user mode” and
becomes active, performing accordingly to your programmed “logic functions”. There are 3
classical ways to configure your FPGA.

 You use a cable from your PC to the FPGA. And run a software on your PC to send
data through the cable.
 You use a micro controller on your board, with an adequate firmware to send data to
the FPGA.
 You use a “boot-PROM” on your board , connected to the FPGA. That configures the
FPGA automatically at power-up (FPGA vendors have such special boot-PROMs in
their catalogs) during development. The first method is the easiest and quickest. Once
your FPGA design works you probably don‟t need the PC anymore, so the other 2
methods come in use. FPGA configuration can quickly become a complex subject. So
you might want to skip this section. Especially if you intend to use an already made
FPGA development board. Development boards usually comes with a special cable
that you can use to configure the FPGA from your PC with no knowledge of the
underlying interface.

FPGA pins fall into 2 categories: “dedicated pins” and “users pins”. About 20%-30%
of the pins of an FPGA are "dedicated pins” which means that they are hardcoded to a
specific function.

The dedicated pins fall into 3 following categories.

 Power pins: ground and core/IO power pins.
 Configuration pins: used to “download” the FPGA.
 Dedicated inputs, or clock pins: These are able to drive large net inside the
FPGA, suitable for clock or signals with large fan-outs.

The rest are user pins (called “IOs”, or “I/Os”, or “user I/Os”, or “user IOs”, or “IO pins”). IO
stands for “input – output”.
1. You usually have total control over user IOs. They can be programmed to be inputs,
outputs, or bi-directional (tri-stable buffers).

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2. Each “IO pins” is connected to an “IO cell” inside the FPGA. The “IO cells” are
powered by the VCCIO pins ( IO power pins).
3. An FPGA has many VCCIO pins, usually all connected to the same voltage. But new
generations of FPGAs have a concept of “user IO banks”. The IOs are split into
groups, each having its own VCCIO voltage. That allows using the FPGA as a voltage
translator device useful for example if one part of your board works with 3.3V logic,
and another with 2.5V.

FPGA power
FPGAs usually require two voltages to operate, a “core voltage” and an “IO voltage”. Each
voltage is provided through separate power pins.

 The internal core voltage (called VCCINT here) is fixed (set by the model of FPGA
that you are using.) It is used to power the logic gates and flip flops inside the FPGA.
The voltage was 5V for older FPGA generations and is coming down as new
generation come (3.3V, 2.5V, 1.8V, 1.5V, 1.2V and even lower for the latest devices).
 The IO voltage (called VCCIO here) is used to power the I/O blocks (=pins) of the
FPGA. That voltage should match what the other devices connected to the FPGA
except.

4.XC3S400

1.3.7 Required tools for interfacing

There are other hardware interface with FPGA kit shown below:
1) The clock circuit: connect to one of the pins on board 100 KHz clock oscillator.

2) There are ten pin header on TKB3S daughter board intended for use as a GPIO(General
Purpose Input Output). These connect to various interface header blocks on the TK base inter
face card.

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3) The key board circuit: connect the header1 on TKB3S to the keyboard matrix header CNkey
. This enables TKB3SXX to scan and read the keyboard.

4) THE 8 LED’S: This 8 led are use for program status display and can be programmed by the
user. Connect the TKB3SXX header pin 1 thru 8 to thru 8 block header marked CNLED.

1.3.8 Flow of FPGA Programming

HARDWARE
DESCRIPTION
TESTBENCH

CHECK SYNTAX

SIMULATOR SYSTEM CO
VERIFICATION

SYNTHESIS

PLACE AND ROUTE

BIT STREAM

TIMING ANALYSIS

PLATFORM FPGA

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2. Design

2.1 Canvas
2.1.1 AEIOU summary Canvas

2.1.2 Empathy summary Canvas

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2.1.3 Product development Canvas

2.1.4 Ideatation Canvas

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2.1.5 Business Model Canvas

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3. VHDL

3.1 Introduction of VHDL

VHDL is a hardware description language that can be used to model a digital system. It
contains elements that can be used to describe the behaviour or structure of the digital system,
with the provision for specifying its timing explicitly. The language provides support for
modelling the system hierarchically and also supports top-down and bottom-up design
methodologies. The system and its subsystems can be described at any level of abstraction
ranging from the architecture level to gate level. Timing can also be explicitly modelled in
the same description.
The VHDL language can be regarded as an integrated amalgamation of the following
languages: Sequential language + concurrent language + net-list language + timing
specifications + Waveform generation language => VHDL
Some of the basic VHDL building blocks that are used in almost every description •Entity:
All designs are expressed in terms of entities. An entity is the most basic building block in a
design. The uppermost level of the design is the top-level entity. If the design is hierarchical,
then the top-level description will have lower-level descriptions contained in it. These lower
level descriptions will be lower-level entities contained in the top-level entity description.
•Architecture: All entities that can be simulated have an architecture description. The
architecture describes the behaviour of the entity. A single entity can have multiple
architectures. One architecture might be behavioural while another might be a structural
description of the design.
•Configuration: A configuration statement is used to bind a component instance to an
entityarchitecture pair. A configuration can be considered like a parts list for a design. It
describes which behaviour to use for each entity, much like a parts list describes which part
to use for each part in the design.
•Package: A package is a collection of commonly used data types and subprograms used in a
design. Think of a package as a toolbox that contains tools used to build designs.
•Driver: This is a source on a signal. If a signal is driven by two sources, then when both
sources are active, the signal will have two drivers.
•Bus: The term “bus” usually brings to mind a group of signals or a particular method of
communication used in the design of hardware. In VHDL, a bus is a special kind of signal
that may have its drivers turned off.
•Attribute: An attribute is data that are attached to VHDL objects or predefined data about
VHDL objects. Examples are the current drive capability of a buffer or the maximum
operating temperature of the device.
•Generic: A generic is VHDL‟s term for a parameter that passes information to an entity. For
instance, if an entity is a gate level model with a rise and a fall delay, values for the rise and
fall delays could be passed into the entity with generics.

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•Process: A process is the basic unit of execution in VHDL. All operations that are performed
in a simulation of a VHDL description are broken into single or multiple processes.
VHDL is used to describe a model for a digital hardware device. This model specifies the
external view of the device and one or more internal views. The internal view of the device
specifies the functionality or structure, while the external view specifies the interface of the
device through which it communicates with the other models in its environment. The device
to device model mapping is strictly a one- to -any. That is, a hardware device may have
manydevice models. For example, a device modelled at a high level of abstraction may not
have a clock as one of its inputs, since the clock may not have been used in the description.
Also the data transfer at the interface may be treated in terms of say, integer values, instead of
logical values. In VHDL, each device model is treated as a distinct representation of a unique
device, called an entity in this text. Figure 2.5 shows the VHDL view of a hardware device
that has multiple device models, with each device model representing one entity. Even
though entity I through N represents N different entities from the VHDL point of view, in
reality they represent the same hardware device.

5.Device Model

The entity is thus a hardware abstraction of the actual hardware device. Each entity is
described using one model that contains one external view and one or more internal views. At
the same time, a hardware device may be represented by one or more entities.

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3.2 Comparison

3.2.1 Comparison of VHDL and Verilog

VHDL (VHSIC Hardware Description Verilog

Language)
Multiple design units may be separately Compilation order of code in a single file and that
Compiled. of multiple files is different.
User defined Data types. Data types are defined by Verilog language and
not by user
Procedures and functions are placed in packages There is no concept of package here. Procedures
so that they are available to any design unit that and functions used within a model must be
wishes to use them. defined in the module.
Less intuitive at first as it is very strongly typed It is easier to grasp and understand.
and there are many ways to model the same
circuit.
More constructs and features for high level Only for parameterize models by overloading
modelling in VHDL. parameter constants.
Attribute “foreign” allows architectures and Verilog models are non-standard and so may not
programs to be modeled in another language. be usable by another Verilog tools.
Library concept is used in VHDL for storing No concept of library in Verilog.
compiled entities, architectures, packages and
configurations.

They can manage large design structure. There are no statements in Verilog to manage
. large designs.

They allow concurrent procedure calls. They don‟t allow concurrent task calls.

VHDL has generic and configuration statements They are not found in Verilog
useful in test harnesses.

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3.2.2 Comparison of CPLD and FPGA

CPLD (Complex Programmable Logic Device) FPGA (Field Programmable Logic Device)

Logic blocks of CPLD contain multiple macro Logic blocks of FPGA can be small as well as
cells. large but are never as large as those of CPLD.
They contain logic gates, lookup table and
flipflops
It has less flexible architecture. It has more flexible architecture.

Delay through CPLD is more predictable and Delay here is variable and unpredictable.
shorter, because of continuous interconnect.
Used where high performance logic is required. Used where processing of input must be
performed at very high speed.

Faster in performance. Slower in performance than CPLD.

They use continuous interconnected structure. They use segmented interconnected structure.

Density is low to high. Density is medium to high.

Device utilization is high. Device utilization is moderate.

Signals that travel to different locations through Here no two signals can be guaranteed to arrive
different paths in the device arrive at their their destination at the same time. Hence they
destinations without much delay. Hence CPLD have signal skew
have negligible signal skew.

Expensive. Less expensive.

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4. Cryptography

4.1 Introduction Of Cryptography

Cryptography allows people to carry over the confidence found in the physical world to the
electronic world, thus allowing people to do business electronically without worries of deceit
and deception. Every day hundreds of thousands of people interact electronically, whether it
is through e-mail, e-commerce (business conducted over the Internet), ATM machines, or
cellular phones. The perpetual increase of information transmitted electronically has lead to
an increased reliance on cryptography. Cryptography is extremely useful, there is a multitude
of applications, many of which are currently in use. A typical application of cryptography is a
system built out of the basic techniques. Such systems can be of various levels of complexity.
Some of the more simple applications are secure communication, identification,
authentication, and secret sharing. More complicated applications include systems for
electronic commerce, certification, secure electronic mail, key recovery, and secure computer
access.
Cryptography today might be summed up as the study of techniques and applications that
depend on the existence of difficult problems. Cryptanalysis is the study of how to
compromise (defeat) cryptographic mechanisms, and cryptology is the discipline of
cryptography and cryptanalysis combined.
Encryption is the transformation of data into a form that is as close to impossible as possible
to read without the appropriate knowledge Its purpose is to ensure privacy by keeping
information hidden from anyone for whom it is not intended, even those who have access to
the encrypted data. Decryption is the reverse of encryption; it is the transformation of
encrypted data back into an intelligible form. Encryption and decryption generally require the
use of some secret information, referred to as a key. For some encryption mechanisms, the
same key is used for both encryption and decryption; for other mechanisms, the keys used for
encryption and decryptions are different.
There are two types of cryptosystems: secret-key and public-key cryptography: In a public-
key cryptosystem, the private key is always linked mathematically to the public key.
Therefore, it is always possible to attack a public-key system by deriving the private key from
the public key. Typically, the defense against this is to make the problem of deriving the
private key from the public key as difficult as possible. For instance, some public-key
cryptosystems are designed such that deriving the private key from the public key requires
the attacker to factor a large number, it this case it is computationally infeasible to perform
the derivation. The algorithms like the RSA, RC4, RC6 are some of the public-key
algorithms. The public-key algorithms are much suited for software implementation rather
than hardware implementation.
Now one of the applications of where cryptography can be used is secure communication.
This basically, uses the private-key type of cryptosystem where a single key can b used for
both encryption and decryption. Block cipher is an Encryption/Decryption scheme which
breaks up the plaintext/cipher text messages to be transmitted/received into strings (called
Blocks) of fixed length. It encrypts/decrypts one block at a time, thus all the transformations
and operations must be executed over a byte or a set of bytes.

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

5. Secure Hash Algorithm

A hash function is simply an algorithm that takes a string of any length and reduces it to a
unique fixed length string. Hashes are used to ensure data and message integrity, password
validity as well as the basis of many other cryptographic systems. It is impossible to re-create
a message from a given a fingerprint. The secure hash function is Collision Free that means
that the two strings would not have the same hash function.

5.1 Classification and Comparison of SHA

6.Classification of SHA

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

5.2 Specification Of SHA 1

Max input size - 264-1

Fixed output bit – 160
Internal Block Size – 512
Basic operation used - AND ,XOR , Rotation ,Modulo 232 Addition
Implementation on FPGA board – XC3S400
Simulation on Xilinx
One Way Function – It can not be decrypted ,only encryption part is there

5.3 Block Diagram of SHA

7.Block Diagram

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

5.4 Flow Of Design

Start

Initialization of five functions in BE format

according to MD‟s

160 bits input string

Dividing into characters (including space)

Convert characters into their ASCII and then Binary

Put them together and append 1

If length
< 448
No

Padding zeroes (996 – yes

length = no. of zeroes)
A

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

C
Padding zeroes (448 – length = no. of zeroes)

Divide into words(32 bits) = 16 words

Extension of words (80 words)

Making groups of 4 words i.e. i-16, i-13, i-8,i-2; where i=16 to

79; In those groups do XORing and Left rotate by factor 1

Divide 80 words into 4 groups

Define functions for different groups

From the outputs of the functions Make „Temp‟ variable

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

Redefine initialised functions using variables

Convert them into HEX and put them together

Result

5.5 Important Properties

Each hash is unique but always repeatable.That means that the word 'cat' will hash to
something that no other word hashes too, but it will always hash to the same thing.
The function is 'one way'.Meaning that if you are given the value of what 'cat' hashes too but
you didn't know what made it, you would never be able to find out that 'cat' was the original
word.There are many different hash functions but the one will be concentrating on today is
called the Secure Hash Algorithm 1 or SHA-1.

5.6 SHA Algorithm

The step by step algorithm which is shown in the flow chart is explained here. The following
example will explain the process of SHA.

Step 0: Initialize some variables

There are five variables that now need to be initialized.

 h0 = 01100111010001010010001100000001
 h1 = 11101111110011011010101110001001
 h2 = 10011000101110101101110011111110
 h3 = 00010000001100100101010001110110
 h4 = 11000011110100101110000111110000

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Step 1: Pick a string

In this example I am going to use the string: 'A Test'.

A Test

Step 2: Break it into characters

You must now break the string into characters.

 A
 (Space)
 T
 e
 s
 t

Note that spaces count as characters.

Step 3: Convert characters to ASCII codes

Each character should now be converted from text into ASCII. ASCII or the 'American
Standard Code for Information Interchange' is a standard that allows computer to
communicate different symbols by assigning each one a number. No matter what font or
language you use, the same character will always have the same ASCII code.

 65
 32
 84
 101
 115
 116

Note that 'T' and 't' are different ASCII characters.

Step 4: Convert numbers into binary

Binary is simply base two. All base ten numbers are now converted into 8-bit binary
numbers. The eight-bit part means that if they don't actually take up a full eight place values,
simply append zeros to the beginning so that they do.

 01000001
 00100000
 01010100
 01100101
 01110011
 01110100

Step 5: Append '1' to the end

Put the numbers together:
010000010010000001010100011001010111001101110100

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

Append the number '1' to the end:

0100000100100000010101000110010101110011011101001

Step 6: Append '0's' to the end

In this step you add zeros to the end until the length of the message is congruent to 448 mod
512. That means that after dividing the message length by 512, the remainder will be 448. In
this case, the length of the original message in binary is 48 + 1 from the last step. That means
that we will need to add a total of 399 zero's to the end.

01000001001000000101010001100101011100110111010010000000000000000000000000-
00000000000000000000000000000000000000000000000000000000000000000000000000-
00000000000000000000000000000000000000000000000000000000000000000000000000-
00000000000000000000000000000000000000000000000000000000000000000000000000-
00000000000000000000000000000000000000000000000000000000000000000000000000-
00000000000000000000000000000000000000000000000000000000000000000000000000-
0000

If your original message were 56 characters long, it would be exactly 448 digits long once
converted into binary. After adding the '1' to the end of that, the new message would be 449
characters long. If that were the case you would need to append 575 zero's to make the
message congruent to 448%512.If your original message were 64 characters long, it would be
exactly 512 digits long once converted into binary. After adding the '1' to the end of that, the
new message would be 513 characters long. If that were the case you would need to append
447 zero's to make the message congruent to 448%512.

Step 6.1: Append original message length

This is the last of the 'message padding' steps. You will now add the 64-bit representation of
the original message length, in binary, to the end of the current message.In this case our
original message was 48 characters long.48 in binary is expressed as: 110000
However, since the number must be 64-bits or digits long we must now add 58 zero's to the
beginning of that number prior to adding it to the current message.

01000001001000000101010001100101011100110111010010000000000000000000000000-
00000000000000000000000000000000000000000000000000000000000000000000000000-
00000000000000000000000000000000000000000000000000000000000000000000000000-
00000000000000000000000000000000000000000000000000000000000000000000000000-
00000000000000000000000000000000000000000000000000000000000000000000000000-
00000000000000000000000000000000000000000000000000000000000000000000000000-
00000000000000000000000000000000000000000000000000000000000000110000

The message length should now be an exact multiple of 512.

Step 7: 'Chunk' the message

We will now break the message up into 512 bit chunks. In this case the message is only 512
bit's long, so there will be only one chunk that will look exactly the same as the last step.

01000001001000000101010001100101011100110111010010000000000000000000000000-
00000000000000000000000000000000000000000000000000000000000000000000000000-
00000000000000000000000000000000000000000000000000000000000000000000000000-
00000000000000000000000000000000000000000000000000000000000000000000000000-

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

00000000000000000000000000000000000000000000000000000000000000000000000000-
00000000000000000000000000000000000000000000000000000000000000000000000000-
00000000000000000000000000000000000000000000000000000000000000110000

Step 8: Break the 'Chunk' into 'Words'

Break each chunk up into sixteen 32-bit words

 0: 01000001001000000101010001100101
 1: 01110011011101001000000000000000
 2: 00000000000000000000000000000000
 3: 00000000000000000000000000000000
 4: 00000000000000000000000000000000
 5: 00000000000000000000000000000000
 6: 00000000000000000000000000000000
 7: 00000000000000000000000000000000
 8: 00000000000000000000000000000000
 9: 00000000000000000000000000000000
 10: 00000000000000000000000000000000
 11: 00000000000000000000000000000000
 12: 00000000000000000000000000000000
 13: 00000000000000000000000000000000
 14: 00000000000000000000000000000000
 15: 00000000000000000000000000110000

Step 9: 'Extend' into 80 words

This is the first sub-step. Each chunk will be put through a little function that will create 80
words from the 16 current ones.This step is a loop. What that means is that every step after
this will be repeated until a certain condition is true.In this case we will start by setting the
variable 'i' equal to 16. After each run through of the loop we will add 1 to 'i' until 'i' is equal
to 79.

Step 9.1: XOR

We begin by selecting four of the current words. The ones we want are: [i-3], [i-8], [i-14] and
[i-16]. That means for the first time through the loop we want the words numbered: 13, 8, 2
and 0.

 0: 01000001001000000101010001100101
 2: 00000000000000000000000000000000
 8: 00000000000000000000000000000000
 13: 00000000000000000000000000000000

However, the next time through the loop we want words: 14, 9, 3 and 1.
After the fifth time through the loop we will want words: 17, 12, 6 and 4.
Note that word 17 doesn't exist yet, but it will after the first run of the loop.
That means that after sixteen passes through the loop we will be using entirely words that
aren't part of the original sixteen.

Now that we have our words selected we will start by performing what's known as an 'XOR'
or 'Exclusive OR' on them. In the end all four words will be XOR'ed together, but you can

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

think of it as first doing [i-3]XOR[i-8] then XOR'ing that by [i-14] and that again by [i-16].
XOR is one of a few simple logical operators. All it means is that you compare the two
numbers bit by bit and if exactly one of them has the value '1', output a '1'. However, if both
numbers have a '0' for that bit, or they both have a '1', output a '0'. This works very similar to
a logical 'OR' which will be used later. The only difference is that an 'OR' will return a '1' so
long as either column has a '1' even if both of them do.

Let's see how it works:

:
1011010101
:
0101001011
example XOR

Out:
1110011110

So for our example we begin by XOR'ing:

13:
00000000000000000000000000000000
8:
00000000000000000000000000000000
13 XOR 8

Out:
00000000000000000000000000000000

Now we XOR that with word number [i-14]:

:
00000000000000000000000000000000
2:
00000000000000000000000000000000
(13 XOR 8) XOR 2

Out:
00000000000000000000000000000000

Now we XOR that with word number [i-16]:

:
00000000000000000000000000000000
0:
01000001001000000101010001100101
((13 XOR 8) XOR 2) XOR 0

Out:
01000001001000000101010001100101

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

Step 9.2: Left rotate

Perform a left bit rotation by a factor of one. This is very simple. All you do is remove the
first digit on the left and add a '0' to the end. This effectively shifts the number over to the left
by one. Here's how it looks:
Output from the last step:
01000001001000000101010001100101
Left Rotate 1:
10000010010000001010100011001010
Once you are done with that, you can store the variable as a new word. In this case it will be
word number 16(keep in mind that we start counting at 0).

After step nine is complete we will now have 80 words that look like this:

 0: 01000001001000000101010001100101
 1: 01110011011101001000000000000000
 2: 00000000000000000000000000000000
 3: 00000000000000000000000000000000
 4: 00000000000000000000000000000000
 5: 00000000000000000000000000000000
 6: 00000000000000000000000000000000
 7: 00000000000000000000000000000000
 8: 00000000000000000000000000000000
 9: 00000000000000000000000000000000
 10: 00000000000000000000000000000000
 11: 00000000000000000000000000000000
 12: 00000000000000000000000000000000
 13: 00000000000000000000000000000000
 14: 00000000000000000000000000000000
 15: 00000000000000000000000000110000
 16: 10000010010000001010100011001010
 17: 11100110111010010000000000000000
 18: 00000000000000000000000001100000
 19: 00000100100000010101000110010101
 20: 11001101110100100000000000000001
 21: 00000000000000000000000011000000
 22: 00001001000000101010001100101010
 23: 10011011101001000000000001100011
 24: 00000100100000010101000000010101
 25: 11011111110101110100011001010101
 26: 00110111010010000000000000000111
 27: 00000000000000000000001100000000
 28: 00100100000010101000110010101000
 29: 01101110100100000000000111101110
 30: 00010110100001000001000111000001
 31: 10110010100011110001100111110110
 32: 11010000101000111111001010100011
 33: 01010110011101100000110000000010
 34: 10010000001010100011001100100000
 35: 10101000010001010100000111101101

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

 36: 01101101010110000100011100000011
 37: 11001010001111000110010011011010
 38: 01100110100001010100011000100111
 39: 00110111010010000011000110000111
 40: 01010010101011011000110011010110
 41: 11011110010010000001111011100001
 42: 01101000010000010001110000010001
 43: 00101000111100011001111110101011
 44: 00000011001111011000100100010111
 45: 11111100110001001100000110100110
 46: 00010000101001100111010111011101
 47: 10100001000110010101101011001001
 48: 11011101110000010001100111100111
 49: 01100001101110100100110110100110
 50: 01101000010101000110010111110110
 51: 00101110100100110100011011110111
 52: 11010010101101011000101100101010
 53: 11010011110010011110001000011010
 54: 00010100001110111111001110110110
 55: 00110101010110011111110100001011
 56: 01101001110010001101011001110100
 57: 00000110011100000111111010110101
 58: 01101100111000100001101111110110
 59: 00100110110111011001110100011101
 60: 10001110101111000001001010101011
 61: 11000101111011001100010100000111
 62: 11111111000000100000010100100011
 63: 11110110100011011111000110011110
 64: 00110011011000101101111011000100
 65: 01101100101101101110000110001111
 66: 01000001000111000000100101101000
 67: 11010001110010111100111001101001
 68: 01001001000010010001011101110000
 69: 11000100110000011010011011111100
 70: 10100110011101011101110100010000
 71: 00011001010110101100101010100001
 72: 11100101000100110110101101110101
 73: 11010100110111011011111001101111
 74: 01110100001100011001010100101001
 75: 10101111110100111111101000001101
 76: 11011000110101010111110100101111
 77: 00000111001000100000111010011001
 78: 10001011100011011111100111110101
 79: 10110111011010010100111100111110

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

Step 10: Initialize some variables

Set the letters A-->E equal to the variables h0-->h4.

 A = h0
 B = h1
 C = h2
 D = h3
 E = h4

Step 11: The main loop

This loop will be run once for each word in succession.

Step 11.1: Four choices

Depending on what number word is being input, one of four functions will be run on it.
Words 0-19 go to function 1.
Words 20-39 go to function 2
Words 40-59 go to function 3
Words 60-79 go to function 4

Function 1
Remember that 'OR' function I mentioned earlier, we're going to be using that and a logical
'AND‟for this function'.Just to refresh: A logical 'OR' will output a '1' if either or both of the
inputs are '1'.A logical 'AND' will output a '1' if the first input and the other is a '1'.
For all logical operations a '0' will be output if the conditions are not met. The only other
logical operator we will be using is called a 'NOT'. A logical not only takes one input and
outputs the opposite. If you put in a '1' you will get a '0', if you put in a '0' you will get a '1'. A
logical 'NOT' is often represented as an exclamation (!) point.

The first step of function 1 is to set the variable 'f' equal to: (B AND C) or (!B AND D)
B:
11101111110011011010101110001001
C:
10011000101110101101110011111110
B AND C

Out:
10001000100010001000100010001000

!B:
00010000001100100101010001110110
D:
00010000001100100101010001110110
!B AND D

Out:
00010000001100100101010001110110

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

B AND C:
10001000100010001000100010001000
!B AND D:
00010000001100100101010001110110
(B AND C) OR (!B AND D)

F:
10011000101110101101110011111110

The second step of function 1 is to set the variable 'k' equal to:
01011010100000100111100110011001

Function 2
For this function we will be using the 'XOR' operation exclusively.Just to refresh: A logical
'XOR' will output a '1' if either the first or the second of the inputs are '1' but not both.

The first step of function 2 is to set the variable 'f' equal to: B XOR C XOR D
Of course by this time our variables have changed. Here's what this step will actually look
like by the time we get to it:

B:
11011100100010001001111001110101
C:
10110101000101000100100011110000
B XOR C

Out:
01101001100111001101011010000101

B XOR C:
01101001100111001101011010000101
D:
01001110101011001011101010110111
(B XOR C) XOR D

F:
00100111001100000110110000110010

The second step of function 2 is to set the variable 'k' equal to:
01101110110110011110101110100001

Function 3
For this function we will be using the 'AND' and 'OR' operations.The first step of function 3
is to set the variable 'f' equal to: (B AND C) OR (B AND D) OR (C AND D)By this time our
variables have changed again. Here's what this step will actually look like by the time we get
to it:

B:
01000100110000000111111001110111

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

C:
00011010100110110011101010111011
B AND C

Out:
00000000100000000011101000110011

B:
01000100110000000111111001110111
D:
01010011011001010110101011100100
B AND D

Out:
01000000010000000110101001100100
C:
00011010100110110011101010111011
D:
01010011011001010110101011100100
C AND D

Out:
00010010000000010010101010100000

B AND C:
00000000100000000011101000110011
B AND D:
01000000010000000110101001100100
(B AND C) OR (B AND D)

Out:
01000000110000000111101001110111

(B AND C) OR (B AND D):

01000000110000000111101001110111
C AND D:
00010010000000010010101010100000
((B AND C) OR (B AND D)) OR (C AND D)

F:
01010010110000010111101011110111

The second step of function 3 is to set the variable 'k' equal to:
10001111000110111011110011011100

Function 4
Function 4 is exactly the same as function 2 except that we will set 'k' equal to
11001010011000101100000111010110.

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

Step 11.2: Put them together

After completing one of the four functions above, each variable will move on to this step
before restarting the loop with the next word. For this step we are going to create a new
variable called 'temp' and set it equal to: (A left rotate 5) + F + E + K + (the current word).
Notice that other than the left rotate the only operation we're doing is basic addition. Addition
in binary is about as simple as it can be.We'll use the results from the last word(79) as an
example for this step.
Alrot 5:
00110001000100010000101101110100
F:
10001011110000011101111100100001
Alrot 5 + F

Out:
110111100110100101110101010010101

Notice that the result of this operation is one bit longer than the two inputs. This is just like
adding 5 and 6, you will need a new place value to represent the answer. For everything to
work out properly we will need to truncate that extra bit eventually. However, we
do not want to do that until the end!

Alrot 5 + F:
110111100110100101110101010010101
E:
11101001001001111110100110101011
Alrot 5 + F + E

Out:
1010100101111110101101010001000000

Alrot 5 + F + E:
1010100101111110101101010001000000
K:
11001010011000101100000111010110
Alrot 5 + F + E + K

Out:
11101110000010111011001011000010110

Alrot 5 + F + E + K:
11101110000010111011001011000010110
Word 79:
10110111011010010100111100111110
Alrot 5 + F + E

Out:
100000100111110001101110010101010100

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

Now we need to truncate the result so that the next operations will work smoothly. We will
remove as much of the beginning(left) until the number is 32 bits or 'digits' long.
32-bit temp:
00100111110001101110010101010100

The only thing left to do at this point is 're-set' some variables then start the loop over. We
will be setting the following variables as such:

 E=D
 D=C
 C = B Left Rotate 30
 B=A
 A = temp

Step 12: The end

Once the main loop has finished there is very little left to do. All that's left is to set:

 h0 = h0 + A
 h1 = h1 + B
 h2 = h2 + C
 h3 = h3 + D
 h4 = h4 + E

If these variables are longer than 32 bits they should be truncated.

For our example the 'h' variables will now have these values:

 h0 = 10001111000011000000100001010101
 h1 = 10010001010101100011001111100100
 h2 = 10100111110111100001100101000110
 h3 = 10001011001110000111010011001000
 h4 = 10010000000111011111000001000011

Finally the variables are converted into base 16 (hex) and joined together.

 8f0c0855
 915633e4
 a7de1946
 8b3874c8
 901df043

Final Hash Text Of The String „A Test‟ is

8f0c0855915633e4a7de

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

6. Design Summary
Example 1 - $cEt

8 Example 1-$cEt

Implemented Example On FPGA Board

Example 1 - $cEt

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

Example 2 - _(space)@!

9 Example 2 _(space)@!

Example 3- SHA

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

10 Example 3- SHA

Example 4 – EC16

11 Example 4- EC16

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

7. Application

1) Public Key Algorithms

 Password Logins
 Encryption Key Management
 Digital Signatures
2)Integrity Checking

 Virus and Malware Scanning

3)Authentication

 Secure Web Connections

 (PGP, SSL, SSH, S/MIME)

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

8. Work plan

8.1 Work done in ODD semester

 Study of VHDL
 Different types of modeling.
 Advantages of VHDL.
 Studied how to write code in Xilinx.
 Designing of simple codes of operation in that are going to be used further in VHDL
in Xilinx software.
 Simulation of codes.
 Learnt downloading code on FPGA board.
 Study of SHA algorithm
 How it works & its advantage.
 Key features.

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

 Selection of SHA based on complexity.

 Division of the codes according to block diagram.

8.2 WORK DONE IN EVEN SEMESTER (TILL 8/3/2016)

 Learnt basic syntax of VHDL.

 Divided whole algorithm in different modules.
 Wrote code for different nine modules.
 Combine all modules codes in one (using mapping).
 Wrote code for whole algorithm (synthesized and with correct output).
 Implementation of the algorithm on FPGA board.

9. Summary

The field of cryptography is eventually changing, new algorithms new techniques of

implementation are constantly being derived.Keeping in view that an efficient
implementation of SHA block cipher to satisfy the security requirement of efficient
encryption. The core provides privacy, integrity, authenticity and replay protection of
data.future work includes further resource optimization to achieve lower power and higher
throughput. The work done, implementation of Simplified Secure Hash Algorithm (SHA) can
be used for Optimized cryptographic model of Secure Communication. The encryption carried
out on XILINX gives good performance. But for the best performance, we can optimize the
different blocks of SHA algorithm.

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

10. References
1. Douglas Perry, “VHDL Programming by Example”, 4th Edition,McGraw–Hill
publication, ISBN0071400702, 978007140070
2. Andrew S. Tanenbaum , “Computer Networks” , 5th Edition , Pearson
Education.ISBN13:978-0-13-212695-3
3. J. Bhasker, “VHDL Prime”,Pearson Education,3rd Edition ,2002
4. William Stallings, Cryptography and network security: Principles and practice,
Prentice Hall, Upper Saddle River, New Jersey, 2003.
5. Morris Mano, “Digital Logic & Computer Design”, 3rd Edition, Pearson Prentice Hall,
ISBN 971-81-317-0070-9
6. http.//www.metamorphosite.com
7. http.//www.unixwiz.net/techtips/iguide-crypto-hashes.html
8. http.//www.eda.org/rassp/vhdl/models/standards/std_logic_textio.vhd
http.//www.ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1277460
9. Spartan 3 XC3S400 Architecture and XILINX Software/Official Xilinx Website:
http://www.xilinx.com/support/documentation/user_guides/ug331.pdf

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FPGA Implementation Of SHA Using VHDL Team ID- 48859

11. Appendix
11.1 PERIODIC PROGRESS REPORT (PPR)
11.2 PATENT DRAFTING EXERCISE (PDE)
11.3 PLAGIARISM REPORT

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