2010 International Conference on Advances in Computer Engineering

Leakage Current Reduction in 6T Single Cell

SRAM at 90nmTechnology
Shilpi Birla Neeraj Kr. Shukla Debasis Mukherjee R.K. Singh
E&CE Deptt E&CE Deptt E&CE Deptt E&CE Deptt
SPSU, Udaipur (India) ITM, Gurgaon (India) KEC, Kumaon (India)
ITM, Gurgaon (India)

Abstract-The emerging Wireless Sensor Network
technologies are facilitating novel applications in health
monitoring, industrial monitoring and security surveillance.
The small physical dimensions of wireless sensor nodes often
restrict the energy source to a small battery. The limited
energy consumption requirement demands for ultra-low power
sensing, processing and communication. This paper targets the
modeling and simulation of CMOS leakage currents and its
minimization approach to reduce the power consumption by a
single cell SRAM cache. The popular approaches for leakage
reduction are the data retention gated ground, and dynamic
threshold voltage for cache. The work focuses on the
simulation of a SRAM Cell for the data retention gated ground
and drowsy mode SRAM Cell which shows that the current
reduction of around 25% in s simulation model, respectively in
comparison with the conventional cell with no current
reduction technique.
Keywords-Deep Sub-micron, Leakage Current, Sub-
Threshold Voltage.
I. INTRODUCTION
According to ITRS roadmap in 2002, memory chip will
occupy 90% of chip area in 2013 [1]. Recent surveys in this
area shows, a roughly around 30% of the semiconductor
business (world-wide) is due to semiconductor memory
chips. In recent years as the need of leakage reduction in
high-processors and microcontroller architectures, memory
structures increases, there have been many research
activities on low-voltage SRAM dynamic and standby
techniques. Most of the researchers reported circuit
techniques in this area focusing on the designs at the sleep
mode, .g., an array of dynamically-controlled sleep
transistors was used to provide a finely programmable
standby VDD [2].
II. CONVENTIONAL 6T SRAM CELL
The Static Random Access Memory (SRAM) is found as
an integral component in many embedded applications.
Traditionally an SRAM is mainly formed by an array of
CMOS Cells which has Six-Transistors along with a number
of other peripheral circuitry, e.g., row decoder, column
decoder, sense amplifier, write buffer, etc.[1]. As the IC
process technology scales down, the device oxide thickness
and the device operating voltage continuously following a
down path. It is found by many researchers and commented
very smartly that the gate oxide thickness in recent and
future IC process technology has approached its limit
especially when direct tunneling cause the gate leakage in
the ON-State as well as in the OFF-State of the MOS
transistor operation. Further, lowering the operating voltage
of the MOS Cell will lower the stability of SRAM Cell by
approaching its limit towards the SNM [9,11].
To address the current leakage problem, several
techniques have been proposed at the circuit level, e.g.,
Standby Leakage Control using Transistor Stack, Multiple
Vth Scheme (Multithreshold Voltage CMOS, Dual
Threshold Voltage CMOS, Variable Threshold Voltage
CMOS, Dynamic Threshold Voltage CMOS, Double Gate
Dynamic Threshold SOI CMOS, etc.) [3].
The structure of conventional SRAM with 6T cell is
shown in Fig. 1. In the following we describe the read and
write operation in conventional SRAM [1].
Fig. 1 Conventional 6T SRAM Cell
A. Write Operation
The row and column address decoded and select one cell
from memory array. For a write, this bit-line driving
conducts simultaneously with the row and column decoding
by turning on proper write buffer. After this step, the bit-line
pair will forced into full-swing logic level. If the value of
the stored bit in the target cell is opposite to the value being
written, then cell flipping process will take place. At the end
of write operation all bit-lines pre-charged to the VDD and
get ready for next read or write operation [2].
B. Read Operation
The row and column address decoded and select the
target cell. After the word-line go to height voltage, the
target cell connected to bit-line and bit-line-bar. The so-
called cell current through a driver of target cell will
discharge the voltage of either bit-line or bit-line-bar

978-0-7695-4058-0/10 $26.00 © 2010 IEEE 292

DOI 10.1109/ACE.2010.42
progressively and this resulted in a difference voltage
between the bit-line and bit-line-bar. [10]
The sense amplifier is turned on to amplify the small
difference voltage at bit-line pair into full-swing logic
signals. At the end of read operation all bit-line precharged
to the VDD.
III. LEAKAGE COMPONENTS
The leakage current of a deep submicron CMOS
transistor consists of three major components: junction
tunneling current, sub threshold current, and gate tunneling
current,as shown in fig.1
A. Junction Tunneling Leakage
The reversed biased p-n junction leakage has two main
components: one is minority carriers’ diffusion near the
edge of the depletion region and the other is due to electron-
hole pair generation in the depletion region of the reverse
biased junction [12]. The junction tunneling current is an
exponential function of junction doping and reverse bias
voltage across the junction.
B. Subthreshold Leakage
Subthreshold leakage is the drain-source current of a
transistor when the gate-source voltage is less than the
threshold voltage. More precisely, sub threshold leakage
happens when the transistor is operating in the weak
inversion region. The subthreshold current depends
exponentially on threshold voltage, which results in large
subthreshold current in short channel devices.
C. Gate Tunneling Leakage
Electrons (holes) tunneling from the bulk silicon through
the gate oxide into the gate results in gate tunneling current
in an NMOS (PMOS) transistor. Gate tunneling current is
composed of three major components: (1) gate to source and
gate to drain overlap current, (2) gate to channel current,
part of which goes to source and the rest goes to drain, and
(3) gate to substrate current. In bulk CMOS technology, the
gate to substrate leakage current is several orders of
magnitude lower than the overlap tunneling current and gate
to channel current. On the other hand, while the overlap
tunneling current dominates the gate leakage in the OFF
state, gate to channel tunneling dictates the gate current in
the ON condition. Since the gate to source and gate to drain
overlap regions are much smaller than the channel region,
the gate tunneling current in the OFF state is much smaller
than gate tunneling in the ON state .
IV. LEAKAGE REDUCTION SCHEMES FOR SRAM CELL
Reduction in dimension, increase of doping, reduction
of VT etc causes the increase of leakage current in every
generation. Today the amount of leakage current has gone to
such a limit that it is affecting power consumption and
normal transistor behavior to a great extent. So, leakage
reduction technique is the demand of modern age. Here we
have discussed theoretically the two good techniques for
leakage reductions and the simulation model is presented for
a 6T conventional SRAM with no-leakage reduction
293
technique and with a leakage reduction technique, the DRG
technique, in this paper.
A. Data Retention Gated Ground Scheme
In the DRG Scheme, the unused portion of the memory
core is put to the low leakage mode. It uses an extra NMOS
transistor in leakage path to turned off if unused and turned
on if in use in the unused or used portion of the memory
core.
A. Transistor stacking effect
This takes place when more than one transistor in series
is turned off. Thus the transistor stacking places the unused
parts of memory in a low leakage current mode. An
additional NMOS is introduced inside the leakage path. That
transistor is kept on for used portion. So, there is no effect in
normal operation of memory. But for the unused portion, the
extra NMOS is kept off. It does not affect the normal
operation of memory but reduces the amount of leakage
current to a great extent due to transistor stacking effect
[7,9].
B. Drowsy Scheme
In the SRAM operation there is mainly two stages. One
is when read or write operation is done. It can be assumed as
active mode when actual data transaction takes place. On the
other hand when there is no data transaction only
information preserve is done by the latching phenomena of
memory. It is found that there is very low supply voltage
needed for preservation of data. Drowsy cache method puts
memory in a low power supply drowsy mode when only
data preservation is needed. It uses multiple supply voltage
sources. It supply high voltage when access of memory
contents is needed [6, 8]. Leakage current is decreased as
supply voltage decreases. Reduced supply voltage and
reduced leakage current together make a huge reduction in
leakage current [8].
Thus, the memory core is put in the low-power drowsy
mode when the information prevention is required and in the
high-power mode before the access of the contents. The
leakage current reduces with the voltage scaling. This
reduced leakage and supply voltage results in a huge
reduction of the leakage power [12].
V. SIMULATION RESULTS
A. Conventional 6-T SRAM Cell
Here, Fig. 5(a) shows the 6T conventional SRAM and
5(b) shows the simulation results when no technique is
being applied. It is found that before the application of the
pulse, there was a current of 8.2µA. When a pulse is being
applied, there was a drastic change in current of 1.8nA is
seen. The peak of is is about 45µA.

Fig. 5(a) A Conventional SRAM in 90 nm Technology
Fig. 5(b) Leakage Current in 90nm Technology for 6T Conventional
SRAM
B. Data Retention Gated Ground Scheme
Here, Fig.6 (a) shows the 6T conventional SRAM with
DGR Technique applied to it and 6(b) shows the simulation
results when no technique is being applied. In it is found
that before the application of the pulse, there was a current
of 113pA. When a pulse is being applied, there was a drastic
change in current of 100pA is seen.
Fig.6(a) A SRAM with DGR Scheme
294
Fig. 6(b) Leakage Current in 90nm Technology for DGR Scheme
CONCLUSION
In this paper the low leakage technique is successfully
implemented in Cadence platform at 90nm technology. The
read, write and preservation of data are happening correctly.
Power consumption wave forms are also observed. Power
consumption takes place when there is no initialization of
SRAM state. The same simulation is done for the DGR-
technique, before and after the application of pulse, after
multiple iterations it is found that there is drastic change in
current is seen.
ACKNOWLEDGMENT
The authors are very grateful to the respective organizations
for their help and encouragement.
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