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2016 International Conference on Material Science and Civil Engineering (MSCE 2016)

ISBN: 978-1-60595-378-6
 

Design of Digital PID Controller Based on FPGA

Shi-kui XIEa, Sheng-nan JIb, Jie-tao WUc, Pei-gang LId and Chao-rong LIe†
Department of Physics and Key Laboratory of ATMMT Ministry of Education Zhejiang
Sci-Tech University
Hangzhou 310018, China
a694335975@qq.com, b522699740@qq.com, c513731862@qq.com, dpgli@zstu.cn,
e
crli@zstu.edu.cn

PID controller has been widely used in many different areas such as power systems, drives
control, automotive mechatronics, aerospace, process control, and robotics. Recently, FPGA
(field programmable gate array) has become an alternative solution for the realization of digital
control algorithm systems. In this paper FPGA-based incremental PID (Proportional, Integral,
Derivative) controller is designed and simulated. After the analysis of PID control algorithm,
VerilogHDL language is used to design the software programs. Simulation results show the
effectiveness and feasibility of the proposed method.

Keywords: PID Control; FPGA; VerilogHDL.

1. Introduction
PID controller consist of proportional unit, integral unit and derivative unit is used
for closed loop automatic control technology. The clear structure and adjustable
parameters make the PID controller suitable for all kinds of control objects [1-3]. The
main idea of it is to set up a mathematical model that describing the dynamic
characteristics of the system according to the requirement of controlling. PID control
is based on proportional control; and integral control can eliminate steady state error,
but it may increase overshoot; differential control can speed up the response speed of
large inertial system and decrease overshoot. By adopting the control strategy of
adjusting proportion, differential and integral parameters, the optimum system
response and control effect are achieved. However, with the method above we can
not completely avoid the damaging effects of the running fly and computer
malfunction to the whole control system when use a microprocessor. Luckily, the
appearance of FPGA(field programmable gate array) provides a new method for the
design of PID controller. High integration, small size, low power consumption, high
reliability and flexible design method make it repeated programmable, repeated used
and even practical SOC(System On Chip). Recently, FPGA have become an
alternative solution for the realization of digital control algorithm systems, which
were previously dominated by general-purpose microprocessor systems. Another

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advantage of FPGA-based platforms is their capability to execute concurrent
operations, allowing parallel architectural design of different digital controller
systems. The architectures are implemented in FPGA EP4CE6E22C8N (Cyclone IV
Family of company Altera) which delivers an optimal balance of low risk, low cost,
and low power cost for this applications.

2.PID control Algorithm


The complete PID control expression is:

 1 det  
u t   k P et   et dt  Td
t

 Ti 0 dt 
 (1)

In the digital control system, the realization of the PID control algorithm must
be discredited by the numerical approximation method. Addition instead of integral,
backward differential instead of differential, the simulation PID algorithm is
discredited into difference equations. After calculation, we get:

u k   k P ek   k I ek   k D ek   ek  1 (2)

u k   u k  1  k p ek   ki ek  1  k d ek  2  (3)


Where the coefficients kI, kD, and kp,ki,kd are evaluated by the expressions:

k PT k T
kI  , k D  P d , k p  k P  k I  k D , ki  k P  2k D , k d  k D
Ti T
From Eq. (3), it can be seen that the incremental control algorithm is only
related to the last three sampling values, without a large amount of data storage and
accumulation, and not easy to cause accumulation of error, small amount of
computation and good real-time performance. Therefore, we made the top-level
design as is shown in figure 1. There are three modules in this project. The
implementation process of each module is described in details. The software
programming environment used is Quartus II, and the simulation tool is
modelsim-altera. VerilogHDL language is used during the programming.

 
Figure 1. Three modules: piancha, val and pwm of the PID top-level design.

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2.1.Module piancha
The first module piancha as is shown in figure 1 was designed to get the error
between the given value tar_te and the A/D conversion of the resulting feedback
value tes_te, and then pass it to the subsequent modules to deal with. After the reset
operation, the internal designed counter register counts every rising edge of clock
pulse. The difference between tar_te and tes_te was get when counting to the end of
sampling period. At the second sampling point, e(k) was passed to e(k-1), then get
refreshed. And at the third sampling point, e(k-1) was passed to e(k-2), e(k) was
passed to e(k-1) and then get refreshed again. The simulation waveforms are shown
in Figure 2. It can be seen that this module is feasible and effective.

Figure 2. simulation waveform of module piancha.

2.2.Module val
The function of the second module val as is shown in figure 1 is to create the duty
cycle of PWM waveform. Calculation is based on the value e(k), e(k-1) and e(k-2)
delivered by the module piancha. The picture shows every step of the calculation
process in figure 3. In this module, subtraction is used according to Eq. (3). We have
two ways to deal with it. The first method is to use complement arithmetic algorithm.
The other way is to use the signed operator that is supported by VerilogHDL since
2001. The MSB( Most Significant Bit) of the data is used as a symbol to carry out
operation. It is convenient for the dealing of the signed data[4][5]. We choose the
second method to calculated data at the same frequency with module piancha.
Simulation waveform is shown in figure 4 from which it can be seen that this
module can calculate the correct value according to Eq. (3).

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Figure 3. The specific steps of calculating from the errors to the variety of duty cycle.

Figure 4. simulation waveform of module val.

2.3.Module pwm
Module pwm is relatively simple. Its role is to output the PWM signal according to
the duty cycle delivered by module val. There is a built-in counter, when the counter
value is less than val, the port PWM is set high, otherwise low. The waveforms in
figure 5 show that no matter how val changes, the output port is high when the count
value is less than val. Each pulse of cnt_test in the figure represents a condition that
the counter value is 2000000, and to be set 0.

Figure 5. simulation waveform of module pwm.

3.Simulation of PID Control System


After combining the three modules and the preparation of top-level documents and
engineering documents, the whole control system can be simulated by the test file.
The proportion, integral and differential coefficients are selected as kp=3,ki=2 and
kd=1 as an example. Clock frequency is selected as 50MHz. We can observe the
system response by analysis the simulation waveform of the whole system illustrated

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in figure 6. The tar_te, tes_te, te_test and val_test in the picture respectively represent
set value, sampling value, e(k) and PWM duty cycle (val) .

 
Figure 6. simulation waveform of PID control system. 
 
As the waveforms shown, when the sample value (1000) is less than the set
value(5000), the val output from the PID controller is gradually increased until e(k)
is equal to 0 or negative. After that, the sampling value(8000) is greater than the set
value(5000) because of that the inertia of the system, e(k ) in the graph changing into
a negative value, and the PWM duty cycle becomes smaller along with the reduce of
val calculated according to Eq. (3). Obviously, adjustment of PWM duty cycle has a
certain delay than the change of e(k). Therefore, there will be overshoot and
damped oscillation. The purpose of proportional control is to eliminate the error as
soon as possible, but it will introduce larger overshoot and larger instability. The
introduction of integral control can largely reduce the steady-state error. Differential
control can reduce overshoot and improve stability. In engineering, the parameters
can be flexibly adjusted to get better control effect.

4.Conclusions
FPGA have the advantage of integration, high speed, low power, algorithm
implemented by hardware circuit. In this paper, the digital circuit is designed based
on FPGA. It could improve the operation speed and reliability of the controller. With
the development of technology, FPGA is bound to play an increasingly important
role in the field of auto-control.

Acknowledgments
This work was supported by Natural Science Foundation of China (Nos.51172209
and 91122022), and by the Program for Changjiang Scholars and Innovative
Research Team in University.

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