module add_sub(x,y,z);

input [11:0]x;
input [11:0]y;
output reg[11:0]z;
always@(x or y)
begin
if(x>y)
z=x;
else
z=y;
end
endmodule

module mux(lut1,lut2,lut3,lut4,mode,p);
input [11:0]lut1;
input [11:0]lut2;
input [11:0]lut3;
input [11:0]lut4;
input [1:0]mode;
output reg[11:0]p;
always@(lut1 or lut2 or lut3 or lut4 or mode)
begin
case(mode)
2'b00:p=lut1;
2'b01:p=lut2;
2'b10:p=lut3;
2'b11:p=lut4;
endcase
end
endmodule

module top(a,b,s);
input [11:0]a;
input [11:0]b;
output [11:0]s;
reg [12:0]temp;
wire [1:0]mode;
wire [11:0]z;
wire [11:0]x;
wire [11:0]y;
wire [11:0]lut1;
wire [11:0]lut2;
wire [11:0]lut3;
wire [11:0]lut4;
wire [11:0]p;
wire [11:0] out;
add_sub a1(x,y,z);
mux m1(lut1,lut2,lut3,lut4,mode,p);
always@(a or b)
begin
temp=a+b;
end
assign s=temp[11:0];
endmodule