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Engineering) Seventh Semester (C.B.S.)
DSP Processor & Architecture
P. Pages : 2 NIR/KW/18/3527/3535
Time : Three Hours *1810* Max. Marks : 80
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Notes : 1. All questions carry marks as indicated.
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2. Solve Question 1 OR Questions No. 2.
3. Solve Question 3 OR Questions No. 4.
4. Solve Question 5 OR Questions No. 6.
5. Solve Question 7 OR Questions No. 8.
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6. Solve Question 9 OR Questions No. 10.
7. Solve Question 11 OR Questions No. 12.
8. Assume suitable data whenever necessary.
9. Diagrams should be given whenever necessary.
10. Illustrate your answers whenever necessary with the help of neat sketches.
11. Use of non programmable calculator is permitted.
1. a)
b) nt
Elaborate how pipelined architecture in DSP processors have improved its performance.
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OR
b) Justify for a TMS 320 C5X processor the memory access procedure is consisting of 8
onchip RAM memory access.
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b) Explain the operations performed when the TMS 320 C5X issues the following 6
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instructions;
i) ADD C 20 h
ii) SMMR ARO 1800 h
iii) BLDP 00 h
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OR
4. a) A attenuator is to be designed using a DSP processor TMS 320 C5X. Illustrate the design 10
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stages required, onchip peripherals used. Also draw a system block diagram.
b) Explain the role of status registers in determining the acquication of real time signal. 4
5. a) An image processing application needs to be designed using a DSP processor based starter 13
kit with C5X. The image to be acquired has only two color tones i. e. black & grey. The
images are of the size 50 50 pixcels. The real time signal to be processed should be
acquired using which configuration. Also write a sample ALP for the same.
OR
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6. a) Discuss the various functions available in C5X DSK starter kit. 6
7. a) Write a short note on interrupts of TMS 320 C54 XX & how they are handled. 7
b) How the program control works when the TMS 320 C54XX is executing a instruction in 6
data addressing mode.
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OR
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9. a) Elaborate the cross platform Development process in TMS 320 C6X. 4
b) Discuss the architecture of Motorola DSP 563XX Explain how its is advantageous over TI 9
DSP's.
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OR
OR
12. a) A time domain sequence of 80 elements is to be convolued with another sequence of 100 5
elements using FFT & IFFT operations. Determine the total number of complex
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b) Elaborate digital decimation filter implementation for decimation factor = 3 using 3 tap 9
FIR filter. Also realize the final FIR filter using delay elements. Summing points &
multipliers.
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