1.

2.

3.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Celu_mod is

Port ( B2, B3 : in STD_LOGIC; A_out,DOS_out,TRES_out,ST_out,D_out : out STD_LOGIC;

est : out STD_LOGIC_VECTOR (2 downto 0));

end Celu_mod;
architecture Behavioral of Celu_mod is

type estados is (START,A_E,DOS_E,D_E,TRES_E);

signal ep:estados;

signal clk_4Hz_S:std_logic;

signal ti:integer range 0 to 2;

begin

process(clk)

variable t:integer range 0 to 50000000;

begin

if (rising_edge(clk)) then

t:=t+1;

if (t<=1) then

clk_4Hz_s<='1';

elsif (t<12500000) then

clk_4Hz_s<='0';

else

t:=0;

end if;

end if;

end process;

process(clk_4Hz,B2,B3)

begin

if (rising_edge(clk_4Hz_s)) then

case ep is

when START=>

if (B2=’0’ and B3=’0’) then

 ep<=START;

elsif (B2=’1’) then

ep<=A_E;

ST<=’1’;

elsif (B3=’1’) then

ep<=D_E;

ST<=’1’;

end if;

when A_E=>

ti<=ti+1;

if (B3=’0’ and ti=1) then

ep<=A_E;

elsif (B2=’1’ and ti=1) then

ep<=DOS_E;

ST<=’1’;

elsif (B3=’1’) then

ep<=D_E;

elsif (B3=’0’ and ti=2) then

ep<=START; A_out<=’1’;

A_out<=1;ST<=’1’;

end if;

when DOS_E=>

ti<=ti+1;

if (B3=’0’ and ti=1)then

ep<=DOS_E;

elsif (B2=’1’ and ti=1) then

ep<=A_E;

ST<=’1’;

elsif (B3=’0’ and ti=2) then

ep<=START; DOS_out <=’1’;

 elsif (B3=’1’) then

DOS_out<=’1’; ST<=’1’;

ep<=D_E;

ti<=0;

end if;

when TRES_E=>

ti<=ti+1;

if (B2=’0’ and ti=1) then

ep<=TRES_e;

elsif (B3=’1’ and ti=1) then

ep<=D_E; ST<=’1’;

elsif (B2=’0’ and ti=2) then

ep<=START;

TRES_out<=’1’;

elsif (B2=’1’) then

ep<=A_E;

TRES_out<=’1’; ST<=’1’;

end if;

when D_E=>

ti<=ti+1;

if (B2=’0’ and ti=1) then

ep<=D_e;

elsif (B2=’0’ and ti=2) then

ep<=START; D_out<=’1’;

elsif (B2=’1’) then

ep<=A_E;

ST<=’1’;

elsif (B3=’1’ and ti=1) then

ep<=TRES_E;
 ST<=’1’;

end if;

end case;

end if;

end process;

process(ep)

begin

case ep is

when START=>

est<="000";

when A_E=>

est<="010";

when DOS_E=>

est<="001";

when TRES_E=>

est<="100";

when D_E=>

est<="011";

end case;

end process;

end Behavioral;
4.

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ControlUnit is
port (
 clk : in std_logic; -- clock
rst_n : in std_logic; -- reset
inicio : in std_logic; -- señal de inicio
otra_carta : in std_logic; -- otra carta
plantarse : in std_logic; -- plantarse
status : in std_logic_vector(1 downto 0);
maquina_lista : out std_logic; -- maquina lista
ctrl : out std_logic_vector(8 downto 0)); -- Control

end ControlUnit;

architecture arch_ControlUnit of ControlUnit is

-- señal estados
type t_st is (s0, s1, s2, s3);
signal current_state, next_state : t_st;
-- señales status

signal status_aux : std_logic_vector (1 downto 0);

alias perdida: std_logic is status_aux (1);

begin

perdida <= status(1);

ctrl <= control_aux;
p_next_state : process (current_state, inicio, plantarse, otra_carta, perdida) is
begin -- process p_next_state

control_aux <= (others => '0');

case current_state is

when s0 =>
 maquina_lista <= '1';
rst_con <= '1';
rst_acc <= '1';
rst_zer <= '1';

if inicio = '1' then

next_state <= s1;
else
next_state <= s0;
end if;

when s1 =>

rst_per <= '1';

ce_cont <= '1';

if perdida = '1' then

next_state <= s0;
elsif perdida = '0' then
if plantarse = '1' then
next_state <= s0;
elsif plantarse = '0' then
if otra_carta = '1' then
next_state <= s2;
else
next_state <= s1;
end if;
end if;
end if;

when s2 =>
 ld_acc <= '1';
ld_zero <= '1';
next_state <= s3;

when s3 =>

ld_per <= '1';

we_ram <= '1';
next_state <= s1;

when others => null;

end case;
end process p_next_state;

p_status_reg : process (clk, rst_n) is

begin
if rst_n = '0' then
current_state <= s0;
elsif rising_edge(clk) then
current_state <= next_state;
end if;
end process p_status_reg;

end arch_ControlUnit;