A New Inductive Wireless Power Transfer Topology

Using Current-Fed Half Bridge CLC Transmitter LC

Receiver Configuration
Suvendu Samanta. Student Member, IEEE Akshay Kumar Rathore, Senior Member, IEEE
Concordia University Concordia University
1515 St. Catherine West, 1515 St. Catherine West,
Montreal, Quebec, Canada H3G 1M8 Montreal, Quebec, Canada H3G 1M8
s_amanta@encs.concordia.ca arathore@encs.concordia.ca

Abstract – A new current-fed topology for wireless inductive [14]. In VSI topology the transmitter coil (TC) and Receiver coil
power transfer (IPT) application using half-bridge circuit is (RC) side compensation networks are generally series LC type
proposed and analyzed. Conventional IPT circuits employ parallel [5], [10], [16] or LCL type [2], [9]. In bi-directional power
L-C resonant tank/compensation network to transfer power transfer system LCL topology is preferred for improved control
effectively through air-gap. However, in medium power application, facility [9]. Direct C-AC converter topology offer the benefit of
this topology suffers from a major drawback that the voltage stress
across the inverter switches are considerably high due to high
having less number of power conversion stages [14]. However
reactive power consumed by the loosely coupled coil. In the the major limitation is that the components are rated for peak
proposed topology, his is mitigated by adding a properly designed power. Also since, the AC source/utility current is not directly
capacitor in series with the coils. During grid-to-vehicle (G2V) controlled by any power factor corrected (PFC) converter hence,
operation, the power flow is controlled through variable switching high quality source current may not be achieved.
frequency modulation to achieve extended ZVS of the inverter
switches. For G2V operation, the converter circuit is analyzed and
simulated using PSIM 9.3. Analytical and simulation results are
verified through experimental results obtained by testing a 1.2kW
lab-prototype.

Index Terms—Wireless Power Transfer, Inductive Power

Transfer, Current-fed, Voltage Doubler.

I. INTRODUCTION
Fig. 1. Typical power flow diagram of an inductive WPT system feeds power to
ith increasing environmental issues, it is clear that electric
W
vehicle (EV) is the major solution for future transportation.
EV battery

Current-fed converter has several advantages in IPT circuit

However, the major limitation of EV lies in limited battery
storage capacity. Recent studies have demonstrated that even
with as low as 20% of battery capacity, an EV can travel longer
distance if the opportunistic charging technology is adopted
using wireless power transfer (WPT) technology [1]. Though this
concept of transferring power wirelessly was stated long back by
Nicola Tesla, but recent advancement of high frequency and high
power semiconductor devices have made this technology feasible
for practical use [2]-[3].
Several wireless inductive power transfer (IPT) circuit
topologies based on different design of transmitter and receiver
coils and associated resonance circuits have been discussed in
[2]-[21]. Typical power flow diagram of an inductive WPT
system feeds power to EV battery is shown in Fig. 1. Generally
DC-AC inversion stage is chosen as voltage source inverter
(VSI) topology [2], [5], [9]-[10] or matrix converter topology
when compensation capacitors are connected in parallel with TC.
Properly designed parallel capacitor allows flowing the high
reactive component current drawn by the TC to generate required
induced voltage in the RC [11]-[12], [15]. The current and
voltage profiles of the coils are almost pure sinusoidal since, the
parallel capacitor provides much lower impedance to the higher
order harmonics. Also inductor present in the DC link provides
natural short circuit protection during inverter fault. However
one limitation of this converter in the medium power application
is that the inverter switch voltage stress is high due to supply of
high reactive power from parallel capacitor [12]. In order to
eliminate this issue, a new converter topology is presented in this
paper where the tank resonant circuit is (C) (LC) type and is
suitable for medium power applications including EV charging.

978-1-5090-0737-0/16/$31.00 ©2016 IEEE

 Fig. 2. Wireless power transfer (DC-DC conversion) stage using current-fed half-bridge circuit

Ideally the duty cycle of S1 and S2 are 0.5 and their gating
II. PROPOSED WIRELESS IPT TOPOLOGY
signals are complimentary.
Fig. 2 shows complete power circuit of DC-DC wireless IPT
stage where the TC side converter is current-fed half bridge
topology and RC side is voltage doubler topology. In order to
make current-fed IPT circuit suitable for medium power such as
EV battery charging application, some topological changes are
made. Instead of using conventional parallel L-C resonant tank in
the transmitter network, the compensation capacitor is split into
two. One part is connected in series (Cs) with the TC and other is
in parallel (Cp) as shown in Fig. 2. The impedance of TC due to
high leakage is reduced significantly by the series capacitor and
the effective TC impedance reduces to ሾ߱‫ܮ‬ଵ െ ͳȀሺ߱‫ܥ‬௦ ሻሿ.
Hence, the parallel capacitor needs to supply only a fraction of
total reactive power demand keeping all the merits of current fed
converter i.e. low current stress at inverter switches and low
harmonic content in coil currents etc. At the RC side a capacitor,
C2 is connected in series with RC to compensate the reactive
power absorbed by the coil.
The half-bridge current-fed inverter injects a square wave
current to transmitter side resonant tank network. The
components of TC side tank network is designed such that the
input current magnitude, Ii is minimum for a given output power.
Parallel capacitor, Cp provides much lower impedance to the
higher order harmonics compare with the TC branch. Thus
higher order harmonic current in Ii passes through the capacitor,
Cp and TC gets almost pure sinusoidal current. Because of
mutual coupling, receiver coil gets a voltage proportional to
mutual inductance (M), current (I1) and operating frequency (Ȧ).
However, appropriate capacitive reactive power compensation is
needed to compensate the effect of high leakage inductance of
receiver coil. In the proposed topology a series capacitor, C2
compensates the reactive power. Finally the power in the receiver
network is rectified through the voltage doubler circuit and feeds
the load. The steady state operation of the converter for grid to
vehicle (G2V) is described here.
A) Steady state operation:
To explain the steady state operation of the proposed converter, Fig. 3. Steady state voltages and currents of different components for one
consider that the inverter leg switches S1 and S2 are operating at switching cycle
fixed duty cycle and power is controlled by variable frequency.
 voltage. The equivalent circuit during interval t2-t3 remains same
as shown in Fig. 4b.
Interval III (t3-t4- t5): At instant t3 switch S2 is triggered but
since, the voltage across this leg (S2-D2) is negative, the first leg
of the inverter (S1-D1) keeps on conducting. Thus simultaneous
zero voltage and zero current turn-on is achieved for S2. At
instant t4 S1 is turned-off and immediately total DC link current,
Id is transferred to S2-D2 as shown in Fig. 4c. The first leg of the
inverter (S1-D1) gets a positive voltage after this instant and S1
blocks this voltage. In practical the switching overlap interval i.e.
t3-t4 is very short, typically less than 0.5μs but sufficient enough
to turn on switch S2.
Interval IV (t5- t6- t7- t8): At instant t5 RC current polarity
changes and diode D3 commutates diode D4. At instant t6
inverter output voltage polarity changes and a negative voltage
appears across S1-D1 and diode D1 takes this voltage. At instant
t7, S1 is triggered but due to presence of negative voltage across
S1-D1, the second leg (S2-D2) keeps on conducting. This leads
to soft turn-on of switch S1. At instant t8, gating signal of S2
becomes low and S1 takes total DC link current, Id as shown in
Fig. 3.

B) Derivation of component ratings:

Fig. 5 shows AC side equivalent circuit of the proposed
converter where the input and output are modeled as current
source and voltage source respectively. Applying power balance
and considering active power flows in ac side due to fundamental
component only, RMS values of AC side voltage and current
expressions are given as,

ܸ௥ Ǥ ‫ܫ‬ଶ ൌ ܸ௢ Ǥ ‫ܫ‬௢ ǡ (1)

Fig. 4. Equivalent circuits of the proposed converter during subintervals of a గ గ
‫ܫ‬ଶ ൌ  Ǥ ሺʹǤ ‫ܫ‬௢ ሻ ൌ  Ǥ ‫ܫ‬௢ ǡ (2)
switching cycle ଶξଶ ξଶ
ξଶ
However, to make sure the continuity of stiff DC link current, Id ܸ௥ ൌ  Ǥ ܸ௢ . (3)
గ
slight overlap is given and this is considered in steady state
RC side converter input voltage, Vr and current, I2 are in same
operation. The operating power factor at the output of the half
phase because, Vr changes its direction immediately when I2
bridge current fed inverter is considered to be lagging to achieve
polarity changes. Here current I2 or voltage Vr phase is
ZVS at device turn-on. However, soft-switching at device turn-
considered as reference phasor. Applying KCL at TC side
off is also possible if this power factor is leading.
network inverter output, the inverter current is given as,
Interval I (t0-t1-t2): Consider that at t0 instant switch S1 is on
and S2 is off. In this condition switch S1 takes complete DC link ఠమ ெ஼ೞ ூమ ஼ೞ
current, Id as shown in Fig. 3 and 4a. During this interval t0-t1-t2 a ‫ܫ‬௜ ൌ ‫ܫ‬ଵ ൅ ‫ܫ‬௣ ൌ ቂ ቃ ൅ ݆ ቂܸ߱௜ ቀ‫ܥ‬௣ െ ቁቃ (4)
ሺఠమ ௅భ ஼ೞ ିଵሻ ሺఠమ ௅భ ஼ೞ ିଵሻ
positive voltage with same magnitude as vi appears in the second
leg of the inverter i.e. S2-D2. Switch S2 blocks this positive where, M is mutual inductance between TC and RC. Applying
voltage. During the interval t0-t1 receiver side rectifier diode D3 KVL at the RC side network, the input voltage to the RC side
rectifies the RC current, i2. At instant t1 RC current becomes zero converter is given as,
ଵ
as shown in Fig. 3 and diode D3 turns off at zero current. Hence ܸ௥ ൌ ݆߱‫ܫܯ‬ଵ െ ‫ܫ‬ଶ ሾ݆߱‫ܮ‬ଶ ൅ ሿ. (5)
௝ఠ஼మ
zero reverse recovery of diode D3 is achieved. During interval
t1-t2 diode D4 rectifies the RC current, i2 as shown in equivalent The value of capacitors Cp and Cs are chosen such that inverter
circuit Fig. 4b. output current, Ii magnitude is lower and C2 is chosen such that
Interval II (t2-t3): At instant t2 inverter output voltage changes bridge input voltage, Vr is maximum. This is done by eliminating
polarity because the power factor at the output of the inverter is second term in both (4) and (5). From (4) and (5) the required
considered lagging. From this instant the second leg of the capacitances are calculated as,
inverter (S2-D2) gets a negative voltage and D2 blocks this
 operation are two, S1 and S2. Due to current source at the input
of the inverter the minimum duty cycle of the switches are
limited to 0.5. However, keeping duty cycle fixed at 0.5, the
inverter switching frequency can be varied to achieve the desired
output power. The impedance at the output of the inverter i.e.
input to the TC tank network is derived as,
Fig. 5. AC side equivalent circuit of the proposed converter

ଵ ଵ
߱௢ଵ ൌ ǡ ߱௢ଶ ൌ . (6)
಴೛ ಴ೞ ඥ஼ೝ ௅మ
ඨ௅భ ൬಴ శ಴ ൰
೛ ೞ

Effective power transfer is achieved by equalizing inverter

switching frequency, Ȧo (=2ʌfo), transmitter coil resonance
frequency, Ȧo1 and receiver coil resonance frequency, Ȧo2.
Applying KVL in the receiver side loop, transmitter coil current
is calculated as,
ξଶ ௏೚
‫ܫ‬ଵ ൌ െ݆ . (7)
గ ఠ೚ ெ

Applying KVL and KCL in transmitter side and using (6) and
(7), RMS value of voltage across TC and voltage across series
capacitor, Cs is derived as,
ξଶ ௅భ గ
ܸଵ ൌ ቀ ቁ ܸ௢ െ݆ ߱௢ ‫ܫܯ‬௢ (8)
గ ெ ξଶ

ξଶ ௏
ܸ௦ ൌ െ Ǥ ೚ (9) Fig. 6. Impedance and phase angle at the output of inverter i.e. the input of
గ ఠ೚ మ ஼ೞ ெ
transmitter coil resonant network for different Vo/Io ratio.
Applying KVL, RMS value of inverter output voltage, Vi is
calculated by adding (8) and (9) and applying KCL inverter ଵ ଵ
ܼ௜ ൌ ȀȀ ൤൜݆߱ሺ‫ܮ‬ଵ െ ‫ܯ‬ሻ ൅ ൠ ൅ ൜݆߱‫ܯ‬ȀȀ ൬݆߱ሺ‫ܮ‬ଶ െ
output current is calculated as, ௝ఠ஼೛ ௝ఠ஼೛
ଵ
ξଶ ௏೚ ଵ గ ξଶ ௏೚ ‫ܯ‬ሻ ൅ ൅ ܴ௘ ൰ൠ൨ (13)
ܸ௜ ൌ ቀ߱௢ ‫ܮ‬ଵ െ ቁെ݆ ߱௢ ‫ܫܯ‬௢ ൌ Ǥ െ ௝ఠ஼೛
గ ఠ೚ ெ ఠ೚ ஼ೞ ξଶ గ ఠ೚ మ ஼೛ ெ
గ
݆ ߱௢ ‫ܫܯ‬௢ , (10) where, Re is equivalent load resistance at the input of receiver
ξଶ
side rectifier. From (1), (2) and (3) Re in terms of output
గ ξଶ ௏೚ ஼೛ ଵ ଵ
resistance is calculated as,
‫ܫ‬௜ ൌ ߱௢ ଶ ‫ܥܯ‬௣ ‫ܫ‬௢ െ ݆ Ǥ ൬ ൅ െ ߱௢ ‫ܮ‬ଵ ൰ . (11)
ξଶ గ ெ ఠ೚ ஼ೞ ఠ೚ ஼೛
ଶ ௏೚ ଶ
From (10) it is clear that 1/߱௢ ‫ܥ‬௦ term appears due to presence of ܴ௘ ൌ  Ǥ ൌ ܴ௢ . (14)
గమ ூ೚ గమ
series capacitor Cs. This is a major advantage of the proposed
topology compare with existing parallel L-C topology. From (10) For different values of ܴ௢ magnitude and phase of Zi is plotted
and (11) power factor at the inverter output is derived as, in Fig. 6. The power at the output of the inverter is derived as,
ଶ
గమ ఠ೚ మ ெమ ூ೚ ூ ଶξଶ
ܿ‫ ߮ݏ݋‬ൌ ܿ‫ݏ݋‬ሺ߮௜ െ ߮௩ ሻ ൌ ܿ‫ ݏ݋‬ቈ‫ି݊ܽݐ‬ଵ ቊ ቋെ ܲ௜௡௩ ൌ  ‫ܫ‬௜ ଶ Ǥ ܴ݁ሺܼ௜ ሻ ൌ ‫ܫ‬௜ ଶ ȁܼ௜ ȁܿ‫ ߮ݏ݋‬ൌ ቀ ೏ Ǥ ቁ ȁܼ௜ ȁܿ‫߮ݏ݋‬. (15)
ଶ௏೚ ቀఠ೚ ௅భ ି భ ቁ ଶ గ
ഘ೚ ಴ೞ

ଶ௏೚ ଵ ଵ ଵ
‫ି݊ܽݐ‬ଵ ൜ Ǥ ൬ ൅ െ ߱௢ ‫ܮ‬ଵ ൰ൠ቉. (12) The DC link current, Id is constant in current-fed converter and
గమ ఠ೚ మ ெమ ூ೚ ఠ೚ ஼ೞ ఠ೚ ஼೛
this is ensured by previous stage converter or power factor
correction (PFC) rectifier. Hence, power transferred through the
C) Control strategy for variable power output: proposed converter is proportional to real part of the tank input
In the proposed topology shown in Fig. 2, output power impedance. In order to achieve ZVS at device turn-on the
control cannot be done through fixed frequency variable duty converter is operated at lagging power factor side. From Fig. 6 it
cycle. This is because the basic switching devices during G2V is clear that when the inverter switching frequency is decreased
from unity power factor (UPF) line, input impedance is reduced.
Hence, power transferred is also reduced.

III. SELECTED WIRELESS PAD

Selection of IPT pad is crucial because the co-efficient of

coupling and exposure of leakage flux to passengers in EV
depends on the structure of IPT pad. IPT pads can be classified
broadly as flux guided pads and non-flux guided or core less IPT
pads. Using ferrite blocks or bars [1], [5], [10] flux guided IPT
pads are developed. In this paper UU type core is selected for its
simple structure and easy to implement [10]. Fig. 4 shows the
UU type IPT pad used in the experiment to verify the operation
of the proposed topology. From the coil current expressions
given in (3) and (7) the power loss in TC, RC and the coil to
efficiency is calculated as,
ଵ
ߟ௖ ൌ మ ೇ೚ ഏమ ಺೚
. (16)
ଵା మ ௥ ା ௥
ഏ ಺೚ ሺಾഘ೚ ሻమ భ మ ೇ೚ మ

where, r1 and r2 are TC and RC coil resistances.

Fig. 9. Simulation results at fs=47.6kHz, Po=1.15kW, Vo=325V.

Selecting suitable parameter values of passive components such

Fig. 7. Selected UU type IPT pad for the experimental verification of converter
IV. SIMULATION AND EXPERIMENTAL RESULTS
that Ȧo1 is close to Ȧo2, Fig. 2 circuit is simulated using PSIM
software. A 1.2kW lab-prototype is developed to verify the
mathematical analysis and simulation results. Selected circuit
parameter values for passive components are same for both
simulation and experiment as listed in Table 1. Fig. 5a shows
experimental set-up where SKHI 61(R) is used as gate driver and
DSP TMS320F28335 is used as digital control platform.

TABLE 1 : SELECTED CIRCUIT PARAMETERS

Parameters Selected Values

Input DC current, Id 6.5 A
DC link inductor, Ld1, Ld2 2 mH
TC, RC inductances, L1, L2 210 μH, 210.5 μH
Mutual inductance, M 41 μH
TC resonating capacitors, Cp, Cs 100 nF, 100 nF
TC resonating capacitor, Cr 47.6 nF
TC, RC unloaded Q factors 265 and 266
Converter switching frequency 48 kHz (rated)
Coil turns ratio 1:1
Output voltage, vo 325 V (rated)
Fig. 8. 1.2kW experimental set-up Load impedance, Ro 95 Ÿ (rated)
 Fig. 9 shows simulation results of the proposed converter for
1.15kW power output and corresponding inverter switching
frequency is fs=47.6kHz. The duty cycle of the inverter switches
are kept constant at 0.5 and input current, Id is kept constant at
6.5A. From (7) and (8) calculated RMS value of transmitter coil
voltage and current are 760V and 12A respectively. Fig. 9
simulation results also give same value.

Fig. 11. Experimental results at fs=46.1kHz, Po=800W, Vo=275V and

Fig. 10. Experimental results of (a) transmitter and receiver coil voltages and
currents, (b) voltage across the components of transmitter side resonant tank, (c)
inverter output and rectifier input voltages and currents, and (d) ZVS turn-on of
device S2 at fs=47.6kHz, Po=1.15kW, Vo=325V
inverter switch duty cycle fixed at 0.5
From the profiles of inverter output voltage, vi series capacitor
voltage, vs and TC voltage, v1 it is clear that inverter switches get
approximately half of v1. It is well predicted from (8), (9) and
(10). This is a major advantage of this topology over existing
parallel L-C topology that the voltage stress of the switches are
significantly lower in the proposed topology. From receiver side
rectifier input voltage, vr and current, i2 profiles it is clear that the
diodes D3 and D4 turn off at the zero current. This leads to soft
recovery of D3 and D4. Fig. 9 simulation result also validates the
theoretical analysis that lagging power factor at the inverter
output ensures ZVS turn-on of the devices.
Fig. 12. Experimental results at fs=45.1kHz, Po=500W, Vo=220V and inverter
switch duty cycle fixed at 0.5
Fig 10 shows experimental results of the proposed converter
for the same operating condition as simulation results. Fig. 10a
shows experimental results of current and voltage across
transmitter and receiver coils for 1.15kW power output during
grid to vehicle operation. Experimentally obtained RMS values
of TC voltage and current are 765V and 12A respectively which
are very close to the results obtained from simulation and
mathematical analysis. Also, the profile of TC voltage and
current are almost free from harmonics which are expected
because of the presence of parallel capacitor, Cp.
Fig. 10b shows experimental results of voltages across TC
network components. The voltage across the parallel capacitor,
vi determines the voltage rating of current-fed converter switches.
In this topology this voltage is a reduced fraction of TC voltage
v1 and this is possible because of subtraction of series capacitor
voltage, vs from v1. Since, in this paper Cs and Cp are equal,
hence the voltage reduction is also almost half as seen in Fig.
10b. These results are well predicted from the voltage
expressions given in (8), (9) and (10). Hence proposed converter
validates the improved performance over conventional parallel
LC resonant tank.
Fig. 10c shows experimental results of AC voltage and
current waveforms at the output of current-fed half bridge
inverter and at the input of voltage doubler converter. It is clear
from this results that the inverter output power factor is slight
lagging and this is suitable for ZVS turn-on. Also voltage and
current at the input to the voltage doubler circuit are in same
phase when the converter operates in rectifier mode. This leads
to soft recovery of the diodes D3 and D4.
Fig. 10d shows soft-switching characteristics of the second leg
of current-fed inverter switches (S2 and D2). It is clear from the
result that the voltage across S2-D2 is slightly negative at the
instant when S2 is turned on. Thus diode D2 blocks this voltage.
Hence zero voltage turn-on of inverter switch S2 is achieved.
Fig 11 and 12 shows experimental results for 800W and 500W
power output at corresponding inverter switching frequencies of
46.1 kHz and 45.1 kHz, respectively. Experimental results at
different power output clearly show the suitability of the
proposed converter in medium power application. From Fig. 11d
and 12d, it is clear that inverter output power factor is lagging
and when switch S2 is triggered the voltage across S2 and D2
were negative. Diode D2 blocks this negative voltage and other
leg switch S1 keeps on conducting. Hence ZVS turn-on of S2 is
achieved. Since, the inverter output power factor is always kept
lagging, ZVS turn on of devices is always ensured irrespective of
load change. Similar turn-on soft switching characteristics are
also achieved for switch S1.
V. CONCLUSIONS
A new WPT circuit using half-bridge current-fed voltage
doubler is presented. The proposed topology ensures lower
inverter output voltage compared to existing parallel LC resonant
tank allowing lower switch voltage rating. It helps proper
selection and low conduction losses of inverter semiconductor
devices. Due to presence of parallel capacitor, almost pure
sinusoidal voltage and current profiles are achieved at TC. Fixed
duty cycle and variable switching frequency modulation switches
inverter is capable of meeting load power requirement. Keeping
inverter output power factor lagging, soft-switching turn-on of
inverter switches are always ensured irrespective of load change.
Mathematical analysis is reported to understand the operation,
design and develop such a system and is verified by simulation
results. Experimental results demonstrate the effectiveness and
performance of the proposed current-fed circuit for the medium
power applications.
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