pplication of adjustable speed drives grams.

However, a proliferation of diode and thy-

(ASDs), especially for industrial applica- ristor rectifiers as ASD front-ends has resulted in
tions, provide significant energy savings serious utility interface issues as well as power
and increased productivity compared to constant quality degradation such as supply current and
speed motors. The Electric Power Research Insti- voltage harmonics, reactive power, flicker and res-
tute (EPRI) estimates that electric motors consti- onance problems in industrial applications. Volt-
tute 60% of total power utilization. However, only age distortion due to current harmonics is
a small percentage of these motors are ASDs. It is becoming a major problem for the utilities at dis-
estimated that use of ASDs for variable speed oper- tribution levels. Utilities more frequently encoun- I
ation, such as for compressors, pumps and fans, will ter harmonic related problems, such as higher I
result in 30% energy :savings and in a short pay- transformer and line losses, reactive power, and res- I
I
back period for additional ASD costs. EPRI projec- onance problems, required derating ofdistribution I
tions indicate that a large percentage of constant equipment, harmonic interactions between cus- I
I
speed motors will be ri-trofitted with ASDs. tomers or between the utility and load, reduced I
Many electric utilities are promoting the use of system stability and reduced safe operating mar- I
I
ASDs through aggressive rebate and incentive pro- gins. To mitigate harmonic related problems utili- I
I
I
Bhattacharya is with the Dept. of Electricaland Computer Engineering, University of Wisconsin-Madison,Madison, I
I
Wl (bhattach@cae.wisc.i:du).Frank was with York lnt’l. Corp., York, PA, andis now with Westinghouse, Science I
andTechnology Center, Pittsburgh, PA (frdnktm@westinghouse.cam). Divan is with Sojit Switching Corp.I Middle- I
I
ton, WI (deepdck@sofssitch.com). Banerjee is with the Electric Power Research Institute of Palo Alto, C A I
(bbanerjee@eprinet,epri,c?m).This article appeared in its original form at the 1996 IAS Annual Meeting, San I
Diego, Calzfornia. I

1077-2618/981$10.0001~~~8
IEEE IEEE Industry Applications Magazine September/October 1998

I
 TeK 5OOkS/s 2 Acqs
ties are increasingly enforcing IEEE 519, the
recommended harmonic standard, particularly for
large and industrial customers I t zs znzportant to note
that IEEE 5 19 hamonzcstandards ave only applzcableat
thepoznt of common couplzng (PCC) of the utzlzty-plant
znterface New specificationsoften treat it as an equzp- I /
500A mI
I
ment standard, a clear misapplication.
Since harmonic compensation by itself does not
provide any direct benefit or increased productiv-
ity to the user, except through reduced load out-
ages and reduced susceptibility to harmonic
I related problems, there is seldom any motivation
I
I for users to voluntarily meet IEEE 5 19 harmonic
I
standards In fact, harmonic standards often provide
I Fig. 2. Supply line current waveform i I {200 Aldiu}
I a deterrent to the widespread application of ASDs
I with ASD recrifier fron-end, t=2msldiu.
I
and therefore does not provide the anticipated en-
I ergy savings As a result, some ASD manufacturers mF. The IGBT PWM inverter has a switching fre-
I have started to integrate active filter solutions with
I quency of 2 kHz and drives a high efficiency 503
I ASD front-ends to meet IEEE 5 19 harmonic stan-
I
hp induction motor. Fig. 2 shows an experimental
dards at the utility-plant interface To justify the
supply line current i, waveform for a 460 V supply
additional cost of harmonic compensation, ASD
system with transformer leakage inductance of
manufacturers provide supplementary value-added
L , = 40yH (3.2%). The supply current is quasi-
features such as higher displacement power factor
square and has a total harmonic distortion (THD)
(DPF), line voltage regulation against supply volt-
i of 26.8% at input power of 270 kW. The short cir-
I age sags and swells,compensation for supply voltage
I flicker and unbalance, and mitigation of any possi- cuit current at 460 V transformer secondary is ap-
I
ble sourceisink resonance conditions [l). proximately 17.6 kA. The PCC is defined on the
I
I This article presents an active filter solution for transformer secondary side (Fig. 1).The short cir-
I
a utility interface of an ASD for air-conditioner cuit ratio (SCR) at PCC is 31.0 and IEEE 519 al-
I lowable supply current i, T H D is 8.0%.
I chiller application to meet IEEE 519 harmonic
I standards In the next section we discuss the ASD The ASD manufacturer specifications include,
I
I rectifier front-end characteristics and specifica- to meet IEEE 5 19, harmonic current T H D limits
I tions set by the ASD manufacturer The following at the utility-plant PCC interface with minimum
I supply side inductance of L,= 22 p H , which is
I section details the selection of active filter solution
I based on manufacturers specifications, cost goals 1.76% with a SCR of 58.6 at PCC. Hence, the
I IEEE 5 19 supply current T H D limit is 12%. How-
I and cost structure. Following that, the implemen-
I tation of the parallel active filter system is given ever, there is no specification for maximum supply
I side inductance L , and the system is required to
I The next two sections discuss the synchronous refer-
I ence frame controller and current regulator devel- meet the IEEE 5 19 harmonic current T H D limit for
I all such cases. Note that L , 2 6 5 p H (5.2%) results
I oped along with their hardware based implemen-
I tations for the parallel active filter system The last in a SCRS 20 and in this case the maximum allow-
I
two sections describe, respectively, design consider- able supply current T H D is 5%. Hence, the har-
I
I ations for inverter switching ripple filter and experi- monic filtering solution has to be designed to meet
I mental results for utility interface of an integrated the worst case supply current T H D limit of 5%.
I
I parallel active filter system with a450 kW ASD load The resonant frequency of dc side inductor L,
I and dc link capacitor C, is 47.5 Hz. The PWM in-
I
ASD Rectifier Front-End Topolo y And verter supplying the 503 hp induction motor is
I
I
I
Specifications For Harmonic Fi tering f VoltsiHertz controlled and enters pulse dropping
mode around 52 Hz, which increases the motor
I
I ASD Rectifier Front-end Topology line current THD. Another inadvertent affect of
Fig 1 shows the rectifier front-end topology used the PWM inverter pulse dropping mode is that it
in the 450 kW air-conditioner chiller ASD. It con- causes interaction with the L , - C, dc link filter,
sists of a diode bridge rectifier with dc side induc- which results in the generation of subharmonics in
tor L , = 2 5 0 p H and dc link capacitor C, = 45 the input supply current i, at around 33 Hz. The
presence of the subharmonics can be seen by
slightly unequal supply current i, peak values of

1
Diode Rectifier ,L, PWM Inverter
500 A and 540 A as shown in Fig. 2. Subharmonics
&i
& in the supply current have an adverse impact on the
harmonic filtering solution as well as on the active
filter rating. They result in increased supply cur-
Fig. 1, ASD front-end rectifier topology. rent distortion. The impact of subharmonic supply

/E€€ lndusfry Appbfions Mogozine Sepfember/Ocfober I 998

 ~

I
I
I
I
I
I
I
currents on the design and implementation of par- current limits are to be met up to the 50th I
allel active filter system is discussed later, in the ex- I
harmonic in the supply current. I
perimental results section. The issue of ASD load w Supply current T H D as low as possible for I
induced subharmonics as well as supply side in- voltage harmonic sensitive applications such I
I
duced subharmonics in the supply current has not as for hospital environments. I
yet been addressed in the framework of IEEE 5 17 w Displacement power factor greater than 0.95 I
I
recommended harmonil: standards. from 12.5% to 105% load rating, to match I
This ASD rectifier front-end represents a com- highest possible displacement power factor I
I
mon topology for high power diode and thyristor offered by lowest cost diode rectifier front- I
rectifiers. The dc side inductor L , results in contin- end with dc side capacitor. I
I
uous and quasi-square wave supply line currents, Losses of active filter system lower than 1% of I
with significantly reduced T H D and peak currents, load rating, i.e., less than 4.5 k W oflosses for I
I
compared to the lowest cost diode rectifier-dc side maximum load of 450 kW. I
capacitor solution [a]. Meet given cost goals, including switching I
I
The supply side ac inductance L , at PCC deter- ripple filter and active filter protection and I
mines the overlap anglc during commutation and switchgear cost. I
the maximum dzidt . For ‘stiff ac supply systems or W Meet given size, maximum weight and floor I
I
ac systems with low supply side inductance L , , space area. I
these rectifier front-ends have very small overlap w Meet given packaging constraints, such as the I
I
angle and are beset wii:h very high diidt related active filter system should be mounted and in- I
problems. Consequently., these rectifier front-ends tegrated inside the ASD enclosure to elimi- I
I
require very high bandwidth and high frequency nate on-site installation cost and connections. I
PWM inverters for harmonic filtering to meet W Active filter systems should operate and I
I
IEEE 5 19 harmonic limits, with their concomitant meet IEEE 519 harmonic standards under I
cost penalties. all supply and load conditions such as, in the I
I
The IEEE 5 19 harmonic standards are applica- presence of maximum allowable 5 % supply I
ble only at the utility-plant PCC interface. The voltage harmonics, f 1 0 % supply voltage I
I
utility-plant interface characteristics depend on swellsisags, up to 10% supply voltage un- I
the PCC transformer leakage inductance (which balance and in presence of supply current I
I
determines the SCR at I’CC) and it also depends on subharmonics. I
the ac and dc side filtering elements used with the Active filter systems, including the switching I
I
rectifier front-end. Hence, active filtering of har- ripple filter, should not harmonically interact I
monic front-ends require a systems approach. A with the supply and ASD rectifier front-end. I
simple classification of the harmonic performances The active filter system should also mitigate I
I
of various utility interfke harmonic front-end sys- any supplyiload resonance problems. I
tems and their impact on active filtering require- w An active filter system should nor affect the I
I
ment and rating is given in El], [2]. The dc side and operationofthe ASD, i.e., it should beable to I
ac side filtering elements of the rectifier front-end isolate itself during active filter faults. It I
I
have the following effect on supply current distor- should also be self protecting during system I
tion. The dc side inductor L , smoothes the dc link and ASD faults. I
I
current and minimizes supply voltage unbalance These specifications provide the ASD manufac- I
effects, thus enabling application of cost effective turer with the following value-added supplemen- I
I
active filtering solutions. Supply or ac side induc- tary features in addition to complying with IEEE I
tance reduces supply current i, T H D and peak 5 17 harmonic standards: I
I
value. It also reduces the diidt of supply current z , Displacement power factor greater than 0.95 I
by increasing the commutation overlap period. over the entire load range of 12.5% to 105% I
I
Supply side inductance also provides value-added load rating. I
features such as immunity to supply side transients w Reduced voltage distortion at utility-plant I
due to capacitor switchmgs and ride through capa- PCC interface; this feature increases practical I
I
bilities during supply voltage sagsiswells[ I ) , [2). viability for voltage harmonic sensitive loads I
such as for hospital environments. I
I
Single ASD enclosure, which eliminates in- I
stallation cost and minimizes size, weight I
Specifications for Harmonic Filtering I
and floor space. I
The specifications for harmonic filtering as set by I
the ASD manufacture1 for air-conditioner chiller I
I
ASD application are as follows: Selection of Active Filter I
Supply current T HD to meet IEEE 5 17 har- Topology for Harmonic Filtering I
I
monic limits at utility-plant PCC interface Several active filter topologies, including hybrid I
in presence of maximum allowable 5% sup- active filters, were considered in order to meet I
I
ply voltage distortion. IEEE 5 19 harmonic IEEE 5 19 harmonic standards at the utility-plant

/E€€ Industry ApplicationsMagazine September/October 1998

I
I
I
I
I
I
I PCC interface and other specifications set by the damping by the active filter inverter.
I
I ASD manufacturer Since the optimal active filter Start-up, sequencing and active filter system
I solution is application and utility interface specific protection issues, including cost of isolation
I
I [l},the goal was to match the ASD rectifier front- and protection switchgear.
I end characteristics with a harmonic filtering solu- Topology I1 (hybrid series active filter system)
I
I tion to not only meet IEEE 5 19 harmonic stan- and topology I11 (hybrid parallel active filter sys-
I dards, but overall system specifications tem) do not meet the overall displacement power
I
I Design and analysis at a detailed level for the factor specification, requiring additional cou-
I following three topologies El}, 161 were done for pling transformer and complex protection and
I
I cost and performance comparisons isolation switchgear. They also do not meet cost,
I Topology I Parallel active filter system size, weight and floor space goals. Hybrid active
I
I m Topology I1 Hybrid series active filter system filter systems-topologies I1 and 111-provide
I c31, r51 value-added harmonic isolation feature and re-
I Topology 111. Hybrid parallel active filter duced voltage distortion at PCC, which is desir-
I
I system E41 able for voltage harmonic sensitive loads such as
I for hospital environments [l},[3]-[6}. However,
I
I performance and rating of hybrid series and hy-
I brid parallel active filter systems are adversely af-
I The parallel active filter system meets fected by active filter terminal voltage notching
I
I overall speczfications and constitutes the due to rectifier commutation.
I
I optimal harmonic filtering sohtion. The parallel active filter system (topology I)
I meets overall specifications and constitutes the op-
I
I timal harmonic filtering solution for given ASD
I rectifier front-end topology. This is primarily due
I
I The following factors were considered for active to dc side inductor L , which reduces supply cur-
I filter topology selection rent THD and consequently reduces required ac-
I
I Ability to meet IEEE 519 harmonic stan- tive filter kVA rating. This ASD rectifier front-end
I dards, including for ‘stiff supply systems and significantly reduces lower order harmonics ( 5 th
I
I in presence of maximum allowable 5% sup- and 7th), compared to the lowest cost diode recti-
I ply voltage distortion fier front-end with dc side capacitor, and enables
I Impact of voltage notching due to rectifier application of parallel active filter system. A pure
I
I front-end ar the active filter terminal on the active filter solution meets the high displacement
I performance and rating of the active filter power factor requirement over the entire ASD load
I
I kVA rating and cost of active and passive fil- range compared to either the hybrid’series or hy-
I ter components brid parallel active filter approach and it also re-
I
I Overall displacement factor from 12 5% to quires significantly less protection and switchgear
I 105% load rating cost. Line voltage notching due to rectifier commu-
I
I Losses of active filter system, including switch- tation does not adversely impact the performance
I ing ripple filter and rating ofparallel active filter systems, as verified
I
I Ability to provide value-added features such as by experimental results. The ASD manufacturer’s
I harmonic isolation between supply and load, cost emphasis and availability of water cooling for
I
I voltage regulation in presence of *IO% supply inverter devices due to air-conditioner chiller appli-
I voltage swellsisags, immunity to supply and cation constitute important factors that enabled a
I cost competitive parallel active filter system.
I load transients and ride-through capability.
I Ability for maximum integration with the Parallel active filter systems have the following
I
I
ASD-i e , capability of using the same ASD advantages [1}-[12):
I dc bus, one unit packaging to minimize cost, Viable and cost-effective.for low to medium
I size, weight and floor space LVA industrial loads where system engineer-
I
I Sensor requirement and control complexity ing effort is a large part of overall cost.
I Affect of supply voltage distortion, supply Do not create displacement power factor
I
I voltage sagsiswells and unbalances, and sup- problems and utility loading.
I ply side or ASD load induced subharmonics Supply side inductance L , does not affect the
I
I in the supply current, on the performance harmonic compensation capability of parallel
I and rating of the active filter to meet IEEE active filter system.
I
I 5 19 harmonic standards Controlled as a harmonic current source and
I Bandwidth and switching frequency of active its controller implementation is simple.
I
I filter inverter Can damp harmonic propagation in a distri-
I w Damping/mitigation of supplyiload side res- bution feeder or between two distribution
I
I onances, including additional cost and band- feeders 112).
I width requirement for providing active Performance, controlled as a harmonic cur-

la
I

IEEE Industry Applicniions Mognzine September/Ociober l 998

 rent source, is not affected by supply voltage
harmonics.
Provides immunity from ambient harmonic
loads.
w Protection and sequencing is relatively easy
and does not require expensive isolation
switchgear. Switching
Has a high possibility of system integration Ripple Filter
with various harmonic front-ends with com-
mon functionalities. Parallel
w Can be installed as :i ‘black box’ solution with Active Filter
minimal system level design expense and Inverter
provides viable retrofit options.
w Is scalable for higher load kVA rating by par-
alleling units. vdc
It is to be noted that parallel active filter sys- I
I
tems are not suitable for high peak harmonic cur- Fig. 3. Parallel active filter system. I
rent loads due to their !Large rating requirement. I
Furthermore, large rated PWM inverters with
high current bandwidth have higher losses and cost maximum dc bus voltage reference Vd:,, is re-
penalties. Hence, the efficiency of large rated paral- I
stricted to 750 V in case of +lo% higher supply I
lel active filter is a constraint for harmonic com- voltageV, = 506V. This constraint is due to use of I
pensation at high power levels. Also parallel active 1200 V IGBTs devices and their protection in case I
I
filter systems need to address line interaction of of short circuits. The nominal dc bus voltage is not I
switching ripple filter with supplyiload, operation fixed at its maximum reference voltage Vd:man= 750 I
I
under supply voltage distortion and unbalanced I
V for all supply voltage conditions, in order to re-
supply/ load conditions [2], [lo], C111. Interac- I
duce inverter switching losses and to meet a loss I
tions of the switching ripple filter with supply/ I
specification of less than 1% of load kVA rating by
load can be damped within the bandwidth of active I
the active filter system. I
filter inverter, by incorporating ‘active damping’ I
The dc bus capacitance C6*, is 12.5 mF. ASD
feature in the active filter controller. I
load induced subharmonic currents present in the I
supply, increase dc bus voltage fluctuation by 5% I
I
Parallel Active Filter :System Implementation as shown by experimental results in Fig. 13. Sub- I
Fig. 3 shows a parallel active filter system includ- harmonic supply currents also increase the dc bus I
I
ing switching ripple filter to provide harmonic fil- capacitance (C6,‘,) requirement by 25%. Mitiga- I
tering for a 450 k W ASD rectifier front-end. The tion of subharmonics by parallel active filter results I
I
parallel active filter inverter is rated 130 kVA in a significant increase in active filter inverter rat- I
based on rms active filter current i f = 165 A and ing and is not implemented for this application. I
The inverter output filter inductance L , = 75 I
rms active filter terminal voltage V f = 460 V. The I
IGBT inverter is implemented with a switching pHor 1.7% on the inverter kVA base. Design con- I
siderations for inverter switching ripple filter (as I
frequency f, of 20 kHz to achieve current band- I
width of around 2 kHz. well as its effectiveness in providing damping to I
both supply and load induced resonances) is dis- I
The peak harmonic or active filter current i, is I
377 A for full load fundamental rms current of 565 cussed in detail three sections hence. I
The parallel active filter approach is based on the I
A. Two paralleled 200 A IGBTs constitute one I
switch and are used to provide better thermal man- principle of injection of load harmonic currents and I
is characterized by non-sinusoidal current reference I
agement. The IGBTs used have positive tempera- I
ture coefficient with respect to collector current to tracking and a high current regulator bandwidth re- I
quirement. The parallel active filter is controlled as I
ensure current sharing. The IGBTs are water- I
cooled, which does not require significant addi- a harmonic current source and requires a suitable I
tional cost for the air-conditioner chiller applica- controller for extraction of load harmonic currents, I
I
tion. However, maxirnum water temperature and an appropriate current regulator, which are dis- I
applied to the heat sink is 43°C and provides a cussed in the next two sections respectively. I
I
challenging thermal design problem. I
The active filter inverter nominal dc bus volt- Synchronous Reference Frame Controller I
for Parallel Active Filter System I
age V, is 682 V for nominal supply voltage of 460 I
V. The reference dc bus voltage is linearly changed and its Implementation I
Fig. 4 shows the synchronous reference frame (SRF) I
in case of supply voltage swellsisags of &lo%. The I
ASD manufacturer’s specifications allow up to controller developed for parallel active filter sys- I
tem. The load current z I is measured and load cur- I
*IO% supply voltage swellsisags respectively. The

m
l

/E€€ Industry Applications Magazine I September/Ortober I 998

 I
I
I
I
I
!
I
rent harmonics are extracted in the synchronous to any phase errors introduced by low-pass filters
I d e- q e reference frame by a posztzwe sequence SRF This is advantageous compared to most other con-
I trollers, such as those with a notch-filter imple-
I controller. The controller also uses a negative se-
I quence SRF based controller to extract fundamen- mentation, which will introduce considerable
I phase errors at fundamental as well as at harmonic
I tal negative sequence load current and a dc bus
I voltage controller to regulate active filter inverter frequencies [ S } , [13} For example, the minimum
I phase error for a second order notch-filter imple-
I dc bus voltage The three sub-system controllers
I are shown in Fig. 4. mented with a typical switched capacitor filter
I
In the positive sequence SRF controller, the such as LTC-1064 is 4 2% at 60 Hz
I
I unit vectors are generated by +ee
for synchronous The extraction of load current harmonic com-
I d e- q e reference frame transformation The unit ponents IS achieved by a high-pass filter imple-
I
I vectors are derived by a phase lock-loop (PLL) cir- mentation in synchronous d ' - q' reference frame
I The low-pass filters extract the dc components in
I cuit on the active filter terminal voltageVJ In the
I synchronous d e- q e reference frame the fundamen- synchronous d e- q' reference frame which corre-
I
I tal positive sequence components are transformed to sponds to fundamental positive sequence load cur-
I rent components in stationary d ' - q' reference
I dc pantztzes zn d and q e axes andall hamonzc compo-
I nents are transfirmed to ac quantztzes wztb LZ frequency frame the high-pass filter implementation is real-
I
I shzJt of 60 Hz.The dc quantities are extracted by ized as (1-LPF) to extract all ac components in
I low-pass filters (LPF) implemented in both d e and synchronous d e- q reference frame Transforma-
I
I q e axes Since the signal to be extracted is dc in tion of these ac components into a stationary
I
I both d e and q' axes, filtering of the signal in the d'- q' reference frame yields all harmonic compo-
I synchronous d e- q e reference frame is insensitive nents of load current z L
I
I
I

I
I
I
-w ds - qs de - qe I
I to to
I
I
de - qe ds - qs
I
I
+ ls,ds I
From PLL
I
I cos-e,
sin4
t t f f I
I
I

Voltage Vfc
+

Fig. 4 . Synchronous reference frame controller for parallel active filter system.

y
I

/E€€ Industry Applicutions Maguzine m September/October 1998

 I
I
I
I
I
I
I
I
In the presence of a fundamental negative se- sequence component. The higher load current har- I
I
quence supply, voltage unbalance, typically monics are similarly transformed into multiples of I
around l%,supply current i, and load current i, 360 Hz in synchronous d - q reference frame. I
will consist of fundamental negative sequence I
The cut-off frequency of low-pass filters can I
component. The positive sequence SRF controller be designed to be as low as 1 Hz or even 0.1 Hz, I
transforms the fundamental negative sequence I
since the low-pass filters are required to extract I
load current component into a 120 Hz component only dc quantities and to provide adequate atten- I
in a synchronous d e- q' reference frame. This 120 I
uation to ac components corresponding to har- I
Hz component will not be extracted by low-pass monic frequencies. A low cut-off frequency I
filters implemented to 'extract only dc quantities I
enables use of lower order filters, and also I
with low cut-off frequency. Hence, it is inverse achieves adequate attenuation to 360 Hz compo- I
transformed into a fundamental negative sequence I
nent corresponding to both 5th and 7th har- I
component in stationary d '- q' reference frame, at monic frequencies in t h e synchronous I
the positive sequence SRF controller output. I
d' - q e reference frame. Low cut-off frequency of I
A separate heterodyning for the fundamental low-pass filters improves closed loop system sta- I
negative sequence load current component is provided in bility margin, albeit with slower transient re- I
I
the synchronous d e - q e reference frame by the sponse. Since signal extraction at dc is achieved I
negative sequence SRF controller. In this case the with zero phase error, phase lag characteristics of I
I
unit vectors are generated by -0# as shown in Fig. low-pass filters are inconsequential, provided at- I
4. I n t h e negative sequence synchronous tenuation of 360 Hz component and its multi- I
d e- q e reference frame, the fundamental negativese- I
ples meet controller design specifications. This I
quence load current components are transformed into dc feature enables use of cascaded first order I
quantities. The dc quantities are extracted by I
low-pass filters with the same cut-offfrequency. I
low-pass filters, as in the positive sequence SRF The SRF controller implementation is sensitive I
controller. The extracted dc quantities in d e and I
to dc offsets and gains. This requires that the de- I
q e axes are inverse transformed to fundamental sign of low-pass filters be maximally flat with con- I
negative sequence load current components in sta- I
stant gain up to the cut-off frequency and requires I
tionary d ' - q' reference frame and subtracted the use of dc offset cancellation techniques. The
from the positive sequence SRF controller output. low-pass filters used in the SRF controller im-
Hence, the active filter inverter reference current
p l e m e n t a t i o n are realized by t h i r d order
i; does not contain any fundamental negative
Sallen-Key structure to provide maximally flat
sequence load current component. This ensures
butterworth low-pass filter characteristics with
that the parallel active filter does not compensate for
a cut-off frequency of 10 Hz. Sallen-Key realiza-
fundamental negative sequence current in the sup-
plylload andperforms only its intendedfunction of load tion provides minimal sensitivity to low-pass filter
harmonic current compensation. Consequently, the component values such as resistor and capacitor
SRF controlled active filter inverter does not re- values and tolerances.
quire an increased rating proportional to supply Continuous time low-pass filter implementa-
voltage unbalance and it also prevents overload- tions are preferred over sampled-data switched ca- I
ing of the active filter inverter in presence of sup- pacitor based low-pass filter implementations I
because of aliasing concerns for higher order har- I
ply voltage unbalance [14]. I
The dc bus voltage controller to regulate active monics, especially 25th-50th harmonics. Accord- I
ing to the ASD manufacturers specifications, IEEE I
filter inverter dc bus voltage is detailed later in I
this section. 519 harmonic current limits are to be met up to I
50th supply current harmonics. For example, a I
I
sampling frequency of 3 kHz has a signal band- I
Implementation of the Synchronous width up to 1.5 kHz (i.e. up to 25th harmonic fre- I
Reference Frame Controller I
quency) and introduces aliasing errors for 25th- I
The SRF controller is implemented by analog/ digital 50th harmonic frequencies. Increasing the sam- I
hardware and therefore circumvents the sampling I
pling frequency is not a viable solution because the I
and computation delay problems associated with a sampling frequency f,,,J,,, of switched capacitor I
DSP based imp1ement;wion. The sampling and filters is given by the relationship f,a,,, / f o = 25 I
I
computation delays are critical for an active filter to 100, where f , is the designed cut-off frequency I
application. They constitute a major limitation for of low-pass filter. Hence, a designed cut-off fre- I
I
high frequency reference current tracking with a quency f,specifies the sampling frequency f,6,,Jp,, . I
DSP based implementation. Desired low cut-off frequency f , for the low-pass I
I
The dominant 5th and 7th load current har- filter constrains the sampling frequency. The sam- I
monics are both transformed to 360 Hz in the pling frequency in turn determines the maximum I
I
synchronous d ' - q e reference frame. This is be- harmonic frequency that can be completely com- I
cause the 5th harmonic is a negative sequence com- pensated in the supply current without any I
I
ponent whereas the 7th harmonic is a positive aliasing concerns.

/€€E Industry Applications Magazine I September/October 1998

h
I Note that separate heterodyning for fundamen- This will modify the active filter harmonic refer-
I
I tal negative sequence load current components al- ence current i; extracted from the load current
I lows implementation of low-pass filters with the and generated by positive and negative sequence
I
I same low cut-ofifrequency of I O Hz as that used for the SRF controllers. Consequently, the supply cur-
I extraction of fundamental positive sequence load rent will have harmonics, since the active filter
I
I current components. controller is based on the principle of load har-
I monic compensation. Further, in the presence of
I
I Parallel Active Filter D C Bus Control supply voltage distortion, active filter terminal
I A dc bus PI controller regulates the dc bus voltage voltage harmonics will interact with dc bus volt-
I
I to its reference value V,: and compensates for the age controller generated reference harmonic cur-
I
inverter losses as shown in Fig 4 The dc bus con- rents. This interaction will result in a real power
I
I troller generates a fundamental reference current to transfer between the inverter dc bus and the sup-
I provide the real power transfer required to regulate ply: Thus filtering of measured Vdc also ensures
I that any power transfer between the inverter dc
I dc bus voltage and for compensation of the inverter
I losses The nominal reference dc bus voltage is bus and supply for dc bus voltage regulation, is
I only at fundamental frequencies and not as a re-
I Vd: = 682 V for a nominal supply voltage of 460 V
I sult of harmonic frequencies. This avoids har-
I This reference dc bus voltage V:, is linearly modi-
monic oscillations in the active filter current i f
I
I fied in case of supply voltage sagsiswells, to reduce and supply current i,. The required filtering of
I inverter switching losses The maximum dc bus measured V, is dependent on the dc bus capaci-
I
voltage referenceVd:me is restricted to 750 V in the tor Cbu value. The dc bus capacitor Cbu value is
case of + 10% higher supply voltage V, = 506 V sized according to the desired V, voltage ripple
This constraint is due to the use of 1200 V IGBTs specifications.
devices and their protection in case of short cir- In this implementation, the measuredVdc is fil-
I
I cuits The output ofthe PI controller is clamped by tered by a single pole low-pass filter, with a cut-off
I a limiter to allow a maximum permissible dc bus frequency of 10 kHz, to filter out the 20 kHz in-
I
I voltage of m O V verter switching frequency and side-band fre-
I quency generated V, ripple: This filtered V,
I
I
signal is further filtered by a 5th order switched ca-
I pacitor low-pass filter with cut-off frequency of
I The supply current will huue 150 Hz, to attenuate 360 Hz component and its
I
I
I
harmonics, since the activefilter multiples. Hence, the dc bus voltage controller
will not actively compensate theV,, ripple compo-
I
I
controller is based on the principle of nent at 360 Hz by generating additional 5th and
I
I
loud hurnzonic compensution. 7th harmonic reference currents for the active filter
I in stationary d ’- q’ reference frame.
I
I In the presence of a supply voltage unbalance,
the fundamental negative sequence component of
I The measured dc bus voltage V,, used for feed-
I the active filter current i f will result in a 120 Hz
I back requires filtering to attenuate ac components V, ripple component. The 120 HzV, component
I present inV, The dominant ac components ofV, can be significant for a typical supply voltage un-
I
I are at 360 Hz and its multiples This is because balance of +lo%. Unlike 360 Hz and its multiple
I both 5th and 7th harmonics of active filter current harmonic components in V, , the 120 Hz Vdc com-
I
I
I
,
z are transformed into 360 Hz (6th harmonic) ac ponent needs to be detected and controlled, to
component on the inverter dc bus side and result in minimize its adverse affect on active filter current
I
I dc bus voltage ripple. Note that 5th harmonic is a regulation. Hence, this 120 Hz V, component is
I negative sequence component whereas 7th har- not filtered and therefore the low-pass filter cut-off
I
I monic is a positive sequence component. Similarly, frequency is set at 150 Hz.
I higher harmonics of active filter current zf result The design of PI regulator gains and dc bus ca-
I
I in dc bus voltage ac components at multiples of pacitance cbu, are based on the specified supply
I 360 Hz, which are proportional to harmonic cur- voltage unbalance, inverter output filter induc-
I
I
rent amplitudes tance L , ,and the PWM switching frequency. The
I If the ac components present in dc bus voltage PI regulator output is also bandwidth limited to
I V, are not attenuated for dc bus voltage feedback
I
eliminate any lower order ( j t h , 7th, l l t h , 13th)
I loop, they will generate harmonic reference cur- harmonic frequencies. This again ensures that any
I rents in order to eliminate these ac components real power required to regulate dc bus voltage V,, ,
I from Vdc For example, a 360 Hz ac component of is derived at the fundamental frequency and not as
I V, will generate 5th and 7th harmonic reference a result of harmonic frequencies.
I
I currents in the stationary d * - q’ reference frame, The measured active filter terminal voltage Vf
I in order to eliminate the 360 Hz V,, component is transformed into a positive sequence synchro-
I

lp IFFE Industry ApplicationsMuguzine k September/October I998

nous d B- q e reference frame as shown in Fig. 4. termined fixed switching period. Hence, it enables
Heterodyning of fundamental positive sequence the constant switching frequency operation and its l
V, voltage components is achieved by extracting advantages. This is in contrast to hysteresis based I
the dc quantities in the synchronous d e- 4’ refer- current regulators, which do not generate an in- I
I
ence frame by low-pass filters as in the positive se- verter ‘average voltage’ vector reference, but rather I
quence SRF controller. The dc bus PI controller employ either a fixed or variable hysteresis current I
I
’output is multiplied with the extracted dc quan- band to force inverter leg switchings. Hysteresis I
tities in the synchronous d e - q e reference frame, current regulators suffer from phase interaction I
I
to generate an active filter current reference for dc problems as well as low frequency current errors, es- I
bus voltage regulation and is added to the output pecially for non-sinusoidal multiple frequency
of the positive sequence SRF controller. Note that tracking. Hysteresis current regulators also generate
multiplication of the dc bus voltage controller an undesirable ‘white noise’ current spectrum as a
ourpur with the fundamental positive sequence result of variable inverter switching frequency [2].
active filter terminal voltage V, components en- Direct generation of an inverter ‘average volt-
sures that the real power required for dc bus volt- age’ reference for current regulation can also be
age regulation is derived only at the fundamental achieved by synchronous or stationary frame PI
frequency. based current regulators r161, [171. However, in
The active filter three phase reference currents this case, the transformation of current errors to in-
,* . *
z,.. ,l F , and i;‘ are generated as shown in Fig. 4 and verter reference voltages is achieved by a frequency
implemented by a suitable current regulator as dis- dependent PI controller which introduces significant
cussed in the next main section. phase shift for multiple and high frequency current
references. Hence, it is not suitable as acurrent reg-
Predictive Current Re!gulator with Charge Error ulator for active filter applications.
Control for Parallel Active Filter Implementation Fig. 5 shows the proposed predictive current
Realizations of harmonic free utility interface ap- regulator with charge error control implemented in I
the stationary d q’ reference frame for parallel
I-
I
plications by parallel active filters are characterized I
by the following current regulator requirements active filter reference current i; tracking. This cur- I
I
for the inverter: rent regulator generates an ‘averagevoltage’ refer- I
w non-sinusoidal multiple frequency current I
ence vector for the inverter without any frequency I
tracking dependent transformation of current errors to ref- I
w ability to operate with low inverter output I
erence voltages, unlike a synchronous or stationary I
filter inductances-typically L , < 5% frame based PI current regulator. The charge error I
w high diidt reference current tracking and part ofthe current regulator is based on the concept I
I
high current regulator bandwidth for track- of minimizing the integral of the current error, or equiv- I
ing of high frequency harmonics alently minimizing the charge error over every switching I
I
minimization of low as well as high fre- period T,w.The motivation for charge error based I
quency current errors current regulator is to compensate for current er- I
I
desired implementation by a constant swit- rors due to uctiue filter reference current change, espe- I
ching frequency PWM scheme cially of higher harmonics within one switching period I
maintain predictable current ripple bounds I
T,u,.It also compensates for current errors due to I
w avoid phase inter.actions and limit cycles in inverter non-idealities and due to current regulator I
the current I
implementation errors. Inverter non-idealities in- I
w low sensitivity to inverter output filter in- clude dead-time delays, device voltage drop and I
ductance L , error and voltage V, estimation I
non-ideal device switching characteristics. Cur- I
error in the current regulator rent regulator implementation errors include cur- I
w low sensitivity to analogidigital implemen- I
rent and voltage measurement errors, sample and I
tation issues such as sample and hold (SIH) hold (SIH) delays and parameter error for estimated I
delays and inverter dead-time delays I
filter inductor value L , . The resultant high fre- I
w ability to implement higher inverter switch- I
ing frequency without DSP or p P limita- quency current averaging over every switching pe- I
tions of computat ional delays riod TJ,,,, minimizes both high frequency and low I
I
w allow a simple and cost-effective implemen- frequency current errors. Further, this feature en- I
tation sures predictable current ripple bounds and en- I
I
Hysteresis and predictive current regulators ables operation with low and cost-effectiveinverter I
[l5] are the only two viable choices for tracking output filter inductances ofL, < 5% El8l. I
Implementation of the proposed predictive cur- I
non-sinusoidal multiple frequency current refer- I
ences with high diidt . Predictive current regula- rent regulator in a complex d’-q’ stationary ref- I
I
tors allow carrier-based PWM implementations by erence frame as shown in Fig. 5 , implicitly achieves I
explicitly generating an inverter ‘uverage voltage’ decoupling of phases and alleviates concerns of I
I
vector reference to be synthesized within a prede- phase interactions and limit cycles in the active fil- I

I€€€ Industry Applicotions Mogozine m leptember/ff ctober I998

I
I
I
I
I
I
I ter current Z, Decoupling of phases also ensures
I
itates current error update every half switching pe-
I predictable peak-peak current ripple for a given dc riod T,, 12. For a reference voltage vector in sector
I bus voltage V, , active filter terminal voltage V,
I I, a typical inverter switching sequence within one
I and filter inductor L , value Active filter current switching period Tlu,,is given by inverter switch-
I z, peak value, peak-peak ripple and rms value are
I ing states 0127-7210. In this case, to improve
I important criteria for the filter inductor L, design. tracking of higher harmonic active filter current
I The proposed predictive current regulator is
I references, the current error is updated every
I implemented as a dzscrete-tzme sumpled system in the
TJw12,which results in unequultime on the same in-
I stationary d’- q’ reference frame The current er-
I verter switching state within one switching period
I ror AzfqdJ= zJqd, - z;qh (represented in the vector T,, . In a conventional implementation, for example,
I
I notation and also in Eq 1) generates the inverter the time on switching state 2 is identical for both half
I
I ‘averagevoltage’ reference by the sum of two paral- periods of a switching period; only the switching se-
I lel paths In the first parallel path, the current error quence is reversed in the two half periods to achieve
I
I Azfqd, is sampled every half switching period current averaging per switching period.
I (T,w 12 )instead ofeveryT,w,to improve tracking of In the second parallel path, the integral of the
I
I hzgber hurmonzc uctzvefilter currents due t o thew refer- current error or equivalently the charge error is de-
I ence change wztbzn one swztcbzngperzodTw This sam- termined and reset every switcbingperiodTJw.This is
I
I
pled current error is used to generate an inverter achieved by an integrator reset and sample and
I rzference voltage component by multiplying with hold (SIH) circuit. The charge error value at the
I
I L, 1% as in a conventional predictive or dead- end of a switching period is used to generate a cor-
I rection term for the reference voltage vector of the
I beat controller Note that L, represents the esti-
next switching period. Ifthe integrator for the cur-
I
I mated filter inductor value The necessity of a half rent error is allowed to run free it will accumulate
I switching period update is evident from the fact low frequency current errors as well as incur inte-
I
I that for a switching frequency of 20 kHz(T,, = grator saturation problems during start-up and
I 5Ops), the 50th harmonic ( 3 kHz) reference cur- transients. The integrator reset operation generates
I
rent incurs a phase delay of 27” over a half switch- the charge error over every switching period T,w,
ing period T,w 12 = 25p s. The charge error is biased positive or negative over
I Synthesis of the inverter ‘averagevoltage’ refer- a switching period. The ‘weighting factor’ W T
I ence by a space vector based PWM modulator facil- multiplying the charge error determines the high
I
I
I
I
I
I v
I S4qs
I Active Filter SIH
I Reference
I Current
I
I
I
’
S
t S l H
A
---t -
I
I
I
I
I
I
I
I
I
I
I
I
I

t t
Integrator ResetTSW Tswi2
Measured 1
Active Filter
Terminal
Voltage
3 Phase

2 Phase
svtds
I

Fig. 5. Predictive current regulator with charge error control.

a IFF€ lndusfry ApplicationsMagazine September/October 1998

 ~

I
I
I
I
I
I
I
I
frequency current averaging window as a ratio of and high frequency current averaging in the I
I
switching periodT,w.For iexample,W T =1.O implies presence of these delays can be achieved by propor- I
current averaging over one switching period and tionally changing the 'weighting factor' W T by I
W T < 1.0 implies a current averaging window I
the ratio of total delay Tdele,to a switching period I
greater than Tiw.The charge error is reconverted to T,, greater or less than unity, depending on the I
an equivalent current error AichdrEe
di by dividing by I
sign of the current error Ai ,qd I
T,w.This is then added to sampqed current error The equations describing the current regulator I
Aifqd,from the first parallel path. The result- I
operation in vector notation are:
,
ing quantity is multiplied with L 1% to gen-
I
I
I
erate reference voltage across inductor L , to I
regulate active filter invixter reference current i; . I
I
The inductor reference voltage vector V,, is I
I
given in Eq. 2. I
The inverter reference voltages in the stationary I
I
d ' - g ' frame are generated by adding the I
@ I
feedforward d'- q' active filter terminal voltage I
I
V, signal to the inductsor reference voltage V , , I
and is given in Eq. 3. The feedforward V, signal is I
I
sampled synchronozlsly every Tlw12 period and si- I
multaneously with the current error AiIqd signal. I
where i ,qd, and iiYd,
are measured and reference ac- I
The charge error signal is also synchronowly sam- I
pled every T,w period with all the other signals. tive filter current vectors respectively, and Vi,,,is I
the measured active filter terminal voltage vector. I
However, the same charge error value is added at I
two consecutive T,w12 sampling instants, i.e., at Note that the prefix 's' denotes sampled quantities I
the start and middle of' a sampling period. The in Figs. 5 and 6. The current regulator generates re- I
I
feedforward of active filter terminal voltage V, in quired inductor reference voltage vector v, and I
the current regulator reduces the required gain of inverter reference voltage vector V,,,,,* . e in- & ' I
I
the current control feedback loop, thereby increas- verter reference voltage vector v,:~d< is imple- I
I
ing the stability of current control feedback loop. I
The charge error control serves the following mented by an analog space vector modulator as I
described in the next subsection. The ratio of the I
four functions: I
compensates for current errors due to high actual to nominal dc bus voltage (V, / V i ) is pro- I
frequency reference current change within a vided as a feedforward signal, as in most high per- I
I
switching period and enables high frequency formance current regulators. I
reference current tracking Active filter implementations are characterized I
I
w compe2sates for errors due to mismatch be- by high PWM modulation index operation. The I
tween L , and actual L , -a drawback of con- nominal dc bus voltage is 682 V with active filter I
I
ventional predictive current regulators terminal voltage V, = 460 V. The inverter voltage I
enables high frequency current averaging in available for current regulation is therefore 32 V. I
I
presence of sample and hold (SIH) delays and Consequently, the current regulator saturates I
inverter dead-time delays under high diidt conditions during rectifier com- I
I
compensates for measurement errors of i, mutation periods. In such cases, the average in- I
and V, signals. verter voltage reference vector VzIv is attenuated I
&. I
Errors due to the above mentioned conditions to the maximum PWM modulation index with the I
result in an inverter voltage reference error. This voltage reference vector angle unchanged. This oc- I
I
results in a current tracking error which is cor- c u r s a s a n a t u r a l c o n s e q u e n c e of t h e I
rected in the next (k+l)th switching period implementation of the space vector modulator by an I
I
+
T,w( k I), by the accumulated charge error from analog hardware circuit (to be described next). This
strategy achieves high dynamic response preserving
I
I
the previous kth switching period Tsw ( k ) . The ac- I
the simplicity of the PWM modulator implementa- I
cumulated charge error generates a corrective in-
tion. However, under such conditions the harmonic I
verter reference voltage in the next ( k + l ) t h I
content in the compensated supply current increases. I
switching period T,w( k .t1). The proposed predictive current regulator I
Sample and hold (SIH) delays are typically scheme allows a direct voltage based PWM imple- I
1- 2 ps, and inverter dead-time delays are typically I
mentation by generating an average inverter volt- I
3 - 5 p s . Hence, the total delay T,+ is in the range age reference vector V,:vdi. This facilitates I
of 4 - 7 ps. This total delayTd8,, is significant since I
implementation of constant &itching frequencycar- I
it constitutes 10 - 15% of a 20 kHz PWM switch- rier-based PWM schemessuch as space vector modu- I
ing period T,= 50p.s. Charge error minimization I
lators. Carrier-based PWM schemes, such as space I

I€€€ Industry Applications Mogozine September/October 1998

@
I
I
I
I
I
I vector modulators, achieve decoupling of phases by applications such as active filters, where the in-
I
I implementing prescribed adjacent state inverter verter reference voltage vector Vz:u changes every
1dJ
I voltage vectors over one switching period. This is es- switching period
I
I sential for minimization of low frequency current er- Symmetrical inverter dead-time compensation
I rors and predictable peak to peak current ripple. is provided by addingisubtracting a feedforward
I
I voltage depending on the sign of the active filter
I current as shown in Fig 6 The resulting space vec-
I Analog Space Vector Modulator
I tor modulating waveform is regularly sampled,
I Implementation synchronized to the peak of the triangle waveform,
I Fig. 6 shows an analog hardware circuitfor space vector
I and compared with a 20 kHz triangle waveform to
I modulator implementation to generate inverter generate inverter switchings In this implementa-
I switchings. The fact that the modulating function tion the switching frequency is 20 kHz In the
I
I of the space vector is identical to that of a modified practical current regulator circuit, the implemen-
I regular sampled sine-triangle PWM scheme includ- tation delay IS Sps, ofwhich 2 p s is contributed by
I
I ing all triplens, enables an analog hardware circuit sample and hold delay and 3 ps by inverter dead-
I implementation. The diode bridge configuration time delay
I
I extracts all triplens from the three phase inverter
I reference voltages. This extracted zero sequence
I
I voltage forms the offset voltage for the three phase Selection and Design Issues of Switching Ripple
I inverter reference voltages. This offset voltage filter for Parallel Active Filter Inverter
I
I achieves centering of the active adjacent space A switching ripple filter at the output of the ac-
I vectors with predefined placement of leading and tive filter inverter is required to sink high
I trailing edge zero vectors within a switching pe-
I frequency switching harmonics produced by the
I riod, e.g. the inverter switching sequence for sec- inverter switchings, thereby reducing switching
I tor I is given by inverter states 0127-7210. frequency and EM1 currents in the supply and
I
I Analog hardware circuit implementation of a high frequency harmonics into the ASD rectifier
I space vector modulator is simple, cost-effective, front-end If effectively designed, switching rip-
I
I and allows an arbitrarily high inverter switching ple filters can also provide attenuation for higher
I frequency, unconstrained by DSP i p P speed limi- harmonic supply currents which are above the cur-
I
I tations. This analog hardware space vector modu- rent regulator bandwtdtb of parallel acme filter zn-
I lator implementation is especially beneficial for verter However, they have the caveat of attracting
I
I
I
I
I Deadtime
I Triangle Carrier
I Waveform
I FSW= 20kHz
I Measured

Ah
I Filter Current 7 4 7 4
I
I
I
I Sa
I
I
I
I
I
I
I 1 2Phase
sb
I
I
I svTtvds
I to
3Phase

I
I
I Inverter
I ds - q S
I Reference
I Voltages
I or
I Inverter
Output of Predictive Gate
I
I Current Regulator or Natural Signals
I
I Decision
I
I
I
I
I
I
I
I Fig. 6. Andlog implementation of space vector PWM modulator.

/E€€ lndusfry Applimfions Maguzine = Sepfember/Orfober I998

 I
I
I
I
I
I
I
I
sourceisink resonances with supply line inductance Topology (ii) in Fig. 7 is employed to provide a I
L , and/or rectifier load. sink for the dominant inverter switching frequency I
I
Active damping of any supply or load induced ripple by a tuned L - C circuit. In this case, the I
resonance conditions with the switching ripple fil- damping resistor R, can be typically small, which I
I
ter can be provided by the active filter inverter is desirable as it increases the effective quality fac- I
within its current regulator bandwidth [lo], E12). tor Qof tuned L - C circuit and it also alleviates the I
I
Active damping feature can be easily incorporated active filter terminal voltage V, distortion prob- I
in the proposed SRF controller shown in Fig. 4.To lem. However, a large R, is required to provide I
I
implement active damping the active :filter termi- broad-band damping for supply and/or load in- I
nal voltage harmonic V,, is extracted, multiplied duced resonance conditions and consequently, re- I
I
by a gain, and added as a feedforward compensat- introduces an active filter terminal voltage v, I
ing voltage signal, similar to the feedforward volt- distortion problem. In the presence of supply volt- I
I
age signal V, in Fig. 5 . Note that ‘stiff supply age distortions, active damping is required for I
systems (i.e. low supply side inductance L,) signif- high Q factor designs. I
I
icantly increase the reson.antfrequency and interac- The damping resistor R, design sensitivity can I
tion problems with the switching ripple filter. be reduced by a conventional high-pass circuit as I
I
This requires higher inverter current bandwidth shown in topology (iii) in Fig. 7, which can also be I
for active damping than that required fior harmonic L - C tuned to the dominant inverter switching I
compensation. Higher inverter current: bandwidth frequency. To provide effective broad-band damp- I
I
requires higher PWM switching frequency with ing in case of supply and/or load side resonance I
their concomitant cost penalties and higher conditions, the impedance offered by inductor L I
I
switching losses. Hence, active damping under needs to be significantly larger compared to the I
‘stiff supply system conditions does not constitute damping resistor R, . This imposes a design con- I
I
a cost-effectiveand viable harmonic filtering solu- straint on inductor L value and it is often cost- I
tion to meet IEEE 5 19 harmonic standards. effective to implement topology (i), rather than I
I
Active damping has not been implemented in justify the cost of a large inductor in topology I
this application because the ASD load character- (iii). The circuit in topology (iii) also requires ac- I
I
istics are well defined and there are no capacitive tive damping feature in presence of supply volt- I
or linear loads in the system. Hence, even under age distortions. I
I
the presence of supply voltage harmonics, there is I
no possibility of supply-load and/or active filter lmplementation of Switching Ripple Filter I
I
inverter-load resonance conditions. This results The approach implemented for this application, as I
in cost savings in terms of reduced inverter band- shown in topology (iv) of Fig. 7, is to provide two I
width requirement and inverter losses. However, separate paths-one for the dominant inverter I
I
there is a potential of supply and switching ripple switching frequency ripple current at 20 kHz and I
filter resonance in the presence of upp ply voltage the other for broad-band damping of any supply I
I
harmonics. The switching ripple filter is designed and/or load induced resonances by a damping resis- I
to damp any possible csscillations due to supply tor R , . The filter branch L - C is tuned at the I
I
voltage harmonics, active filter, and load current inverter switching frequency of 20 kHz to sink I
transients and harmonics, as discussed shortly. dominant inverter switching frequency ripple cur- I
I
Fig. 7 shows the various switching ripple filter rent. The parallel branch ofR, and capacitor C pro- I
topologies. The standard industry solution is to in- vides broad-band damping to supply and/or load I
I
corporate a damping resistor R, in series with a induced resonances. I
high-pass filter capacitor.C as shown in topology (i) I
in Fig. 7. The effectiveness of this solution is lim-
ited to a narrow frequency band and it is applica-
tion and system operating point specific. The
design ofR, is sensitive to system parameters. The
damping resistor R , also contributes to significant
voltage distortion at the active filter terminal volt-
age Vf, which is detrimental for voltage harmonic
sensitive loads connected at PCC, such as for hospi-
tal environments. Note however that a minimum
value ofR, is required for all switching ripple filter (ii) (iii)
topologies to damp sustained filter oscillations due
to any supply and/or had transients. Further, in Fig. 7. Switching ripple filter topologies considered for parallel active filter
the presence of supply voltage harmonics, R , pro- inverter. Switching ripple filter topology (iv) implemented with
vides the damping required for harmonic compen- L , = 2 1 k H , C T = 3 k F , R , =50mQ,C = 5 0 m F , R d =1.7Qforparallel
sation method based on load current detection. active filter inverter w i t h switching frequency of 20kHz.
I
I

IFF€ Industry Applicotions Mogozine September/October I998

 I
I
I
I
I
Tek 5OOkWs 31 ACqS However, the trade-off is increased losses and rat-
I 1
I I ing of the damping resistor R , .
The rms current rating of the switching ripple
filter components at 450 kW input power to the
ASD, supply voltage V,= 460 V, active filter in-
verter dc bus voltageVdc = 682 V, inverter switch-
ing frequency f, = 20 kHz and current regulator
implementation delay of 5p s are:
,
R The current rating of L T , C and R filter
branch is 5.8 A rms with 1.6 A peak funda-
mental current and 5.7 A rms of 20 kHz
switching frequency ripple current.
1 The current rating of R , is 6.4 A rms.
The current rating ofcapacitor C is 8.6 Arms
and 7.0 A peak fundamental current.

I
t
Ch2 1.00 V M2.OOms L i n e J ov
I The current rating of all switching ripple filter
components is small and meets given specifica-
tions of cost, size, weight and packaging. This
also results in a cost-effective design since it elim-
5ljB 1 OOV 2.00ms
inates the need for higher inverter current band-
Fig. 8. Active filter reference current i ; [lo0 Aldiv) and actual current if w i d t h t h a n t h a t r e q u i r e d for h a r m o n i c
{loo Aldiv), t = 2msIdiv. compensation. This design demonstrates that to-
I pology (iv) (Fig. 7) provides a viable and
I cost-effective solution for inverters with fixed
I The specification of a displacement power fac-
I switching frequency PWM schemes.
tor greater than 0 95 at 12 5% load condition con-
I Note that in this application since the value of
I strains the maximum filter capacitor value C =
I 50 pF The inverter switching ripple filter branch capacitor C is small (50pF), the switching ripple
I
I ,
consisting ofL ,C T , R , is designed with the con-
filter does not provide any significant reduction in
active filter terminal voltage V J notch area. This is
I straint that C << C, typically C, < 10 C such
I
that all the fundamental active filter terminal volt- also evident from measured line-line voltage VI
I given in Fig. 11.
I age appears across the capacitor C For a resonant
I For inverters that have a broad-band current
I frequency of 20 kHz and chosen C = 3pF, the
I resonant inductor is calculated as L = 2 1pH The , spectrum, such as those with hysteresis current
I
I
quality factor Q of the tuned L - C branch is , regulators or discrete pulse-width modulated reso-
nant DC link inverters, the switching ripple filter
I around 3000 with R , = 50mQ R , can be either
I an external resistor or equivalent series resistor topology (v) in Fig. 7 provides an effective solu-
I
I ,
(ESR) of inductor L Note that since C < 10 C , , tion. The two parallel branches provide filtering
over two different frequency ranges. The high-pass
I capacitor C does not change the filtering character-
I
I istics of the L i , C ,, R , filter branch The entire ,
filter capacitor C provides filtering within the ac-
I switching frequencyripple current component at 20 tive damping bandwidth or current regulator
I
I kHz therefore flows through the L - C branch , bandwidth of the inverter. The smaller filter capac-
itor C and resistor R , provide damping to supply
I The resistor R, is designed such that it damps any
I and/or load induced resonant frequencies higher
I supply and/or load induced resonances beyond the
I inverter current regulator bandwidth and does not than the inverter current regulator bandwidth. To-
I
require active damping by the inverter pology (v) reduces the design sensitivity of damp-
I
ing resistor R , and associated active filter terminal
I The inverter has a current regulator bandwidth in
I voltage V, distortion concerns.
I excess of 2 1 kHz, since IEEE 519 harmonic limits
I are met up to the 35th harmonic This is validated by
I
I
the experimental results in the next section Conse- Experimental Results
quently, the inverter provides active damping for Experimental results are presented for the parallel
I any supply and/or load induced resonance condi-
I active filter system with the ASD rectifier front-
I tion below 2 1 kHz The damping resistor end operating at an input power of 252 kW The
I R , = 17Q is therefore chosen such that R, < 10 measured supply line-line voltage is 476 V and has
I
I times the impedance of C - L switching ripple a voltage T H D of 2 3%-1 7% of 5th, and 0 7% of
I filter branch above 2 1 kHz, to provide effective
I 7th, harmonic distortion The measured supply
I damping above the inverter current regulator voltage also has a 1.3% negatlve sequence unbal-
I bandwidth This design ofthe damping resistor R, ance. The high percentage of measured negative se-
I
I also ensures that the fundamental current deter- quence supply voltage unbalance demonstrates the
I mined by capacitor C flows through R, and does necessity of the negative sequence SRF controller
I
I not increase the current rating of C and L , for extraction of the fundamental negative se-
I

/E€€ lndusfry ApplicationsMuguzine = September/October 1998

 I
I
I
I
I
I
I
quence component from measured load current. effectiveness ofdesigned switching ripple filter un- I
'Stiff supply conditions, with supply side induc- der 'stiff supply line conditions, supply voltage I
I
tance of L , = 4 0 p H (3.2%) results in a SCR of harmonics, and supply voltage unbalance condi- I
31.0 at PCC. Hence, IE,EE 519 allowable supply tions. The designed switching ripple filter also I
I
current i, T H D is 8.0%. eliminates EM1 currents in the supply and provides I
Figs. 8 and 9 show experimental results of the damping to any possible harmonic interactions be- I
I
parallel active filter harrnonic reference current i; tween the supply, load, and switching ripple filter. I
Fig. 12 shows the supply current spectras before I
tracking by actual current if , overlaid on the same I
and after harmonic compensation by the parallel I
plot. The reference harmonic current i; is ex-
active filter system. The supply current T H D be- I
tracted by the SRF controller previously described. I
fore harmonic compensation is 26.8% and is re- I
The experimental results in Fig. 8 and 9 validate duced to 4.1% after harmonic compensation by the I
I
the desired performance of the proposed predictive
current regulator and its implementation by an an-
alog hardware based spa-cevector modulator. The Tek 2 50MS/s 5 Acqs
IT
saturation problems of the current regulator dur-
ing high dildt rectifier commutation periods (or
Vi voltage notching periods) is evident from the
experimental result in Fig. 9 on an expanded time
scale. Rectifier commutation results in V, voltage
notching; it consequently requires higher inverter
reference voltage magnitude (i.e. magnitude of
Vtzvqd,in Fig. 5 ) for current regulation. A saturation
of the current regulator results from limited in-
verter dc bus voltage V4,cmagnitude and fluctua-
tion of the dc bus voltage between (approximately)
720 V and 685 V. This is due to subharmonic cur-
rents generated in the supply by ASD load at 33
Hz. (The variation in the active filter inverter dc
, bus voltage Vdtripple is shown in Fig. 13.)
Fig. 10 shows the supply current i, (or load cur-
rent i,~)waveform before harmonic compensation, Math3 1.00 V 400us
and the resulting supply current i, waveform after
harmonic compensation by the parallel active filter Fig. 9. Active filter reference current i; { l 00 Aldiv) and actual current i f
system. The supply curr'ent z, ,after compensation, {lo0 Aldiu}, t = 4 0 0 p ldiu , Note expanded time scale to show current
has distortions corresponding to high di'iidt recti- regulator performance.
I
fier commutation periods of 400ps at an input
power of 252 kW. This is due to saturation of the Tek SOOkS/s 27 Acqs
[T 1
current regulator during rectifier commutation
periods, as also shown by experimental results in
Figs. 9 and 10.
is (A)
Fig. 11 shows measured active filter line-line (Before)
terminal voltage V, . V!, is a typical line voltage
notching waveform for diode bridge rectifier front-
ends. The high dvldt instants correspond to recti-
fier commutation notches in the voltageV, and re-
sult in supply current distortion, as shown in Fig.
10. Note that Figs. 10 a.nd 11 are synchronized in
It I
time to show the effect 'of V, voltage notching on
the supply current. To 'demonstrate the effective-
ness of the designed switching ripple filter topol-
ogy in Fig. 7(iv), the active filter terminal line-line
I
voltage V, is measuresd witboat connecting the
switching ripple filter, whereas supply current i,
after compensation in Fig. 10 is measured wich rhc 2.00 V M2.00ms L i n e 1 -105 V
switching ripple filter cmonnected. Hence, Vt volt-
Math3 2.00 V 2.00ms
age has high frequency content in addition to line
voltage notching, whereas supply current i r after Fig. 10. Supply current i {400 Aldiv) before and after harmonic
~

compensation is devoid 'of any high frequency con- Compensation &yparallel active filter system, t = 2 ms I div ;commutation
tent, as shown in Fig. 10. This result validates the notch width t = 4 0 0 p .

w
I

If€€
Industry Applications Magazine I Sepfember/October 1998
 Tek Run: 5OOkS/S H i Res parallel active filter system. The supply current
3
! 1
T H D of 4.1% complies with the worst case allow-
able IEEE 517 T H D limit of 5% for short circuit
ratios less than 20.
Individual supply current harmonic distortions
are given in Fig. 12 along with their IEEE 5 17 har-
monic limits for SCR = 3 1.This result also demon-
strates the high current bandwidth achieved by the
predictive current regulator with charge error con-
trol and implemented by an analog hardware based
space vector PWM modulator. Note that the com-
pensated supply current i, T H D is in the presence
of supply voltage T H D of 2.3%; it also includes
ASD load induced subharmonics at 33 Hz.
The presence of a subharmonic in the supply
current is evident from the measured supply cur-
rent in Fig. 2 and from measured active filter in-
t 1 verter dc bus voltage ripple in Fig. 13. Hence, the
M2.00ms Line% -105V
200mv measured supply current T H D after harmonic
Fig. 11, Active f i l t e r line-line t e r m i n a l voltuge V,. f200 V l d i u ] , t = 2msldiv compensation is under worst case system condi-
u n d commutution notch width t = 400p s. N o t e high frequency content and tions. Note that with the active filter off, the mea-
line notches d u e t o rectifier commututiolz. sured terminal voltage V, T H D is 7.0% (4.0% of
I 5th, 2.2% of7rh, 2.3% of I l t h a n d 2.2% of 13th).
After the active filter is started, the terminal volt-
25.0% age V, T H D is reduced to 2.5% (0.7% of 5th,
0.2% of 7th, 0.6% of 1l t h and 0.6% of 13th). The
V, voltage T H D of 2.5 % is largely due to a back-
%Fund
ground supply voltage distortion of 2.3%. This
demonstrates that other voltage harmonic sensi-
tive loads can be connected at PCC, and the parallel
12.5% active filter system provides a viable solution for
harmonic compensation of voltage harmonic sensi-
tive loads.
Fig. 13 shows the active filter inverter dc bus
voltage variation. Due to the ASD load induced 33
Hz subharmonic component in the supply current,
the dc bus voltage has a 27 H z (60-33 Hz) compo-
0.0%
Fund 5 7 11 13 17 19 23 25 29 31 nent. The peak-peak dc bus voltage ripple in Fig.
Phase A Current Amplitude Spectrum 13 is -approximately 35.0 V. The dc bus voltage
(a) also has a 120 Hz component due to negative se-
quence supply voltage V,unbalance of 1.3%.
2 5%

IEEE 519 Conclusions

% Fund
limit for Adjustable speed ac drives with low input current
SCR = 31
T H D are becoming increasingly important in in-
dustry Although IEEE 519 is a recommended
5th 7.0%
7th 7.0% standard which applies at a plant’s point of com-
1.3% 11th 3.5%
13th 3 5% mon coupling, it is frequently interpreted as being
17th 2.5%
19th 2.5%
equivalent to an equipment standard This is pri-
2316 1.0% marily because there is no other relevant standard
25th 1.0%
29th 1.0% in the US which currently applies to equipment In
31th 1.0%
the higher power ranges (above 1000 hp), it is
quite common to see inverter systems bid with
0.0% high input power factor However, it is not neces-
Fund 5 7 11 13 17 19 23 25 29 31
sarily true at lower drive ratings, where the added
Phase A Current Amplitude Spectrum
cost of the input harmonic correction, and the lack
(b)
of any applicable standard, do not make the issue
Fig. 12. Supply current i I spectra ( a ) before harmonic compensution an important one for the drive end users This is
T H D =26.8% a n d ( 6 ) a f t e r harmonic compensution T H D = 4.1%. Note likely to change as increased integration of inverter
different y-axis scules (percentage hurmonicsj f o r cuses (uj and (b). and motor occurs, and where single point responsi-

m /€E€ Industry ApplicationsMagazine I September/October 1998


bility is accepted by system houses for meeting
overall system performance specifications.
This article has detailed the implementation of
a parallel active filter, which is integrated within a
450 k W adjustable speed drive to provide an over-
all system which conforms to IEEE 5 19,and which
provides significant benefits on a system level. The
design of the active filter is seen to be driven by
overall system specifications which include input
current THD, efficiency, displacement power fac-
tor, a high level of integration with the load con-
verter, and cost targets.
Active filter operation and control has been an-
alyzed at a detailed level, and fundamental issues
relating to current regulator topology and opera-
tion, limits on compensation capability, dc bus
control, switching frequency ripple suppression,
etc., have all been addressed, and have all been
shown to be very important in terms of helping
the system meet its performance objectives. The
overall drive system including the active filter,
meets IEEE 519 by reducing the supply current
T H D from 26.8% without the active filter to
4.1% with the active filter operating. This is
achieved in presence of supply voltage T H D of
2.3% and filter terminal voltage Vf unbalance of
1.3% and, includes an ASD load induced subhar-
monic component at 3.3 Hz. Further, individual
harmonic limits are met up to the 35th harmonic.
This unity power factor 450 k W adjustable speed
ac drive is now in production.
Acknowledgments
This project has been funded by the Electric Power
Research Institute, Pacific Gas & Electric (PG&E)
and York International Corporation. Support from
the Wisconsin Electric Machines and Power Elec-
tronics Consortium (WEMPEC) is also gratefully
acknowledged.
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I
I
I
I
I
I
Tek 1OOkS/s 2 1 ACqS
IT 1
r--
I
t
t 1
M10.0ms Line/ ov
SO.OmV%
Fig. 13. Active filter inverter DC bus voltage ripple (measured with scope
ac coupled) V,, f l 2 Vldiv}, t = l0msldiv.
I
[6] H. Akagi, “New Trends in Active Filters for Power Condi-
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IFF€ lndustry Applicotions Moguzine m September/October 1998
@