Superlattices and Microstructures 77 (2015) 209–218

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Superlattices and Microstructures

journal homepage: www.elsevier.com/locate/superlattices

Effect of thin gate dielectrics and gate materials

on simulated device characteristics of 3D double
gate JNT
A. Baidya, V. Krishnan, S. Baishya, T.R. Lenka ⇑
Department of Electronics and Communication Engineering, National Institute of Technology Silchar, Assam 788010, India

a r t i c l e i n f o a b s t r a c t

Article history: In this paper a novel Silicon based three dimensional (3D) double-
Received 14 August 2014 gate Junctionless Nanowire Transistor (JNT) of 20 nm gate length
Received in revised form 5 November 2014 is proposed. The device characteristics such as gate characteristics
Accepted 11 November 2014
and drain characteristics are studied with the help of Sentaurus
Available online 25 November 2014
TCAD by using different gate materials such as Al, Ti, n+ Polysilicon,
Au and using different ultra thin gate dielectrics such as SiO2, Si3N4
Keywords:
Dielectric
and HfO2. The effect of various work functions and dielectrics on the
JNT threshold voltage of the JNT is also analysed. From the TCAD simu-
MOSFET lation results it is observed that high-K material (HfO2) as gate
Nanowire dielectric shows better drain characteristics with respect to others.
TCAD The JNT with Al as gate material gives better current characteristics
Work function with respect to others. It is also analysed that under flat-band con-
dition the driving of drain current does not directly depend on the
gate-oxide capacitance but depends upon the channel doping con-
centrations. Thus by choosing the proper gate material and gate
dielectric combinations, the desired device characteristics could
be obtained for JNT.
Ó 2014 Elsevier Ltd. All rights reserved.

1. Introduction

The Junctionless Nanowire Transistor (JNT) is a heavily-doped nanowire resistor with a MOS gate,
which controls the flow of current [1]. Its operation principle is similar to MOSFET with the absence of

⇑ Corresponding author.
E-mail address: trlenka@gmail.com (T.R. Lenka).

http://dx.doi.org/10.1016/j.spmi.2014.11.007
0749-6036/Ó 2014 Elsevier Ltd. All rights reserved.
210 A. Baidya et al. / Superlattices and Microstructures 77 (2015) 209–218

source and drain junctions. The concept of Junctionless Nanowire Transistor (JNT) developed at
Tyndall National Institute, Ireland in 2010 [1]. It was the first transistor successfully fabricated with-
out junctions [1–3]. The conventional MOSFETs have junctions and its gate is electrically insulated
from the region where the gate controls. The fabrication of these junctions is difficult and expensive
due to several process steps [4]. These junctions are the significant source of leakage currents leading
to significant power dissipation due to the latch-up problem in CMOS circuits. Therefore elimination of
these problems leads to cheaper and denser microchips [4,5]. In order to overcome the short channel
effects of nanoscale devices, sub-threshold current conduction and leakage currents in MOS transis-
tors, a novel junctionless transistor is proposed in this paper.
The JNT uses a simple nanowire of silicon surrounded by an electrically isolated gate dielectric that
acts to gate the flow of electrons through the wire. The nanowire is heavily n-doped, making it an
excellent conductor. Generally the gate, comprising Silicon, is heavily p-doped; and its presence
depletes the underlying Silicon nanowire by preventing carriers flow across the gate [6–7]. The thresh-
old voltage of JNT is strongly dependent on doping concentration of the nanowire [8]. In this paper a
double gate 3D Junctionless Nanowire Transistor with channel length of 20 nm is proposed and the
authors have investigated the effect of ultra thin gate dielectrics and gate materials on device
characteristics.
The device structure and its physics with operation principle are described in Section 2 followed by
simulation method in Section 3. The results and discussions which include I–V characteristics by vary-
ing gate dielectrics with Al gate electrode and polysilicon gate followed by I–V characteristics by vary-
ing gate materials keeping SiO2 as gate dielectric are discussed in Section 4. The conclusion has been
drawn in Section 5.

2. Device structure and its physics

The Sentaurus TCAD generated 3D structure of the proposed n-channel double gate JNT is shown in
Fig. 1. Unlike the conventional MOSFET there is no source-substrate junction and drain-substrate junc-
tion in the proposed JNT as shown in this figure.
The source, substrate and drain are uniformly n-doped with concentrations of 1.5  1019 cm3.
Here 10 nm thickness of the channel is considered for this device, so that it could be fully depleted
to prevent the current conduction between source and drain and hence the device goes cut-off.
Though the channel is narrow with very heavily n-doped concentrations, enough current could be
obtained out of the device, when it is turned ON. The dimensions of the device are enlisted in Table 1.
In conventional MOS transistor channel is formed on the surface. So they are referred as surface
channel conduction devices, whereas in the proposed JNT, the channel is rather formed in the bulk
of the transistor [9,10]. So it is a bulk channel conduction device. Therefore this device has got several
advantages over MOS transistors and became a promising candidate for future CMOS technology
[8,11,12]. The effect of gate electric field is less at the centre as compared to the surface thereby

Fig. 1. The Sentaurus TCAD generated 3D structure of JNT.

 A. Baidya et al. / Superlattices and Microstructures 77 (2015) 209–218 211

Table 1
Structural parameters of the Junctionless Nanowire Transistor (JNT).

Dimensions Parameters
Gate length 20 nm
Gate width 12 nm
Channel thickness 10 nm
Doping of the channel 1.5  1019 cm3
Oxide thickness 10 Å

contributing less to the scattering effects and hence higher mobility compared to normal MOSFET’s
[13]. The bulk planar JNT is highly scalable due to the absence of source and drain junctions [9].
When the gate voltage is negative, the electrons below (above) the top (bottom) gate start to repel
away and the channel region starts getting depleted. As we go on decreasing the gate voltage, more
regions under the gate start getting depleted and at a particular gate voltage the depletion regions
from the top and bottom side will meet and the source and drain are isolated from each other. Thus,
due to full depletion there is no conduction channel between source and drain and the device goes
cut-off as shown in Fig. 2(a). The process of channel formation is shown in Fig. 2 which is generated
by Sentaurus TCAD.
With the increase of gate voltage from cut-off state, the region at the centre of the channel slowly
comes out of depletion and carriers start to replace the depleted region. As we further increase the
gate voltage, more and more carriers start occupying the channel at centre. At a particular gate voltage
there will be enough number of electrons accumulated at the centre, so as to form a conduction chan-
nel between source and drain. Thus the current starts conducting and the device turns ON. This volt-
age at which the current starts flowing between drain and source is called threshold voltage of the
device, VTh as shown in Fig. 2(b). Now the region between source and drain is partially depleted. As
we go on increasing the voltage above VTh, more and more carriers occupy the channel near the centre
and the width of the conduction region increases as shown in Fig. 2(c)–(d). The current will increase
exponentially with gate voltage. As we increase the gate voltage, at a particular point the whole chan-
nel goes out of depletion and becomes neutral. The gate voltage at which this happens is called the
flat-band voltage (VFB), above which the drain current starts to saturate. At this point, the vertical elec-
tric filed is minimum, as the whole channel is now neutral.

3. Simulation method

The 3D Double Gate Junctionless Nanowire Transistor is simulated using Synopsys TCAD, where its
structure is designed using Sentaurus Structure Editor and 3D meshing of the device is done using Sen-
taurus Mesh tool. The device has been simulated using Sentaurus Device simulator.
The current transport in the device has been modelled by using a drift–diffusion model by solving
self-consistent solution of Poisson and carrier continuity equations. Several models such as Silicon
bandgap narrowing model, recombination models such as Auger, SRH and avalanche are used for
device simulation with mobility models including doping dependence, high-field saturation and trans-
verse field dependence. Further Sentaurus Visual and Inspect tool is used for post processing of output
data and extracted parameters in a data exploration environment.

4. Results and discussions

The effects of different thin dielectrics and different gate electrodes on the characteristics of JNT are
discussed here.

4.1. Varying gate dielectrics with Al gate electrode

In this section, the effects of different dielectrics such as HfO2, Si3N4 and SiO2 on the device char-
acteristics of JNT are presented. Here Al is considered as the gate electrode material. The thickness of
212 A. Baidya et al. / Superlattices and Microstructures 77 (2015) 209–218

Fig. 2. Channel formation process in JNT for different gate voltages. (a) Full depletion in Junctionless Nanowire Transistor at cut-
off state with gate voltage (VG) below threshold voltage (VTh); (b) JNT with gate voltage (VG) equal to threshold voltage (VTh); (c)
JNT with gate voltage (VG) above threshold voltage (VTh); (d) JNT with more increased gate voltage (VG) to get prominent channel.
 A. Baidya et al. / Superlattices and Microstructures 77 (2015) 209–218 213

gate oxide is kept constant instead of fixing Effective Oxide Thickness (EOT), so that the influence of
different dielectrics on device characteristics could be clearly understood. The ID–VGS characteristics of
this device are presented in Fig. 3. From this figure it is observed that the drain ON current is increas-
ing, as we increase the oxide dielectric. This is because as we increase gate dielectric, gate oxide capac-
itance is increasing as given in Eq. (1), which results in an increased charge carriers in the channel and
hence the increased ON current.
o ox A
C ox ¼ ð1Þ
t ox
where Cox is the oxide capacitance, eox is the gate oxide dielectric constant, A is the gate area and tox is
the physical oxide thickness.
It is also observed here that when high-K dielectric oxides are used, threshold voltage seems to
have shown a slight increase in this device. The trapped charges in the oxide will also increase as
we use high-K dielectrics. As the threshold voltage is increased, the OFF state current is less in the case
of high-K dielectrics and hence these devices can be scaled without degradation in sub-threshold per-
formance. It is also seen that the ID–VGS curve is steeper for the case of HfO2. Hence sub-threshold
slope is less in this case, hence improved short channel effects as compared to other MOS transistors.
The first approximation drain current of the JNT under saturation region can be expressed as [3]
1 qlNd W Si T Si 2
IDsat ffi V dsat ð2Þ
2 L
where
 
qN D T Si qN D T Si
V Dsat ¼ V G  V FB  þ ð3Þ
2eSi C ox
Here q is the electronic charge, l is the mobility of electron, Nd is the doping concentration, wSi is
width of the nanowire, TSi is thickness of the nanowire, eSi permittivity of silicon, Cox is the oxide
capacitance, VG is the gate voltage applied and VFB is the flat band voltage.
Using charged based modelling total drain current of junctionless double-gate FET can be written
as [14,15]
Z FB Z D 
W W
ID ¼  l  q  ND  T Si  V DS   l  Q Si  dVjacc þ Q Si  dVjdep ð4Þ
L L S FB

Fig. 3. Gate characteristics of JNT using different dielectric materials (i.e. HfO2, Si3N4 and SiO2) keeping Al as gate electrode.
214 A. Baidya et al. / Superlattices and Microstructures 77 (2015) 209–218

where QSi is charge density in the semiconductor, TSi is thickness of silicon nanowire, L is channel
length and total current is summation of two distinct component i.e. accumulation current and deple-
tion current.
In junctionless transistor, the saturation drain current does not depend directly on the oxide thick-
ness whereas it is proportional to the doping concentration in the nanowire and the doping concen-
trations that used are at the same level in the source and drain regions. Therefore higher speed is
achieved over MOS transistors [3].
The drain characteristics of the JNT with different dielectrics i.e. HfO2, Si3N4 and SiO2 keeping Al as
the gate electrode have been plotted in Fig. 4. The extracted parameters of JNT are enlisted in Table 2.
It is here observed that the ION current and the saturation drain current (IDsat) are maximum when
HfO2 is used as dielectric with respect to Si3N4 and SiO2 dielectrics.

4.2. Varying gate dielectrics with polysilicon gate

In this section the proposed JNT is studied by varying with different gate dielectrics such as HfO2,
Si3N4 and SiO2 keeping polysilicon as gate electrode. The gate characteristics of the device are plotted
in Fig. 5. It is seen that the device characteristics is almost same as that of depicted in Figs. 3 and 4, the
only difference being the shift in the threshold voltage of the device towards positive voltage due to
the higher work function of polysilicon as compared to Al. It is observed from this figure that as we go
on increasing the gate voltage the drain current is linearly increasing until flat band condition is
achieved. However, the drain current in case of HfO2 as dielectric reaches to a maximum of 7 lA at
VGS = 3V, whereas in case of Si3N4 and SiO2 the drain current reaches to 6.5 lA and 6 lA respectively
at the same gate voltage.
The drain characteristics of the JNT with Polysilicon gate with different dielectrics are plotted in
Fig. 6. It is observed here that there is significant increase in drain current when HfO2 is used as

Fig. 4. Drain characteristics of JNT using different dielectric materials (i.e. HfO2, Si3N4 and SiO2).

Table 2
Extracted parameters of JNT using different dielectric materials keeping Al as gate electrode.

Materials Dielectric Threshold voltage (VTh) ION current at VGS = 2 V Drain current (IDsat) at VDS = 2 V
constant (V) (lA) (lA)
HfO2 25 0.5 7.48 29.26
Si3N4 7.5 0.6 6.72 28.95
SiO2 3.9 0.8 6.11 28.66
 A. Baidya et al. / Superlattices and Microstructures 77 (2015) 209–218 215

Fig. 5. Gate characteristics of JNT with polysilicon gate with different dielectrics (i.e. HfO2, Si3N4 and SiO2).

Fig. 6. Drain characteristics of JNT with polysilicon gate with different dielectrics (i.e. HfO2, Si3N4 and SiO2).

dielectric whereas Si3N4 and SiO2 dielectrics also produce nearly same drain current at saturation. The
extracted parameters of the proposed JNT are enlisted in Table 3. It is also observed here that the ION
current at VGS = 2V is more in case of using HfO2 as dielectric with respect to others. The threshold
voltage also increases from 0.5 V to 0.25 V due to high-K material.

4.3. Varying gate materials keeping SiO2 as gate dielectric

In this section the device characteristics of JNT is discussed by keeping gate oxide dielectric as SiO2
and analysed the effects on gate and drain characteristics for different gate materials such as Al, Ti, n+
Poly, and Au. In Fig. 7 it is observed that as the work function of the gate materials decrease, the
threshold voltage also decreases. So for a particular gate voltage, the device with low threshold voltage
will have higher ON current. This is because; the channel must have formed earlier, as VTh is low which
will eventually lead to an enhanced ON current. However, the sub-threshold leakage current, which is
the current flow from source to drain when device is turned OFF, will increase rapidly. Hence short
216 A. Baidya et al. / Superlattices and Microstructures 77 (2015) 209–218

Table 3
Extracted parameters of JNT with polysilicon gate and with different dielectrics (i.e. HfO2, Si3N4 and SiO2).

Materials Dielectric Threshold voltage (VTh) ION current at VGS = 2 V Drain current (IDsat) at VDS = 2 V
constant (V) (lA) (lA)
HfO2 25 0.25 6.71 25.46
Si3N4 7.5 0.3 5.94 25.26
SiO2 3.9 0.5 5.48 25.21

Fig. 7. Gate characteristics of JNT with different gate materials (i.e. Al, Ti, n+ Poly & Au) keeping SiO2 as gate dielectric.

Fig. 8. Drain characteristics of JNT with different gate materials (i.e. Al, Ti, n+ Poly & Au) keeping SiO2 as gate dielectric.

channel effects will come into play and impose constraints on device scaling. As the leakage current
increase it necessitates the need of high static power supply. So by choosing the optimum work func-
tion, we can set the desired threshold voltage of the device and can obtain high ION/IOFF ratio.
Fig. 8 shows the ID–VDS characteristics for different gate electrodes (i.e. Al, Ti, n+ Poly & Au) with
SiO2 as gate dielectric. It is observed from this figure that the drain current is high for low work func-
tion device because the threshold voltage of the device is low and hence the ON current is high. The
 A. Baidya et al. / Superlattices and Microstructures 77 (2015) 209–218 217

Table 4
Extracted parameters of JNT with different gate materials keeping SiO2 as gate dielectric.

Gate Work Threshold voltage (VTh) ION current at VGS = 2 V Drain current (IDsat) at VDS = 2 V
materials function (V) (lA) (lA)
Al 4.28 0.6 6.11 28.66
Ti 4.33 0.4 6.03 28.04
n+ Poly 4.4 0.2 5.94 25.21
Au 5.1 0.4 5.45 18.74

Fig. 9. Threshold voltage of JNT with different gate work functions keeping SiO2 as gate dielectric.

slope of the ID–VDS curve indicates the output conductance of the device. It is also seen from this figure
that the slope is more for low work function device and hence conductance is high for low work func-
tion device.
The extracted parameters of the JNT with different gate materials keeping SiO2 as dielectric are
enlisted in Table 4. It is observed here that the JNT with Al gate material having lowest work function
conducts high ION current and high drain current (IDsat) during saturation. Flat band Voltage (VFB) is a
linear function of gate work function. From two terminal MOS transistor flat band voltage can be writ-
ten as:

Q 0o
V FB ¼ UMS  ð5Þ
C 0ox
where Q 0o is effective interface charges per unit area, C 0ox is total capacitance per unit area between two
end of the oxide and UMS = UM  US, where UM is work function of metal and US is work function of
semiconductor. As gate work function increases VFB also increases which in turn reduces ION and IDsat
current. The observed results are well justified with Eq. (3).
Fig. 9 and Table 4 shows the variation of threshold voltage (VTh) of JNT for different gate materials
used. As the gate work function increases, less amount of negative voltage is required to make the
channel fully depleted which means that the threshold voltage increases. Increase in gate work func-
tion shifts the threshold voltage value from negative to positive. Thus by changing the gate work func-
tion, desired value of threshold voltage can be obtained.

5. Conclusions

The effects of different gate work functions and gate dielectrics on current voltage characteristics of
the JNT are studied for 20 nm gate length. The characteristics of JNT are identical to those of normal
MOSFET. The device is reduced to nanoscale dimensions for improved speed and high packing density.
218 A. Baidya et al. / Superlattices and Microstructures 77 (2015) 209–218

But the electrostatic integrity has been compromised due to the increased short channel effects and
leakage currents. By setting the appropriate threshold voltage, the aforesaid problems can be mini-
mised. Gate work function engineering is a good method to tailor the threshold voltage of the device.
The threshold voltage of the device increases with the increase of gate work function. As the device
dimensions are scaled down to nanoscale regime, the decrease of threshold voltage leads to an
increased sub-threshold current. Therefore by choosing appropriate gate work function threshold
voltage can be set to optimum value, so that the leakage currents can be avoided. The effect of differ-
ent dielectrics on characteristics of JNT is also studied. It is observed that under flat-band condition the
driving of drain current of the JNT does not directly depend on the gate oxide capacitance. So the IDsat
is nearly same for all the dielectrics considered here. The drain current can be increased by increasing
the doping concentration in the channel. Thus by choosing the proper gate material and gate dielectric
combinations, the desired characteristics could be obtained for JNT.

Acknowledgement

The authors acknowledge the Microelectronics Computational Lab of Department of Electronics

and Communication Engineering at National Institute of Technology Silchar, India for providing all
necessary facilities to carry out the research work.

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