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STM32F103x8 STM32F103xB
Performance line, ARM-based 32-bit MCU with Flash, USB, CAN,
seven 16-bit timers, two ADCs and nine communication interfaces
Preliminary Data
Features
■ Core: ARM 32-bit Cortex™-M3 CPU
– 72 MHz, 90 DMIPS with 1.25 DMIPS/MHz
LQFP48 LQFP100 LQFP64 BGA100
– Single-cycle multiplication and hardware 7 x 7 mm 14 x 14 mm 10 x 10 mm 10 x 10 mm
division
– Nested interrupt controller with 43 ■ Debug mode
maskable interrupt channels
– Serial wire debug (SWD) & JTAG interfaces
– Interrupt processing (down to 6 CPU
cycles) with tail chaining ■ Up to 80 fast I/O ports
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 27
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 28
5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 42
5.3.12 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.3.13 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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STM32F103xx Contents
6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.1 Future family enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
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List of tables STM32F103xx
List of tables
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STM32F103xx List of figures
List of figures
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Introduction STM32F103xx
1 Introduction
This datasheet provides the STM32F103xx performance line ordering information and
mechanical device characteristics.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10xxx Flash programming reference manual, pm0042, available
from www.st.com.
For information on the Cortex-M3 core please refer to the Cortex-M3 Technical Reference
Manual.
2 Description
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STM32F103xx Description
SRAM - Kbytes 10 20 10 20 20
Timers
General purpose 2 3 2 3 3
Advanced Control 1 1 1
SPI 1 2 1 2 2
Communication
I2C 1 2 1 2 2
USART 2 3 2 3 3
USB 1 1 1 1 1
CAN 1 1 1 1 1
GPIOs 32 49 80
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Description STM32F103xx
2.2 Overview
ARM® CortexTM-M3 core with embedded Flash and SRAM
The ARM Cortex-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex-M3 32-bit RISC processor features exceptional code-efficiency, delivering
the high-performance expected from an ARM core in the memory size usually associated
with 8- and 16-bit devices.
The STM32F103xx performance line family having an embedded ARM core, is therefore
compatible with all ARM tools and software.
Figure 1 shows the general block diagram of the device family.
Embedded SRAM
Up to 20 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.
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STM32F103xx Description
Boot modes
At startup, boot pins are used to select one of three boot options:
● Boot from User Flash
● Boot from System Memory
● Boot from SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using the USART.
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Description STM32F103xx
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
● MR is used in the nominal regulation mode (Run)
● LPR is used in the Stop modes.
● Power down is used in Standby Mode: the regulator output is in high impedance: the
kernel circuitry is powered-down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby Mode, providing high
impedance output.
Low-power modes
The STM32F103xx performance line supports three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
● Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
● Stop mode
Stop mode allows to achieve the lowest power consumption while retaining the content
of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI
and the HSE RC oscillators are disabled. The voltage regulator can also be put either in
normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB
wakeup.
● Standby mode
The Standby mode allows to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI and the HSE RC oscillators are also switched off. After entering Standby
mode, SRAM and registers content are lost except for registers in the Backup domain
and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general purpose and
advanced control timers TIMx and ADC.
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STM32F103xx Description
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free running timer for application time out
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
This timer is dedicated for OS, but could also be used as a standard down counter. It
features:
● A 24-bit down counter
● Autoreload capability
● Maskable system interrupt generation when the counter reaches 0.
● Programmable clock source
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Description STM32F103xx
I²C bus
Up to two I²C bus interfaces can operate in multi-master and slave modes. They can support
standard and fast modes.
They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master
mode. A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SM Bus 2.0/PM Bus.
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STM32F103xx Description
Temperature sensor
The temperature sensor has to generate a linear voltage with any variation in temperature.
The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally
connected to the ADC_IN16 input channel which is used to convert the sensor output
voltage into a digital value.
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Description STM32F103xx
Trace
JTAG & SWD pbus POWER
Controller
VDD = 2 to 3.6V
JNTRST VOLT. REG.
VSS
flash obl
JTDI CORTEX M3 CPU Ibus 3.3V TO 1.8V
Interface
FLASH 128 KB
JTCK/SWCLK
JTMS/SWDIO 64 bit @VDD
JTDO Fmax: 72 MHz Dbus
as AF
BusMatrix
SRAM
NVIC System
20 KB @VDD
PCLK1 OSC_IN
GP DMA PCLK2 PLL & XTAL OSC OSC_OUT
CLOCK 4-16 MHz
7 channels HCLK MANAGT
AHB:Fmax=48/72 MHz
FCLK
RC 8 MHz
IWDG
RC 32 kHz
@VDDA
Standby
@VDDA interface
SUPPLY VBAT
NRST SUPERVISION
@VBAT
VDDA POR / PDR Rst OSC32_IN
VSSA XTAL 32 kHz
AHB2 AHB2 OSC32_OUT
PVD Int
APB2 APB1 Backup
RTC ANTI_TAMP
reg
EXTI AWU
80AF
WAKEUP Backup interface
PA[15:0] GPIOA
TIM2 4 Channels
PB[15:0] GPIOB
TIM3 4 Channels
PC[15:0] GPIOC
APB1 : Fmax=24 / 36 MHz TIM 4 8 Channels
PD[15:0] GPIOD
RX,TX, CTS, RTS,
USART2
APB2 : Fmax=48 / 72 MHz
SmartCard as AF
PE[15:0] GPIOE
RX,TX, CTS, RTS,
USART3
SmartCard as AF
2x(8x16bit)SPI2
MOSI,MISO,SCK,NSS
4 Channels as AF
3 compl. Channels
TIM1
Brk input I2C1 SCL,SDA,SMBAL
MOSI,MISO, as AF
SCK,NSS as AF SPI1
I2C2 SCL,SDA
as AF
RX,TX, CTS, RTS,
SmartCard as AF USART1 bxCAN
USBDP/CANTX
@VDDA USBDM/CANRX
USB 2.0 FS
16AF 12bit ADC1 IF
VREF+
SRAM 512B
VREF- 12bit ADC2 IF
WWDG
Temp sensor
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STM32F103xx Pin descriptions
3 Pin descriptions
BOOT0
VDD_3
VSS_3
PC12
PC11
PC10
PA15
PA14
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD_2
PE3 2 74 VSS_2
PE4 3 73 NC
PE5 4 72 PA 13
PE6 5 71 PA 12
VBAT 6 70 PA 11
PC13-ANTI_TAMP 7 69 PA 10
PC14-OSC32_IN 8 68 PA 9
PC15-OSC32_OUT 9 67 PA 8
VSS_5 10 66 PC9
VDD_5 11 65 PC8
OSC_IN 12 64 PC7
OSC_OUT 13 LQFP100 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
VSSA 19 57 PD10
VREF- 20 56 PD9
VREF+ 21 55 PD8
VDDA 22 54 PB15
PA0-WKUP 23 53 PB14
PA1 24 52 PB13
PA2 25 51 PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PA3
VSS_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
VDD_4
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS_1
VDD_1
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Pin descriptions STM32F103xx
BOOT0
VDD_3
VSS_3
PC12
PC11
PC10
PA15
PA14
PD2
PB9
PB8
PB7
PB6
PB5
PB4
PB3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VBAT 1 48 VDD_2
PC13-ANTI_TAMP 2 47 VSS_2
PC14-OSC32_IN 3 46 PA13
PC15-OSC32_OUT 4 45 PA12
PD0 OSC_IN 5 44 PA11
PD1 OSC_OUT 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
PC1 9 LQFP64 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA 12 37 PC6
VDDA 13 36 PB15
PA0-WKUP 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PA3
VSS_4
PC5
VDD_4
PA4
PA5
PA6
PA7
PC4
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
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PA15
PA14
PB9
PB8
PB7
PB6
PB5
PB4
PB3
48 47 46 45 44 43 42 41 40 39 38 37
VBAT 1 36 VDD_2
PC13-ANTI_TAMP 2 35 VSS_2
PC14-OSC32_IN 3 34 PA13
PC15-OSC32_OUT 4 33 PA12
PD0 OSC_IN 5 32 PA11
PD1 OSC_OUT 6 LQFP48 31 PA10
NRST 7 30 PA9
VSSA 8 29 PA8
VDDA 9 28 PB15
PA0-WKUP 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13 14 15 16 17 18 19 20 21 22 23 24
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
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STM32F103xx Pin descriptions
PC14- PC13-
A OSC32_IN ANTI_TAMP PE2 PB9 PB7 PB4 PB3 PA15 PA14 APA13
PC15-
B OSC32_OUT VBAT PE3 PB8 PB6 PD5 PD2 PC11 PC10 PA12
C OSC_IN VSS_5 PE4 PE1 PB5 PD6 PD3 PC12 PA9 PA11
D OSC_OUT VDD_5 PE5 PE0 BOOT0 PD7 PD4 PD0 PA8 PA10
E NRST PCD PE6 VSS_4 VSS_3 VSS_2 VSS_1 PD1 PC9 PC7
G VSSA PA0-WKUP PA4 PC4 PB2 PE10 PE14 PB15 PD11 PD15
H VREF– PA1 PA5 PC5 PE7 PE11 PE15 PB14 PD10 PD14
J VREF+ PA2 PA6 PB0 PE8 PE12 PB10 PB13 PD9 PD13
K VDDA PA3 PA7 PB1 PE9 PE13 PB11 PB12 PD8 PD12
AI16001
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Pin descriptions STM32F103xx
I / O Level(2)
Pins
Type(1)
Main function(3)
LQFP100
BGA100
LQFP48
LQFP64
Pin name Default alternate functions
(after reset)
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STM32F103xx Pin descriptions
I / O Level(2)
Pins
Type(1)
Main function(3)
LQFP100
BGA100
LQFP48
LQFP64
Pin name Default alternate functions
(after reset)
PA4/SPI1_NSS/ SPI1_NSS(6)/
G3 14 20 29 I/O PA4
USART2_CK/ADC_IN4 USART2_CK(6)/ ADC_IN4
H3 15 21 30 PA5/SPI1_SCK/ ADC_IN5 I/O PA5 SPI1_SCK(6)/ ADC_IN5
PA6/SPI1_MISO/ SPI1_MISO(6)/
J3 16 22 31 I/O PA6
ADC_IN6/TIM3_CH1 ADC_IN6/TIM3_CH1(6)
PA7/SPI1_MOSI/ SPI1_MOSI(6)/
K3 17 23 32 I/O PA7
ADC_IN7/TIM3_CH2 ADC_IN7/TIM3_CH2(6)
G4 - 24 33 PC4/ADC_IN14 I/O PC4 ADC_IN14
H4 - 25 34 PC5/ADC_IN15 I/O PC5 ADC_IN15
J4 18 26 35 PB0/ADC_IN8/ TIM3_CH3 I/O PB0 ADC_IN8/TIM3_CH3(6)
K4 19 27 36 PB1/ADC_IN9/ TIM3_CH4 I/O PB1 ADC_IN9/TIM3_CH4(6)
G5 20 28 37 PB2 / BOOT1 I/O FT PB2/BOOT1
H5 - - 38 PE7 I/O FT PE7
J5 - - 39 PE8 I/O FT PE8
K5 - - 40 PE9 I/O FT PE9
G6 - - 41 PE10 I/O FT PE10
H6 - - 42 PE11 I/O FT PE11
J6 - - 43 PE12 I/O FT PE12
K6 - - 44 PE13 I/O FT PE13
G7 - - 45 PE14 I/O FT PE14
H7 - - 46 PE15 I/O FT PE15
PB10/I2C2_SCL/
J7 21 29 47 I/O FT PB10 I2C2_SCL/USART3_TX(5)(6)
USART3_TX
PB11/I2C2_SDA / I2C2_SDA/
K7 22 30 48 I/O FT PB11
USART3_RX USART3_RX(5)(6)
E7 23 31 49 VSS_1 S VSS_1
F7 24 32 50 VDD_1 S VDD_1
SPI2_NSS(5)
PB12/SPI2_NSS /
/I2C2_SMBAl(5)/
K8 25 33 51 I2C2_SMBAl/ USART3_CK / I/O FT PB12
USART3_CK(5)(6)/
TIM1_BKIN
TIM1_BKIN(6)
PB13/SPI2_SCK / SPI2_SCK(5)/
J8 26 34 52 USART3_CTS / I/O FT PB13 USART3_CTS(5)(6)/
TIM1_CH1N TIM1_CH1N (6)
PB14/SPI2_MISO / SPI2_MISO(5)
H8 27 35 53 USART3_RTS / I/O FT PB14 /USART3_RTS(5)(6)
TIM1_CH2N TIM1_CH2N (6)
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Pin descriptions STM32F103xx
I / O Level(2)
Pins
Type(1)
Main function(3)
LQFP100
BGA100
LQFP48
LQFP64
Pin name Default alternate functions
(after reset)
PB15/SPI2_MOSI SPI2_MOSI(5)/
G8 28 36 54 I/O FT PB15
TIM1_CH3N TIM1_CH3N(6)
K9 - - 55 PD8 I/O FT PD8
J9 - - 56 PD9 I/O FT PD9
H9 - - 57 PD10 I/O FT PD10
G9 - - 58 PD11 I/O FT PD11
K10 - - 59 PD12 I/O FT PD12
J10 - - 60 PD13 I/O FT PD13
H10 - - 61 PD14 I/O FT PD14
G10 - - 62 PD15 I/O FT PD15
F10 - 37 63 PC6 I/O FT PC6
E10 38 64 PC7 I/O FT PC7
F9 39 65 PC8 I/O FT PC8
E9 - 40 66 PC9 I/O FT PC9
PA8/USART1_CK/ USART1_CK/
D9 29 41 67 I/O FT PA8
TIM1_CH1/MCO TIM1_CH1(6)/MCO
PA9/USART1_TX/ USART1_TX(6)/
C9 30 42 68 I/O FT PA9
TIM1_CH2 TIM1_CH2(6)
PA10/USART1_RX/ USART1_RX(6)/
D10 31 43 69 I/O FT PA10
TIM1_CH3 TIM1_CH3(6)
PA11 / USART1_CTS/ USART1_CTS/
C10 32 44 70 CANRX / USBDM/ I/O FT PA11 CANRX(6)/
TIM1_CH4 TIM1_CH4(6) / USBDM
PA12 / USART1_RTS/ USART1_RTS/
B10 33 45 71 CANTX / USBDP/ I/O FT PA12 CANTX(6) /
TIM1_ETR TIM1_ETR(6) / USBDP
A10 34 46 72 PA13/JTMS/SWDIO I/O FT JTMS/SWDIO PA13
F8 - - 73 Not connected
E6 35 47 74 VSS_2 S VSS_2
F6 36 48 75 VDD_2 S VDD_2
A9 37 49 76 PA14/JTCK/SWCLK I/O FT JTCK/SWCLK PA14
A8 38 50 77 PA15/JTDI I/O FT JTDI PA15
B9 - 51 78 PC10 I/O FT PC10
B8 - 52 79 PC11 I/O FT PC11
C8 - 53 80 PC12 I/O FT PC12
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STM32F103xx Pin descriptions
I / O Level(2)
Pins
Type(1)
Main function(3)
LQFP100
BGA100
LQFP48
LQFP64
Pin name Default alternate functions
(after reset)
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Memory mapping STM32F103xx
4 Memory mapping
The memory map is shown in Figure 6.
reserved 1 Kbit
6 0x4001 3C00
USART1 1 Kbit
0x4001 3800
0xC000 0000 reserved 1 Kbit
0x4001 3400
SPI1 1 Kbit
0x4001 3000
TIM1 1 Kbit
0x4001 2C00
5 ADC2 1 Kbit
0x4001 2800
ADC1 1 Kbit
0x4001 2400
0xA000 0000
reserved 2 Kbits
0x4001 1C00
Port E 1 Kbit
4 0x1FFF FFFF 0x4001 1800
reserved Port D 1 Kbit
0x1FFF F9FF 0x4001 1400
Port C 1 Kbit
0x8000 0000 OPTION BYTES 0x4001 1000
Port B 1 Kbit
0x1FFF F800 0x4001 0C00
Port A 1 Kbit
0x4001 0800
3 EXTI 1 Kbit
SYSTEM MEMORY 0x4001 0400
AFIO 1 Kbit
0x4001 0000
0x1FFF F000
0x6000 0000 reserved 35 Kbits
0x4000 7400
PWR 1 Kbit
0x4000 7000
2 BKP 1 Kbit
0x4000 6C00
reserved 1 Kbit
reserved 0x4000 6800
PERIPHERALS bxCAN
0x4000 0000 1 Kbit
0x4000 6400
shared 512 byte 1 Kbit
0x4000 6000 USB/CAN SRAM
USB Registers 1 Kbit
0x4000 5C00
1 I2C2 1 Kbit
0x4000 5800
I2C1 1 Kbit
SRAM 0x4000 5400
0x2000 0000
reserved 7 Kbits
0x4000 0C00
TIM4 1 Kbit
0x4000 0800
TIM3 1 Kbit
0x4000 0400
TIM2 1 Kbit
0x4000 0000
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STM32F103xx Electrical characteristics
5 Electrical characteristics
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Electrical characteristics STM32F103xx
STM32F103xx pin
STM32F103xx pin
C = 50 pF
VIN
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VBAT 3.3 V
Backup circuitry
Po wer swi tch (OSC32K,RTC,
1.8-3.6 V
Wake-up logic
Backup registers)
Level shifter
OUT
IO
GP I/Os Logic
IN Kernel logic
(CPU,
Digital
VDD
VDD & Memories)
1/2/3/4/5 Regulator
5 × 100 nF VSS
+ 1 × 10 µF 1/2/3/4/5
3.3V
VDD
VDDA
VREF
VREF+
10 nF Analog:
10 nF VREF- ADC
+ 1 µF RCs, PLL,
+ 1 µF
...
VSSA
ai14125
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STM32F103xx Electrical characteristics
IDD_VBAT
VBAT
IDD
VDD
VDDA
ai14126
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Electrical characteristics STM32F103xx
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STM32F103xx Electrical characteristics
20 µs/V
tVDD VDD rise/fall time rate
20 ms/V
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Electrical characteristics STM32F103xx
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STM32F103xx Electrical characteristics
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Electrical characteristics STM32F103xx
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STM32F103xx Electrical characteristics
72 MHz 21
Oscillator running at 8 MHz with PLL, code 48 MHz 18
running from Flash, all peripheral disabled
36 MHz TBD mA
(see RCC register description): fPCLK1=
fHCLK/2, fPCLK2=fHCLK 24 MHz 13
16 MHz TBD
8 MHz 7.8
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Electrical characteristics STM32F103xx
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STM32F103xx Electrical characteristics
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Electrical characteristics STM32F103xx
VHSEH
90%
10%
VHSEL
tr(HSE) tW(HSE) t
tf(HSE) tW(HSE)
THSE
ai14143
VLSEH
90%
10%
VLSEL
tr(LSE) tW(LSE) t
tf(LSE) tW(LSE)
TLSE
ai14144b
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STM32F103xx Electrical characteristics
Resonator with
integrated capacitors
CL1
OSC_IN fHSE
Bias
8 MH z controlled
RF
resonator gain
OSC_OU T STM32F103xx
REXT(1)
CL2
ai14145
1. REXT value depends on the crystal characteristics. Typical value is in the range of 5 to 6RS.
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Electrical characteristics STM32F103xx
RF Feedback resistor 5 MΩ
Recommended load capacitance
CL1
versus equivalent serial RS = 30 kΩ 15 pF
CL2
resistance of the crystal (RS)(1)
VDD = 3.3 V
I2 LSE driving current 1.4 µA
VIN = VSS
gm Oscillator Transconductance 5 µA/V
tSU(LSE)(2) startup time VSS is stabilized 3 s
1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details
2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768
kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer
Resonator with
integrated capacitors
CL1
OSC32_IN fLSE
Bias
32.768 kH z RF controlled
resonator gain
OSC32_OU T STM32F103xx
CL2
ai14146
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STM32F103xx Electrical characteristics
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Electrical characteristics STM32F103xx
tWUSLEEP(2) Wakeup from Sleep mode Wakeup on HSI RC clock 0.75 TBD µs
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STM32F103xx Electrical characteristics
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Electrical characteristics STM32F103xx
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STM32F103xx Electrical characteristics
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
0.1 to 30 MHz 12 12
VDD = 3.3 V, TA = 2 5 °C,
LQFP100 package 30 to 130 MHz 22 19 dBµV
SEMI Peak level
compliant with SAE J 130 MHz to 1GHz 23 29
1752/3
SAE EMI Level 4 4 -
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Electrical characteristics STM32F103xx
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
● A supply overvoltage is applied to each power supply pin
● A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
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STM32F103xx Electrical characteristics
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Electrical characteristics STM32F103xx
1 0 kΩ
STM32F103xx
STM32F103xx
1 0 kΩ
ai14147b
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STM32F103xx Electrical characteristics
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Electrical characteristics STM32F103xx
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 16 and
Table 31, respectively.
Unless otherwise specified, the parameters given in Table 31 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 7.
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STM32F103xx Electrical characteristics
90% 10%
50% 50%
10% 90%
Maximum frequency is achieved if (tr + tf) £ 2/3)T and if the duty cycle is (45-55%)
when loaded by 50pF
ai14131
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Electrical characteristics STM32F103xx
VDD
External
reset circuit
RPU Internal Reset
NRST
FILTER
0.1 µF
STM32F101xx
ai14132b
1 tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 72 MHz 13.9 ns
0 fTIMxCLK/2 MHz
Timer external clock
fEXT
frequency on CH1 to CH4 f
TIMxCLK = 72 MHz 0 36 MHz
ResTIM Timer resolution 16 bit
16-bit counter clock period 1 65536 tTIMxCLK
tCOUNTER when internal clock is
selected fTIMxCLK = 72 MHz 0.0139 910 µs
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STM32F103xx Electrical characteristics
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Electrical characteristics STM32F103xx
VDD VDD
4 .7 kΩ 4 .7 kΩ STM32F103xx
100Ω
SDA
I2C bus 100Ω
SCL
S TART REPEATED
S TART
tsu(STA) S TART
SDA
tf(SDA) tr(SDA) tsu(SDA)
S TOP tsu(STA:STO)
th(STA) tw(SCKL) th(SDA)
SCL
tw(SCKH) tr(SCK) tf(SCK) tsu(STO)
ai14149b
400 TBD
300 TBD
200 TBD
100 TBD
50 TBD
20 TBD
1. TBD = to be determined.
2. RP = External pull-up resistance, fSCL = I2C speed,
3. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external
components used to design the application.
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STM32F103xx Electrical characteristics
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Electrical characteristics STM32F103xx
NSS input
tSU(NSS) tc(SCK) th(NSS)
CPHA= 0
SCK Input
CPOL=0
tw(SCKH)
CPHA= 0 tw(SCKL)
CPOL=1
Figure 20. SPI timing diagram - slave mode and CPHA = 11)
NSS input
tSU(NSS) tc(SCK) th(NSS)
CPHA=1
SCK Input
CPOL=0
tw(SCKH)
CPHA=1 tw(SCKL)
CPOL=1
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STM32F103xx Electrical characteristics
High
NSS input
tc(SCK)
CPHA= 0
SCK Input
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
SCK Input
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INP UT MS BIN BI T6 IN LSB IN
th(MI)
MOSI
M SB OUT B I T1 OUT LSB OUT
OUTUT
tv(MO) th(MO)
ai14136
USB characteristics
The USB interface is USB-IF certified (Full Speed).
Input levels
Output levels
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Electrical characteristics STM32F103xx
Figure 22. USB timings: definition of data signal rise and fall time
Crossover
points
Differen tial
Data L ines
VCRS
VS S
tf tr
ai14137
Driver characteristics
tr Rise time(1) CL = 50 pF 4 20 ns
tf Fall Time(1) CL = 50 pF 4 20 ns
trfm Rise/ fall time matching tr/tf 90 110 %
VCRS Output signal crossover voltage 1.3 2.0 V
1. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
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STM32F103xx Electrical characteristics
Table 40. ADC accuracy (fPCLK2 = 14 MHz, fADC = 14 MHz, RAIN <10 kΩ, VDDA =
3.3 V)(1)
Symbol Parameter Conditions Typ Max Unit
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Electrical characteristics STM32F103xx
EG
(1) Example of an actual transfer curve
1023
(2) The ideal transfer curve
1022 V –V (3) End point correlation line
DDA SSA
1LSB = -----------------------------------------
1021 IDEAL 1024
(2)
ET=Total Unadjusted Error: maximum deviation
ET between the actual and the ideal transfer curves.
7 (3) EO=Offset Error: deviation between the first actual
(1) transition and the first ideal one.
6
EG=Gain Error: deviation between the last ideal
5 transition and the last actual one.
EO EL ED=Differential Linearity Error: maximum deviation
4 between actual steps and the ideal one.
3 EL=Integral Linearity Error: maximum deviation
ED between any actual transition and the end point
2 correlation line.
1 LSBIDEAL
1
0
1 2 3 4 5 6 7 1021 1022 1023 1024
VSSA VDDA ai14395
VDD STM32F103xx
VT
0.6V
RAIN AINx RADC
12-bit A/D
conversion
VT
VAIN CAIN(1) 0.6V IL±1mA CADC
ai14150
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STM32F103xx Electrical characteristics
Figure 25. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32F103xx
VREF+
(see note 1)
1 µF // 10 nF VDDA
1 µF // 10 nF
VSSA /VREF+
(see note 1)
ai14388
Figure 26. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32F103xx
VREF+/VDDA
(See note 1)
1 µF // 10 nF
VREF–/VSSA
(See note 1)
ai14389
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Electrical characteristics STM32F103xx
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STM32F103xx Package characteristics
6 Package characteristics
Figure 27. LFBGA100 - low profile fine pitch ball grid array package outline
Seating plane
C
ddd C
A2 A4 A3 A1 A
D
B
D1
e F A
K
J F
H
G
F E1 E
E
D
C e
B
A
1 2 3 4 5 6 7 8 9 10
Table 42. LFBGA100 - low profile fine pitch ball grid array package mechanical data
mm inches
Dim.
Min Typ Max Min Typ Max
A 1.700 0.067
A1 0.270 0.011
A2 1.085 0.043
A3 0.30 0.012
A4 0.80 0.031
b 0.45 0.50 0.55 0.018 0.020 0.022
D 9.85 10.00 10.15 0.388 0.394 0.40
D1 7.20 0.283
E 9.85 10.00 10.15 0.388 0.394 0.40
E1 7.20 0.283
e 0.80 0.031
F 1.40 0.055
ddd 0.12 0.005
eee 0.15 0.006
fff 0.08 0.003
N (number of balls) 100
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Package characteristics STM32F103xx
Dpad 0.37 mm
0.52 mm typ. (depends on solder
Dsm
mask registration tolerance
Solder paste 0.37 mm aperture diameter
– Non solder mask defined pads are recommended
– 4 to 6 mils screen print
Dpad
Dsm
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STM32F103xx Package characteristics
A1
E1 E
c
L1
L
h
ai14397
Table 43. LQFP100 – 100-pin low-profile quad flat package mechanical data
mm inches
Dim.
Min Typ Max Min Typ Max
A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
b 0.17 0.22 0.27 0.007 0.009 0.011
C 0.09 0.20 0.004 0.008
D 16.00 0.630
D1 14.00 0.551
E 16.00 0.630
E1 14.00 0.551
e 0.50 0.020
θ 0° 3.5° 7° 0° 3.5° 7°
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 0.039
Number of pins
N 100
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Package characteristics STM32F103xx
A1
E1 E
e
c
L1
L
ai14398
Table 44. LQFP64 – 64 pin low-profile quad flat package mechanical data
mm inches
Dim.
Min Typ Max Min Typ Max
A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
b 0.17 0.22 0.27 0.007 0.009 0.011
c 0.09 0.20 0.004 0.008
D 12.00 0.472
D1 10.00 0.394
E 12.00 0.472
E1 10.00 0.394
e 0.50 0.020
θ 0° 3.5° 7° 0° 3.5° 7°
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 0.039
Number of pins
N 64
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STM32F103xx Package characteristics
D A
D1 A2
A1
E1 E e
c
L1
L
ai14399
Table 45. LQFP48 – 48 pin low-profile quad flat package mechanical data
mm inches(1)
Dim.
Min Typ Max Min Typ Max
A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
b 0.17 0.22 0.27 0.007 0.009 0.011
C 0.09 0.20 0.004 0.008
D 9.00 0.354
D1 7.00 0.276
E 9.00 0.354
E1 7.00 0.276
e 0.50 0.020
θ 0° 3.5° 7° 0° 3.5° 7°
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 0.039
Number of pins
N 48
1. Values in inches are converted from mm and rounded to 3 decimal digits.
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Package characteristics STM32F103xx
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STM32F103xx Order codes
7 Order codes
STM32F103C6T6 32 10
LQFP48
STM32F103C8T6 64 20
STM32F103R6T6 32 10
STM32F103R8T6 64 20 LQFP64
STM32F103RBT6 128 20
STM32F103V8T6 64 20
LQFP100
STM32F103VBT6 128 20
STM32F103V8H6 64 20
LFBGA100
STM32F103VBH6 128 20
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Revision history STM32F103xx
8 Revision history
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STM32F103xx
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