Proceedings of the National Power Systems Conference (NPSC) - 2018, December 14-16, NIT Tiruchirappalli, India

Dynamic Overcurrent Saturation of Distributed

Sources in a DC Microgrid System
Debasish Dhua, A. B. Shyam, Sandeep Anand and Soumya Ranjan Sahoo
Department of Electrical Engineering, Indian Institute of Technology Kanpur, India
debasish.dhua@gmail.com, shyam.ab33@gmail.com, me.sandeepanand@gmail.com, srsahoo@iitk.ac.in

Abstract—Due to the advancement of microgrids, the electrical

distribution network is transforming rapidly. The close proximity
of distributed generations, loads and widespread use of power
electronic converters have brought enormous flexibility and
controllability to the distribution system. The transient studies of
dc microgrid need more attention to ensure stable and reliable
operation of the converters. One of the important phenomena is
overloading of a source converter during a large load transient.
The source current may increase due to the large increase in load
connected to its proximity. Conventionally this issue is addressed
by using a static current limit, which protects the converters.
However, this leads to significant disturbances in the system,
especially when this converter recovers from saturation due to
other converters sharing the load. A suitable dynamic over-
current saturation technique, proposed in this paper is advanta-
geous over the existing constant current saturation method. This
paper shows a detailed procedure of determining the dynamic
current limit and its implementation in the controller in line with
the device manufacturers’ guidelines for the enhanced operating
condition in dc microgrid.
Index Terms—anti-winding, boost converter, current limit, dc
microgrid, dynamic saturation, overcurrent control
I. I NTRODUCTION
With the growing interest in Distributed Generation (DG)
using of the microgrid, the power electronic converter topolo-
gies and their control techniques are rapidly evolving. Re-
cently, the dc distribution system is gaining popularity because
of its simplicity, less number of conversion stages, the absence
of reactive power and harmonics, enhanced use of modern
dc loads. [1]. A typical dc microgrid which is shown in Fig.
1 consists of multiple DGs, energy storage units and loads
connected to the same dc bus. It possesses the flexibility to be
operated in grid-connected mode or islanded mode. In case of
grid-connected mode, the grid interacts with the dc bus through
an interfacing bidirectional converter. In dc microgrids, the
DGs inject power into the distribution network through power
electronic converters having multiple control layers: primary,
secondary and tertiary. The control of dc/dc power converters
under different operating conditions is receiving significant
attention. [2]–[4].
A common practice to deal with the controlled parameter
when it exceeds a preset value is to use a constant saturation.
The immediate effect of introducing the saturation under
large-signal disturbances is integrator windup which causes
additional issues into the system like the sluggish response,
oscillations in the system. Some of the accepted anti-winding
978-1-5386-6159-8/18/$31.00 © 2018 IEEE
Fig. 1. A generic representation of dc microgrid.
methods are recommended in [5] which mostly require under-
standing the response of the system and suitable tuning of the
controller. Although the concept of saturating the uncontrolled
system output is not new, the choice of saturation margin is
not distinctly elaborated in the existing literature.
To tackle the problem related to large load disturbances
across a converter, multiple control strategies have been in-
troduced in [6]–[8] which include load current feed-forward
compensation and hysteric current mode control. The limita-
tion of these analog control methods mostly lies in large com-
ponent size, parameter modification, and complex calculation
procedure. In [9], [10] two separate digital control techniques
have been discussed for steady-state and transient responses
which improve the dynamic response of the system at the
cost of higher settling time. To protect the dc/dc converters
in transients under the complex dynamics of modern loads,
nonlinear control [11], [12] and robust control [13]–[15]
techniques are discussed. However, to estimate the controller
operation most of the developed control techniques require
the knowledge of load which changes during operation and
that may enhance the non-linearities and number of system
states. Therefore, a component independent and simple control
algorithm is essential to address the transient issues related to
large load disturbances across a converter. The desired control
technique should also possess the ability to limit the current
independent of the load fluctuations.
Under large load disturbances closer to one of the sources,
its output current may exceed the preset current limit which
may damage the power electronic devices (PEDs). Therefore,
it is mandatory to specify the current limit considering the
 Proceedings of the National Power Systems Conference (NPSC) - 2018, December 14-16, NIT Tiruchirappalli, India
Fig. 2. Diagram of a boost converters
recommended safe operating region of the device. Hence,
dynamic current saturation is the most optimum solution to
support the system while protecting the PED of the individual
converters. Dynamic saturation methods have been incorpo-
rated in [16]–[18]; which have only considered the stability
aspect of the system, instead of directly considering the device
current carrying capabilities. The primary objective of this pa-
per is to introduce the dynamic saturation limit maintaining the
thermal capacity limit of the power semiconductor devices and
bringing up the coordination between the parallel connected
dc microgrid source converters.
This paper is organized as follows: section II details with the
thermal characteristics and Safe-Operating-Area (SOA) of the
power semiconductor device. Section III depicts the proposed
dynamic saturation scheme. Section IV elaborates the anti-
winding method adopted in this paper. Section V includes
the simulation results and subsequent discussions. Section VI
concludes the paper.
II. T HERMAL C HARACTERISTICS OF MOSFET AND SOA
S ELECTION
In a dc/dc converter, for example, boost converter as shown
in Fig. 2, the output capacitor voltage drops abruptly when
there is a sudden increase in load demand. To maintain the
capacitor voltage, the inductor current increases so as to
draw more power from the input side. Therefore, the power
electronic device is made to carry a larger current under
transient high load demands.
The thermal characteristics of MOSFET under over-current
condition can be correctly estimated from the manufacturers’
datasheet [19]. Under ideal heat dissipation environment, the
current passing through the MOSFET can be broadly classified
into two categories, continuous dc current which is considered
for a duration of more than 10 seconds and pulsed current
which is regarded for the device ON duration of 1 second or
less. The maximum possible current values can be determined
from the maximum dissipated power as given below so that
the device channel temperature does not exceed its thermal
limit.
Tch (max) − Tc
PD = (1)
R(ch−c)
Tch (max) − Tc
PDP = (2)
r(ch−c) (t)
Fig. 3. Normalized data and mean plot derived from the MOSFET datasheets
and s
PD
ID = (3)
RDS(on) (max)
s
PDP
IDP = (4)
RDS(on) (max)
where, ID is the maximum dc current, IDP is the maximum
pulsed currents, PD is the maximum continuous dissipated
power, PDP are the maximum pulsed dissipated power in
the MOSFET. Tch(max) is the maximum channel tempera-
ture, TC is the case temperature, Rth(ch−c) is the steady-
state thermal resistance, rth(ch−c) (t) is the transient thermal
resistance which is a function of the pulse width, RDS(on) is
the maximum drain-source on-state resistance at the maximum
channel temperature. Values of all the above parameters are
directly available in the data-sheet except rth(ch−c) (t) which is
a function of time and is affected by the thermal capacitance of
the device. Therefore, the calculation of the IDP vs tw which
can be implemented for the thermal protection of the device
in overcurrent condition involves the following steps,
• Step I: Determine rth(ch−c) (t) from rth(ch−c) /Rth(ch−c)
vs tw plot from datasheet using the available information
of Rth(ch−c) . Since in this case, the MOSFET is consid-
ered for extended exposures to overcurrent condition, tw
is taken for single pulse with pulse duration starting from
10 µsec to 10 s.
• Step II: Calculate IDP vs tw using (2) and (4).
• Step III: Normalize the individual plots obtained from
different datasheets with corresponding MOSFET rated
currents.
After plotting the individual normalized data for IDP vs
tw obtained from different data-sheets [20]–[26] of different
manufacturers, the mean plot is derived by calculating the
mean of the data points corresponding to each specified pulse
duration, as shown in Fig. 3. By using the basic curve fitting
 Proceedings of the National Power Systems Conference (NPSC) - 2018, December 14-16, NIT Tiruchirappalli, India
Fig. 4. A typical MOSFET SOA plot with different limits indicated
technique for cubic polynomials, an equation for the mean plot
is generated which is given by,
It = 0.019x3 + 0.21x2 − 0.18x + 1.2
x = log10 (tw )
According to the initial part, for tw < 1 ms of the plot,
the calculated pulse current is significantly large but the pre-
scribed Safe Operating Area (SOA) of a MOSFET datasheet
introduces some restrictions for pulse currents of different
pulse widths. The restrictions generated by different limits are
indicated in Fig. 4. In this study, the maximum current Limit
information is considered from it.
Therefore, the normalized current value is restricted to 4
times the maximum package rated current which is equal to
4Ir for the pulse duration up to 1 ms. For the pulse duration
of 1 ms to 1s, the current must follow (5)-(6) and gradually
reduces as the pulse duration increases so as to maintain the
thermal limit. After 1s the MOSFET carrying current must
not exceed the maximum package limit rated current which is
equal to Ir .
III. P ROPOSED A LGORITHM FOR DYNAMIC S ATURATION
From the Section II, it is clear that the MOSFET must be
undergone through a limited amount of current for a limited
duration and the MOSFET can withstand higher value of
overcurrent for the shorter duration without hitting its thermal
limits. To implement this concept in a boost converter it is
necessary to dynamically saturate the input inductor current
even if higher current is demanded by the output capacitor to
maintain its voltage at the preset reference value. The closed-
loop controller for the dc/dc converter is shown in Fig. 5, with
its dynamic saturation block for inductor current reference
shown in red. Input and output of the saturation block are
indicated as ii and io respectively.
The purpose of the dynamic saturation block is to determine
the output current io for the specific input current ii by mon-
itoring the duration t for which the over-current is demanded
and by finally comparing it with the device rated current ir .
Fig. 5. Closed-loop control scheme with dynamic saturation block shown in
red
(5)
(6)
Fig. 6. The flowchart of dynamic current saturation algorithm
The dynamic control algorithm is developed based on the
technique shown in the flowchart in Fig. 6, where ’Y’ and ’N’
are marked to indicate the decision YES and NO, respectively
during signal flow. The entire overcurrent saturation method
is classified into three categories based on the duration t. For
the duration of 1 ms, it is kept with the limit of 4Ir . The
over-current duration 10 ms < t < 1 s is of prime interest,
during which the multiplication factor it is estimated based on
(5) which reduces with time. After 1 s duration of continuous
overcurrent, the saturation block strictly keeps it within the
rated value. For every measurement of the saturation block
input current ii if the ii > ir comes as true, the overcurrent
duration computation starts with ’count t’ whereas, if it comes
as false the counter resets and the saturation block output
current io becomes equal to ii . It is clear from the flowchart,
once the current hits the saturation limit the converter operates
in current control mode instead of taking care of the output
voltage.
IV. S ELECTION OF A NTI - WINDING M ETHOD
Since the proposed method deals with the protection of
the MOSFET under over-current condition by saturating the
current dynamically, this avoids saturation up to some level
of load change. However, in case of a higher load change,
 Proceedings of the National Power Systems Conference (NPSC) - 2018, December 14-16, NIT Tiruchirappalli, India

Fig. 7. A typical dc microgrid system.

winding up effect may be visible due to the saturation limit.

The integral windup effect in PI controller is observed when
the control signal saturates the actuator. A further rise of the
control signal causes the integrator to accumulate error. Later,
when the control signal gets reduced, the error has to wind
down for a long time which leads to large overshoot and
larger settling time [27]. Primarily there are four different anti-
windup methods [28]–[30], i) conditional integrator, ii) limited
Integrator, iii) tracking anti-windup, iv) modified tracking
method. In this case, the conditional integrator method is
adopted as the anti-winding technique by limiting the integra-
tion procedure above a certain value which is slightly higher
than the desired dynamic saturation level.

V. S IMULATION R ESULTS AND D ISCUSSION

The simulated dc microgrid system to test the proposed
scheme is shown in Fig. 7. It consists of four boost converters
C1 , C2 , C3 and C4 each having a local load connected to it. Fig. 8. The simulation results with no saturation for inductor current
Power sharing among the converters is achieved by emulating reference. (a) converter output currents (b) converter output voltages, (c)
converter 4 saturation block input and output signals ii and io , (d) converter
droop resistance in each of it, d. Out of the four loads, L1 , L2 4 voltage control loop error signal ev with simulation time
and L3 are resistive loads whereas, L4 consists of resistive
load and controlled current sink in parallel. The current sink
adds stress to the converter C4 under overload condition. The objective of this simulation is to observe the coordi-
The data used in simulation for different converters and nation provided by the parallel connected source converters
distribution lines are listed in Table I and Table II. when one of them is overloaded due to the large change in
nearby load. Further, it would help to explore this phenomenon
TABLE I in presence of dynamic current saturation technique developed
DC MICROGRID SYSTEM PARAMETERS in previous sections.
During the simulation, initially, the total average load is
Parameter Value
Converter nominal voltage 400 V maintained to be 50% of rated load. At 0.1 second a large step
Converter power rating 32 kW change in load is introduced across C4 through the controlled
Cable resistance r1 , r2 , r3 0.25 Ω current sink which demands close to 1.5 times the rated
Cable inductance l1 , l2 , l3 0.27 mH
current. At 0.9 second the controlled current sink is removed
and the total load demand returns to the initial condition.
The advantage of the proposed dynamic current saturation
TABLE II
B OOST CONVERTER PARAMETERS
technique over the existing constant saturation is elaborated
through the following cases.
Parameter Value
Input voltage 200 V A. Case - I : Without Saturation
Rated output voltage 400 V
Rated power 32 kW In this case, there is no saturation applied to limit the
Switching frequency 10 kHz inductor current, the response of the 4-converters dc microgrid
Input inductance 2 mH system is shown in Fig. 8. In absence of the saturation limit,
Output capacitance 1000 µF
Current loop Kp , Ki 0.11, 565. 4 the inductor current of C4 reaches up to 120 A due to the
Voltage loop Kp , Ki 0.03, 48.5 large change in load at 0.1 second as depicted in Fig. 8(a). The
Droop gain 0.25 Ω output current of other converters are at their rated values or
 Proceedings of the National Power Systems Conference (NPSC) - 2018, December 14-16, NIT Tiruchirappalli, India
Fig. 9. The simulation results with constant saturation for inductor current
reference. (a) converter output currents (b) converter output voltages, (c)
converter 4 saturation block input and output signals ii and io , (d) converter
4 voltage control loop error signal ev with simulation time
below since C4 supports the voltage completely by enhancing
its output current. The further the distance from the stressed
converter C4 , the lower the impact on the converter voltage
and current waveforms as seen from Fig. 8(a) and Fig. 8(b).
C4 voltage is seen as 370 V whereas, the other converter
voltages are close to the rated value with corresponding
voltage drop due to individual droop resistance, higher the
output current higher is the voltage drop due to the droop
resistance. The saturation block input and output currents ii
and io overlap each other in this case as seen in Fig. 8(c) and
make error signal zero all throughout the simulation except
at the switching transients which is shown in Fig. 8(d). It is
evident that the MOSFET in C4 will be severely stressed in
this case and the thermal blow out is evident well ahead of
the time when the large load is removed.
B. Case - II : With Constant Saturation
In presence of a constant saturation, the inductor current
reference of each converter is limited to 150 A. Therefore, C4
output current stays at the rated value of 80 A even when the
large change in load is applied similar to the previous case,
as shown in Fig. 9(a). The voltage regulation is even worse
Fig. 10. The simulation results with dynamic saturation for inductor current
reference. (a) converter output currents (b) converter output voltages, (c)
converter 4 saturation block input and output signals ii and io , (d) converter
4 voltage control loop error signal ev with simulation time
in this case because the converter output current is forcefully
restricted by introducing the constant saturation. It is seen from
Fig. 9(b), C4 output voltage is at 355 V. The presence of
the constant saturation is clearly seen in Fig. 9(c). As there
is a constant difference maintained in between ii and io , a
constant error value is noticed in Fig. 9(d) but is restricted by
the adopted anti-winding technique. In this case, the PED of
each converter will be protected at the cost of poor voltage
regulation by limiting the inductor current within a specified
value.
C. Case - III : With Dynamic Saturation
In this case, a dynamic saturation is applied to the inductor
current reference which reduces it, as the overcurrent duration
increases. From Fig. 10(a) it is clearly seen that C4 output
current gradually reduces from 120 A to 80 A, whereas, C3
output current increases to support C4 output voltage due to its
proximity. From Fig. 10(b), the output voltages can be noticed,
where C4 voltage level is improved to 365 V than in Case II.
The saturation block output current io is reducing with time
when the input current ii is kept constant at slightly higher
value by using the anti-winding technique as shown in Fig.
10(c). Subsequently, the error in Fig. 10(d) also grows but stay
 Proceedings of the National Power Systems Conference (NPSC) - 2018, December 14-16, NIT Tiruchirappalli, India
within an acceptable limit as the difference between ii and io
increases with time. In presence of the dynamic saturation, the
device is protected from the thermal blow out in addition to
the improved transient voltage undershoot.
VI. C ONCLUSION
In this paper, the limitation of the existing constant current
saturation technique is introduced in boost converter in dc mi-
crogrid system. The significance of the power semiconductor
device manufacturers’ guidelines to tackle the thermal stress
caused by the device overcurrent is emphasized. A detailed ap-
proach has been developed here to include this thermal margin
into the converter control scheme followed by the algorithm
implemented. It is evident that the MOSFET may get damaged
due to the flow of current more than its rated values for a
significant duration. To protect it from the thermal blow out, an
algorithm is developed which enables it to carry high current
up to short time duration (1 ms) and thereafter, it gradually
reduces until the current reaches its rated output value within
the 1-second interval. Moreover, in a dc microgrid having
multiple converters, the transient output voltage undershoot is
also improved due to the additional power delivering capacity
in presence of dynamic saturation in comparison to that of
constant overcurrent saturation technique. Hence, this paper
realizes the protection of the power semiconductor device, at
the same time utilizing it to the fullest, with a simple and
effective control method. Although this technique is applied
to boost converter in this case, it can also be applied to other
dc/dc converters.
ACKNOWLEDGMENT
This work is supported by the project Indo-UK Center for
Education and Research in Clean Energy by Department of
Science & Technology (DST), Govt. of India and U.S.-India
collAborative for smart diStribution System wIth Storage (UI-
ASSIST) funded by Indo-US Science and Technology Forum
(IUSSTF).
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