Flat Design: 60 Seconds Timer 24

7 Seg 7 Seg
LED LED

BCD- BCD-
7 Seg 7 Seg

BCD Mod 6
Clock Divider
Counter Counter

POR

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Design Issues 25

• Accuracy
– Clock Frequency
• Area
– Clock frequency, Divider
– BCD, Mod-6 or Mod-60 counter ?
• Timing
– Max frequency – Divider
• Electrical Specs
– 7 Segment LED driving
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 CPU Specifications 26

• Example 8 bit Micro-processor

8 bit ALU, Data Bus D7 – D0
4, 8 bit registers
16 Instructions, (4 bit op code, 2 bits each for Src & Dst Registers)
64 KB Address space, Address lines A15 – A0
Program counter 16 bit, Stack Pointer 16 bit
No separate IO space
Controller – hard wired
De-multiplexed Address and Data bus
1 Interrupt
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CPU Design 27

• Partition: Functional blocks with interfaces (signals)

• Top-down Design
• At each level
Specifications / Functional description
Timing specifications
Electrical specifications

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 Top-down Design 28

• Complex designs cannot be done in one shot, one need to partition it

to logical blocks, each of which may have to be further partitioned, till
one end up with basic blocks like multiplexers, adders, incrementers,
registers, decoders etc.
• This calls for domain knowledge for proper partitioning and
identifying the interfaces and to decide the timing detail at the
interfaces.

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CPU Level 0 29

CLK RD/

RST WR/

INTR CPU A15:0

D7:0

• Functional: Multi-cycle Execution, Instruction set, …

• Timing: Bus Cycle, Interrupt, Clock, Reset, ..
• Electrical: Bus driving

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 CPU Level 1 30

Data Bus D7:0

CLK

IR_L INST REG RA_L PC_IS

TR1_L SP_IS
TR1 TR2_L TR2 RA_E REG A
PC_L0
RB_L SP_L0
INST DEC
RB_E REG B PC_L1
PC SP_L1 SP
RC_L
RC_E REG C PC_OS
SP_OS
AL_S RD_L
PC_E
ALU RD_E REG D SP_E
AL_E
CLK
AL_S, AL_E
RST RA_L, RB_L, RC_L, RD_L AD_S
CONTR-
OLLER RA_E, RB_E, RC_E, RD_E
INTR
IR_L, TR1_L, TR2, L
PC_IS, PC_L0, PC_L, PC_OS, PC_E A15:0
SP_IS, SP_L0, SP_L1, SP_OS, SP_E, AD_S

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CPU Level 1 31

• Data Path
– Registers, Combinational Circuit
– (R  C  R), (R  R)

• Controller
– Finite State Machine (FSM)
– Registers, Combinational Circuit

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 Datapath 32

• Datapath is where data movement and computation happens. It usually comprises of registers to
hold the input/intermediate/final data values and combinational circuits implementing all the
computations.
• In the case of CPU, Register file, ALU with registers at it input, Program Counter block and Stack
pointer block forms the datapath.
• Controller provides the timing or control signals to enable various outputs of registers, give latch
signals to registers, specify the operation of combinational circuit, to select various path through
which data moves (through Multiplexers) etc.
• Controller does no computation, merely provides the timing signals.
• This helps as to partition individual blocks as at the point of partitioning individual blocks we need
not bother about sequence of operations or its timing, we need to concentrate the functionality in
terms of computation, data movement etc.

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Controller 33

• Controller does no computation, merely provides the timing signals.

• A single controller can provide the control signals for all the blocks
which work synchronously with it.
• Separate controller is required, if, another block whose operation is
not synchronous to this block.
• Even if all the blocks works synchronous to each other, to manage
complexity multiple controllers or hierarchy of controllers may be
used.

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 CPU Level 2: Registers 34

• Registers use flip-flops. Main control we require is to enable the

register to latch the input data, at proper instant.
• Normally this done on an active clock edge qualified by a level
control signal from controller (i.e. Input data is latched on the register,
up on the active clock edge while the control signal (e.g. RA_L) is
high.
• Such a scheme allows the continuous latching of input data, if the
control signal is kept high.

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CPU Level 2: Registers 35

D Q D7:0

RA_E

RA_L
CK
CLK

8-bit Register (8, Edge triggered flip-flops)

8 Tri-state gates
1, 2-input AND gate
Note: There is a timing issue with this scheme

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 CPU Level 2: Registers 36

• The previous scheme has a timing problem.

• Also, it adds skew in the clock path, clock path delay would increase the hold
time as we have seen earlier, which can create timing issues like hold time
violation.
• Hence, the scheme in following slide is used. Here, the clock goes unqualified to
the clock of register. The control is in the data path.

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CPU Level 2: Registers 37

0
D Q D7:0
D7:0 1

RA_L RA_E

CLK CK

8-bit Register (8, Edge triggered flip-flops)

8, Tri-state gates
1, 8-bit 2 to 1 Multiplexer

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 CPU Level 2: Registers 38

• A mux steers the input to the input of the register. Problem with this
approach is that, since the clock is active always, input gets latched.
To hold the stored value, when input is not selected, output of register
is re-circulated back to the input.
• The flip side is the higher power dissipation in registers due to
continuous clocking.

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Program Counter 39

• PC is incremented at every clock cycle, hence need a 16 bit incrementor.

• PC output drives the address bus along with stack pointer, a 16-bit, 2 to 1 mux
is required.
• On instructions like jump the address on the data bus has to be loaded to PC.
Data bus being 8-bit, this has to be done in 2 steps, that calls for PC register to
be 2, 8-bit registers with separate latch signals.
• Up on reset and on interrupt PC has to be loaded with specific addresses, this
calls for path selection at the input.
• On instructions like call, the PC value has to go to data bus (to memory), hence
an 8-bit 2-to-1 mux is required at the output.

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8
 Program Counter 40

• We do not need to worry about the sequence of operations or timing of the

signals at this point, we need to identify the data movement and various
operations to be able to do the next level design.
• Sequencing and timing will be done while designing the controller.

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CPU Level 2: Program Counter 41

D7:0
PC-RST
PC-INT

PC_L0
CLK PCS(0)
PC-IS
PC-IS
+1
PC_L1 PC_L1
CLK PC(1) CLK PC(0)

From SP

AD-S PC-OS

A15:0 PC-E
D7:0

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 CPU Level 2: Program Counter 42

• 3, 8-bit Registers
• 2, 8-bit 4 to 1 Multiplexers
• 1, 16 bit Incrementer
• 1, 16-bit 2 to 1 Multiplexers
• 1, 8-bit 2 to 1 Multiplexers
• 8 Tri-state gates

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CPU Level 2: Program Counter 43

• How to write VHDL Code for the Program counter?

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 CPU Level 2: Program Counter 44

data
D7:0
PC-RST
PC-INT

PC_L0
CLK PCS(0)
PC-IS pcs
PC-IS
+1
PC_L1 PC_L1
CLK PC(1) CLK PC(0)
pco(15:8)
from-SP pco(7:0)

AD-S PC-OS
address data1
A15:0 PC-E
data D7:0
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Program Counter: VHDL Code 45

pc: process (clk) if (pc_l0 = '1') then

begin pcs <= data;
if (clk'event and clk = '1') then end if;
if (pc_l1 = '1') then end if;
case pc-is is
when “00” => pco <= pco + 1;
when “01” => pco <= pc-int; address <= pco when (ad-s = ‘1’)
when “10” => pco <= pc-rst; else from-SP;
when others => pco <= data & pcs; data1 <= pco(15 downto 8) when
end case; (pc-os = ‘1’) else pco(7 downto 0);
end if; data <= data1 when (pc-e = ‘1’)
else (others => ‘0’);
end process;
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