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9 STUDY OF TMS320C6748
DATE:
AIM:
DESCRIPTION:
This new board reduces design work with freely downloadable and duplicable
board schematics and design files. A wide variety of standard interfaces for
connectivity and storage enable you to easily bring audio, video and other
signals onto the board.
BASIC ARCHITECTURE:
The device DSP core uses a 2-level cache-based architecture. The level 1
program cache (L1P) is a 32-KB direct mapped cache, and the level 1 data
cache (L1D) is a 32-KB 2-way, set-associative cache. The level 2 program
cache (L2P) consists of a 256-KB memory space that is shared between
program and data space. L2 memory can be configured as mapped memory,
cache, or combinations of the two. Although the DSP L2 is accessible by
other hosts in the system, an additional 128KB of RAM shared memory is
available for use by other hosts without affecting DSP performance.
For security-enabled devices, TI’s Basic Secure Boot lets users protect
proprietary intellectual property and prevents external entities from
modifying user-developed algorithms. By starting from a hardware-based
“root-of-trust”, the secure boot flow ensures a known good starting point for
code execution. By default, the JTAG port is locked down to prevent
emulation and debug attacks; however, the JTAG port can be enabled during
the secure boot process during application development. The boot modules
are encrypted while sitting in external nonvolatile memory, such as flash or
EEPROM, and are decrypted and authenticated when loaded during secure
boot. Encryption and decryption protects customers’ IP and lets them
securely set up the system and begin device operation with known, trusted
code.
Basic Secure Boot uses either SHA-1 or SHA-256, and AES-128 for boot
image validation. Basic Secure Boot also uses AES-128 for boot image
encryption. The secure boot flow employs a multilayer encryption scheme
which not only protects the boot process but offers the ability to securely
upgrade boot and application software code. A 128-bit device-specific cipher
key, known only to the device and generated using a NIST-800-22 certified
random number generator, is used to protect customer encryption keys.
When an update is needed, the customer uses the encryption keys to create
a new encrypted image. Then the device can acquire the image through an
external interface, such as Ethernet, and overwrite the existing code. For
more details on the supported security features or TI’s Basic Secure Boot,
refer to the TMS320C674x/OMAP-L1x Processor Security User’s Guide
(SPRUGQ9).
INTERFACES:
The peripheral set includes: a 10/100 Mbps Ethernet media access controller
(EMAC) with a management data input/output (MDIO) module; one USB2.0
OTG interface; one USB1.1 OHCI interface; two I2C Bus interfaces; one
multichannel audio serial port (McASP) with 16 serializers and FIFO buffers;
two multichannel buffered serial ports (McBSPs) with FIFO buffers; two serial
peripheral interfaces (SPIs) with multiple chip selects; four 64-bit general-
purpose timers each configurable (one configurable as a watchdog); a
configurable 16-bit host-port
interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins,
with each bank containing 16 pins with programmable interrupt and event
generation modes, multiplexed with other peripherals; three UART interfaces
(each with RTS and CTS); two enhanced high-resolution pulse width
modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP)
module peripherals which can be configured as 3 capture inputs or 3 APWM
outputs; two external memory interfaces: an asynchronous and SDRAM
external memory interface (EMIFA) for slower memories or peripherals; and
a higher speed DDR2/Mobile DDR controller.
The EMAC provides an efficient interface between the device and a network.
The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100
Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is
available for PHY configuration. The EMAC supports both MII and RMII
interfaces.
A video port interface (VPIF) is included providing a flexible video I/O port.
The rich peripheral set provides the ability to control external peripheral
devices and communicate with external processors.
The device has a complete set of development tools for the DSP. These tools
include C compilers, a DSP assembly optimizer to simplify programming and
scheduling, and a Windows® debugger interface for visibility into source
code execution.
The LCDK does not have an onboard emulator. An external emulator from TI,
such as the XDS200 or a third-party emulator will be required to start
development.
PACKAGE CONTENT:
C6748 LCDK
SPECIFICATIONS:
Processor
Memory
128 MB DDR2 SDRAM running at 150MHz 128 MB 16-bit wide
NAND FLASH
3 Transfer Controllers
O 2 SP x SP → SP Per Clock
• Software Support TI
DSP BIOS™
Chip Support Library and DSP Library
• 128KB of RAM Shared Memory
• 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
16-Byte FIFO
• LCD Controller
• Two Serial Peripheral Interfaces (SPIs) Each with Multiple Chip Selects
• One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address and Data
Bus for High Bandwidth
Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and
12-Bit) Video Capture Channels
• Real-Time Clock (RTC) with 32-kHz Oscillator and Separate Power Rail
Dead-Band Generation
• Packages:
361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-
mm Ball Pitch
361-Ball Pb-Free PBGA [ZWT Suffix], 0.80-mm Ball Pitch
• Choose the location for the workspace, where your project will be
saved.
• Click on Empty Project in the Project Template Section, and then click
on Finish.
• Go to Project -> Build project. If your code doesn’t have any errors
and warnings, a message will be printed in the console window
showing the message: **** Build Finished ****. Otherwise errors or
warnings are displayed, if any.
• After building the project successfully, connect the kit with the
system using the JTAG emulator and power the kit. Connect
additional components if necessary.
• To generate any graphs, click on the Tools tab -> Graphs and select
the required type of graph. Specify its properties in the given window
and click on OK. The graph is displayed in a separate window.
Result:
DATE:
AIM
APPARATUS REQUIRED
ALGORITHM
In the main function, create a loop which stores sine wave values in
the array for each iteration.
PROGRAM
#include
<stdio.h>
#include<math
> #define freq
500 float
m[128];
void main()
{
int i=0;
for(i=0;i<127;
i++)
m[i]=sin(2*3.14*freq*i/24000);
printf("%f\n",m[i]);
}
}
OUTPUT
RESULT
Thus a sine wave was generated using TMS320C6748 kit and the output
was observed and verified.
EXPT. NO. 11 LINEAR CONVOLUTION
DATE:
AIM
APPARATUS REQUIRED:
ALGORITHM:
PROGRAM
#include<stdio.h>
#define Length1 4
#define Length2 3
float x[Length1+Length2-1]={1,2,3,4,0,0};
float h[Length1+Length2-1]={5,6,7,0,0,0};
float y[Length1+Length2-1];
void main()
{
int n, k;
y[n]+=x[k]*h[n-k];
}
printf("Convolution Output =\n");
for(n=0; n<(Length1+Length2-1);
n++) printf("%f\n", y[n]);
}
OUTPUT
RESULT
DATE:
AIM
APPARATUS REQUIRED
ALGORITHM
scanf("%d",&n);
scanf("%d",&x[i]);
scanf("%d",&h[j]);
for(i=n;i<m;i++)
h[i]=0;
n=m;
}
for(i=m;i<n;i++)
x[i]=0;
m=n;
}
y[0]=0;
a[0]=h[0];
a[j]=h[n-j];
y[0]+=x[i]*a[i];
for(k=1;k<n;k++)
y[k]=0;
for(j=1;j<n;j++)
{
a[i]=x2[i];
y[k]+=x[i]*x2[i];
}
}
printf("The circular convolution is:\n"); /*Display the result*/
for(i=0;i<n;i++)
printf("%d \t",y[i]);
}
Output:
RESULT:
DATE:
AIM
APPARATUS REQUIRED
ALGORITHM
Initialise arrays for storing real and imaginary part of the output.
Using a loop, calculate real part and imaginary part for each
index as follows: sumre=sumre+x[n]*cos(2*pi*k*n/N) and
sumim=sumim-x[n]* sin(2*pi*k*n/N).
#include<stdio.h>
#include
<math.h
>
int N,k,n,i;
int x[32];
void main(void)
{
printf(" enter the length of the sequence\n");
scanf("%d",&N);
for(k=0;k<N;k++)
sumre=0;
sumim=0;
for(n=0;n<N;n++)
}
out_real[k]=sumre;
out_imag[k]=sumim;
printf("X([%d])=\t%f\t+\t%fi\n",k,out_real[k],out_imag[k]);
OUTPUT
RESULT
DATE:
AIM
APPARATUS REQUIRED
ALGORITHM
Program:
#include <math.h>
#define PI 3.14159265358979
samples[i].real=0.0;
samples[i].imag=0.0;
}
for (i = 0 ; i < PTS ; i++) //swap buffers
x1[i] = sqrt(samples[i].real*samples[i].real+
samples[i].imag*samples[i].imag);
} //end of main
//FFT FUNCTION
index = 0;
lower_leg = upper_leg+leg_diff;
temp1.real = (Y[upper_leg]).real +
(Y[lower_leg]).real; temp1.imag =
(Y[upper_leg]).imag + (Y[lower_leg]).imag;
temp2.real = (Y[upper_leg]).real -
(Y[lower_leg]).real; temp2.imag =
(Y[upper_leg]).imag - (Y[lower_leg]).imag;
(Y[lower_leg]).real =
temp2.real*(w[index]).real -
temp2.imag*(w[index]).imag;
(Y[lower_leg]).imag = temp2.real*(w[index]).imag
+temp2.imag*(w[index]).real;
(Y[upper_leg]).real = temp1.real;
(Y[upper_leg]).imag = temp1.imag;
index += step;
leg_diff = leg_diff/2;
step *= 2;
j = 0;
k = N/2;
while (k <= j)
{
j = j - k;
k=k/2;
}
j = j + k;
if (i<j)
temp1.real = (Y[j]).real;
temp1.imag = (Y[j]).imag;
(Y[j]).real = (Y[i]).real;
(Y[j]).imag = (Y[i]).imag;
(Y[i]).real = temp1.real;
(Y[i]).imag = temp1.imag;
}}
return;
}
OUTPUT
RESULT
DATE:
AIM
APPARATUS REQUIRED
ALGORITHM
PROGRAM
#include<stdio.h>
#include
<math.h
> int
i,w,wc,c,
N; float
H[100];
float
mul(float,
int); void
main()
{
H[w]=1/sqrt(1+mul((w/(float)wc),2*N));
printf("H[%d]=%f\n",w,H[w]);
for(i=0;i
<x-
1;i++)
a*=a;
return(a);
}
OUTPUT
RESULT
Thus IIR low pass filter was implemented using TMS320C6748 kit and
the output was observed and verified.
EXPT. NO. 16 IMPLEMENTATION OF FIR FILTERS
DATE:
AIM
APPARATUS REQUIRED
ALGORITHM
PROGRAM
#include<stdio.h>
#include<math.h>
#define PI 3.14
void main()
{
const int sampf=10000;
const int cutf=1000;
float value,a,b,output;
int nyqf,n,c0;
int *coeff;
coeff = (int *)0xc0001000;
nyqf=sampf/2;
c0=cutf/nyqf;
for(n=-5;n<6;n++)
{
if(n==0)
output = 0.5;
else
a = (n * PI)/2;
b=n * PI;
value = sin(a);
output = value/b;
}
OUTPUT
RESULT
Thus FIR low pass filter was implemented using TMS320C6748 kit and
the output was observed and verified.
CONTENT BEYOND THE SYLLABUS
AIM
APPARATUS REQUIRED
ALGORITHM
Median filtering:
Define the box and median filters, and vary the boundaries of
the filters by changing matrix dimensions.
PROGRAM
%Media
filtering
clc
Clear all;
Close all;
a=imread('horse.jpg');
subplot(3,3,1),imshow(a),title('Original image')
subplot(3,3,2),imshow(b),title('Salt & pepper
noise') subplot(3,3,3),imshow(uint8(c1)),title('3 x
3 smoothing')
subplot(3,3,4),imshow(uint8(c2)),title('5 x 5
smoothing')
subplot(3,3,5),imshow(uint8(c3)),title('3x 3
Median filter')
subplot(3,3,6),imshow(uint8(c4)),title('5 x 5
Median filter')
subplot(3,3,7),imshow(uint8(c5)),title('7 x 7
Median filter')
subplot(3,3,8),imshow(uint8(c6)),title('9 x 9
Median filter')
%Histogram
equalisation clc
Clear all;
Close all;
a=imread('babyincradle.
png'); %perform
histogram equalization
b=histeq(a);
subplot(2,2,1),imshow(a),title('original image')
subplot(2,2,2),imshow(b),title('After histogram
equalization')
subplot(2,2,3),imhist(a),title('original histogram')
subplot(2,2,4),imhist(b),title('After histogram equalization')
RESULT
DATE:
AIM
APPARATUS REQUIRED
ALGORITHM
PROGRAM
fs=8000;
x=audioread('Hello.wav');
ss1=x(1:700);
[ac1,lags1]=xcorr(ss1);
ss4=x(1800:1860);
[ac4,lags4]=xcorr(ss4);
subplot(2,2,1);
plot(ss1);
legend('Voiced speech');
subplot(2,2,2);
plot(lags1,ac1);
xlim([lags1(1),ac1(end)]);
legend('Autocorrelation of voiced
speech'); subplot(2,2,3);
plot(ss4);
legend('Unvoiced
speech');
subplot(2,2,4);
plot(lags4,ac4);
xlim([lags1(1),lags
1(end)]);