20I3 International Conference on Circuits, Power and Computing Technologies [ICCPCT-20I3]
Enhanced Area Effi cient Architecture for
Modified CSLA
R.Priya,
PG Student, ME Communication Systems,
Mepco Schlenk Engineering College, Sivakasi.
priyaramasamy. 33@gmail.com
Abstract- In the design of Integrated circuits, area occupancy
plays a vital role because of increasing necessity of portable
systems. Carry Select Adder (CSLA) is a fast adder used in data­
processing processors for performing fast arithmetic functions.
From the structure of the CSLA, the scope is to reduce the area of
CSLA based on the efficient gate-level modification. In this paper
128 bit Regular Linear CSLA, Modified Linear CSLA, Regular
Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA
architectures have been developed and compared. However, the
Regular CSLA is still area-consuming due to the dual Ripple­
Carry Adder (RCA) structure. For reducing area, the CSLA can
be implemented by using a single RCA and an add-one circuit
instead of using dual RCA. Comparing the Regular Linear CSLA
with Regular SQRT CSLA, the Regular SQRT CSLA has reduced
area as well as comparing the Modified Linear CSLA with
Modified SQRT CSLA; the Modified SQRT CSLA has reduced
area. The results and analysis show that the Modified Linear
CSLA and Modified SQRT CSLA provide better outcomes than
the Regular Linear CSLA and Regular SQRT CSLA respectively.
This project was aimed for implementing high performance
optimized FPGA architecture. Modelsim 10.0c is used for
simulating the CSLA and synthesized using Xilinx PlanAhead13.4.
Then the implementation is done in Virtex5 FPGA Kit.
Keywords-Field Programmable Gate Array (FPGA), Area efficient,
Carry Select Adder (CSLA), Square-root CSLA (SQRT CSLA).
I. INTRODUCTION
Design of area efficient high speed data path logic
systems are one of the most essential areas of research in VLSI.
In digital adders, the speed of addition is controlled by the time
required to propagate a carry through the adder. The sum for
each bit position in an elementary adder is
sequentially only after the previous bit position was summed
and a carry propagated into the next position. Bedriji proposed
[1] that the problem of carry propagation delay is overcome by
independently generating multiple radix carries and using this
carries to select between simultaneously generated
Akhilash Tyagi introduced a scheme to generate carry bits with
block carry in 1 from the carries of a block with block carry in 0
[4]. Chang and Hsiao proposed [3] that instead of using dual
RCA, a CSLA scheme using an add one circuit to replace one
RCA. Youngioon Kim and Lee Sup Kim introduced
multiplexer based add one circuit was proposed to reduce the
area with negligible speed penalty. Yajuan He et al proposed an
area efficient Square-root CSLA (SQRT CSLA) scheme based
on a new first zero detection logic [9]. Ramkumar and Harish
proposed [8] Binary to Excess 1 converter (BEC) technique,
978-1-4673-4922-2113/$31.00 ©2013 IEEE
128 bit
J.Senthil Kumar
Assistant Professor. Department of ECE.
Mepco Schlenk Engineering College. Sivakasi.
senvimj ag@gmail.com
which is a simple and efficient gate level modification to
significantly reduce the area of SQRT CSLA. Padma Devi et al
proposed [10] modified CSLA designed in different stages
which reduces the area. CSLA is used in many computational
systems to relieve the problem of carry propagation delay by
independently generating multiple carries and then select a carry
to generate the sum [1]. However, the CSLA is not area efficient
because it uses multiple pairs of RCA to generate partial sum
and carry by considering carry in 0 and carry in 1, then the final
sum and carry are selected by the multiplexers (MUX).
The basic idea of this work is to use BEC instead of
RCA with carry in 1 in the regular CSLA to achieve lower area
[2], [3] and [4]. The main benefit of BEC comes from the lesser
number of logic gates than the n-bit Full Adder (FA). The
details of BEC are discussed in section II. The CSLA has been
chosen for comparison with the proposed design as it has a
lower area [5], [6]. The area evaluation methodology of the
regular Linear CSLA and regular SQRT CSLA are presented in
section III. The area evaluation methodology of the modified
Linear CSLA and modified SQRT CSLA are presented in
section IV. The FPGA implementation details and results are
analyzed in section V. Finally this work is concluded in section
VI.
II. BINARY TO EXCESS-I CONVERTER (BEC)
The main idea of this work is to use BEC instead of
RCA with carry in=1 in order to reduce the area of the regular
Linear CSLA as well as regular SQRT CSLA. To replace the n­
bit RCA, an n+ I-bit BEC is required. A structure and the
function of 3-bit BEC are shown in Fig. 1 and Table I,
generated respectively. The Boolean expressions for 3-bit BEC is shown
below (note the functional symbols�NOT, & AND, /\XOR)
X O=�B O (1)
X l =B O /\BI (2)
X2 = B2 /\ (B O & BI) (3)
sums.
a: e.a 90
a
'Xl. XI xo
Fig. I A 3-bit BEe
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TABLE I TABLE 11
FUNCTION TABLE OF THE 3-BIT BEC AREA COUNT OF THE 16-B1T REGULAR LINEAR CSLA GROUPS

INPUT OUTPUT
B[2:01 X[2:01 GROUP AREA COUNT
000 001
Groupl 52
001 010
010 011 Group2 117
011 100
Group3 117
100 101
101 110
Group4 117
110 111
111 000
The structure of the 16-bit regular SQRT CSLA is
shown in Fig. 3. It has 5 groups of different size RCA. Each
III. AREA EVALUAnON METHODOLOGY OF REGULAR
group contains dual RCA and MUX. The linear carry select
16-BIT LINEAR CSLA AND SQRT CSLA
adder has one main disadvantage that is high area usage. This
The structure of the 16-bit regular Linear CSLA is disadvantage can be rectified by SQRT CSLA. So SQRT CSLA
shown in Fig. 2. It has 4 groups of same size RCA. Each group is an improved one of linear CSLA. The time delay of the linear
contains dual RCA and MUX. It accomplishes the addition by adder can decrease by having one more input into each set of
adding small portions of bits (each of equal size) and wait for adders than in the previous set. This is called SQRT CSLA. The
the carry to complete the calculation. Both sum and carry are steps leading to the evaluations are given here. In the regular
calculated for both possible solutions. The linear carry select SQRT CSLA, the group3 has two sets of 3-bit RCA. The
adder is constructed by chaining a number of equal length adder selection input of 8:4 mux is c3. If the c3 = 0, the mux select
stages. Here the equal size of inputs is given to each block of the fust RCA output (Cin=O) otherwise it select second RCA output
adder.The steps leading to the evaluations are given here. In the (Cin=l). The output of group3 are Sum [6:4] and carryout, c6.
regular Linear CSLA, the group3 has two sets of 4-bit RCA. Then the area count of group3 is determined as follows:
The selection input of 10:5 mux is c7. If the c7 = 0, the mux
Gate count = 87 (FA + HA + MUX)
select first RCA output (Cin=O) otherwise it select second RCA
FA =65 (5*13)
output (Cin=l). The output of group3 are Sum [11:8] and
HA = 6 (1*6)
carryout, c11. Then the area count of group3 is determined as
MUX = 16 (4*4)
follows:
Gate count = 117 (FA + HA + MUX) Similarly the estimated area of the other groups in the regular
FA =91 (7 *13) SQRT CSLA are evaluated and listed in Table III.
HA = 6 (1*6)
MUX = 20 (5*4)

Similarly the estimated area of the other groups in the regular

Linear CSLA are evaluated and listed in Table II.

.\115:12) B115:12) A17:l) B17:l)

Caul SUDlIl5:11J Sum1l0:7) Suml6:lJ SUOlI3:2J SUOIll:0J

Fig. 3. Regular 16-bit SQRT CSLA

COOl Sum [15:12) Sum 111:8) Sum (7:4) Sum 13:0)

Fig. 2. Regular 16-bit Linear CSLA

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TABLE III TABLE IV

AREA COUNT OF THE 16-BTT REGULAR SQRT CSLA GROUPS AREA COUNT OF THE 16-BIT MODIFIED LINEAR CSLA GROUPS

GROUP AREA COUNT

GROUP AREA COUNT
Group I 52
Group] 26
Group2 89
Group2 57 Group3 89

Group3 87 Group4 89

Group4 117
The structure of the 16-bit modified SQRT CSLA is
GroupS 147
shown in Fig. 5. It has 5 groups of different size RCA and BEC.
IV. AREA EVALUAnON METHODOLOGY OF MODIFIED Each group contains one RCA, one BEC and MUX. In the
16-BIT LINEAR CSLA AND SQRT CSLA modified SQRT CSLA, the group3 has one 3-bit RCA which
has 1 HA and 2 HA for carry in = O. Instead of another 2-bit
The structure of the proposed 16-bit Linear and SQRT
RCA with carry in = 1 a 4-bit BEC is used which adds one to
CSLA using BEC for RCA with carry in = 1 to optimize the
the output from 3-bit RCA. The selection input of 8:4 mux is c3.
area is shown in Fig. 4 and Fig. 5 respectively. The 16-bit
If the c3 = 0, the mux select RCA output otherwise it select
modified Linear CSLA has 4 groups of same size RCA and
BEC output. The output of group3 are Sum [6:4] and carryout,
BEe. Each group contains one RCA, one BEC and MUX. . In
c6. Then the area count of group3 is determined as follows:
the modified Linear CSLA, the group3 has one 4-bit RCA
which has 3 FA and 1 HA for carry in = O. Instead of another 4- Gate count = 66 (FA + HA + MUX + BEC)

bit RCA with carry in = 1 a 5-bit BEC is used which adds one to FA =26 (2*13)

the output from 4-bit RCA. The selection input of 10:5 mux is HA = 6 (1*6)
c7. If the c7=0, the mux select RCA output otherwise it select
BEC output. The output of group3 are Sum [11:8] and carryout, MUX =16 (4*4)

cll. Then the area count of group3 is determined as follows: NOT = 1, AND = 2 (2*1), XOR = 15 (3*5)
Gate count = 89 (FA + HA + MUX + BEC)
BEC (4-BIT) = NOT + AND + XOR = 18
FA =39 (3*13)
Similarly the estimated area of the other groups in the modified
HA = 6 (1*6) SQRT CSLA are evaluated and listed in Table V.

MUX = 20 (5*4) _-%.[l:S:llJ B(15:11J AIIO:7] B[10:7] _-'.[6:4J B[6:4J A(3:2J BIl::] A(I:OJ BII:O]

NOT = 1,

AND = 3 (3*1)

XOR = 20 (4*5)

BEC (5-BIT) = NOT + AND + XOR = 24

Similarly the estimated area of the other groups in the modified
Linear CSLA are evaluated and listed in Table IV.
COUI Sum [15:11] Sum 110:7] Sum (6:4) Sum [3:2] 5um[I:0]

Fig. 5. Modified 16-bit SQRT CSLA

TABLE V
AREA COUNT OF THE 16-BlT MODIFIED SQRT CSLA GROUPS

GROUP AREA COUNT

Group] 26

Group2 43

Group3 66
Group4 89
Coul S UUl (l5:12] Sum (11:8J S U ID (7 : 4] Sum (3:0]
GroupS 113
Fig. 4. Modified 16-bit Linear CSLA

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Comparing Tables II and III with Tables IV and V, it is clear from the result analysis the 128-bit Modified SQRT CSLA has
that the 16 bit proposed modified Linear as well as SQRT CSLA reduced area compared with Regular Linear CSLA, Regular
save 84 gate and 97 gate areas than the regular Linear CSLA SQRT CSLA and Modified Linear CSLA. The area of the
and regular SQRT CSLA respectively. proposed design shows a decrease for 16-bit, 32-bit, 64-bit and
128-bit sizes which indicate the success of the method and not a
V. FPGA IMPLEMENTATION RESULTS
mere tradeoff of delay for area. The Modified CSLA
This work has been developed using Verilog-HDL. It
architecture is therefore, low area, simple and efficient for VLSI
was simulated using Modelsim Altera 1 O.0c and synthesized
hardware implementation.
using Xilinx PlanAhead 13.4. This design was implemented in
Virtex5 kit. Table VI exhibits the area count of all types of
REFERENCES
CSLA structures. The gate reduction in the area as a function of
the bit size is shown in Fig. 6. It is clear that the area of the 16-
[1] 0.1. Bedrij, "Carry-select adder, " IRE Trans. Electron.
bit, 32-bit, 64-bit and 128-bit proposed modified SQRT CSLA
Computer., pp. 340-344, 1962.
is reduced when compared with the area of other CSLAs.
[2] B. Ramkumar, H.M. Kittur, and P. M. Karman, "ASIC
TABLE VI implementation of modified faster carry save adder, "
COMPARISON OF CSLAs BASED ON AREA COUNT Eur. J. Sci. Res., vol. 42, no. 1, pp.53-58, 2010.
[3] T. Y. Ceiang and M. 1. Hsiao, "Carry-select adder using
AREA AREA
single ripple Carry adder, " Electron. Lett, vol. 34, no.
BIT COUNT OF COUNT
TYPES 22, pp. 2101-2103, Oct. 1998.
SIZE LINEAR OF SQRT
[4] Y. Kim and L.-S. Kim, "64-bit carry-select adder with
CSLA CSLA
reduced area, " Electron. Lett. vol. 37, no. 10, pp. 614-
Regular 871 868 615, May 2001.
32 bit
[5] J. M. Rabaey, Digtal Integrated Circuits-A Design
Modified 675 674 Perspective.Upper Saddle River, NJ: Prentice-Hall,
2001
Regular 1742 1736 [6] Y. He, C. H. Chang, and J. Gu, "An area efficient 64-
64 bit
Bit square Root carry-select adder for low power
Modified 1387 1348
Applications, " in Proc. IEEE Int. Symp.Circuits Syst.,
vol. 4, pp. 4082-4085, 2005.
Regular 3679 3472
128 bit [7] Cadence, "Encounter user guide, " Version 6.2.4,
March 2008.
Modified 2811 2696
[8] Ramkurnar, B. and Harish M Kittur, "Low Power and
Area Efficient Carry Select Adder ", IEEE
Transactions on Very Large Scale Integration (VLSI)
4000
3500
-+-Regular Systems, pp.I-5, 2012.
Linear CSLA [9] He, Y. Chang, C. H. and Gu, J. "An Area Efficient 64-
.. 3000
c:: Bit Square Root Carry-Select Adder For Low Power
� 2500 ___ Modified
0 Applications, " in Proc. IEEE Int. Symp. Circuits Syst.,
u 2000 Linear CSLA
IV Vol.4, pp. 4082-4085, 2005.
QI
... 1500 ....... Regular [10] Padma Devi, Ashima Girdher and Balwinder Singh
<C
1000 SQRTCSLA "Improved Carry Select Adder with Reduced Area
500 and Low Power Consumption, " International Journal
�Modified
0 of Computer Applications, Vo1.3, No.4, pp. 14-18,
SQRTCSLA
16 bit 32 bit 64 bit 128 bit 1998.
Bit Size [11] Akhilesh Tyagi, "A Reduced-Area Scheme for Carry­
Select Adders, " IEEE Transactions on Computers,
Vo1.42, No.10, pp.1l63-1170, 1993.
Fig. 6 Comparison of CSLAs based on Area count

VII. CONCLUSION
This project presented a simple approach to reduce the
area of CSLA architecture. The reduced number of gates of this
work offers the great advantage in the reduction of area. Totally

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