BK Coe358 2016 PDF

EMBEDDED SYSTEMS
DEPARTMENT OF COMPUTER ENGINEERING
COE 358 EMBEDDED SYSTEMS
Dipl.-Ing. B. Kommey
050 770 3286
4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 1

EMBEDDED SYSTEMS
“What has been hidden from the

wise and the prudent has been
revealed to the baby and the
suckling”
Robert Nasta Marley

EMBEDDED SYSTEMS
Overview
Embedded
Systems
Embedded Applications
Systems
Reference
Books
Course
Outline
Course Info

EMBEDDED SYSTEMS
Course Information
COE 358 Embedded Systems Requirements
3hrs Teaching Strong Programming Knowledge in C
2hr Practicals Basic Operating System Knowledge
3 Credit Hours Strong Knowledge in Electronics

EMBEDDED SYSTEMS
Course Grading
Class Work
Final Exams 5%
70%
Mid-
Attendance
Semester
5%
Exams (20%)

EMBEDDED SYSTEMS
Course Outline
Introduction to Embedded Systems – lecture 1
The Processor (CPU Interfacing) – lecture 2
Memories – lecture 3
Peripherals – lecture 4

EMBEDDED SYSTEMS
Course Outline
Converters – lecture 5
Software – lecture 6
Embedded Systems Development – lecture 7
Embedded Communications – lecture 8

EMBEDDED SYSTEMS
Course Outline
Buses – lecture 9
Polling & Interrupts – lecture 10
Buffering & DMA – lecture 11
Embedded Operating Systems – lect. 12
Security and Cryptography – lecture 13

EMBEDDED SYSTEMS
References Books

EMBEDDED SYSTEMS
References Books

EMBEDDED SYSTEMS
References Books

EMBEDDED SYSTEMS
References Books

EMBEDDED SYSTEMS
References Books

EMBEDDED SYSTEMS
References Books

EMBEDDED SYSTEMS
References Books

EMBEDDED SYSTEMS
Embedded System Overview

Embedded System
What is Embedded Software and Embedded

Embedded System Tools for System
System ? Components Developments Application
Development
Demo

EMBEDDED SYSTEMS
What is Embedded System ?
Application
Definition
Areas
EMBEDDED SYSTEMS
Embedded System Components
Hardware Software

EMBEDDED SYSTEMS
Introduction to Embedded Systems

Computing systems are everywhere
Most of us think of “desktop” computers

PC’s, Laptops, Mainframes and Servers
But there’s another type of computing system far more

common

EMBEDDED SYSTEMS

Embedded computing systems
–Computing systems contained within electronic devices
–Hard to define. Nearly any computing system other than a

desktop computer
–Billions of units produced yearly, versus millions of
desktop units
–Perhaps 50 per household and per automobile

EMBEDDED SYSTEMS

Embedded systems
are in here

EMBEDDED SYSTEMS
Introduction
and here.
to Embedded Systems

EMBEDDED SYSTEMS
Introduction
and even
to Embedded Systems
here...
Almost everywhere
EMBEDDED SYSTEMS
Embedded System
Components
Hardware Software

EMBEDDED SYSTEMS
Embedded System Hardware
Digital Analog
Converters
Components Components

EMBEDDED SYSTEMS
Embedded System Software
Application Exception
Programs Handlers

EMBEDDED SYSTEMS

Digital
Components
Processors CPU Memories Buses Peripherals

EMBEDDED SYSTEMS
Analog
Components
Controllers
Sensors Actuators
( IO Ports)

EMBEDDED SYSTEMS
Converters
Analog-Digital Digital-Analog
ADC DAC

EMBEDDED SYSTEMS
Thank You
bkommey.coe@knust.edu.gh
nii_kommey@msn.com
Tel: 050 770 32 86

Whatsup: 050 7703286
Skype_id: calculus.affairs

EMBEDDED SYSTEMS
“Don’t forget your history and

know your destiny”
Robert Nasta Marley

EMBEDDED SYSTEMS
Overview
Processor CPU
Classifications Types

EMBEDDED SYSTEMS
Overview
Processor Classifications
Application
Application
General Single Specific Int.
Specific IC,
Purpose (GP) Purpose (SP) Processor,
(ASIC)
(ASIP)

EMBEDDED SYSTEMS
Overview
Processor Types
Digital Signal
Microprocessor Microcontroller
Processor
(uP) (uC)
(DSP)

EMBEDDED SYSTEMS
Processors
The Central Processing Unit CPU is the most important
component in embedded system.
The CPU exists in integrated form along with memory
and other peripherals
A processor is an artifact that computes or run
algorithms.
It has a controller and data path
EMBEDDED SYSTEMS
Processors
Processors classifications
- General purpose processor (GP)

- Single purpose processor (SP)
- Application Specific Integrated Circuits (ASIC)
- Application Specific Integrated Processor (ASIP)
EMBEDDED SYSTEMS
General Purpose Processors
General Purpose A GP is a programmable device used

Processor in a variety of application
• It is usually called a microprocessor
• It does variety of computation tasks
• It has functional flexibility and low cost at high volumes
• Slow and power hungry

EMBEDDED SYSTEMS
General Purpose Processors
GP Features Program Memory

• Data path with large register file
• Arithmetic Logic Unit ALU
Benefits Low time-to-market

• Examples: Intel Pentium, AMD Athlon, Freescale PowerPC

EMBEDDED SYSTEMS
Single Purpose Processors

Single purpose (SP) processors on the other hand,
- Performs one particular computation task
-Fast and power efficient
-Functional inflexibility
-high cost at low volumes

EMBEDDED SYSTEMS
Application-Specific Integrated Circuits ASIC

Digital circuit designed to execute exactly one program
It may contain coprocessor and or hardware accelerator
Features
- contains only the components needed to execute a single program
- No program memory
Benefits
- Fast
- Low power
- Small size
EMBEDDED SYSTEMS
Application-Specific Integrated Circuits ASIC

Custom-designed circuits necessary if
ultimate speed or energy efficiency is the goal
and large numbers can be sold
Approach suffers from long design times and

high costs

EMBEDDED SYSTEMS
GP vrs. ASIC
GP: ASIC:
• Programmable controller • Hardwired controller
• Control logic is stored in memory • No need for program memory
• Fetch / decode overhead and cache
• General data-path • No fetch / decode overhead
• Typical bit-width (8, 16, 32, 64) • Highly tuned data-path
• Complete set of ALU • Custom bit-width
• Large set of registers • Custom ALU
• Custom set of registers
EMBEDDED SYSTEMS
Application-specific Int. Processor (ASIP)

Are programmable processors optimized for a particular
ASIP class of application having common characteristics
• It is a comprise between general-purpose and ASIC (custom hardware)
Features Program memory

• Optimized data path
• Special functional units
EMBEDDED SYSTEMS
ASIP
ASIP Benefits Some flexibility
• Good performance, size and powerExamples
Examples DSP, Video Signal Processor, Network Processor

EMBEDDED SYSTEMS
Digital Signal Processor (DSP)

DSP is designed based on the modified Harvard Architecture to
handle real-time signals
The features of these processors are suitable for implementing signal
processing algorithms
DSP – a modified Harvard

Architecture
EMBEDDED SYSTEMS
DSP Characterization
Microprocessors specialized for signal processing applications
Harvard architecture
Two to Four memory accesses per cycle
Dedicated hardware performs all key arithmetic operations in 1 cycle
Very limited SIMD(Single Instruction Multiple Data) features and

Specialized, complex instructions
Multiple operations per instruction
Dedicated address generation units
EMBEDDED SYSTEMS
DSP Characterization
Specialized addressing
Hardware looping.
Interrupts disabled during certain operations
Limited or no register Shadowing
Rarely have dynamic features
Relatively narrow range of DSP oriented on-chip
peripherals and I/O interfaces
Synchronous serial port
EMBEDDED SYSTEMS
Microprocessor
A microprocessor is a general purpose digital computer central processing unit
It contains:
Arithmetic Logic Unit ALU
Program Counter PC
Stack Pointer SP
Working Registers
Clock Timing Circuit and
Interrupt Circuit

EMBEDDED SYSTEMS
Microcontroller (uC)
A microcontroller is a true computer on a chip.
uC incorporates all the features found in a microprocessor

(ALU, PC, SP and Registers)
uC has added features needed to make a complete

computer (ROM, RAM, Parallel IO, Serial IO, and Counters)
EMBEDDED SYSTEMS
Microcontroller (uC) Blockdiagram

EMBEDDED SYSTEMS
uC vary in data size 8 bit uC
4 bit uC Examples
Examples Intel 8051
Hitachi HMCS40 Motorola 68HC11
Toshiba TLCS47 TI TMS7500
National COP420 Atmel ATmega128
TI TMS1000

EMBEDDED SYSTEMS
16 bit uC 32 bit uC
Examples Examples
Hitachi H8/532 Intel 80960
Intel 8096 Freescale/Motorola
National HPC16164 PowerPC
ARM Cortex

EMBEDDED SYSTEMS
Microprocessor vrs. Microcontroller

Microprocessor is concerned with rapid movement of code and data from
external addresses to the chip.
Microcontroller is concerned with rapid movement of bits within the chip
Microcontroller can function as a computer with no addition of external

digital parts
Microprocessor must have many additional parts to be operational

EMBEDDED SYSTEMS
The CPU

EMBEDDED SYSTEMS
The CPU
Converts data into information
Control center
Set of electronic circuitry that executes stored program
instructions
Two parts
Control Unit (CU)
Arithmetic Logic Unit (ALU)
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Control Unit CU
Part of the hardware that is in-charge
Directs the computer system to execute stored program

instructions
Communicates with other parts of the hardware

EMBEDDED SYSTEMS
Arithmetic / Logic Unit ALU
Performs arithmetic operations

Performs logical operations

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Arithmetic Operations
Addition
Subtraction
Multiplication
Division

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Logical Operations
Evaluates conditions
Makes comparisons
Can compare
Numbers
Letters
Special characters

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Registers
Special-purpose
High-speed
Temporary storage
Located inside CPU
Instruction register
Holds instruction Data register
currently being Holds data waiting to be processed
executed
Holds results from processing

EMBEDDED SYSTEMS
Secondary
Types of Storage
Data that will eventually be used
Long-term
Memory
Data that will be used in the near future
Temporary
Faster access than storage
Registers
Data immediately related to the operation being executed
Faster access than memory
EMBEDDED SYSTEMS
Measuring Storage Capacity

KB – kilobyte GB – gigabyte
•1024 bytes •Billion bytes
•Some diskettes •Hard disks
•Cache memory •CDs and DVDs
TB – terabytes
MB – megabyte •Trillion bytes
•Million bytes •Large hard disks
•RAM
EMBEDDED SYSTEMS
Executing Programs
CU gets an instruction and places it in memory
CU decodes the instruction
CU notifies the appropriate part of hardware to
take action
Control is transferred to the appropriate part of

hardware
Task is performed
Control is returned to the CU
EMBEDDED SYSTEMS
Machine Cycle
I-time
CU fetches an instruction from memory and puts it into a register
CU decodes the instruction and determines the memory location of

the data required

EMBEDDED SYSTEMS
Machine Cycle
E-time
Execution
CU moves the data from memory to registers in the
ALU
ALU is given control and executes the instruction
Control returns to the CU
CU stores the result of the operation in memory

or in a register
EMBEDDED SYSTEMS
System Clock
System clock produces pulses at a fixed rate
Each pulse is one Machine Cycle
One program instruction may actually be several instructions to the

CPU
Each CPU instruction will take one pulse

CPU has an instruction set – instructions that it can understand and
process
EMBEDDED SYSTEMS
Data Representation On/Off

Binary number system is used to
represent the state of the circuit

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Bit, Byte, Word

BIT
Binary DigIT
On/off circuit
1 or 0
BYTE
8 bits
Store one alphanumeric character
WORD
Size of the register
Number of BITS that the CPU processes as a unit

EMBEDDED SYSTEMS
Coding Schemes
ASCII
Uses one 8 bit byte
28 = 256 possible combinations or characters
Virtually all PCs and many larger computers

EMBEDDED SYSTEMS
Coding Schemes
EBCDIC
Uses one 8 bit byte
28 =256 possible combinations or characters
Used primarily on IBM-compatible mainframes

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Coding Schemes
Unicode
Uses two 8 bit bytes (16 bits)
216 = 65,536 possible combinations or characters
Supports characters for all the world’s languages
Downward-compatible with ASCII

EMBEDDED SYSTEMS
Microprocessor Components
Control Unit – CU
Arithmetic / Logic Unit – ALU
Registers
System clock
EMBEDDED SYSTEMS
Bus Line
Paths that transport electrical signals
System bus
Transports data between the CPU and memory
Bus width
Number of bits of data that can be carried at a time
Normally the same as the CPUs word size
Speed measured in MHz

EMBEDDED SYSTEMS
Speed and Power

What makes a computer fast?
Microprocessor speed
Bus line size
Availability of cache
Flash memory
RISC computers
Parallel processing
EMBEDDED SYSTEMS
Computer Processing Speed

Time to execute an instruction
Millisecond
Microsecond
Nanosecond
Modern computers
Picosecond
In the future

EMBEDDED SYSTEMS
Microprocessor Speed
Clock speed
Megahertz (MHz)
Gigahertz (GHz)
Number of instructions per second
Millions of Instructions Per Second (MIPS)
Performance of complex mathematical operations
One million floating-point operations per second (Megaflop )

EMBEDDED SYSTEMS
Instruction Sets
CISC Technology
Complex Instruction Set Computing
Conventional computers
Many of the instructions are not used

EMBEDDED SYSTEMS
Instruction Sets
RISC Technology
Reduced Instruction Set Computing
Small subset of instructions
Increases speed
Programs with few complex instructions
Graphics
Engineering
EMBEDDED SYSTEMS
Types of Processing
Serial processing
Execute one instruction at a time
Fetch, decode, execute, store

EMBEDDED SYSTEMS
Types of Processing
Parallel Processing
Multiple processors used at the same time
Can perform trillions of floating-point
instructions per second (teraflops)
Ex: network servers, supercomputers
EMBEDDED SYSTEMS
Types of Processing
Pipelining
Instruction’s action need not be complete before the next begins
Fetch instruction 1, begin to decode and fetch instruction 2
EMBEDDED SYSTEMS
Thank You
nii_kommey@msn.com
Tel. 050 770 32 86

Whatsup: 0507703286

EMBEDDED SYSTEMS
“In the abundance of water, the

fool is thirsty”
Robert Nasta Marley

EMBEDDED SYSTEMS
Overview
Memory
Memory Memory Virtual

Definition
Types Management Memory

EMBEDDED SYSTEMS
Overview
Memory
Definition
Storage-
Writeability
permanance

EMBEDDED SYSTEMS
Overview
Memory
Types
ROM RAM
OTP
ROM EPROM EEPROM
ROM
SRAM/
Flash NVRAM
DRAM
EMBEDDED SYSTEMS
Memories
What is a memory?
-Artifact that stores bits
-Storage fabric and access logic
Write-ability
-Manner and speed a memory can be written
Storage-permanence
-ability of memory to hold stored bits after they are written
Different types of memories
-Flash, SRAM, DRAM, etc.
EMBEDDED SYSTEMS
Storage Write-ability
High End
• Processor writes to memory simply and quickly e.g. RAM
Middle Range
• Processor writes to memory, but slower e.g. FLASH, EEPROM
Lower range
• Special equipment, “programmer”, must be used to write to memory e.g. EPROM, OTP ROM
Low end
• Bits stored only during fabrication e.g. Mask-programmed ROM
EMBEDDED SYSTEMS
Storage Permanance
High End
• Essentially never loses bits e.g. mask-programmed ROM
Middle Range
• Holds bits days/months/years after memory’s power source turned off e.g. NVRAM
Lower Range
• Holds bits as long as power supplied to memory e.g. SRAM
Low End
• Begins to lose bits almost immediately after written e.g. DRAM
EMBEDDED SYSTEMS
Storage Write-ability and Permanence

EMBEDDED SYSTEMS
Memory Capacity & Organization

The number of bits that a semiconductor memory chip can store is called chip
capacity.
It can be in units of Kbits (kilobits), Mbits (megabits), and so on.
Memory chips are organized into a number of locations within the IC.
Each location can hold 1 bit, 4 bits, 8 bits, or even 16 bits, depending on how it is
designed internally.

EMBEDDED SYSTEMS
Memory Speed
Speed
The speed of the memory chip is commonly
referred to as its access time.
The access time of memory chips varies

from a few nanoseconds to hundreds of
nanoseconds, depending on the IC
technology used in the design and
fabrication process. Powers of 2
EMBEDDED SYSTEMS
Memory Types
ROM (read-only memory)
ROM is a type of memory that does not lose its contents when the
power is turned off.
For this reason, ROM is also called nonvolatile memory.
PROM (programmable ROM) and OTP

PROM is programmed by blowing the fuses.
If the information burned into PROM is wrong, that PROM must be
discarded since its internal fuses are blown permanently.
EMBEDDED SYSTEMS
Memory Types
EPROM (erasable programmable ROM) and UV-EPROM
Pin Configurations for 27xx ROM Family

EMBEDDED SYSTEMS
Memory Types
EEPROM (electrically erasable programmable ROM)
Some EEPROM and Flash Chips

EMBEDDED SYSTEMS
Memory Types
Flash memory EPROM
flash memory can be programmed while it is in its socket on the

system board, it is widely used to upgrade the BIOS ROM of the
PC.
flash memory is semiconductor memory with access time in the

range of 100 ns compared with disk access time in the range of
tens of milliseconds.
EMBEDDED SYSTEMS
Memory Types
Mask ROM
Mask ROM refers to a kind of ROM in which the contents are

programmed by the IC manufacturer.
Mask ROM is used when the needed volume is high

(hundreds of thousands) and it is absolutely certain that the
contents will not change.
EMBEDDED SYSTEMS
Memory Types
RAM (random access memory)
RAM memory is called volatile memory since cutting off the power to the IC
results in the loss of data.
SRAM (static RAM)
Storage cells in static RAM memory are
made of flip-flops and therefore do not
require refreshing in order to keep their
data.
This is in contrast to DRAM.

2Kx8 SRAM Pins

EMBEDDED SYSTEMS
Memory Types
NV-RAM (nonvolatile RAM)
New type of nonvolatile RAM called
NV-RAM.
Like other RAMS, it allows the CPU to

read and write to it, but when the
power is turned off the contents are
not lost.
Some SRAM and NV-RAM Chips
EMBEDDED SYSTEMS
Memory Types
Checksum byte ROM
checksum will detect any corruption of the contents of ROM
DRAM (dynamic RAM)
uses a capacitor to store each bit requires

constant refreshing due to leakage
256Kx1 DRAM

EMBEDDED SYSTEMS
Memory Types
DRAM organization
Packaging issue in DRAM

In DRAM there is a problem of packing a large number of cells into
a single chip with the normal number of pins assigned to addresses

EMBEDDED SYSTEMS
Memory Address Decoding

Simple logic gate address decoder
Logic Gate as Decoder

EMBEDDED SYSTEMS
Memory Address Decoding

Using the 74LS138 3-8 decoder
74LS138 as Decoder
74LS138 Decoder
EMBEDDED SYSTEMS
8051 Interfacing With External ROM

EA pin
Connect the EA pin to Vcc to indicate
that the program code is stored in the
µC's on-chip ROM.
To indicate that the program code is

stored in external ROM, this pin must be
connected to GND. 8051 Pin Diagram
EMBEDDED SYSTEMS
8051 Interfacing With External ROM

P0 and P2 role in providing addresses
74LS373 D Latch
Address/Data Multiplexing
EMBEDDED SYSTEMS
8031/51 Interfacing With External ROM
Data, Address, and Control Buses for the 8031 8031 Connection to External Program ROM

EMBEDDED SYSTEMS
8031/51 Interfacing With External ROM
PSEN
On-chip and Off-chip Program Code Access
On-chip and off-chip code ROM
In such a system we still have EA = Vcc, meaning that upon reset the 8051
executes the on-chip program first; then, when it reaches the end of the on-
chip ROM it switches to external ROM for the rest of the program code.
EMBEDDED SYSTEMS
8051 Data Memory Space
Data memory space
8051 Connection to External Data ROM

External ROM for data
For the ROM containing the program code, PSEN is used to fetch the code.
For the ROM containing data, the RD signal is used to fetch the data.
EMBEDDED SYSTEMS
MOVX instruction
8031 Connection to External Data ROM and External Program ROM

EMBEDDED SYSTEMS
MOVX instruction for external RAM data
8051 Connection to External Data RAM

EMBEDDED SYSTEMS

A single external ROM for code and data
A Single ROM for Both Program and Data

EMBEDDED SYSTEMS
8031 system with ROM and RAM
8031 Connection to External Program ROM, Data RAM, and Data ROM
EMBEDDED SYSTEMS

Interfacing to large external memory
8051 Accessing 256Kx8 External NV-RAM

EMBEDDED SYSTEMS

ACCESSING 1 K-BYTE SRAM IN ASSEMBLY
PMR Register Bits for 1K-byte SRAM of DS89C4x0 Chip

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Memory Management
We have two kinds of memory management: (static and
dynamic)
Static
provides tasks with temporary data space.
The system’s free memory is divided into a pool of fixed sized
memory blocks.
When a task finishes using a memory block it must return it to
the pool.
EMBEDDED SYSTEMS
Memory Management
Another way is to provide temporary space for tasks is

via priorities:
A high priority pool : is sized to have the worst-case
memory demand of the system
A low priority pool : is given the remaining free memory
EMBEDDED SYSTEMS
Memory Management
Dynamic
employs memory swapping, overlays, multiprogramming with
a fixed number of tasks (MFT), multiprogramming with a
variable number of tasks (MVT) and demand paging.
Overlays allow programs larger than the available memory to

be executed by partitioning the code and swapping them from
disk to memory.
EMBEDDED SYSTEMS
Memory Management
MFT: a fixed number of equalized code parts are in
memory at the same time.
MVT: is like MFT except that the size of the partition
depends on the needs of the program.
Demand paging : have fixed-size pages that reside in

non-contiguous memory, unlike those in MFT and MVT
EMBEDDED SYSTEMS
Memory Allocation
is the process of assigning blocks of memory on request
Memory for user processes is divided into multiple

partitions of varying sizes.
Hole : is a block of available memory.

EMBEDDED SYSTEMS
Memory Allocation
Static Memory Allocation
means that all memory is allocated to each process or thread when

the system starts up. In this case, you never have to ask for memory
while a process is being executed. This is very costly.
The advantage of this in embedded systems is that the whole issue of

memory-related bugs-due to leaks, failures, and dangling pointers-
simply does not exist .
EMBEDDED SYSTEMS
Memory Allocation
Dynamic Memory Allocation
How to satisfy a request of size n from a list of free holes. This
means that during runtime, a process is asking the system for a
memory block of a certain size to hold a certain data structure.
Some RTOSs support a timeout function on a memory request.

You ask the OS for memory within a prescribed time limit
EMBEDDED SYSTEMS
Memory Allocation
Buddy Memory Allocation

allocates memory in powers of 2
it only allocates blocks of certain sizes
has many free lists, one for each permitted size
EMBEDDED SYSTEMS
Dynamic Storage-Allocation Schemes

First-fit:
Allocate the first hole that is big enough, so it is fast
Best-fit:
Allocate the smallest hole that is big enough; must search entire list,
unless ordered by size.
Buddy:
it divides memory into partitions to try to satisfy a memory request as
suitably as possible.
EMBEDDED SYSTEMS
Thank You
nii_kommey@msn.com
Tel: 050 770 32 86

Whatsup: 0507703286

EMBEDDED SYSTEMS
“Only a fool lean up on his own

misunderstanding”
Robert Nasta Marley

EMBEDDED SYSTEMS
Overview
Peripherals
Stepper
Timers Counters Watchdog UART PWM LCD Keypad
Motor

EMBEDDED SYSTEMS
Peripherals
Perform specific computation task
Custom single-purpose processors, designed by for a unique

task
Standard single-purpose processors are “Off-the-shelf” and

pre-designed for a common task

EMBEDDED SYSTEMS
Timers
Timer is a very common and useful peripheral.
It is used to generate events at specific times or
measures duration of specific events which are external
to the processor
Timer is a programmable device i.e. the time period can
be adjusted by writing specific bit patterns to some
registers called timer control register
EMBEDDED SYSTEMS
Timers
Basic timer
16-bit up counter Cnt

Clk 16
Top
Reset

EMBEDDED SYSTEMS
Timers
In short, timers are used
measure time intervals
To generate timed output events
To measure input events
Top: max count reached
Timer has range and resolution eg. 8MHz 16 bit Timer
EMBEDDED SYSTEMS
Counter
Counter is like a timer, but counts pulses on a general
input signal rather than clock
Example
count cars passing over a sensor
can often configure device as either a timer or
counter
EMBEDDED SYSTEMS
Counter
Timer/counter
Clk
2x1 mux 16-bit up counter Cnt
16
Cnt_in Top
Reset
Mode

EMBEDDED SYSTEMS
Watchdog Timer
A watchdog timer is a safety feature, which resets the

processor if the program becomes stuck in infinite loop
It main function is to protect the system against

malfunctions

EMBEDDED SYSTEMS
UART
UART: Universal Asynchronous Receiver Transmitter
-Takes parallel data and transmits serially
-Receives serial data and converts to parallel
Parity:
extra bit for simple error checking
Start bit, stop bit
Baud rate
-Signal changes per second
-Bit rate, sometimes different
EMBEDDED SYSTEMS
Pulse Width Modulator PWM

PWM generates pulses with specific high/low times
Duty cycle: % time high
eg. Square wave: 50% duty cycle
Common use:
control average voltage to electric device ( Simpler than DC-DC
converter or digital-analog converter), dc motor speed, dimmer
lights
EMBEDDED SYSTEMS
LCD
Liquid Crystal Display

N rows by M columns
Controller build into the LCD module
Simple microprocessor interface using ports
Software controlled
EMBEDDED SYSTEMS
Keypad
N1
N2
N3 k_pressed
N4
M1
M2
M3
M4 4
key_code key_code
keypad controller
N=4, M=4
EMBEDDED SYSTEMS
Stepper Motor Controller

Stepper motor:
rotates fixed number of degrees when given a “step” signal
In contrast, DC motor just rotates when power applied, coasts
to stop
Rotation achieved by applying specific voltage sequence to
coils
Controller greatly simplifies this
EMBEDDED SYSTEMS
Analog Components - Sensors

Microprocessors see what is happening in the real world via
sensors
Types of sensors
- Temperator sensor
- Optical sensors
- Magnetic sensors
- Motion / acceleration sensors
- Sound sensors
- Pressure sensors
EMBEDDED SYSTEMS
Analog Components
Sensors and actuators are the bridge between cyber

(digital, discrete in time, sequential)
and physical (continuum, continuous, concurrent)

EMBEDDED SYSTEMS
Analog Components
Example of sensors:
Cameras, accelerometers, microphones,

magnetometers, radar, chemical sensors,
pressure sensors, switches,
photoresistors,compass
EMBEDDED SYSTEMS
Analog Components
Example of actuators:
Motor controllers, solenoids, LEDs,

laser, LCD, Plasma displays,
loudspeakers, valves, relays, buzzers
EMBEDDED SYSTEMS
BUSes
BUS
• An artifact that transfers bits. It could be wires, air, or fiber and interface
logic
Bus Connectivity Scheme
• Serial Communication, Parallel Communication or Wireless

Communication

EMBEDDED SYSTEMS
BUSes
BUS
Protocols
• Ports
• Timing Diagrams
• Read and write cycles
Others
• Arbitration scheme, error detection/correction, DMA, etc.

EMBEDDED SYSTEMS
Wireless Communication
Infrared (IR)
Electronic wave frequencies just below visible light spectrum
Diode emits infrared light to generate signal
Infrared transistor detects signal, conducts when exposed to infrared
light
Cheap to build
Need line of sight, limited range
EMBEDDED SYSTEMS
Radio frequency (RF)
Electromagnetic wave frequencies in radio spectrum
Analog circuitry and antenna needed on both
sides of transmission
Line of sight not needed, transmitter power

determines range
EMBEDDED SYSTEMS
Serial Communication
A single wire used for data transfer
One or more additional wires used for control
(but, some protocols may not use additional control
wires)
Higher throughput for long distance communication,
often across processing node
Lower cost in terms of wires (cable)
Examples: USB, Ethernet, RS232, I2C, etc.
EMBEDDED SYSTEMS
Parallel Communication
Multiple buses used for data transfer
One or more additional wires used for control
Higher throughput for short distance communication
• Data misalignment problem
• Often used within a processing node
Higher cost in terms of wires (cable)
Example: ISA, AMBA, PCI, etc.

EMBEDDED SYSTEMS
Other Timer Structures 16/32-bit timer
Interval timer Timer with a terminal

Clk 16-bit up
counter 16 Cnt1
Indicates when desired time count
16-bit up
Top1
interval has passed

Clk
counter 16 Cnt
16-bit up Cnt2
counter 16
We set terminal count to =

Reset Top2
desired interval Top Time with prescaler
Prescaler 16-bit up
Clk
counter
Number of clock cycles =

Terminal count
Desired time interval / Mode
Clock period
EMBEDDED SYSTEMS
Other Timer Structures 16/32-bit timer
Cascaded counters Timer with a terminal

Clk 16-bit up
counter 16 Cnt1
count
Top1
Clk 16-bit up
counter 16 Cnt
16-bit up
Prescaler 16 Cnt2
counter
Reset Top2
Divides clock =
Top Time with prescaler
Increases range, Clk Prescaler 16-bit up
decreases resolution
counter
Terminal count
Mode

EMBEDDED SYSTEMS
Example: Reaction Timer

indicator light reaction button
LCD time: 100 ms
Measure time between turning light on and user pushing button

16-bit timer, clk period is 83.33 ns, counter increments every 6 cycles
Resolution = 6*83.33=0.5 microsec.

Range = 65535*0.5 microseconds = 32.77 milliseconds
Want program to count millisec., so initialize counter to 65535 –
1000/0.5 = 63535
EMBEDDED SYSTEMS
Example: Reaction Timer indicator

light
reaction
button
LCD time: 100 ms
/* main.c */ while (user has not pushed reaction button){

if(Top) {
#define MS_INIT 63535 stop timer
void main(void){ set Cnt to MS_INIT
int count_milliseconds = 0; start timer
reset Top
configure timer mode
count_milliseconds++;
set Cnt to MS_INIT
}
wait a random amount of time }
turn on indicator light turn light off
start timer printf(“time: %i ms“, count_milliseconds);
}
EMBEDDED SYSTEMS
Watchdog Timer
osc clk overflow overflow
to system reset
prescaler scalereg timereg or
interrupt
checkreg
Must reset timer every X time unit, else timer generates a signal
Common use: detect failure, self-reset
Another use: timeouts
e.g., ATM machine
16-bit timer, 2 microsec. resolution
timereg value = 2*(216-1)–X = 131070–X ; For 2 min., X = 120,000 microsec.
EMBEDDED SYSTEMS
Watchdog Timer
/* main.c */ watchdog_reset_routine(){
/* checkreg is set so we can load
main(){ value into timereg. Zero is loaded
wait until card inserted into scalereg and 11070 is loaded into
call watchdog_reset_routine timereg */
while(transaction in progress){ checkreg = 1

if(button pressed){ scalereg = 0
perform corresponding action timereg = 11070
call watchdog_reset_routine }
}
void interrupt_service_routine(){
/* if watchdog_reset_routine not called every < 2 minutes, eject card
interrupt_service_routine is called */ reset screen
} }

EMBEDDED SYSTEMS
Serial Transmission Using UARTs

embedded device
1 1 0 1
0 1
0 1
1 0 0 1 1 0 1 1 1 0 0 1 1 0 1 1
Sending UART Receiving UART

start bit end bit
data
1 0 0 1 1 0 1 1

EMBEDDED SYSTEMS
Controlling a DC motor with a PWM

5V
void main(void){
/* controls period */
PWMP = 0xff;
From
/* controls duty cycle */ processor DC
MOTOR
PWM1 = 0x7f;
while(1){};
} 5V
The PWM alone cannot drive the DC motor,
a possible way to implement a driver is
using an MJE3055T NPN transistor. A
B
EMBEDDED SYSTEMS
LCD Controller
E communications bus
R/W
RS
DB7–DB0
8
microcontroller LCD controller

EMBEDDED SYSTEMS
LCD Controller
CODES
I/D = 1 cursor moves left DL = 1 8-bit
I/D = 0 cursor moves right DL = 0 4-bit
S = 1 with display shift N = 1 2 rows
S/C =1 display shift N = 0 1 row
S/C = 0 cursor movement F = 1 5x10 dots
R/L = 1 shift to right F = 0 5x7 dots
R/L = 0 shift to left

EMBEDDED SYSTEMS
LCD Controller
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description
0 0 0 0 0 0 0 0 0 1 Clears all display, return cursor home
0 0 0 0 0 0 0 0 1 * Returns cursor home
Sets cursor move direction and/or

0 0 0 0 0 0 0 1 I/D S
specifies not to shift display
ON/OFF of all display(D), cursor
0 0 0 0 0 0 1 D C B
ON/OFF (C), and blink position (B)
0 0 0 0 0 1 S/C R/L * * Move cursor and shifts display
Sets interface data length, number of

0 0 0 0 1 DL N F * *
display lines, and character font
1 0 WRITE DATA Writes Data
void WriteChar(char c){
RS = 1; /* indicate data being sent */

DATA_BUS = c; /* send data to LCD */
EnableLCD(45); /* toggle the LCD with appropriate delay */
}
EMBEDDED SYSTEMS
Thank You
nii_kommey@msn.com
Tel: 050 770 32 86

Whatsup: 0507703286

EMBEDDED SYSTEMS
“The exhibition of true wisdom

has to do with practical solutions
to problems and not theoretical
proposals”
Mensah Otabil

EMBEDDED SYSTEMS
Converters
Converters
Analog-Digital Digital-Analog
Converters ADC Converters DAC

EMBEDDED SYSTEMS
Converters
Analog-Digital
Converters ADC
Successive Integrating
Tracking Sigma-
Flash ADC Approximation (Dual-
ADC Delta ADC
ADC Slope) ADC

EMBEDDED SYSTEMS
Converters
Digital-Analog
Converters DAC
AD7801 ADV7120

EMBEDDED SYSTEMS
Analog-Digital Converters ADC

ADCs are used to bring analog input to microcontroller
An ADC accepts an analog input, a voltage or a current and
converts it to a digital word that can be read by
microcontroller.
ADC has two input pins i.e. A reference pin (maximum value
that the ADC can convert) and the signal to be measured.
EMBEDDED SYSTEMS
Analog-Digital Converters ADC

It has one output pin, a digital word that represents
in digital form the input value

EMBEDDED SYSTEMS
ADC – Input-Output Graph

The step size of y bit ADC is defined by Reference input/2y and
is called the ADC resolution

EMBEDDED SYSTEMS
ADC – Resolution
The resolution of an ADC is determined by the

reference input and the word width.
The resolution defines the smallest voltage change

that can be measured by the ADC.
EMBEDDED SYSTEMS
ADC Types
Types of ADC
- Tracking ADC
- Flash ADC
- Successive Approximation ADC
- Integrating (Dual-Slope) ADC
- Sigma-Delta ADC
EMBEDDED SYSTEMS
Tracking ADC

EMBEDDED SYSTEMS
Tracking ADC
The tracking ADC has a comparator, a counter and a DAC
The comparator compares the input voltage to the DAC output
voltage
If input is higher than the DAC voltage, the counter counts up
If input is lower than the DAC voltage, the counter counts
down
The drawback of a tracking ADC is speed
EMBEDDED SYSTEMS
Flash ADC
The flash ADC is the fastest type available.

A flash ADC has one comparator per voltage step.
EMBEDDED SYSTEMS
Flash ADC
A 4-bit ADC will have 16 comparators, an 8-bit ADC will have 256
comparators.
One input of all the comparators is connected to the input to be
measured.
The other input of each comparator is connected to one point in a
string of resistors.
As you move up the resistor string, each comparator trips at a higher
voltage.

EMBEDDED SYSTEMS
Flash ADC
All of the comparator outputs connect to a block of logic that
determines the output based on which comparators are low
and which are high.
The conversion speed of the flash ADC is the sum of the

comparator delays and the logic delay.
Flash ADCs are very fast, but take enormous amounts of IC real
estate to implement.
EMBEDDED SYSTEMS
Successive Approximation ADC

EMBEDDED SYSTEMS
Successive Approximation ADC

The successive approximation converter is similar to the tracking ADC
in that a DAC/counter drives one side of a comparator and the input
drives the other.
The difference is that the successive approximation register performs a

binary search instead of just counting up or down by one

EMBEDDED SYSTEMS
Integrating (Dual-Slope) ADC

EMBEDDED SYSTEMS
A dual-slope converter uses an integrator followed by a

comparator, followed by counting logic.
The integrator input is first switched to the input signal, and

the integrator output charges toward the input voltage.
EMBEDDED SYSTEMS
After a specified number of clock cycles, the integrator input is

switched to a reference voltage and the integrator charges down
toward this value.
When the switch occurs to VREF1, a counter is started, and it counts

using the same clock that determined the original integration time.

EMBEDDED SYSTEMS

When the integrator output falls past a second reference voltage
VREF2, the comparator output goes high, the counter stops, and the
count represents the analog input voltage.
Higher input voltages will allow the integrator to charge to a higher

voltage during the input time, taking longer to charge down to VREF2,
and resulting in a higher count at the output.
Lower input voltages result in a lower integrator output and a smaller

count
EMBEDDED SYSTEMS
Sigma-Delta ADC

EMBEDDED SYSTEMS
Sigma-Delta ADC
The input signal passes through one side of a differential amp,

through a low-pass filter (integrator), and on to a comparator.
The output of the comparator drives a digital filter and a 1-bit

DAC.

EMBEDDED SYSTEMS
Sigma-Delta ADC
The DAC output can switch between -V and V.
The output of the DAC drives the other side of the differential amp, so
the output of the differential amp is the difference between the input
voltage and the DAC output.

EMBEDDED SYSTEMS
Digital-Analog Converter DAC

DACs convert a digital word to a corresponding analog voltage
or current
A DAC is at the heart of most ADCs
DAC applications range from controlling the reference of a
voltage comparator to simulating a sine wave
Analog Device AD7801 is a typical 8 bit voltage output AD7801
EMBEDDED SYSTEMS
Digital-Analog Converter DAC

There are specialized DACs available, eg. ADV7120 is a
DAC designed for video use.
ADV7120 contains three DACs for RGB video signals
Other specialized DACs include audio parts with built-in
volume control and mute functions
There are also DACs that are optimized for use in voice
transmission system like the phone
EMBEDDED SYSTEMS
Thank You
nii_kommey@msn.com
050 770 32 86
Whatsup: 0507703286

EMBEDDED SYSTEMS
“Emancipate yourselves from

mental slavery. None but
ourselves can free our minds”
Robert Nasta Marley

EMBEDDED SYSTEMS
Overview
Embedded
Software
Embedded System Embedded C

Programing Languages Programming
Machine
Assembly C
Code
EMBEDDED SYSTEMS
Software
Several languages used for programming microcontrollers
- Machine language
- Assembly language
- C
- C++
- Basic
EMBEDDED SYSTEMS
Machine Code
Machine code is a binary data that the microcontroller itself
understands
Each instruction has a binary value called opcode
Example: light LED
40B2 5A80 0120
42F2 0029
40F2 0018 002A
EMBEDDED SYSTEMS
Assembly
Instructions are written in words called mnemonics
A program called assembler translates the mnemonics into
machine code
Example: light LED
ORG 0xF000 ; Start of 4KB flash memory
Reset: ; Execution starts here
mov.w #WDTPW|WDTHOLD ,& WDTCTL ; Stop watchdog timer
mov.b #00001000b,& P2OUT ; LED2 (P2.4) on , LED1 (P2.3) off (active low!)
mov.b #00011000b,& P2DIR ; Set pins with LEDs to output
InfLoop: ; Loop forever ...
jmp InfLoop ; ... doing nothing
;-----------------------------------------------------------------------
ORG 0xFFFE ; Address of MSP430 RESET Vector
DW Reset ; Address to start execution
END
EMBEDDED SYSTEMS
Embedded C Programming
C is the most common choice for microcontroller

programming
A compiler translates C into machine code that the CPU can

process

EMBEDDED SYSTEMS
Embedded C Programming
Example: light LED

void main (void)
{
WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer
P2DIR = 0x18; // Set pins with LEDs to output , 0b00011000
P2OUT = 0x08; // LED2 (P2.4) on , LED1 (P2.3) off (active low!)
for (;;) { // Loop forever ...
} // ... doing nothing
}
EMBEDDED SYSTEMS
Criteria For Choosing a Microcontroller

Meeting the computing needs of the task at hand efficiently and cost effectively
Speed
Packaging
Power consumption
The amount of RAM and ROM on chip
The number of I/O pins and the timer on chip
How easy to upgrade to higher performance or lower power-consumption
versions
Cost per unit
EMBEDDED SYSTEMS
Availability of software development tools, such as

compilers, assemblers, and debuggers
Wide availability and reliable sources of the

microcontroller
EMBEDDED SYSTEMS

The 8051 family has the largest number of diversified (multiple source)
suppliers
Intel (original)
Atmel
Philips/Signetics
AMD
Infineon (formerly Siemens)
Matra
Dallas Semiconductor/Maxim
EMBEDDED SYSTEMS
8051 Microcontroller
Intel introduced 8051, referred as MCS-51, in 1981
The 8051 is an 8-bit processor

The CPU can work on only 8 bits of data at a time
The 8051 has
128 bytes of RAM
4K bytes of on-chip ROM
Two timers
EMBEDDED SYSTEMS
One serial port
Four I/O ports, each 8 bits wide
6 interrupt sources
The 8051 became widely popular after allowing

other manufactures to make and market any
flavor of the 8051, but remaining code-compatible
EMBEDDED SYSTEMS

EMBEDDED SYSTEMS
Various 8051 Microcontrollers

The 8051 is a subset of the 8052
The 8031 is a ROM-less 8051
Add external ROM to it
You lose two ports, and leave only 2 ports for I/O operations

EMBEDDED SYSTEMS
8751 microcontroller Various 8051 Microcontroller

UV-EPROM
PROM burner
UV-EPROM eraser takes 20 min to erase
AT89C51 from Atmel Corporation
Flash (erase before write)
ROM burner that supports flash
A separate eraser is not needed
DS89C4x0 from Dallas Semiconductor, now part of Maxim Corp.
Flash
Comes with on-chip loader, loading program to on-chip flash via PC COM port
EMBEDDED SYSTEMS
Various 8051 Microcontroller

DS5000 from Dallas Semiconductor
NV-RAM (changed one byte at a time),
RTC (real-time clock)
Also comes with on-chip loader
OTP (one-time-programmable) version of 8051

8051 family from Philips
ADC, DAC, extended I/O, and both OTP and flash
EMBEDDED SYSTEMS
8051 Programming in C
Compilers produce hex files that is downloaded to ROM
of microcontroller
The size of hex file is the main concern
Microcontrollers have limited on-chip ROM
Code space for 8051 is limited to 64K bytes
C programming is less time consuming, but has larger

hex file size
EMBEDDED SYSTEMS
8051 Programming in C
The reasons for writing programs in C
It is easier and less time consuming to write in C than
Assembly
C is easier to modify and update
You can use code available in function libraries
C code is portable to other microcontroller with little of no
modification
EMBEDDED SYSTEMS
Data Types
A good understanding of C data types for 8051 can help
programmers to create smaller hex files
Unsigned char
Signed char
Unsigned int
Signed int
Sbit (single bit)
Bit and sfr
EMBEDDED SYSTEMS
Data Type – unsigned char

The character data type is the most natural choice
8051 is an 8-bit microcontroller
Unsigned char is an 8-bit data type in the range of 0 – 255 (00
– FFH)
One of the most widely used data types for the 8051
Counter value
ASCII characters
C compilers use the signed char as the default if we do not put
the keyword unsigned
EMBEDDED SYSTEMS
Data Type Examples

Question
Write an 8051 C program to send values 00 – FF to port P1.
Solution:
#include <reg51.h>
void main(void)
{
unsigned char z;
for (z=0;z<=255;z++)
P1=z;}
EMBEDDED SYSTEMS
Question
Data Type Examples
Write an 8051 C program to send hex values for ASCII characters of 0, 1, 2, 3,
4, 5, A, B, C, and D to port P1.
Solution:
#include <reg51.h>
void main(void)
{
unsigned char mynum[] = “012345ABCD”;
unsigned char z;
for ( z = 0; z <= 10; z++)
P1 = mynum[z];}
EMBEDDED SYSTEMS
Question Data Type Examples

Write an 8051 C program to toggle all the bits of P1 continuously.
Solution:
//Toggle P1 forever
#include <reg51.h>
void main(void)
{
for (;;)
{
p1=0x55;
p1=0xAA;
}}
EMBEDDED SYSTEMS
Data Type – signed char

The signed char is an 8-bit data type
Use the MSB D7 to represent – or +
Give us values from –128 to +127
We should stick with the unsigned char, unless the

data needs to be represented as signed numbers
eg. Temperature
EMBEDDED SYSTEMS
Data Type – signed char

Write an 8051 C program to send values of –4 to +4 to port P1.
Solution:
//Signed numbers
#include <reg51.h>
void main(void)
{
char mynum[]={+1,-1,+2,-2,+3,-3,+4,-4};
unsigned char z;
for (z=0;z<=8;z++)
P1=mynum[z];
} 4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 211
EMBEDDED SYSTEMS
Data Type – unsigned and signed int

The unsigned int is a 16-bit data type
Takes a value in the range of 0 to 65535 (0000 – FFFFH)
Define 16-bit variables such as memory addresses
Set counter values of more than 256
Since registers and memory accesses are in 8-bit chunks,
the misuse of int variables will result in a larger hex file

EMBEDDED SYSTEMS
Data Type – unsigned and signed int
Signed int is a 16-bit data type
Use the MSB D15 to represent – or +
We have 15 bits for the magnitude of the number from –

32768 to +32767
EMBEDDED SYSTEMS
Time Delay
There are two ways to create a time delay in 8051 C
Using the 8051 timer

Using a simple for loop
be mindful of three factors that can affect the

accuracy of the delay
EMBEDDED SYSTEMS
Time Delay
The 8051 design
– The number of machine cycle
– The number of clock periods per machine cycle
The crystal frequency connected to the X1 – X2 input pins
Compiler choice
– C compiler converts the C statements and functions to Assembly
language instructions
– Different compilers produce different code
EMBEDDED SYSTEMS
Time Delay Example

Write an 8051 C program to toggle bits of P1 ports continuously with a 250 ms.
Solution:
#include <reg51.h>
void MSDelay(unsigned int); void MSDelay(unsigned int itime)
void main(void) {
{ unsigned int i,j;
while (1) //repeat forever for (i=0;i<itime;i++)
{p1=0x55; for (j=0;j<1275;j++);
MSDelay(250); }
p1=0xAA;
MSDelay(250);}}

EMBEDDED SYSTEMS
Time Delay Example

Write an 8051 C program to get a byte of data form P1, wait ½ second, and then send it to P2.
Solution:
#include <reg51.h>
void MSDelay(unsigned int);
void main(void)
{
unsigned char mybyte;
P1=0xFF; //make P1 input port
while (1){
mybyte=P1; //get a byte from P1
MSDelay(500);
P2=mybyte; //send it to P2}}
EMBEDDED SYSTEMS
Byte Size I/O Example

Write an 8051 C program to get a byte of data form P0. If it is less than 100, send it to P1; otherwise, send it to P2.
Solution:
#include <reg51.h>
void main(void)
{
P0=0xFF; //make P0 input port
while (1)
{
mybyte=P0; //get a byte from P0
if (mybyte<100)
P1=mybyte; //send it to P1
else
P2=mybyte; //send it to P2}}
EMBEDDED SYSTEMS
Bit Addressable I/O Example

The data pins of an LCD are connected to P1. The information is
latched into the LCD whenever its Enable pin goes from high to low.
Write an 8051 C program to send “The Earth is but One Country” to
this LCD.
Solution:
#include <reg51.h>
#define LCDData P1 //LCDData declaration
sbit En=P2^0; //the enable pin
EMBEDDED SYSTEMS
Bit Addressable I/O Example

void main(void)
{
unsigned char message[] =“The Earth is but One Country”;
unsigned char z;
for (z=0;z<28;z++) //send 28 characters
{
LCDData=message[z];
En=1; //a high-
En=0; //-to-low pulse to latch data
}}
EMBEDDED SYSTEMS
Logic Operations
Logical operators
AND (&&), OR (||), and NOT (!)
Bit-wise operators
AND (&), OR (|), EX-OR (^), Inverter (~),
Shift Right (>>), and Shift Left (<<)
These operators are widely used in software
engineering for embedded systems and control
EMBEDDED SYSTEMS
Logic Operations

EMBEDDED SYSTEMS
Logic Operations Example

Write an 8051 C program to toggle all the bits of P0 and P2
continuously with a 250 ms delay.
Using the inverting and Ex-OR operators, respectively.
Solution:
#include <reg51.h>
void MSDelay(unsigned int);
EMBEDDED SYSTEMS

void main(void)
{
P0=0x55;
P2=0x55;
while (1)
{
P0=~P0;
P2=P2^0xFF;
MSDelay(250);}}
EMBEDDED SYSTEMS

Write an 8051 C program to get bit P1.0 and send it to P2.7 after inverting it.
Solution:
#include <reg51.h>
sbit inbit =P1^0;
sbit outbit =P2^7;
bit membit;
void main(void)
{
while (1)
{
membit=inbit; //get a bit from P1.0
outbit=~membit; //invert it and send it to P2.7}}
EMBEDDED SYSTEMS
Data Conversion Example

Write an 8051 C program to convert packed BCD 0x29 to ASCII and display the bytes on P1 and P2.
Solution:
#include <reg51.h>
void main(void)
{
unsigned char x,y,z;
unsigned char mybyte = 0x29;
x =mybyte&0x0F;
P1 =x|0x30;
y =mybyte&0xF0;
y =y>>4;
P2 =y|0x30;}
EMBEDDED SYSTEMS
Data Conversion Example

Write an 8051 C program to calculate the checksum byte for the data 25H, 62H, 3FH, and 52H.
Solution:
#include <reg51.h>
void main(void){
unsigned char mydata[]={0x25,0x62,0x3F,0x52};
unsigned char sum=0;
unsigned char x;
unsigned char chksumbyte;
for (x=0;x<4;x++){
P2=mydata[x];
sum=sum+mydata[x];
P1=sum;
}
chksumbyte=~sum+1;
P1=chksumbyte;
}

EMBEDDED SYSTEMS
Accessing Code RAM

The 8051 C compiler allocates RAM locations
Bank 0 – addresses 0 – 7
Individual variables – addresses 08 and beyond
Array elements – addresses right after variables
Array elements need contiguous RAM locations and that
limits the size of the array due to the fact that we have only
128 bytes of RAM for everything
Stack – addresses right after array elements
EMBEDDED SYSTEMS
RAM Data Space Usage

Write, compile and single-step the following program on your 8051 simulator.
Examine the contents of the code space to locate the values.
Solution:
#include <reg51.h>
void main(void){
unsigned char mydata[100]; //RAM space
unsigned char x,z=0;
for (x=0;x<100;x++)
{
z--;
mydata[x]=z;
P1=z;
}}
EMBEDDED SYSTEMS
Data Serialization
Serializing data is a way of sending a byte of data one bit at a time
through a single pin of microcontroller
Using the serial port
Transfer data one bit a time and control the sequence of data and
spaces in between them
In many new generations of devices such as LCD, ADC, and ROM the
serial versions are becoming popular since they take less space on a
PCB
EMBEDDED SYSTEMS
Data Serialization Example

Write a C program to send out the value 44H serially one bit at a time via P1.0. The LSB should go out first.
Solution:
#include <reg51.h>
sbit P1b0=P1^0;
sbit regALSB=ACC^0;
void main(void){
unsigned char conbyte=0x44;
unsigned char x;
ACC=conbyte;
for (x=0;x<8;x++)
{
P1b0=regALSB;
ACC=ACC>>1;
}}
EMBEDDED SYSTEMS
Thank You
nii_kommey@msn.com
050 770 32 86
Whatsup: 0507703286

EMBEDDED SYSTEMS
“Who the cap fit, let him wear it”
Robert Nasta Marley

EMBEDDED SYSTEMS
Embedded System Development Demo
Embedded System
Development Demo
nanoLOC Embedded
Development PCB Layout
Development Development
Workflow Design
Kit Cycle

EMBEDDED SYSTEMS
Designer Workflow
Evaluation/Revision
/Release
Implementation
Lab Test
Develop prototype
Study requirements

EMBEDDED SYSTEMS
nanoLOC Development Kit
demo
goal content
application

EMBEDDED SYSTEMS
nanoLOC Development Kit

Goal
To demonstrate sample types of applications that could be
developed based on the nanoLOC wireless transceiver chip

EMBEDDED SYSTEMS
nanoLOC Transceiver Chip Features

Operation – 2.4GHz ISM Band license free – slave mode
Modulation – Chirp Spread Spectrum (CSS) technology
Data rate – 2Mbs to 125Kps programmable
MAC controller with CSMA/CA, TDMA and FDMA
Output power - -33dBm to 0dBm programmable
Power supply – 2.4V to 3.6V
Power down mode for increased current saving
Low shutdown current < 2uA
Receiver sensitivity – (-95dBm at BER 0.001 when FEC is off and -97dBm when FEC is on
FDMA with 3 non-overlapping frequency channels
32KHz Real Time Clock available
EMBEDDED SYSTEMS
nanoLOC Block Diagram

EMBEDDED SYSTEMS
Board Design - Brainstorming

EMBEDDED SYSTEMS
PWR Block Diagram-nanoLOC Board LEDs

LED
L1
Keys
L2
Power On/Off Voltage K1,K2,K3,K4
L3
supply switch regulator
L4
TX/RX L5
LED L6
PC connect L7
Serial IO nanoLOC TRX L8
ATmega128L
Light microcontroller Antenna
sensor
Temperature
sensor
PortD ADC/IO JTAG ISP PortB

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Electronic Components
Power supply socket – 2.1mm barrel connector for max 3.0V
power supply
Battery connector pin for 3.0V battery pack
Power On/Off switch
Power on LED to indicate power supply is on
Voltage regulator – dc-dc converter used to boost and supply
constant 3.3 output voltage
nanoLOC transceiver chip – slave -operates between 2.4V-3.6V
Antenna (SMA, SMD)
TX/RX LED to indicate transmission and reception activity
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ATmega128L microcontroller
– master -drives nanoLOC via SPI interface – operates between 2.7V-5.5V
PC connect-DE-9 D-sub connector for serial interface using RS232
Light sensor – light to digital converter TSL2561T
Temperature sensor (AD7814)
IEEE 1149.1 standard JTAG connector for flashing and debugging
purposes
In-System Programming (ISP) connector for on-chip in-system
programming
Six IO ports – ATmega128L provides portA to portF
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8 programmable activity LEDs – Anodes and cathodes
are connected to port via resistors to the ground
Reset button to reset microcontroller and additional
three user programmable buttons
A 32.768kHz quartz for timer or counter oscillator
A 7.3728MHz crystal quartz as an external oscillator
Pin access points for testing and measurements
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PCB Layout – Bill of Materials

Resistors • Crystal quartz
Capacitors • Microcontroller
Transistors • Voltage regulator
Diodes • RS232 connector
Inductors • RS232 driver
Buttons • Jumpers
SMA antenna • LEDs
Switch • Light sensor
nanoLOC RF chip • Temperature sensor
• Barrel connector
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Schematics – Power Supply

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Schematics – nanoLOC Chip

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Schematics – RS232/UART

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Schematics – ATmega128L

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Schematics – Sensors

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Schematics – Board Switch

Things to note
Budget
Dimensions and shape
Components package and size
Layers

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PCB Layout – Board Dimension

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PCB – Layer Components Placement

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PCB – Component Names

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PCB Layout – Top Wiring

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PCB layout – Bottom Wiring

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PCB Layout – nTRX Dev. Board

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PCB Layout - DRC

Design Rule Check (DRC)
Create Gerber files
Create CAM data
Generate Bill of Materials
Place orders for electronic components
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nanoLOC Development Board

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nanoLOC Development kit

Hardware
• 1 usb base station
• 5 nanoLOC development boards
• 5 antennas
• 1 usb cable
• 5 rs232 cables
• 5 power supply adapters
• 1 ATMEL stk500 kit
• 1 jtag programmer
• Software and documentation cd
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Kit Content - Software

nanoLOC device driver • Software demo applications
Development environments • Location demo
software (AVRSTUDIO & WinAVR) • Ranging demo
• Talk demo
• Ping demo
• Light switcher demo
• Sleep and wakeup demo

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Kit Content - Documentations

Kit content – documentation
Development board (quick start guide & user guide)
nanoLOC RF chip (datasheets & user guide)
nanoLOC driver documentation
ATmega uC datasheets
Company products flyers
White papers
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Kit Demo Applications

Light switcher – demonstrates simple sensor or remote control application
Ping – demonstrates establishing a reliable RF link or sending command to
remote nodes in a network
Talk – demonstrates point-to-point wireless communication
Ranging – demonstrates nanoLOC ranging capabilities
Location – combines nanoLOC ranging capabilities to locate objects in 2D space
Sleep and wakeup – demonstrates nanoLOC power down mode and RF chip
initialization

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nTRX Board Software in 10 Steps

1. initialize development board (InitDevBoard())
2. configure nanoLOC (ConfigNanoloc())
3. check PROGMEM table (ProgMemCheck())
4. initialize uC SPI interface (InitSPI())
5. powerup reset nanoLOC (PwrupReset())
6. setup SPI interface to nanoLOC (SetupSPI())
7. initialize Shadow Registers (InitShadowRegs())
8. check nanoLOC to uC communication (TestCom())
9. setup nTRX mode (SetupNTRX())
10. initialize application and enter endless loop (InitApplication())
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Development Cycle

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Thank You
nii_kommey@msn.com
050 770 32 86
Whatsup: 0507703286

EMBEDDED SYSTEMS
“By three methods we may learn

wisdom: First, by reflection, which is
noblest. Second, by imitation, which
is easiest, and third by experience,
which is the bitterest”
Confucius
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Overview
Communications
Parallel Data Serial Data Network Wireless

Communication Communication Communication Communication

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Multiple data, control, and possibly power wires
One bit per wire
High data throughput with short distances

Typically used when connecting devices on same IC
or same circuit board
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Bus must be kept short
long parallel wires result in high capacitance values
which requires more time to charge/discharge
Data misalignment between wires increases as
length increases
Higher cost, bulky
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Infrared (IR)
Electronic wave frequencies just below visible light spectrum
Diode emits infrared light to generate signal
Infrared transistor detects signal, conducts when exposed
to infrared light
Cheap to build
Need line of sight, limited range
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Radio frequency (RF)
Electromagnetic wave frequencies in radio spectrum
Analog circuitry and antenna needed on both sides of

transmission
Line of sight not needed, transmitter power determines range

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Media Access Control (MAC)

Many protocols are taken from computer networks
Connection oriented protocols
CSMA/CD
CSMA/CA
Polling
Token passing
TDMA
Binary countdown (Bit dominance)
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Protocol Overview

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Connection Oriented Protocols
2 nodes per each connection only

If nodes are not directly connected, data is relayed
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Connection Oriented Protocols

Deterministic delay between directly connected
nodes, high delay for indirectly connected nodes
Suitable to systems with low communication
requirements.
Node with pass-through traffic can be fully
occupied. E.g. telephone network service
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Polling
Simple and deterministic
Needs a master node
Master periodically polls slave
nodes
Consumes bandwidth
E.g. military aircraft communication

Simple slave nodes, complex master
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Time Division Multiple Access (TDMA)

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Time Division Multiple Access (TDMA)

Masters broadcasts sync signal to synchronize all clocks
Then each node sends data on its time slot.
Similar but more efficient than polling (synchronize
once vs polling all nodes individually.
more complex nodes due to timing requirements.
Fixed length messages (inflexible)
E.g. satellite communications
.
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Token Ring
Ring shape network

Token (signal) is passed from node to node
.
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Token Ring
Node can hold token, send message all the way round the ring,
and pass token on
Deterministic under heavy load
Some token overhead
Can add priority by having extra field in token
More complexity in detecting token lost
Cable break disrupts network (needs dual ring)
E.g. many Wide Area Networks (WANs)
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Carrier Sense Multiple Access With Collision

Detection (CSMA/CD)
Nodes wait for idle channel before transmitting.

When simultaneously transmission is detected, each node
stops and waits for random time before resending.
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CSMA/CD
Easy to add or take off new nodes without initialization
and configuration
Low overhead at light traffic
Unbound overhead at heavy traffic (messages keeps
colliding) hence low determinacy and efficiency.
Requires detection circuit
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Carrier Sense Multiple Access With Collision

Avoidance (CSMA/CA)

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CSMA/CA
Nodes waits for free network before sending.

When collision happens, jam signal is sent to notify all
nodes, synchronizes clocks and start contention time slot.
Unique time slot is assigned to each node

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CSMA/CA
Rotate time slot for fairness
Network return to normal state when all slots are
unused.
Variations
Reservation CSMA – no. of slots equal to no. of nodes
Not practical if networks has many nodes.
No. of slots less than no. of nodes – randomly allocate slots
to nodes.
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Automotive Standards
Controller Area Network (CAN)
Event triggered, Arbitration
Time Triggered Protocol (TTP)
Time triggered, TDMA
Local Interconnect Network (LIN)
Time triggered, master-slave
Media Oriented System Transport (MOST)
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Manufacturing Automation Standards

Controller Area Network (CAN)
Arbitration
Process Network (P-NET)
Token passing and master-slave
PROcess Field Bus (PROFIBUS)
Token passing and master-slave
Factory Instrumentation Protocol (World FIP)
Centralised arbitration

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Military Standards
MIL-STD 1553
The current 1553 data bus is widely used in military applications, with a
nominal throughput of 1 Mb/s.
MIL-STD 1773
Mil-Std-1773 defines a fiber optic bus. This system is widely used for on-
board command and telemetry transfer between military spacecraft
components, subsystems and instruments, and within complex
components themselves. 1773 AS, has a dual rate of 1 Mb/s or 20 Mb/s.
ARINC 429
A commercial aircraft data bus. It is widely implemented in the
commercial aircraft avionics industry. Performance is 100Kb/s or 12.5Kb/s.
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Computers transfer data in two ways:
Parallel
Often 8 or more lines (wire conductors) are used to transfer
data to a device that is only a few feet away
Serial
To transfer to a device located many meters away, the serial
method is used
The data is sent one bit at a time
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At the transmitting end, the byte of data must be converted

to serial bits using parallel-in-serial-out shift register
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Serial Communication Basics

At the receiving end, there is a serial-in-parallel-out shift
register to receive the serial data and pack them into
byte
When the distance is short, the digital signal can be
transferred as it is on a
simple wire and requires no modulation
If data is to be transferred on the telephone line, it must
be converted from 0s and 1s to audio tones
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This conversion is performed by a device called a
modem, “Modulator/demodulator”
Serial data communication uses two methods
Synchronous method transfers a block of data at a time
Asynchronous method transfers a single byte at a time

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It is possible to write software to use either of these methods,
but the programs can be tedious and long
There are special IC chips made by many manufacturers for
serial communications
UART (Universal Asynchronous Receiver Transmitter)
USART (Universal Synchronous-Asynchronous Receiver-

Transmitter)
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Half- Fullduplex Transmission

If data can be transmitted and received, it is a
duplex transmission
If data transmitted one way a time, it is referred to
as half duplex
If data can go both ways at a time, it is full duplex

This is contrast to simplex transmission
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Half- Fullduplex Transmission

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Start and Stop Bits
A protocol is a set of rules agreed by both the sender

and receiver on
How the data is packed
How many bits constitute a character
When the data begins and ends
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Start and Stop Bits

Asynchronous serial data
communication is widely used for character-oriented transmissions
Each character is placed in between start and stop bits, this is called
framing
Block-oriented data transfers use the synchronous method
The start bit is always one bit, but the stop bit can be one or
two bits
The start bit is always a 0 (low) and the stop bit(s) is 1 (high)

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Start and Stop Bits

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Start and Stop Bits

Due to the extended ASCII characters, 8-bit ASCII data is
common
In older systems, ASCII characters were 7-bit
In modern PCs the use of one stop bit is standard
In older systems, due to the slowness of the receiving
mechanical device, two stop bits were used to give the device
sufficient time to organize itself before transmission of the
next byte
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Start and Stop Bits

Assuming that we are transferring a text file of ASCII characters using 1
stop bit, we have a total of 10 bits for each character
This gives 25% overhead, i.e. each 8-bit character with an extra 2 bits
In some systems in order to maintain data integrity, the parity bit of

the character byte is included in the data frame
UART chips allow programming of the parity bit for odd-, even-, and
no-parity options
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Data Transfer Rate

The rate of data transfer in serial data communication is stated in bps
(bits per second)
Another widely used terminology for bps is baud rate
It is modem terminology and is defined as the number of signal

changes per second
In modems, there are occasions when a single change of signal
transfers several bits of data
As far as the conductor wire is concerned, the baud rate and bps are
the same, and we use the terms interchangeably
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Data Transfer Rate

The data transfer rate of given computer system
depends on
communication ports incorporated into that system
IBM PC/XT could transfer data at the rate of 100 to 9600 bps
Pentium-based PCs transfer data at rates as high as 56K bps
In asynchronous serial data communication, the baud rate is limited
to 100K bps
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RS232 Standard
An interfacing standard RS232 was set by the Electronics
Industries Association (EIA) in 1960
The standard was set long before the advent of the TTL logic family,
its input and output voltage levels are not TTL compatible
In RS232, a 1 is represented by -3 ~ -25 V, while a 0 bit is +3 ~ +25 V,

making -3 to +3 undefined

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RS232 Standard

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RS232 Standard
Since not all pins are used in PC cables, IBM introduced the DB-9
version of the serial I/O standard

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Data Communication Classification

Current terminology classifies data communication equipment as
DTE (data terminal equipment) refers to terminal and computers that send and receive data
DCE (data communication equipment) refers to communication equipment, such as modems
The simplest connection between a PC and microcontroller requires a minimum of three pins,
TxD, RxD, and ground

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RS232 Pins
DTR (data terminal ready)
When terminal is turned on, it sends out signal DTR to indicate that it is ready for
communication
DSR (data set ready)
When DCE is turned on and has gone through the self-test, it assert DSR to indicate that it is
ready to communicate
RTS (request to send)
When the DTE device has byte to transmit, it assert RTS to signal the modem that it has a byte
of data to transmit
CTS (clear to send)
When the modem has room for storing the data it is to receive, it sends out signal CTS to DTE
to indicate that it can receive the data now
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RS232 Pins
DCD (data carrier detect)
The modem asserts signal DCD to inform the DTE that a valid carrier
has been detected and that contact between it and the other modem
is established
RI (ring indicator)
An output from the modem and an input to a PC indicates that the
telephone is ringing
It goes on and off in synchronous with the ringing sound
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8051 Connection to RS232

A line driver such as the MAX232 chip is required to convert RS232 voltage
levels to TTL levels, and vice versa
8051 has two pins that are used specifically for transferring and receiving data
serially
These two pins are called TxD and RxD and are part of the port 3 group (P3.0 and
P3.1)
These pins are TTL compatible; therefore, they require a line driver to make
them RS232 compatible
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Max232
We need a line driver (voltage converter) to convert the R232’s signals to TTL voltage levels
that will be acceptable to 8051’s TxD and RxD pins

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Max233
To save board space, some designers use MAX233 chip from Maxim
MAX233 performs the same job as MAX232 but eliminates the need for
capacitors
Notice that MAX233 and MAX232 are not pin compatible

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Serial Communication Programming

To allow data transfer between the PC and an 8051 system without any error, we must make
sure that the baud rate of 8051 system matches the baud rate of the PC’s COM port
Hyper-terminal function supports baud rates much higher than listed below

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Serial Programming Example

Question
With XTAL = 11.0592 MHz, find the TH1 value needed to have the
following baud rates. (a) 9600 (b) 2400 (c) 1200
Solution:
The machine cycle frequency of 8051 = 11.0592 / 12 = 921.6 kHz, and
921.6 kHz / 32 = 28,800 Hz is frequency by UART to timer 1 to set baud
rate.

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(a) 28,800 / 3 = 9600 where -3 = FD (hex) is loaded into TH1
(b) 28,800 / 12 = 2400 where -12 = F4 (hex) is loaded into TH1
(c) 28,800 / 24 = 1200 where -24 = E8 (hex) is loaded into TH1
Notice that dividing 1/12 of the crystal frequency by 32 is the

default value upon activation of the 8051 RESET pin
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SBUF Register
SBUF is an 8-bit register used solely for serial communication
For a byte data to be transferred via the TxD line, it must be

placed in the SBUF register
The moment a byte is written into SBUF, it is framed with the

start and stop bits and transferred serially via the TxD line
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SBUF Register
When the bits are received serially via RxD, the 8051 deframes
it by eliminating the stop and start bits,
making a byte out of the data received, and then placing it in
SBUF

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SCON Register
SCON is an 8-bit register used to program the start bit, stop bit, and
data bits of data framing, among other things

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SM0, SM1 SCON Register

They determine the framing of data by specifying the number of bits per
character, and the start and stop bits
SM2
This enables the multiprocessing capability of the 8051
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SCON Register
REN (receive enable)
It is a bit-adressable register
When it is high, it allows 8051 to receive data on RxD pin
If low, the receiver is disable
TI (transmit interrupt)
When 8051 finishes the transfer of 8-bit character
It raises TI flag to indicate that it is ready to transfer another byte
TI bit is raised at the beginning of the stop bit
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SCON Register
RI (receive interrupt)
When 8051 receives data serially via RxD, it gets rid of
the start and stop bits and places the byte in SBUF
register
It raises the RI flag bit to indicate that a byte has been
received and should be picked up before it is lost
RI is raised halfway through the stop bit
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Programming Serial Data Transmission

In programming the 8051 to transfer character bytes serially
1. TMOD register is loaded with the value 20H, indicating the use of
timer 1 in mode 2 (8-bit auto-reload) to set baud rate
2. The TH1 is loaded with one of the values to set baud rate for serial
data transfer
3. The SCON register is loaded with the value 50H, indicating serial
mode 1, where an 8-bit data is framed with start and stop bits
4. TR1 is set to 1 to start timer 1
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5. TI is cleared by CLR TI instruction

6. The character byte to be transferred serially is written into
SBUF register
7. The TI flag bit is monitored with the use of instruction JNB
TI,xx to see if the character has been transferred completely
8. To transfer the next byte, go to step 5

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Question
Write a program for the 8051 to transfer letter “A” serially at 4800 baud, continuously.
Solution:
MOV TMOD, #20H ;timer 1,mode 2(auto reload)
MOV TH1, #-6 ;4800 baud rate
MOV SCON, #50H ;8-bit, 1 stop, REN enabled
SETB TR1 ;start timer 1
AGAIN: MOV SBUF, #”A” ;letter “A” to transfer
HERE: JNB TI, HERE ;wait for the last bit
CLR TI ;clear TI for next char
SJMP AGAIN ;keep sending A
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Importance of TI Flag
The steps that 8051 goes through in transmitting a character via TxD
1. The byte character to be transmitted is written into the SBUF
register
2. The start bit is transferred
3. The 8-bit character is transferred on bit at a time
4. The stop bit is transferred
It is during the transfer of the stop bit that 8051 raises the TI flag,
indicating that the last character was transmitted
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5. By monitoring the TI flag, we make sure that we are not
overloading the SBUF
If we write another byte into the SBUF before TI is raised, the

untransmitted portion of the previous byte will be lost
6. After SBUF is loaded with a new byte, the TI flag bit must
be forced to 0 by CLR TI in order for this new byte to be
transferred
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By checking the TI flag bit, we know whether or not the 8051 is ready
to transfer another byte
It must be noted that TI flag bit is raised by 8051 itself when it
finishes data transfer
It must be cleared by the programmer with instruction CLR TI
If we write a byte into SBUF before the TI flag bit is raised, we risk
the loss of a portion of the byte being transferred
The TI bit can be checked by
The instruction JNB TI,xx
Using an interrupt
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Programming Serial Data Receiving

In programming the 8051 to receive character bytes serially
1. TMOD register is loaded with the value 20H, indicating the
use of timer 1 in mode 2 (8-bit auto-reload) to set baud rate
2. TH1 is loaded to set baud rate
3. The SCON register is loaded with the value 50H, indicating
serial mode 1, where an 8-bit data is framed with start and
stop bits
4. TR1 is set to 1 to start timer 1
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5. RI is cleared by CLR RI instruction
6. The RI flag bit is monitored with the use of instruction JNB
RI,xx to see if an entire character has been received yet
7. When RI is raised, SBUF has the byte, its contents are
moved into a safe place
8. To receive the next character, go to step 5
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Write a program for the 8051 to receive bytes of data serially, and
put them in P1, set the baud rate at 4800, 8-bit data, and 1 stop bit
Solution:
MOV TMOD, #20H ;timer 1,mode 2(auto reload)
MOV TH1, #-6 ;4800 baud rate
MOV SCON, #50H ;8-bit, 1 stop, REN enabled
SETB TR1 ;start timer 1
HERE: JNB RI, HERE ;wait for char to come in
MOV A, SBUF ;saving incoming byte in A
MOV P1, A ;send to port 1
CLR RI ;get ready to receive next byte
SJMP HERE ;keep getting data
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Importance of RI Flag
In receiving bit via its RxD pin, 8051 goes through the following steps
1. It receives the start bit
Indicating that the next bit is the first bit of the character byte it is about
to receive
2. The 8-bit character is received one bit at time
3. The stop bit is received
When receiving the stop bit 8051 makes RI = 1, indicating that an entire
character byte has been received and must be picked up before it gets
overwritten by an incoming character

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4. By checking the RI flag bit when it is raised, we know that a
character has been received and is sitting in the SBUF register
We copy the SBUF contents to a safe place in some other register
or memory before it is lost
5. After the SBUF contents are copied into a safe place, the RI flag bit
must be forced to 0 by CLR RI in order to allow the next received
character byte to be placed in SBUF
Failure to do this causes loss of the received character
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By checking the RI flag bit, we know whether or not the 8051 received a character byte
If we failed to copy SBUF into a safe place, we risk the loss of the received byte
It must be noted that RI flag bit is raised by 8051 when it finish receive data
It must be cleared by the programmer with instruction CLR RI
If we copy SBUF into a safe place before the RI flag bit is raised, we risk copying
garbage
The RI bit can be checked by

The instruction JNB RI,xx
Using an interrupt

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Doubling Baud Rate

There are two ways to increase the baud rate of data transfer
To use a higher frequency crystal
To change a bit in the PCON register
PCON register is an 8-bit register
When 8051 is powered up, SMOD is zero
We can set it to high by software and thereby double the baud rate

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Doubling Baud Rate

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Transmitting and Receiving Data Example

Write a C program for 8051 to transfer the letter “A” serially at 4800 baud continuously.
Use 8-bit data and 1 stop bit.
Solution:
#include <reg51.h>
void main(void){
TMOD=0x20; //use Timer 1, mode 2
TH1=0xFA; //4800 baud rate
SCON=0x50;
TR1=1;
while (1) {
SBUF=‘A’; //place value in buffer
while (TI==0);
TI=0;
}}
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Write an 8051 C program to transfer the message “YES” serially at 9600 baud, 8-bit data, 1 stop bit. Do this continuously.
Solution:
#include <reg51.h>
void SerTx(unsigned char);
void main(void){
TH1=0xFD; //9600 baud rate
SCON=0x50;
TR1=1; //start timer
while (1) {
SerTx(‘Y’);
SerTx(‘E’);
SerTx(‘S’);
}
}
void SerTx(unsigned char x){
SBUF=x; //place value in buffer
while (TI==0); //wait until transmitted
TI=0;
}

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Program the 8051 in C to receive bytes of data serially and put them in P1. Set the baud rate at
4800, 8-bit data, and 1 stop bit.
Solution:
#include <reg51.h>
void main(void){
TH1=0xFA; //4800 baud rate
SCON=0x50;
TR1=1; //start timer
while (1) { //repeat forever
while (RI==0); //wait to receive
mybyte=SBUF; //save value
P1=mybyte; //write value to port
RI=0;
}}

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Thank You
nii_kommey@msn.com
050 770 32 86
Whatsup: 0507703286

EMBEDDED SYSTEMS
“It does not matter how slowly

you go as long as you do not
stop”
Confucius

EMBEDDED SYSTEMS
Overview
Buses
Definition Bus Types Standard Buses

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Overview
Bus Types
Synchronous/
Processor-
I/O Bus Backplane Bus Asynchronous
Memory Bus
Bus

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Overview
Standard
Buses
PCI RS232/ RS233 RS422/RS485 IEEE488

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What is a Bus?
A Bus is a shared communication link
It is a single set of wires used to connect multiple subsystems
A Bus is also a fundamental tool for composing large, complex systems
Processor
Input
Control
Memory
Datapath
Output

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Bus

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Advantages of Buses
I/O I/O I/O

Processer Device Device Device Memory
Versatility:
New devices can be added easily
Peripherals can be moved between computer
systems that use the same bus standard
Low Cost:
A single set of wires is shared in multiple ways
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Disadvantage of Buses
It creates a communication bottleneck
The bandwidth of that bus can limit the maximum I/O
throughput
The maximum bus speed is largely limited by:
The length of the bus
The number of devices on the bus
The need to support a range of devices with:
Widely varying latencies
Widely varying data transfer rates
EMBEDDED SYSTEMS
General Organization of a Bus

Control Lines
Data Lines
Control lines:
Signal requests and acknowledgments
Indicate what type of information is on the data lines
Data lines carry information between the source and the
destination:
Data and Addresses
Complex commands
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Master versus Slave

Master issues command
Bus Bus
Master Data can go either way Slave
A bus transaction includes two parts:

Issuing the command (and address) – request
Transferring the data – action
Master is the one who starts the bus transaction by:
issuing the command (and address)
Slave is the one who responds to the address by:
Sending data to the master if the master ask for data
Receiving data from the master if the master wants to send data
EMBEDDED SYSTEMS
Types of Busses
Processor-Memory Bus (design specific)

Short and high speed
Only need to match the memory system
Maximize memory-to-processor bandwidth
Connects directly to the processor
Optimized for cache block transfers
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Types of Busses
I/O Bus (industry standard)

Usually is lengthy and slower
Need to match a wide range of I/O devices
Connects to the processor-memory bus or
backplane bus

EMBEDDED SYSTEMS
Types of Busses
Backplane Bus (standard or proprietary)

Backplane: an interconnection structure within
the chassis
Allow processors, memory, and I/O devices to
coexist
Cost advantage: one bus for all components
EMBEDDED SYSTEMS
Example: Pentium System Organization

Processor/Memory
Bus
PCI Bus
I/O Busses

EMBEDDED SYSTEMS
A Computer System with One Bus: Backplane Bus

Backplane Bus
Processor Memory
I/O Devices
A single bus (the backplane bus) is used for:

Processor to memory communication
Communication between I/O devices and memory
Advantages: Simple and low cost

Disadvantages: slow and the bus can become a major bottleneck
Example: IBM PC - AT
EMBEDDED SYSTEMS
A Two-Bus System Processor Memory Bus

Processor Memory
Bus Bus Bus

Adaptor Adaptor Adaptor
I/O I/O I/O

Bus Bus Bus
I/O buses tap into the processor-memory bus via bus adaptors:
Processor-memory bus: mainly for processor-memory traffic
I/O buses: provide expansion slots for I/O devices
Apple Macintosh-II
NuBus: Processor, memory, and a few selected I/O devices
SCCI Bus: the rest of the I/O devices
EMBEDDED SYSTEMS
A Three-Bus System Processor Memory Bus

Processor Memory
Bus
Adaptor
Bus
Adaptor I/O Bus
Backplane Bus
Bus I/O Bus
Adaptor
A small number of backplane buses tap into the processor-memory bus

Processor-memory bus is only used for processor-memory traffic
I/O buses are connected to the backplane bus
Advantage: loading on the processor bus is greatly reduced
EMBEDDED SYSTEMS
North/South Bridge Architectures: Separate Busses

Processor Memory Bus
Processor Memory
“backside
cache”
Backplane Bus Bus
Adaptor
Separate sets of pins for different functions
I/O Bus
Memory bus Bus

Adaptor
I/O Bus
Caches
Graphics bus (for fast frame buffer)
I/O busses are connected to the backplane bus
Advantage:
Busses can run at different speeds
Much less overall loading!
EMBEDDED SYSTEMS
What defines a bus?

Transaction Protocol
Timing and Signaling Specification
Bunch of Wires
Electrical Specification
Physical / Mechanical Characteristics

– the connectors

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Synchronous Bus
Includes a clock in the control lines
A fixed protocol for communication that is relative to the clock
Advantage:
involves very little logic and can run very fast
Disadvantages:
Every device on the bus must run at the same clock rate
To avoid clock skew, they cannot be long if they are fast
EMBEDDED SYSTEMS
Asynchronous Bus
It is not clocked
It can accommodate a wide range of devices
It can be lengthened without worrying about clock skew
It requires a handshaking protocol

EMBEDDED SYSTEMS
Busses so far
Master Slave °°°
Control Lines
Address Lines
Data Lines
Bus Master: has ability to control the bus, initiates transaction
Bus Slave: module activated by the transaction
Bus Communication Protocol: specification of sequence of events and timing
requirements in transferring information.
Asynchronous Bus Transfers: control lines (req, ack) serve to orchestrate sequencing.
Synchronous Bus Transfers: sequence relative to common clock.
EMBEDDED SYSTEMS
Bus Transaction
Arbitration: Who gets the bus

Request: What do we want to do
Action: What happens in response

EMBEDDED SYSTEMS
Arbitration: Obtaining Access to the Bus

Control: Master initiates requests
Bus Bus
Master Data can go either way Slave
One of the most important issues in bus design:

How is the bus reserved by a device that wishes to use it?
Chaos is avoided by a master-slave arrangement:
Only the bus master can control access to the bus:
It initiates and controls all bus requests
A slave responds to read and write requests
The simplest system:
Processor is the only bus master
All bus requests must be controlled by the processor
Major drawback: the processor is involved in every transaction
EMBEDDED SYSTEMS
Multiple Potential Bus Masters:

the Need for Arbitration
Bus arbitration scheme:
A bus master wanting to use the bus asserts the bus request
A bus master cannot use the bus until its request is granted
A bus master must signal to the arbiter the end of the bus utilization
Bus arbitration schemes usually try to balance two factors:
Bus priority: the highest priority device should be serviced first
Fairness: Even the lowest priority device should never be completely locked out from the bus
Bus arbitration schemes can be divided into four broad classes:
Daisy chain arbitration
Centralized, parallel arbitration
Distributed arbitration by self-selection: each device wanting the bus places a code indicating its identity on the bus.
Distributed arbitration by collision detection:
Each device just “goes for it”. Problems found after the fact.
EMBEDDED SYSTEMS
The Daisy Chain Bus: Arbitrations Scheme

Device 1 Device N
Highest Device 2 Lowest
Priority Priority
Grant Grant Grant

Bus Release
Arbiter Request
wired-OR
Advantage: simple
Disadvantages:
Cannot assure fairness:
A low-priority device may be locked out indefinitely
The use of the daisy chain grant signal also limits the bus speed
EMBEDDED SYSTEMS
Centralized Parallel Arbitration

Device 1 Device N
Device 2
Grant Req
Bus
Arbiter
Used in essentially all processor-memory busses and in high-speed I/O

busses
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Simplest Bus Paradigm
All agents operate synchronously

All can source / sink data at same rate
=> simple protocol
just manage the source and target
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Simple Synchronous Protocol

BReq
BG
R/W Cmd+Addr
Address
Data Data1 Data2
Even memory busses are more complex than this

memory (slave) may take time to respond
it may need to control data rate
EMBEDDED SYSTEMS
Typical Synchronous Protocol

BReq
BG
R/W Cmd+Addr
Address
Wait
Data Data1 Data1 Data2
Slave indicates when it is prepared for data xfer

Actual transfer goes at bus rate
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Increasing the Bus Bandwidth

Separate versus multiplexed address and data lines:
Address and data can be transmitted in one bus cycle
if separate address and data lines are available
Cost: (a) more bus lines, (b) increased complexity
Data bus width:

By increasing the width of the data bus, transfers of multiple words require fewer bus cycles
Example: SPARCstation 20’s memory bus is 128 bit wide
Cost: more bus lines
Block transfers:
Allow the bus to transfer multiple words in back-to-back bus cycles
Only one address needs to be sent at the beginning
The bus is not released until the last word is transferred
Cost: (a) increased complexity
(b) decreased response time for request

EMBEDDED SYSTEMS
Increasing Transaction Rate on Multi-master Bus

Overlapped arbitration
perform arbitration for next transaction during current transaction
Bus parking
master holds onto bus and performs multiple transactions as long as no other master
makes request
Overlapped address / data phases
requires one of the above techniques
Split-phase (or packet switched) bus
completely separate address and data phases
arbitrate separately for each
address phase yield a tag which is matched with data phase
”All of the above” in most modern memory buses
EMBEDDED SYSTEMS
Examples High Speed I/O Bus

graphics
fast networks
Limited number of devices
Data transfer bursts at full rate
DMA transfers important
small controller spools stream of bytes to or from memory
Either side may need to squelch transfer
buffers fill up
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RS422/RS485 – Serial Communication

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Serial Communications
Standards
Cabling
Configuration
Protocol

EMBEDDED SYSTEMS
Standards
The terms RS-232, RS-422, and RS-485 all refer to physical
standards for serial communication developed by the
Electronic Industries Association (EIA).
The standards specify the electrical interface between
equipment.
Any device that conforms to one of the standards above

should be able to communicate with any other device
conforming to the same standard.
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RS-232
By far the most popular of the serial protocols
“Single Ended” meaning the signals are referenced to ground

and therefore limited in cable length
Approx. 50cmmaximum cable length
Many lighting and other devices implement RS-232

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RS-422 and RS-485

These are less often used
Most often found in instrumentation systems in industrial

environments
“Double Ended” signal electronics means much greater distances
Up to 5000cm cable length

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RS-232 Standard Cabling

DB-25 is full industry standard
DB-9 has become more popular over last several years due to compact size.
It is a limited but normally adequate implementation
DTE is Data Terminal Equipment (Computer)

DCE is Data Communications Equipment (Modem)
DTE talks to DCE

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Crossover
DTE should connect to DCE with straight through cable
DTE can connect to DTE and DCE can connect to DCE using a
crossover cable

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Handshaking
Handshaking is the process of ensuring that data not be
transmitted when the receiver is not ready and to ensure error
free transmission.
Handshaking can be either hardware or software
Handshaking may not be required if the amount of data is small.

EMBEDDED SYSTEMS
Minimal Implementations
Although the RS-232 standard uses up to 25 wires, as few as 2 may be
used for 1 way communications, or as few as 3 for 2 way
communications.
The other pins are either looped back on themselves, or not

implemented internally.
The minimum signals are: Ground, TX and RX
Both communicating devices must be satisfied with the cabling

EMBEDDED SYSTEMS
Other Serial Standards

USB, Firewire, SCSI and ethernet are all more sophisticated serial
standards.
To date, they are mostly limited to computer peripherals
Expect to see USB may be a control standard in the future
Ethernet is beginning to be used for control

EMBEDDED SYSTEMS
Configuration
Once the hardware is correctly connected, the data
configuration must be determined and adhered to by both
devices
Data rate (Baud)
Number of data bits (7 or 8)
Number of stop bits
Parity or no parity
Handshaking

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Configuration
The controlled device will have a default configuration

and may be changeable
Normally, best practice is to leave the controlled device in

default and program the controller to that standard.

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Protocols
Each device to be controlled will have a protocol, which are the
“rules”
Often, this is simply a table with the controllable commands

and the data to be sent for that command.
Example:
POWER ON = 0x05(H)
Power Off =0x06(H)
EMBEDDED SYSTEMS
Data Formats
The device protocol may be listed in Hex, Decimal, Binary or

ASCII.
The programmer needs to ensure that the program sends

appropriate data format.

EMBEDDED SYSTEMS
IEEE488
GPIB (IEEE-488) parallel
General Purpose Interface (or Instrument) Bus
originally HPIB; Hewlett Packard

EMBEDDED SYSTEMS
IEEE488
An 8-bit parallel bus allowing up to 15 devices connected to the same
computer port
addressing of each machine (either via menu or dip-switches) determines
who’s who
can daisy-chain connectors, each cable 2 m or less in length
Extensive handshaking controls the bus
computer controls who can talk and who can listen
Many test-and-measurement devices equipped with GPIB
common means of controlling an experiment:
positioning detectors, measuring or setting voltages/currents, etc.
Can be reasonably fast (1 Mbit/sec)
EMBEDDED SYSTEMS
Thank You
nii_kommey@msn.com
050 770 32 86
Whatsup: 0507703286

EMBEDDED SYSTEMS
“Courage is what it takes to stand

up and speak.
Courage is also what it takes to sit
down and listen”
Winston Churchill

EMBEDDED SYSTEMS
Overview
Polling & Interrupts
Interrupt Interrupt
Definitions Service Execution
Routine ISR Steps
EMBEDDED SYSTEMS
Overview
8051
Software Enable/Disable Interrupt
Interrupt
Interrupt Interrupts Priorities
Types

EMBEDDED SYSTEMS
8051 Interrupts Types
8051 Interrupt Types
External
Reset Timer Serial
Hardware
Interrupt Interrupt Interrupt
Interrupt

EMBEDDED SYSTEMS
8051 Interrup Types
External Hardware Interrupt
Level Triggered Edge Triggered

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Polling
The microcontroller continuously monitors the status
of a given device
When the conditions met, it performs the service
After that, it moves on to monitor the next device

until everyone is serviced
EMBEDDED SYSTEMS
Polling
Polling can monitor the status of several devices and

serve each of them as certain conditions are met
The polling method is not efficient, since it wastes much

of the microcontroller’s time by polling devices that do
not need service
EMBEDDED SYSTEMS

An interrupt is an external or internal event that
interrupts the microcontroller to inform it that a device
needs its service
A single microcontroller can serve several devices by

two ways:
(Interrupt, Polling)
EMBEDDED SYSTEMS
Interrupts
Whenever any device needs its service, the device notifies the
microcontroller by sending it an interrupt signal
Upon receiving an interrupt signal, the microcontroller
interrupts whatever it is doing and serves the device
The program which is associated with the interrupt is called

the interrupt service routine
(ISR) or interrupt handler
EMBEDDED SYSTEMS
Polling and Interrupts

The advantage of interrupts is that the microcontroller can serve many
devices (not all at the same time)
Each devices can get the attention of the microcontroller based on the
assigned priority
For the polling method, it is not possible to assign priority since it

checks all devices in a round-robin fashion
The microcontroller can also ignore (mask) a device request for service
This is not possible for the polling method
EMBEDDED SYSTEMS
Interrupt Service Routine ISR

For every interrupt, there must be an interrupt service
routine (ISR), or interrupt handler
When an interrupt is invoked, the microcontroller runs
the interrupt service routine
For every interrupt, there is a fixed location in memory
that holds the address of its ISR
The group of memory locations set aside to hold the
addresses of ISRs is called interrupt vector table
EMBEDDED SYSTEMS
Interrupt Execution Steps

Upon activation of an interrupt, the microcontroller goes
through the following steps
1. It finishes the instruction it is executing and saves the
address of the next instruction (PC) on the stack
2. It also saves the current status of all the interrupts internally
(i.e: not on the stack)
3. It jumps to a fixed location in memory, called the interrupt
vector table, that holds the address of the ISR
EMBEDDED SYSTEMS
Interrupt Execution Steps

4. The microcontroller gets the address of the ISR from the interrupt vector table
and jumps to it
It starts to execute the interrupt service subroutine until it reaches the last
instruction of the subroutine which is RETI (return from interrupt)
5. Upon executing the RETI instruction, the microcontroller returns to the place
where it was interrupted
First, it gets the program counter (PC) address from the stack by popping the top
two bytes of the stack into the PC
Then it starts to execute from that address
EMBEDDED SYSTEMS
Six Interrupts in 8051

Six interrupts are allocated as follows
Reset – power-up reset
Two interrupts are set aside for the timers:
one for timer 0 and one for timer 1
Two interrupts are set aside for hardware external interrupts
P3.2 and P3.3 are for the external hardware interrupts INT0 (or EX1),
and INT1 (or EX2)
Serial communication has a single interrupt that belongs to both
receive and transfer
EMBEDDED SYSTEMS
Six Interrupts in 8051

EMBEDDED SYSTEMS
Enabling and Disabling Interrupts

Upon reset, all interrupts are disabled (masked), meaning that
none will be responded to by the microcontroller if they are
activated
The interrupts must be enabled by software in order for the
microcontroller to respond to them
There is a register called IE (interrupt enable) that is
responsible for enabling (unmasking) and disabling (masking)
the interrupts
EMBEDDED SYSTEMS
Interrupt Enable Register IE

EMBEDDED SYSTEMS
Interrupt Enabling Steps

To enable an interrupt, we take the following steps:
1. Bit D7 of the IE register (EA) must be set to high to allow the
rest of register to take effect
2. The value of EA
if EA = 1, interrupts are enabled and will be responded to if
their corresponding bits in IE are high
If EA = 0, no interrupt will be responded to, even if the
associated bit in the IE register is high
EMBEDDED SYSTEMS
Interrupt Enabling Example

Question:
Show the instructions to
(a)enable the serial interrupt, timer 0 interrupt, and external

hardware interrupt 1 (EX1), and
(b)Disable (mask) the timer 0 interrupt, then
(c)show how to disable all the interrupts with a single
instruction.
EMBEDDED SYSTEMS
Interrupt Enabling Example

Solution:
(a) MOV IE,#10010110B ;enable serial, ;timer 0, EX1
Another way to perform the same manipulation is
SETB IE.7 ;EA=1, global enable
SETB IE.4 ;enable serial interrupt
SETB IE.1 ;enable Timer 0 interrupt
SETB IE.2 ;enable EX1
(b) CLR IE.1 ;mask (disable) timer 0 ;interrupt only
(c) CLR IE.7 ;disable all interrupts
EMBEDDED SYSTEMS
Timer Interrupts
The timer flag (TF) is raised when the timer rolls over
In polling TF, we have to wait until the TF is raised
The problem with this method is that the
microcontroller is tied down while waiting for TF to be
raised, and cannot do anything else
Using interrupts solves this problem and, avoids tying
down the controller
EMBEDDED SYSTEMS
Timer Interrupts
If the timer interrupt in the IE register is enabled, whenever
the timer rolls over, TF is raised, and the microcontroller is
interrupted in whatever it is doing, and jumps to the interrupt
vector table to service the ISR
In this way, the microcontroller can do other until it is notified
that the timer has rolled over

EMBEDDED SYSTEMS

The 8051 has two external hardware interrupts
Pin 12 (P3.2) and pin 13 (P3.3) of the 8051, designated as INT0 and
INT1, are used as external hardware interrupts
The interrupt vector table locations 0003H and 0013H are set aside for
INT0 and INT1
There are two activation levels for the external hardware interrupts
Level trigged
Edge trigged
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EMBEDDED SYSTEMS
Level Trigged Interrupt

In the level-triggered mode, INT0 and INT1 pins are normally high
If a low-level signal is applied to them, it triggers the interrupt
Then the microcontroller stops whatever it is doing and jumps to the
interrupt vector table to service that interrupt
The low-level signal at the INT pin must be removed before the
execution of the last instruction of the ISR, RETI; otherwise, another
interrupt will be generated
This is called a level-triggered or level-activated interrupt and is the
default mode upon reset of the 8051
EMBEDDED SYSTEMS
Sampling Low Level Triggered Interrupt

Pins P3.2 and P3.3 are used for normal I/O unless the INT0 and INT1 bits in the IE
register are enabled
After the hardware interrupts in the IE register are enabled, the controller keeps
sampling the INTn pin for a low-level signal once each machine cycle
According to one manufacturer’s data sheet, The pin must be held in a low state
until the start of the execution of ISR
If the INTn pin is brought back to a logic high before the start of the execution of
ISR there will be no interrupt
If INTn pin is left at a logic low after the RETI instruction of the ISR, another
interrupt will be activated after one instruction is executed
EMBEDDED SYSTEMS
Sampling Low Level Interrupt

To ensure the activation of the hardware interrupt at the INTn
pin, make sure that the duration of the low-level signal is
around 4 machine cycles, but no more
This is due to the fact that the level-triggered interrupt is not

latched
Thus the pin must be held in a low state until the start of the
ISR execution
EMBEDDED SYSTEMS
Edge-Triggered Interrupt
To make INT0 and INT1 edge-triggered interrupts,
we must program the bits of the TCON register
The TCON register holds, among other bits, the IT0 and IT1 flag bits
that determine level- or edge-triggered mode of the hardware
interrupt
IT0 and IT1 are bits D0 and D2 of the TCON register

They are also referred to as TCON.0 and TCON.2 since the TCON
register is bit addressable
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Sampling Edge-Triggered Interrupt

In edge-triggered interrupts, the external source must be held high for
at least one machine cycle, and then held low for at least one machine
cycle
The falling edge of pins INT0 and INT1 are latched by the 8051 and are
held by the TCON.1 and TCON.3 bits of TCON register
Function as interrupt-in-service flags
It indicates that the interrupt is being serviced now and on this INTn
pin, and no new interrupt will be responded to until this service is
finished
EMBEDDED SYSTEMS

Regarding the IT0 and IT1 bits in the TCON register, the
following two points must be emphasized
When the ISRs are finished (that is, upon execution of

RETI), these bits (TCON.1 and TCON.3) are cleared,
indicating that the interrupt is finished and the 8051 is
ready to respond to another interrupt on that pin
EMBEDDED SYSTEMS

During the time that the interrupt service routine is being
executed, the INTn pin is ignored, no matter how many times it
makes a high-to-low transition
RETI clears the corresponding bit in TCON register (TCON.1 or
TCON.3)
There is no need for instruction CLR TCON.1 before RETI in the
ISR associated with INT0
EMBEDDED SYSTEMS
Serial Communication Interrupt

TI (transfer interrupt) is raised when the last bit of the framed data,
the stop bit, is transferred, indicating that the SBUF register is ready
to transfer the next byte
RI (received interrupt) is raised when the entire frame of data,

including the stop bit, is received
In other words, when the SBUF register has a byte, RI is raised to

indicate that the received byte needs to be picked up before it is lost
(overrun) by new incoming serial data
EMBEDDED SYSTEMS
RI and TI Flags and Interrupts

In the 8051 there is only one interrupt set aside for serial
communication. This interrupt is used to both send and receive data
If the interrupt bit in the IE register (IE.4) is enabled, when RI or TI is

raised the 8051 gets interrupted and jumps to memory location 0023H
to execute the ISR
In that ISR we must examine the TI and RI flags to see which one
caused the interrupt and respond accordingly

EMBEDDED SYSTEMS
Use of Serial Interrupt in 8051

The serial interrupt is used mainly for receiving data and is never used
for sending data serially
This is like getting a telephone call in which we need a ring to be

notified
If we need to make a phone call there are other ways to remind

ourselves and there is no need for ringing
However in receiving the phone call, we must respond immediately no
matter what we are doing or we will miss the call
EMBEDDED SYSTEMS
Interrupt Flag Bits

The TCON register holds four of the interrupt flags, in the 8051 the
SCON register has the RI and TI flags

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Interrupt Priority
When the 8051 is powered up, the priorities are assigned according to
the following
In reality, the priority scheme is nothing but an internal polling
sequence in which the 8051 polls the interrupts in the sequence listed
and responds accordingly

EMBEDDED SYSTEMS
Interrupt Priority Example

Question
Discuss what happens if interrupts INT0, TF0, and INT1 are
activated at the same time.
Assume priority levels were set by the power-up reset and

the external hardware interrupts are edge-triggered.

EMBEDDED SYSTEMS

Solution:
If these three interrupts are activated at the same time, they
are latched and kept internally.
Then the 8051 checks all five interrupts according to the
sequence listed in previous table .
If any is activated, it services it in sequence.
Therefore, when the above three interrupts are activated, IE0
(external interrupt 0) is serviced first, then timer 0 (TF0), and
finally IE1 (external interrupt 1).
EMBEDDED SYSTEMS
Interrupt Priority
We can alter the sequence of interrupt priority by assigning a higher
priority to any one of the interrupts by programming a register called
IP (interrupt priority)
To give a higher priority to any of the interrupts, we make the

corresponding bit in the IP register high
When two or more interrupt bits in the IP register are set to high
While these interrupts have a higher priority than others, they are
serviced according to the sequence of interrupts table
EMBEDDED SYSTEMS
Interrupt Priority

EMBEDDED SYSTEMS

Question
(a) Program the IP register to assign the highest priority to

INT1(external interrupt 1), then
(b) discuss what happens if INT0, INT1, and TF0 are activated
at the same time.
Assume the interrupts are both edge-triggered.

EMBEDDED SYSTEMS
Solution:
(a) MOV IP,#00000100B ;IP.2=1 assign INT1 higher priority.
The instruction SETB IP.2 also will do the same thing as the above line since IP is bit-
addressable.
(b) The instruction in Step (a) assigned a higher priority to INT1 than the others; therefore,
when INT0, INT1, and TF0 interrupts are activated at the same time, the 8051 services INT1
first, then it services INT0, then TF0.
This is due to the fact that INT1 has a higher priority than the other two because of the
instruction in Step (a). The instruction in Step (a) makes both the INT0 and TF0 bits in the IP
register 0.
As a result, the sequence in the interrupt table is followed which gives a higher priority to INT0
over TF0
EMBEDDED SYSTEMS
Interrupt Inside an Interrupt

In the 8051 a low-priority interrupt can be interrupted by a
higher-priority interrupt but not by another low priority
interrupt
Although all the interrupts are latched and kept internally, no

low-priority interrupt can get the immediate attention of the
CPU until the 8051 has finished servicing the high-priority
interrupts
EMBEDDED SYSTEMS
Triggering Interrupt by Software

An ISR test can be done by way of simulation with simple instructions
to set the interrupts high and thereby cause the 8051 to jump to the
interrupt vector table
eg. If the IE bit for timer 1 is set, an instruction such as SETB TF1 will
interrupt the 8051 in whatever it is doing and will force it to jump to
the interrupt vector table
We do not need to wait for timer 1 to roll over to have an interrupt

EMBEDDED SYSTEMS
Thank You
nii_kommey@msn.com
050 770 32 86
Whatsup: 0507703286

EMBEDDED SYSTEMS
“Until the philosophy which hold one

race Superior and another Inferior is
finally and permanantly discredited
and abandoned, everywhere is war.”
Robert Nasta Marley

EMBEDDED SYSTEMS
Overview
Buffering & DMA
Concurrency Masking Buffer

(b/n IO) Interrupts Processing

EMBEDDED SYSTEMS
Overview
Buffering & DMA
Direct
Double DMA
Memory
Buffering Configurations
Access DMA

EMBEDDED SYSTEMS
Concurrency Between I/O and Processing

Keyboard command processing
The “B” key is pressed by the user
The “keyboard” interrupts the processor
Jump to keyboard ISR

EMBEDDED SYSTEMS
Concurrency Between I/O and Processing

keyboard_ISR() {
ch < Read keyboard input register
switch (ch) {
case ‘b’ : startGame(); break;
case ‘x’ : doSomeProcessing();
break;
... How long does this
processing take?
}
} return from ISR

EMBEDDED SYSTEMS
Will Events Be Missed?

What happens if another
How fast is the keyboard_ISR()? key is pressed or if a timer
interrupt occurs?
keyboard_ISR(){
ch < Read keyboard input register
switch (ch) {
case ‘b’ : startGame(); break;
case ‘x’ : doSomeProcessing();
break;
... return from ISR
}
}
EMBEDDED SYSTEMS
A More Elegant Solution

Add a buffer (in software or hardware) for input characters.
This decouples the time for processing from the time between
keystrokes, and provides a computable upper bound on the time
required to service a keyboard interrupt.
keyboard_ISR() {
input_buffer[tail++ % BUF_SIZE] = ch;
... Stores the input and then quickly returns
to the “main program” (process)
}
return from ISR

EMBEDDED SYSTEMS
What Can Go Wrong?

1. Buffer could overflow (bigger buffer helps, but there is a limit)
2. Could another interrupt occur while adding the current keyboard
character to the input_buffer?
keyboard_ISR() {
... keyboard_ISR() {
} input_buffer[tail++
% BUF_SIZE] = ch;
return from ISR ...
}

EMBEDDED SYSTEMS
Masking Interrupts
If interrupts are masked (IRQ and FIQ disabled), nothing will be
processed until the ISR completes and returns.
Remember: entering IRQ mode masks IRQs and entering FIQ mode masks FIQs
and IRQs
keyboard_ISR() {
MASK_INTERRUPTS();
UNMASK_INTERRUPTS();
...
}
EMBEDDED SYSTEMS
keyboard_ISR(){
Buffer Processing
MASK_INTERRUPTS();
ch < Read ACIA input register
}
return from ISR
while (!quit){
if (tail != head){
process_command(input_buffer);
remove_command(input_buffer);
}
What happens if another command is }
entered as you remove one from the
input_buffer?
Must be careful when modifying the buffer with interrupts turned on.
EMBEDDED SYSTEMS
Buffer Processing
printStr(char *string) { printStr(“this is a line”);
while (*string) {
outputBuffer[tail++ % BUF_SIZE] = *string++;
}
}
T H I S I S
How about the print buffer?
tail points here and a timer interrupt occurs
Jump to timer_ISR
timer_ISR(){
clockTicks++;
printStr(convert(clockTicks));
}
T H I S I S 2 : 3 0
EMBEDDED SYSTEMS
Critical Sections of Code

printStr(char * string) { printStr(“this is a line”);
MASK_INTERRUPTS;
while (*string){
outputBuffer[tail++ % BUF_SIZE] = *string++;
}
} T H I S I S
Pieces of code that must appear as an tail points here and a timer interrupt occurs
atomic action
Jump to timer_ISR happens after printStr()
timer_ISR(){ completes
clockTicks++;
printStr(convert(clockTicks));
}
T H I S I S A L I N E
Atomic action action that “appears”' to take
place in a single indivisible operation
EMBEDDED SYSTEMS
Increasing Concurrency Between I/O and Programs

We have seen how to use buffers to de-couple the speed of
input/output devices from that of programs executing on the
CPU
And how to deal with the corresponding concurrency problems with
masking of interrupts
Now, how can we push this further??

In particular, can we get the I/O to happen without needing the CPU
for every single operation?!
EMBEDDED SYSTEMS
Programmed I/O
All of our examples so far have used programmed I/O
Programmed I/O: a program running on the processor moves data to/from the
device using instructions.
Either interrupts or polling are used to discover when devices are ready.
Memory
Processor buffer
On-chip
cache program
device
Bus
Processor grabs data from device and copies to buffer “by hand”
(manually)

EMBEDDED SYSTEMS
Direct Memory Access (DMA)

What is Direct Memory Access?
Hardware mechanism that allows peripheral components
to transfer their I/O data directly to and from main memory
without the need to involve the system processor.
Why is Direct Memory Access important?

Use of this mechanism can greatly increase throughput to
and from a device, because a great deal of computational
overhead is eliminated
EMBEDDED SYSTEMS
Direct Memory Access
What is the downside?

Hardware support is required – DMA controllers
DMA “steals” cycles from the processor
Synchronization mechanisms must be provided to avoid
accessing non-updated information from RAM

EMBEDDED SYSTEMS
What is Direct Memory Access?

DMA is a capability provided by some computer bus architectures,
including PCI, PCMCIA and CardBus, which allows data to be sent
directly from an attached device to the memory on the host,
freeing the CPU from involvement with the data transfer and thus
improving the host's performance.

EMBEDDED SYSTEMS

DMA Programming
The programming of a device's DMA controller is hardware specific.
Normally, the OS needs to have the local device address, the physical
memory address on the PC, and the size of the memory block to
transfer.
Then the register that initiates the transfer is set.

EMBEDDED SYSTEMS
Direct Memory Access DMA

EMBEDDED SYSTEMS
Direct Memory Access DMA

DMA transfers overcome the problem of occupying the CPU for the entire time
it's performing a transfer.
The CPU initiates the transfer, then it executes other ops while the transfer is in
progress, finally it receives an interrupt from the DMA controller when the
transfer is done
Hardware using DMA: disk drives, graphics cards, network cards, sound cards
DMA can lead to cache coherency problems
If a CPU has a cache and external memory, then the data the DMA controller has
access to (stored in RAM) may not be updated with the correct data stored in the
cache.
EMBEDDED SYSTEMS
DMA – Cache Coherency Solutions

Cache-coherent systems:
external writes are signaled to the cache controller which

performs a cache invalidation for incoming DMA transfers
or cache flush for outgoing DMA transfers (done by hardware)

EMBEDDED SYSTEMS
DMA – Cache Coherency Solutions
Non-coherent systems:
OS ensures that the cache lines are flushed before an outgoing
DMA transfer is started and invalidated before a memory range
affected by an incoming DMA transfer is accessed.
The OS makes sure that the memory range is not accessed by any
running threads in the meantime.
EMBEDDED SYSTEMS
DMA Transfer
(input example)
software: asks for data (e.g. read called)
1. Device driver allocates a DMA buffer, sends signal to device
indicating where to send the data, sleeps
2. Device writes data to DMA buffer, raises interrupt when finished
3. Interrupt handler gets data from DMA buffer, acknowledges
interrupt, awakens software to process the data
EMBEDDED SYSTEMS
DMA Transfer
hardware: asynchronously pushes data to the system
May push data even if no process is listening!
1. hardware raises an interrupt to announce that new data has arrived
2. interrupt handler allocates a buffer, tells the hardware where to
transfer the data
3. device writes the data to the buffer, raises another

interrupt when transfer is done
4. interrupt handler dispatches the new data, awakens any
relevant process, and takes care of housekeeping
EMBEDDED SYSTEMS
DMA Transfer
Overview (input example – network transfers)
• hardware: must deal with continuous data flow
Use a circular (ring) buffer in memory shared by device and the processor
1. incoming packet placed in next available buffer in the ring
2. interrupt is raised by the device
3. device driver sends packet to kernel code that will process it
4. device driver inserts a new buffer into the ring
(note: buffer allocation occurs at initialization so the insertion of a buffer is
just the selection of an already allocated buffer for the ring)
EMBEDDED SYSTEMS
DMA Transfer
Overview (input example – network transfers)
• pseudo code for read using circular buffer
Err_Type Procedure read(data_type data) {
if (empty_flag) return (ERR_BUF_EMPTY);
else { memory(read_ptr) = data;
full_flag = false;
read_ptr = (((read_ptrB)+1)mod N)+B;
if (read_ptr == write_ptr) empty_flag = true;
return(ErrOK);
}
}
EMBEDDED SYSTEMS
DMA Transfer

EMBEDDED SYSTEMS
DMA – Block Diagram

EMBEDDED SYSTEMS
DMA
Cycle stealing causes the CPU to execute more slowly
Number of required busy cycles can be cut by integrating the DMA and I/O
functions
Path between DMA module and I/O module that does not include the system bus

EMBEDDED SYSTEMS
DMA Configurations

EMBEDDED SYSTEMS
DMA Configurations

EMBEDDED SYSTEMS
Operating System Design Issues

Efficiency
Most I/O devices extremely slow compared to main memory
Use of multiprogramming allows for some processes to be waiting on I/O
while another process executes
I/O cannot keep up with processor speed
Swapping is used to bring in additional Ready processes which is an I/O
operation
Generality
Desirable to handle all I/O devices in a uniform manner
Hide most of the details of device I/O in lower-level routines so that processes and
upper levels see devices in general terms such as read, write, open, close, lock, unlock
EMBEDDED SYSTEMS
I/O Buffering
Reasons for buffering

Processes must wait for I/O to complete before proceeding
Certain pages must remain in main memory during I/O

EMBEDDED SYSTEMS
I/O Buffering
Block-oriented
Information is stored in fixed sized blocks
Transfers are made a block at a time
Used for disks and tapes
Stream-oriented
Transfer information as a stream of bytes
Used for terminals, printers, communication ports, mouse, and
most other devices that are not secondary storage

EMBEDDED SYSTEMS
Single Buffer
Operating system assigns a buffer in

main memory for an I/O request
Block-oriented
Input transfers made to buffer
Block moved to user space when
needed
Another block is moved into the buffer
Read ahead

EMBEDDED SYSTEMS
Single Buffer
Block-oriented
User process can process one block of data while next block is read in
Swapping can occur since input is taking place in system memory, not user
memory
Operating system keeps track of assignment of system buffers to user
processes
Stream-oriented
Used a line at time
User input from a terminal is one line at a time with carriage return signaling the end of
the line
Output to the terminal is one line at a time
EMBEDDED SYSTEMS
Double Buffer
Use two system buffers instead of one
A process can transfer data to or from one buffer while the

operating system empties or fills the other buffer

EMBEDDED SYSTEMS
Circular Buffer
More than two buffers are used
Each individual buffer is one unit in

a circular buffer
Used when I/O operation must

keep up with process

EMBEDDED SYSTEMS
Ring buffer (16 elements, buffer empty)
head
… …
… …
… …
tail The buffer is
… … empty when:
… … tail = head
… …
… …
… …

EMBEDDED SYSTEMS
Ring buffer (after two write operations)
2 elements have been

stored in the buffer
… …
… [0]
… [1]
tail head
… …
in this implementation write
… … operations are followed by the
… … advancing of the head pointer
… … (if possible)
… … (‘post-increment’)

EMBEDDED SYSTEMS
Ring buffer (after two read operations)
Read elements remain

in the buffer, but they
… … can now be overwritten
… [0]
… [1]
… … head
tail
… … (buffer empty)
… …
… …
… …

EMBEDDED SYSTEMS
Ring buffer (after 16 write operations)
[14] [15]
[13] [0] head
[12] [1]
The buffer is
[11] [2]
tail full when:
[10] [3] head = tail – 1
[9] [4]
[8] [5]
[7] [6]

EMBEDDED SYSTEMS
Thank You
nii_kommey@msn.com
050 770 32 86
Whatsup: 0507703286

EMBEDDED SYSTEMS
“Destruction of the poor is in their

poverty. Destruction of the soul is
vanity”
Robert Nasta Marley

EMBEDDED SYSTEMS
Overview
Embedded System OS
Windows Embedded
VxWorks Android
Embedded Linux

EMBEDDED SYSTEMS
Operating System Flavors

Desktop
Windows (9X, XP Home, XP/2000 Pro)
Mac
Server
Windows (XP/2000 Server &Advanced Server)
Unix Varieties
Embedded
Many
EMBEDDED SYSTEMS
What is an Embedded OS?

An "embedded system" is any computer system or computing
device that performs a dedicated function or is designed for
use with a specific embedded software application.
Embedded systems may use a ROM-based operating system or

they may use a disk-based system, like a PC. But an embedded
system is not usable as a commercially viable substitute for
general purpose computers or devices.
EMBEDDED SYSTEMS
What Makes A Good Embedded OS?

Modular
Scalable
Configurable
Small footprint
CPU support
Device drivers
etc...
EMBEDDED SYSTEMS
What Makes A Good RTOS?

Multi-threaded and preemptive
Thread priority has to exist because no deadline driven OS

exists
Must support predictable thread synchronization mechanisms
A system of priority inheritance must exist

EMBEDDED SYSTEMS
Who Are The Embedded OS Players?

Microsoft
Embedded NT/XP
“Real-time” control
Windows CE (CE.NET)
Internet devices
Pocket PC 2002
Handheld PC’s and PDA’s
Wind River Systems
VxWorks
pSOS
EMBEDDED SYSTEMS

 AMIRIX Embedded Linux
Commercial Embedded Linux  Coollogic Coollinux
 Coventive Xlinux
 Esfia RedBlue Linux
 KYZO Pizza Box Linux
 Lineo Embedix
 LynuxWorks BlueCat
 MontaVista Linux..
EMBEDDED SYSTEMS

Open Source Embedded Linux
 Embedded Debian Project

 ETLinux
 uCLinux
 uLinux (muLinux)
……

EMBEDDED SYSTEMS
Who are the Embedded OS players?

 QNX Software Systems
QNX
 Palm PDA
Palm OS
 Symbian
Symbian OS
 Green Hills Software

Integrity..

EMBEDDED SYSTEMS
Microsoft Mobility Platforms Pocket PC

• Information
consumption
• View and some data
Smartphone entry
• Information • Integrated PDA with
consumption phone
• Primarily data • Interoperability with
viewing Office, Exchange Tablet PC
• Integrated phone and SQL Server • Complex document
with PDA • .NET Compact authoring, editing and
• Interoperability Framework active reading
with Exchange • ASP.NET mobile • Note taking and ink
Smart • .NET Compact controls annotating
Personal Framework Notebook PC
• Keyboard centric at the
Objects • ASP.NET mobile • Complex document desk, pen & keyboard
controls authoring, editing and away from the desk
• One-way
reading
network • Keyboard, mouse plus
• Keyboard centric at the pen, ink, and speech
• Information
desk input methods
consumption
• Keyboard and mouse • Full .NET framework
input methods preinstalled
• Full .NET framework • Pen, ink, handwriting and
Increased Functionality available speech recognition API’s
Windows CE Windows Mobile Windows XP/XPE

EMBEDDED SYSTEMS
Windows Embedded Family

EMBEDDED SYSTEMS
VxWorks
VxWorks is a commercial hard real time operating
system developed by wind river systems.
The main idea: use monolithic kernel to schedule user

tasks according to user defined priorities.
Maximize kernel timing predictability.
Gives the users maximal control.

EMBEDDED SYSTEMS
VxWorks
A dedicated real time system, not intended as
a general purpose OS.
lacks many modern OS features that interfere
with real time performance (flat memory
model, no paging).
EMBEDDED SYSTEMS
VxWorks
Scheduling is done using a preemptive priority driven
approach, priorities are chosen arbitrarily by the user (0-255).
Priorities can be changed by the user at runtime but this is
discouraged.
A user can lock a task so that it can’t be preempted even by
higher priority tasks or interrupts.
This allows the use of the fixed priority response time analysis
to check schedule-ability offline.
EMBEDDED SYSTEMS
VxWorks
Is resource sharing aware and has a priority inheritance
built in.
Optimizations in implementation of the context switch
and the return from interrupts.
The kernel never disables NMI (non-maskable interrupts)
so they are always available to the user.
EMBEDDED SYSTEMS
VxWorks - Limitations
Lacks many modern OS features.
Guaranteeing the deadlines is the responsibility of the user at design

time.
Doesn’t support most modern applications and APIs (only a small

subset of POSIX).
Despite the flat memory model dynamic memory allocation still cases
memory fragmenting, which increases timing unpredictability.
EMBEDDED SYSTEMS
VxWorks - Limitations
A dedicated and widely used real time system.
Offers the user maximal control , but also

passes him responsibility for the deadlines.
EMBEDDED SYSTEMS
Tornado — Development Tools

EMBEDDED SYSTEMS
GDB —Debugger

EMBEDDED SYSTEMS
WindView —Tracer and Analyzer

EMBEDDED SYSTEMS
Embedded Linux
A simple view of embedded Linux
Developing process of an embedded devices with embedded

Linux
Embedded Linux VS windows CE

EMBEDDED SYSTEMS
Embedded Linux in various devices:

EMBEDDED SYSTEMS
Developing Process Rehat,bluecat,RTLinux,

From system Linux OS Monta Vista
design select Linux,RTAI,…
OS Porting and http://linux.orghttp:/

test
improvement /www.gnu.org…
Driver and Application

software Tekram,HP,Intel,…
development
EMBEDDED SYSTEMS
Windows Embedded VS Linux Embedded
Both on strong
uptake curve!
Oses targeted in current and next embedded projects,2002,data from EDC

EMBEDDED SYSTEMS
Thank You
nii_kommey@msn.com
050 770 32 86
Whatsup: 0507703286

EMBEDDED SYSTEMS
“It is possible to store the mind

with a million facts and still be
entirely uneducated”
Alec Bourne

EMBEDDED SYSTEMS
Overview
Security & Cryptography
Types of Methods Security

Cryptography
Threats of Attack Mechanisms

EMBEDDED SYSTEMS
Overview
Cryptography
Data
Hashing Rivest Shamir
Encryption Authentication
MD5 Adleman RSA
Standard DES

EMBEDDED SYSTEMS
Security
Threats Mechanisms
Authorization
Interruption
Authentication
Interception
Subject Modification Object

Fabrication
Encryption
Auditing
Data and control stream

EMBEDDED SYSTEMS
Security
Objects
passive entities whose security attributes must be protected
Subjects
active entities that access objects
Threats
potential dangers which harm security
Security Policy
a precise specification to describe appropriate levels of security
Security Mechanism: an implementation of a given security policy
EMBEDDED SYSTEMS
Types of Threats
Interception
an unauthorized subject has gained access to an object, such as stealing
data, overhearing others communication, etc.
Interruption
services or data become unavailable, unusable, destroyed, and so on,
such as lost of file, denial of service, etc.

EMBEDDED SYSTEMS
Types of Threats
Modification
unauthorized changing of data or tempering with services, such as
alteration of data, modification of messages, etc.
Fabrication
additional data or activities are generated that would normally no exist,
such as adding a password to a system, replaying previously send
messages, etc.

EMBEDDED SYSTEMS
Methods of Attack
Eavesdropping
obtaining copies of messages without authority
Masquerading
sending/receiving messages using other’s identifier
Tempering
stealing messages and altering their contents
EMBEDDED SYSTEMS
Methods of Attack
Replaying
storing messages and sending them at later date
Infiltrating
accessing system in order to run programs that implement
the attack (virus, worm, Trojan horse)
Unknown yet
new attacking methods may appear later
EMBEDDED SYSTEMS
Indirect Infiltration
Trojan Horse
A piece of code that misuses its environment. The program seems innocent
enough, however when executed, unexpected behavior occurs.
Worms
Use spawning mechanism; standalone programs. Such facilities may exist
accidentally as well as intentionally.
Viruses
Fragment of code embedded in a legitimate program. Mainly effects personal
PC systems. These are often downloaded via e-mail or as active components in
web pages.

EMBEDDED SYSTEMS
Security Mechanisms
Encryption
transforming data into something an attacker cannot understand, i.e.,
providing a means to implement confidentiality, as well as allowing
user to check whether data have been modified.
Authentication
verifying the claimed identity of a subject, such as user name,
password, etc.
EMBEDDED SYSTEMS
Security Mechanisms
Authorization
checking whether the subject has the right to perform the action
requested.
Auditing
tracing which subjects accessed what, when, and which way. In
general, auditing does not provide protection, but can be a tool
for analysis of problems.
EMBEDDED SYSTEMS
Dedicated Security Mechanism

clients
………
Authentication authorization auditing other

req servers
reply
encrypt/decrypt Trusted secure system kernel
Special servers dedicated to different security issues

EMBEDDED SYSTEMS
Layered Security Mechanism

client
Application + security Application + security
Middleware + security Middleware + security
Operation system and Operation system and

security security
Secure Comm. Secure Comm.

kernel mechanism kernel mechanism
security security

EMBEDDED SYSTEMS
RISSC Security Mechanism

client
Secure server Normal server
RISSC (Reduced Interface for Secure System Components)

Any security-critical server is placed on a separate machine isolated from
end-user systems using low-level secure network interface. Clients run on
different machines and can access the secured server only through these
network interface.
EMBEDDED SYSTEMS
Cryptography
Intruders and eavesdroppers in communication

EMBEDDED SYSTEMS
Cryptography System
DEFINITIONS: Symmetric cryptosystem:
Encryption:
Ke = Kd = K
C = E( P, Ke )
E = Encrypting Algorithm P= D(E( P, K ), K)
P = Plain text
Ke = Encryption key
C = Cipher text Asymmetric cryptosystem:
Decryption:
Ke ≠ Kd
P = D( C, Kd )
D = Decrypting Algorithm
P = D( E(P, Ke), Kd )
Kd = Decryption key
EMBEDDED SYSTEMS
Example: Symmetric cryptosystem

Ceasar Cipher:
K=1
Encryption: C[i] = P[i] + K
Decryption: P[i] = C[i] - K
P = Attack at dawn
C = Buubdl!bu!ebxo

EMBEDDED SYSTEMS
DES: Data Encryption Standard
A symmetric cryptosystem: operate on 64-bit blocks:

• The principle of DES
• Outline of one encryption round

EMBEDDED SYSTEMS
Discussion of DES
The principle of DES is quite simple: initial permutation, 16

rounds of transformation, and final permutation.
Even through the DES algorithm is well known, but the key or
cipher is difficult to break using analytical methods.

EMBEDDED SYSTEMS
Discussion of DES
Using a brute-force attack by simply searching for a key is
possible.
However, for 56-bit key, there are 256 possible key combinations,
if we could search one key in 1 µs, then we need 2283 years to try
all keys. (Distributed.net broke a DES-56 within 22 hours and 15
minutes, by using 100,000 PCs).
Use 3DES (K1, K2, K3), or DES-128 for high security.

EMBEDDED SYSTEMS
Public-Key Cryptosystems: RSA

Public key list
public KE private KD
Encryption Decryption
Plain P Cipher C Plain P
C = E(P, KE) P = D(C, KD)
An asymmetric cryptosystem (Rivest, Shamir, and Adleman, 1978):

• Based on the fact that no methods are known to efficiently find the prime factors of larger
numbers.
EMBEDDED SYSTEMS
Generating RSA Keys

(1) Pick up 3 large prime numbers, let S be the maximum, and X, Y be the rest;
(2) Let N = X * Y;
(3) Assume a unknown number Q, such that
(S * Q) mod (X – 1)(Y – 1) = 1
From (1), we know that S is an prime, and (X -1)(Y-1) is an even number, so there GCD is 1, that is GCD(S, (X-1)(Y-
1) ≡ 1. We can use Euclid Algorithm to calculate: S*Q + (X-1)(Y-1) * R0 = 1
(4) Now, we got a triple (S, Q, N), and have
PSQ mod N ≡ P, that is
( PQ mod N )S mod N ≡ P
encryption
decryption

EMBEDDED SYSTEMS
Example: RSA Cryptosystem (1)

(1) Pick up 97, 47, 79. Let S = 97, X = 47, and Y = 79.
(2) N = X * Y = 3713;
(3) (X-1)(Y-1) = 3588, thus we should solve:
97 * Q + 3588 * R0 = 1, (calculation process omitted)
we have Q = 37, and R0 = -1 (we do not need R0)
(4) Now, we got a triple (S = 97, Q = 37, N = 3713)
char blank A B C … Y Z
code 00 01 02 03 … 25 26
From the above char/code table, we have:

ATTACK AT DAWN  01202001031100012004012314
EMBEDDED SYSTEMS
Example: RSA Cryptosystem (2)

 ATTACK AT DAWN  01202001031100012004012314
 Message is first divided into fixed-length blocks, such as
(0120)(2001)(0311) …
 To encrypt message, calculate each block by using Q = 37, N = 3713:

(0120)37 mod 3713 = 1404
(2001)37 mod 3713 = 2932
(0311)37 mod 3713 = 3536
…
 Integrate block coding together, we have:
140429323536…
 Decryption at the receiver side uses S = 97, N = 3713:

(1404)97 mod 3713 = 0120
(2932)97 mod 3713 = 2001 01202001031100012004012314
(3536)97 mod 3713 = 0311 ATTACK AT DAWN
…
EMBEDDED SYSTEMS
Hashing Function Cryptosystem

 A hash function h = H(m) takes a message m of arbitrary length as input and
produces a fixed-length bit string h as output.
 A hash function is a one-way function, i.e., it is computationally infeasible to
find the input m that corresponds to a known output h.
 The weak collision resistance property, i.e., given m and h = H(m), it is
computationally infeasible to find another m’ (m’≠ m), such that H(m) = H(m’).
 The strong collision resistance property, i.e., when only given H, it is
computationally infeasible to find two different m and m’, such that H(m) =
H(m’).
EMBEDDED SYSTEMS
MD5: Message-Digest
Initialization: Algorithm 5
input： 448 bits 448 bits 448 bits …
padding： 448 64 448 64 …
input1：512 bits input2：512 bits inputK：512 bits
MD5 K-phase process
MD5 is a hash function for computing a 128-bit, fixed-length message digest from an
arbitrary length binary input.
Initialization: dividing input into 448-bit blocks and then padding these blocks into 512-
bit blocks.
EMBEDDED SYSTEMS
MD5: K-phase Hashing
K is the number of padded blocks

Each phase consists four rounds of computations by using four different functions.
Typical application of MD5 is Digital Signature.
EMBEDDED SYSTEMS
Authentication
 How to make the communication between clients and servers (or senders
and receivers) secure? We need to authentication of communication
parties.
 Authentication and message integrity are closely related, cannot go
without each other.
 Commonly use authentication models:
(1) based on a shared secret key
(2) based on a key from KDC (Key Distribution Center)
(3) based on public key
EMBEDDED SYSTEMS
Challenge-response protocol (1)
Authentication based on a shared secret key K A, B

EMBEDDED SYSTEMS
Authentication based on a shared secret key, but using three instead of five
messages. Any problem?
EMBEDDED SYSTEMS
The reflection attack: Bob gave away valuable information

KA, B(RB) without knowing for sure to whom he was giving it.
EMBEDDED SYSTEMS
KDC based protocol (1)
KDC shares a secret key with each of the clients.

KDC hands out a key to both communication parties.
Problem: A  B even before B got the key from KDC.
EMBEDDED SYSTEMS
KDC based protocol (2)
Using a ticket KB, KDC(KA, B) and letting Alice set up a connection to Bob.
EMBEDDED SYSTEMS
Needham-Schroeder Authentication Protocol
A well-known authentication protocol.

Challenge RA1 is called a nonce, a random number used only once.
Uniquely relate two messages to each other.
EMBEDDED SYSTEMS
Public Key Authentication Protocol
Mutual authentication in a public-key cryptosystem.

It is important that Alice must trust that she got the right public key (as well as the most
updated key) to Bob, and not the public key of someone impersonating Bob.

EMBEDDED SYSTEMS
Digital Signatures
A digit signature has the same authentication and legally binding functions
as a handwritten signature.
An electronic document or message M can be signed by an entity A by
encrypting a copy of M in a key KA and attaching it to a plain-text copy of
M and A’s identifier, such as <M, A, E(M, KA)>.
Once a signature is attached to a electronic document, it should be possible
(1) any party that receives a copy of message to verify that the document
was originally signed by the signatory, and (2) the signature can not be
altered either in transmit or the receivers.
EMBEDDED SYSTEMS
Public Key Digital Signatures (1)
Digital signing a message using public-key cryptography.

Problem: the validity of Alice’s signature holds only as long as Alice’s private
key remains a secret and unchanged.
Problem: the signature is too big.
EMBEDDED SYSTEMS
Public Key Digital Signatures (2)
Digitally signing a message using a message digest.

Problem: hash function based signature is no longer safe, such as MD5.

EMBEDDED SYSTEMS
Needham-Schroeder Digital Signatures

1
A，KA，KDC(M)
2
KS(A，M，T)
K
D
A 3 C B
A，M，KS(A，M，T)
4
B，KS(A，M，T)
5
KB，KDC (A，M，T)
KDC verifies A’s signature (step 2). B trusts the KDC.

It would be difficult for A to claim that the signature was forged, for B has a copy that can
be checked with KDC. On the other hand, A could not claim that B forged the signature,
for B does not know the KDC’s secret key.
EMBEDDED SYSTEMS
Access Control
Subject Ref Monitor Object
Request Authorization
A request from a client can be carried out only if the client has sufficient access
rights for that requested operation.
Verifying access rights is called access control, whereas authorization is about
granting access rights.
Many access control models:
Access Control Matrix
Access Control List (Capability List)
Firewalls
EMBEDDED SYSTEMS
Access Control Matrix

Sub/Obj file 1 file 2 file 3 file 4
user 1 owner R/W Exec owner
user 2 -- R owner R/W
user 3 Copy/R owner -- --
(a) Resource ACM
Sub/Obj process 1 process 2 process 3

process 1 -- send Unblock send
process 2 receive -- receive
process 3 Block receive send --
(b) Process communication ACM
Sub/Obj domain A domain B domain C

domain A -- enter --
domain B -- -- enter
domain C enter -- --
(c) Domain communication ACM

EMBEDDED SYSTEMS
Access Control List
ACM is simple and straightforward, but if a system supports thousands

of users and millions of objects, the ACM will be a very sparse matrix.
An ACL (Access Control List) is a column of ACM with empty entries
removed, each object is assumed to have its own associated ACL.
Another approach is to distribute the matrix row-wise by giving each
subject a list of CL (Capability List).

EMBEDDED SYSTEMS
Comparison between ACL and CL
ACL is associated with Object
CL is associated with Subject

EMBEDDED SYSTEMS
Firewalls
A Firewall is a special kind reference monitor to control external access to any
part of a distributed system.
A Firewall disconnects any part of a distributed system from outside world, all
outgoing and incoming packets must be routed through the firewall.
A firewall itself should be heavily protected against any kind of security threads.
Models of firewall:
Packet-filtering gateway
Proxy:
Application-level Proxy
Circuit-level Proxy
EMBEDDED SYSTEMS
Firewalls: Bastian Structure

external network
Bastian
internal network
… protected hosts …
A Bastian is a special computer which provides secure services, including

authentication and access control.
Bastian can be a single machine or a dual-machine.
EMBEDDED SYSTEMS
Firewalls: Bastian + Filtering Gateway

external network
Filtering gateway
… protected machines ...
bastian
internal network
Gateway implements IP packet filtering functions.

A Bastian provides secure services.
EMBEDDED SYSTEMS
Thank You
nii_kommey@msn.com
050 770 32 86
Whatsup: 0507703286

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EMBEDDED SYSTEMS

DEPARTMENT OF COMPUTER ENGINEERING

COE 358 EMBEDDED SYSTEMS

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 1

“What has been hidden from the

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 2

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 3

3hrs Teaching Strong Programming Knowledge in C

2hr Practicals Basic Operating System Knowledge

3 Credit Hours Strong Knowledge in Electronics

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 4

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 5

The Processor (CPU Interfacing) – lecture 2

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 6

Embedded Systems Development – lecture 7

Embedded Communications – lecture 8

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 7

Polling & Interrupts – lecture 10

Buffering & DMA – lecture 11

Embedded Operating Systems – lect. 12

Security and Cryptography – lecture 13

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 8

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 9

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 10

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 11

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 12

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 13

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 14

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 15

Embedded System Overview

What is Embedded Software and Embedded

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 16

Embedded System Overview

What is Embedded System ?

Embedded System Overview

Embedded System Components

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 18

Introduction to Embedded Systems

Most of us think of “desktop” computers

But there’s another type of computing system far more

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 19

Introduction to Embedded Systems

–Hard to define. Nearly any computing system other than a

–Perhaps 50 per household and per automobile

Introduction to Embedded Systems

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 21

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 22

Embedded System Components

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 24

Embedded System Components

Embedded System Hardware

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 25

Embedded System Components

Embedded System Software

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 26

Embedded System Components

Processors CPU Memories Buses Peripherals

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 27

Embedded System Components

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 28

Embedded System Components

4/15/2017 Ing. B. Kommey, bkommey.coe@knust.edu.gh, 0507703286 29

Tel: 050 770 32 86