ECE 6412 - Spring 2006 Prof.

Ayazi

EXAMINATION NO. 2 SOLUTIONS

Problem 1 - (35 points)
The op amps below have identical DC currents and W/L values for transistors with the same
number. Find parametric expressions for entries in the table in terms of bias currents I5 and I7,
Kn’, Kp’, λN, λP, VTN, |VTP|, S=W/L ratios, VDD, VSS, Cc, CL, and identify which is larger in
magnitude for the two circuits. Assume K’n>K’p, VTN= -VTP, λN<λP, (W/L) 1= (W/L)2, VDD=-
VSS. The threshold voltage is larger than the ON (saturation) voltage. Ignore body effect.
USE THE LAST SHEET TO DO YOUR WORK AND THEN WRITE YOUR FINAL
ANSWER/EXPRESSION IN THE TABLE. NO PARTIAL CREDIT.

N-channel Input Op Amp P-channel Input Op Amp

Characteristic N-channel Input Op Amp <,=,> P-channel Input Op Amp

Small-signal ( I 7 (λ6 + λ7 ))−1 = ( I 7 (λ6 + λ7 ))−1
output
resistance
Small-signal 8K N′ K P′ S1S6 = 8K N′ K P′ S1S6
voltage gain
I 5 I 7 (λ2 + λ4 )(λ6 + λ7 ) I 5 I 7 (λ2 + λ4 )(λ6 + λ7 )

Gain- K N′ S1 I 5 > K P′ S1 I 5
bandwidth
Cc Cc
Upper input I5 > 2I5 I5
common VDD − VTP + VTN − VDD − VTP − −
K P′ S3 K P′ S5 K P′ S1
mode voltage
Slew rate(due I5 = I5
to Cc) Cc Cc
Positive (VDD) no expression needed < no expression needed
PSRR

1
Negative no expression needed > no expression needed
(VSS) PSRR

Phase K N′ S1 I 5 CL K N′ S1 I 5 < K P′ S1 I 5 CL K P′ S1 I 5
90o − tan −1 ( ) − tan −1 ( ) 90o − tan −1 ( ) − tan −1 ( )
Margin ′ C
2 K P S6 I 7 C 2 K P′ S6 I 7 2 K N′ S6 I 7 C
C 2 K N′ S6 I 7
(EXTRA
CREDIT)

2
 Problem 2 - (35 points)

The device parameters for the operational amplifier shown below are given in the table.
Ignore the body effect of the MOS transistor and the internal capacitances of all the
transistors.
a. What resistance R in the emitter of Q9 is required to set the first stage bias currents in
the emitters of Q3 and Q4 at 10µA each?
b. Calculate the overall voltage gain of the amplifier, by calculating the effective
transconductances of the differential input stage and the 2nd gain stage, and their
effective output resistances.
c. Calculate the value of the miller capacitance Cc required to obtain a gain-bandwidth
of 2MHz for this op-amp.
d. Calculate the phase margin of this op-amp.

Parameter NPN PNP

Beta 200 50
Early voltage 130V 50V
VBE(on) 0.7V 0.7V
Vt 25mV
MOS
lambda 0.01V-1
µCox 100µA/V2
VTO 0.7V

a) RIC9=Vtln(IC8/IC9)

IC8=(20V-1.4V)/50kΩ=0.372mA

IC9=20µA Æ R=3.65kΩ

g m1 g A 1 1
b) GmI = = m1 = 200 × 10−6 note that : re3 = =
1 + g m1re3 2 V g m3 g m1
RI = r07 || r04 (1 + g m 4 × re 2 ) = r07 || 2r04 = 5.65M Ω
VAnpn VApnp
because : r07 = = 13M Ω and r04 = = 5M Ω
IC 7 IC 4
Æ AvI = GmI × RI = 1130
I
R3 I C13 = Vt ln( C10 ) ⇒ I C13 = 100 µ A
I C13
g mm1 A W A
GmII = = 0.663 × 10−3 note that : g mm1 = 2µ Cox ( )mm1 I mm1 = 1.414 ×10−3
1 + g mm1 R2 V L V

RII = rdsm1 (1 + gmm1 × R2 ) || r013 (1 + g m13 × R3 ) = 2.13M Ω ||1.16M Ω = 0.749M Ω

AvII = GmII RII = 497

Av = AvI × AvII ≅ 561, 610

3
 GmI 200 ×10−6
c) GBW = ⇒ CC = = 15.9 pF
CC 2π × 2 × 10−6
2MHz 2MHz
d) Φ M = 90o − tan−1 ( ) − tan−1 ( )
p2 z
GmII 0.663 ×10−3
p2 = = = 132 × 106 rad = 21.1 MHz
CL 5 × 10−12 sec
GmII 0.663 × 10−3
z= = −12
= 41.69 × 106 rad = 6.64 MHz
CC 15.9 ×10 sec
2 2
⇒ Φ M = 90o − tan −1 ( ) − tan −1 ( ) = 90o − 5.41o − 16.76o = 67.82o
21 6.64

4
Problem 3 - (30 points)
In this problem, you are not asked to provide any numerical calculations. You are only
required to provide expressions. Make sure that your final expression for each section is
clearly identified and legible. For the cascoded two-stage CMOS Op-Amp shown below:

VDD

4
M3 M4 M6

3
1
CC VBP M7

2 VOUT
M1 M2
V− V+ CL
VBN M8

M5
VBIAS M9

VSS

a. Show an expression for the overall voltage gain of this amplifier as a function of
transistor transconductances and output resistances.

Av = g m1 (rds 4 || rds 2 ) × g m 6 [( g m 7 rds 6 rds 7 ) || ( g m8 rds 8 rds 9 )]

14444244443
RII

b. Show the expressions for the poles associated with the two capacitors CC and CL,
as a function of the two capacitance values, transistor transconductances and
output resistances. Assume that CC and CL include the transistor internal
capacitances at their respective nodes.
1 1
p1 = and p2 =
(rds 4 || rds 2 )Cc RII CL

c. If CL>>CC, provide an expression for the unity gain frequency (GB) of the
amplifier.

g m1 g m 6 (rds 4 || rds 2 )
GBW =
CL

5
 d. Show an expression for the pole associated with node 3, in terms of transistors
internal capacitances, transconductances and output resistances. Identify all the
components of the internal capacitances.
1
p3 =
(rds 6 || R3 )C3
C3 = Cgs 7 + Csb 7 + Cgd 6 + Cdb 6
rds 7 + g m8 rds8 rds 9 1 g r r
R3 = ≅ + m8 ds 8 ds 9
1 + g m 7 rds 7 gm7 g m 7 rds 7

e. Is there a right half plane zero in this amplifier that would affect the phase
margin? If there is, provide an expression for the position of this zero.

No, because a miller configuration is not usedÆ there is no RHZ that would affect the
phase margin

f. (EXTRA CREDIT) Show expressions for any pole or zero associated with node
4. Identify all the components of the internal capacitances.

− g m3
p4 =
Cx
Cx = Cgs 3 + Cgs 4 + Cdb3 + Cdb1 + Cgd 1
−2 g m3
z4 =
Cx

6
ECE 6412- Spring 2006 Page 1

;;
Homework No. 1 - Solutions
Problem 1 - (10 points)

;;;;
;;; ;;
A top view of a MOS transistor is n+

;;; ;;
shown. (a) Identify the type of
transistor (NMOS or PMOS) and its p+

;;;
;;;;;
value of W and L.
(b.) Draw the cross-section A-A’ A A'
approxi- mately to scale.
Metal

;;;;
(c) Assume that dc voltage of terminal 1

;;;;
;; ;
is 5V, terminal 2 is 3V and terminal 3 is Poly
0V. Find the numerical value of the
capacitance between terminals 1 and 2, 2
and 3, and 1 and 3. Assume that the dc
value of the output voltage is 2.5V and p-well
that the voltage dependence for pn

;;;;;;;;;;;;;;
;;;;
junction capacitances is for both 3 2 1
transistors is -0.5 (this is called MJ in n-substrate

;; ;; ;;
SPICE).

;
IOX IOX
Solution
IOX

;;
(a.) This transistor is an NMOS

;;;
;;
transistor with the drain as terminal 1, the
gate as terminal 2, and the bulk and
F F

;;;
;;
source connected together to terminal 3.
The W = 26µm and L = 4µm . O O
X X
(b.) The approximate cross-section is
shown (vertical scale is magnified by 4 p+ n+ n+
times).
(c.)With VDS = 5V, VGS = 3V and VT =
0.75V, the transistor is in saturation. p-well 21µm
Therefore, the capacitors are:
C12 = CGD = LD(NMOS)xWxCox S00PES1

= 0.45µm·26µm·0.7fF/µm2 = 8.19fF
C23 = CGS = LD(NMOS)xWxCox + 0.67(WxL)X Cox = 8.19fF + 48.776fF
= 56.966fF
C13 requires the area of the drain (AD) and the perimeter of the drain (PD). These values
are AD = 26µmx10µm = 260µm2 and PD = 2(10+26) = 72µm.
[AD·0.33fF/µm2+PD·0.9fF/µm] [260µm2 ·0.33fF/µm2+72µm·0.9fF/µm]
C13 = CBD = =
5 5
1 + 0.6 1 + 0.6
= 49.29fF
ECE 6412- Spring 2006 Page 2

Problem 2 - (10 points)

Find the numerical values of I1, I2 ,V D , V E , and V C to +2.5V
within ±5% accuracy.
100µm
Solution 1µm
First find I1. This is done by solving the equations I1 = M2 100kΩ
VC
K’W Q1
2 I2
2L (VGS4-VT) I1

and 5V = I1100kΩ + VGS4 VE VD

M3 M4
Solving quadratically gives 50µm 10µm
1µm 1µm
 1  5
VGS42 - VGS42 V T - 12 + V T 2 - 12 = 0
S00PEP1 -2.5V
VGS2 - 1.41667VGS + 0.145833 = 0

This gives VGS = 0.708335 ± 0.5965 = 1.305V ∴ VD = -2.5+1.305 = -1.195V

5-1.195
This value of VGS gives I1 = = 36.95µA
100kΩ
Neglecting the lambda effects, let I2 = 5I1 = 184.75µA
The base-emitter voltage of Q1 is found as
 I2 184.75µA
VE = -VBE1 = -VTln I  = -0.026ln 10fA  = -0.614V
 s
2I2 2x184.75
Finally, the value of VGS2 = K’W 2 /L 2 + VT = 800 + 0.75 = 1.43V

∴ VC = 2.5V - 1.43V = +1.070V

ECE 6412- Spring 2006 Page 3

Problem 3
Find the numerical values of all roots and the VDD
midband gain of the transfer function vout/vin of the RL= RL=
differential amplifier shown. Assume that K N ’ = 10kΩ 10kΩ
100µA/V2, V TN = 0.7V, and λN = 0.04V-1. The CL =1pF
- vout +
CL =1pF
values of Cgs = 0.2pF and Cgd = 20fF.
M1 M2
Solution 100/1 100/1
A small-signal model appropriate for this circuit is vin
shown.
1mA
+
vin Cgd vout
Cgs RL CL S03E1P4
2 rds1 2
gm1vgs1 -
Fig. S03E1S4
Summing the currents at the output nodes gives,
gm1vgs1 + sCgd(vout-vin) + (gds1 + GL)vout + sCL vout = 0
(Note: we are ignoring the fact that vout and vin should be divided by two since it makes no
difference in the results and is easier to write.) Replacing vgs1 by vin gives
-(gm1 - sCgd)vin = [(gds1 + GL) + sCL + sCgd] vout

 1 - sC g d 
vout -(g m1 - sC gd )  -gm1  gm
= =
v in s(C L + C gd ) + (g ds1 + G L ) g ds1 + G L   C + C 
1 + s gLds1 + Gg dL 
gm g ds + G L
∴ MGB = - gm1(rds||RL), Zero = C and Pole = - C + C
gd gd L
1 25
gm = 2·100·100·500 = 3162.3µS and rds = = 500µA = 50 kΩ
λ ID
∴ MGB = -3.162mS·(10kΩ||50kΩ) = -26.35 V/V

3.162x10-3
Zero = = 1.581x1011 radians/sec.
20x10-15
-1
Pole = = -1.1176x108 radians/sec.
1.02x10-12(10kΩ||50kΩ)
ECE 6412- Spring 2006 Page 4

Problem 4
Find the voltage transfer function of the common-gate amplifier VDD
shown. Identify the numerical values of the small-signal voltage
gain, vout/vin, and the poles and zeros. Assume that
RD =
ID =250µA, K N ’ = 100µA/V2, V TN = 0.5,
10kΩ
λ ≈ 0V-1, Cgs = 0.5pF and Cgd = 0.1pF.
20 +
Solution 1 vout
The small signal transconductance is, VBias RS = I -
D
1kΩ
gm = 2·KN·(W/L)ID = 2·100·20·250 = 1mS
vin
rds = ∞
gmvgs
The small signal Rs S04E1P3
model is, - +
vin Cgs vgs Cgd vout
+ RL
-
S04E1S3

The voltage gain can be expressed as follows,

Vout  Vout  Vgs Vout  RL(1/sCgd) 
=
V in  Vgs   V in  , Vgs = -g m RL+(1/sC gd)

Sum currents at the source to get,

V in + V g s Vgs -Gs
Rs + gmVgs + sCgsVgs = 0 → V in = Gs + gm + sCg s
Vout  g m R L   1 1
∴ =  
V in 1+ g m R L   sCgdRL+1  sC gs 
 gm+G s + 1
The various values are,
gmRL 1·10
Voltage gain = 1+ g R = 1+1 = 5V/V
m L
-1 -1
p1 = C R = -13 4 = -109 radians/sec.
gd L 10 ·10

-(gm+Gs) -10-3+10-3
p2 = C = -12 = -4x109 radians/sec.
gs 0.5x10
ECE 6412- Spring 2006 Page 5

Problem 5
Draw the electrical schematic using the proper symbols for the transistors. Identify on your
schematic the terminals which are +5V, ground, input, and output. Label the transistors on

;
the layout as M1, M2, etc. and determine their W/L values. Assume each square in the

;;;;
layout is 1 micron by 1 micron. Find the area in square microns and periphery in microns
for the source and drain of each transistor.

;; ;
;;;;
Metal n+ p+ p-well Poly Contact

;;; ;;;
M1 Ground

;;;;
;;;
;;; ;;;
;;;
M2

+5V
;;;;
;;;;;;
Input
Output

N-Substrate
+5Volts
D1
G1 M1 B1 AS1 = AD1 = 40x8 = 320µm2
W1
= 10
L1 PS1 = PD1 = 8+8+40+40 = 48µm
Input S1 Output
S2
M2 AS2 = 2AS1 = 640 µm2
G2 B2 W2 AD2 = AD1 = 320µm2
= 20
L2 PS2 = 2PS1 =192µm
D2 PD2 = PD1 = 96µm
Ground S01PES1
ECE 6412 - Spring 2006 Page 1

Homework Assignment No. 4 - Solutions

Problem 1
Find the midband voltage gain and the –3dB frequency in Hertz for the circuit shown.
R1=1kΩ C2=1pF

+ +
Vin C1= R2= V1 R3= C3=
V1 Vout
10pF 10kΩ 100 20kΩ 10pF -
-
S02E1P3
Solution
The midband gain is given as,
Vout  20kΩ  10kΩ
V in = -  100  11kΩ = -181.82V/V

To find the –3dB frequency requires finding the 3 open-circuit time constants.
RC10:

RC10 = 1kΩ||10kΩ = 0.9091kΩ → RC10C = 0.9091x10ns

=9.09ns
RC20:
it
vt = it RC10 + R3(it+0.01V1) S02E1S3
= it(RC10 + R3 + 0.01RC10R3) +v -
t

∴ RC20 = RC10 + R3 + 0.01RC10R3 +

Rc10 V1 V R3
=0.9091+20x -
1
(1+0.01·909.1)kΩ = 202.72kΩ 100

RC20C2 = 202.72x1ns =202.72ns

RC30:
RC30 = 20kΩ → RC30C3 = 20x10ns = 200ns
1
ΣT0 = (9.091 + 202.72 + 200)ns=411.82n → ω-3dB = = 2.43x106 rad/s
ΣT 0
2.43x106
f-3dB = = 386.5kHz
2π
ECE 6412 - Spring 2006 Page 2

Problem 2 – (10 points)

Find the midband voltage gain and the exact value of the two poles of the voltage transfer
function for the circuit shown. Assume that RI = 3kΩ, RL = 9KΩ, gm = 1mS, Cgs = 4.5pF
and Cgd = 1pF. Ignore rds.

RI
+
Vin
RL Vout
-
S02E1P4
Solution
The best approach to this problem is a direct analysis.
Small-signal model:
gmVgs gmVs
RI RI
- + + +
Vin Vgs Cgs Cgd Vin Vs Cgs Cgd
RL Vout RL Vout
+ - - -
S02E1S4

1 V in-V s
Vout = gmZLVs where ZL = sR C +1 and RI = gmVs +
L gd
sCgsVs
Solving for Vs from the second equation gives,
V in
Vs = 1+g R +sC R
m I gs I
Substituting Vs in the first equation gives,
V in Vout 1 1
V out = gm ZL 1+g R +sC R → V = gm sR C +1  1+g R +sC R 
m I gs I in  L gd   m I gs I
gmRL 1 1
=  1+g R   sR C +1  sC R  = MBG 1   1 
 
m I  L gd   gd I  1 - s   s
+ 1  p 1 - p
 1+gmRI  1  2
gmRL  1x9 
∴ MBG =  1+g R  = 1+1x3 = 2.25V/V
 m I

1 1 1+gmRI 1+3 8
p1 = -R C = - 9x1ns = 1.1e8 rad/s and p2 =- RICgs = - 3x4.5ns = -2.9x10 rad/s
L gd
ECE 6412 - Spring 2005 Page 1

Homework Assignment No. 6 - Solutions

Problem 1 - (10 points)

For the CMOS op amp VDD=2.5V
shown, find the following
quantities.
1.) Slew rate (V/sec.) 10/1 60/1
10/1
M8 M5 M7
2.) Positive and negative +
output voltage limits (all Cc=3pF vout
vin M1 M2
transistors remain in
saturation) - 10/1 10/1
M6
3.) Positive and negative
input common voltage limits 60/1
M3 M4
(all transistors remain in
saturation and use nominal 40µA 10/1 10/1
parameter values)
4.) Small signal voltage gain VSS=-2.5V S99E2P4
5.) Unity-gainbandwidth (MHz) and 6.) Power dissipation (mW).
Solution
I5 40µA
1.) SR = C = 3pF = 1.1x107V/second ⇒ SR =1.1x10 7V/sec
c
2I7 480µA 480µA
2.) VSD7 = K P(W/L) = 50·60 = 0.4V and VDS6 = 110·60 = 0.2697V
∴ V out (max) = 2.5-0.4 = 2.1V &
V out (min) = -2.5V+0.2697V = -2.230V
2·20
3.) ICM (min) = -2.5V+VGS3 -|VTP| = -2.5V+ 110·10 +0.7V-0.7V
∴ ICM(min) = -2.5+0.191 = -2.309V ⇒ ICM(min) = -2.309V
2·40 2·20
ICM(max) = ? VSD5(sat) = 50·10 = 0.4V and VSG1 = 50·10 + 0.7 = 0.983V
∴ ICM(max) = 2.5 -VSD5(sat) -VSG1 = 2.5-0.4-0.983 = 1.117V
ICM(max) = 1.1171V
gm1gm6 2KPW 1I1
4.) Av = (g +g )(g +g ) gm1 = L1 = 2·50·10·20 = 141µS
sd2 ds4 ds6 sd7
2KPW 6I6
gm6 = L6 = 2·110·60·240 = 1779µS GI = 0.09·20µA = 1.8µS
and GII = 0.09·240µA = 21.6µS
141x1779
∴ Av = 1.8x21.6 = 6,452V A v = 6,452V/V
gm1 141µS
5.) GB = C = 3pF = 47Mrads/sec ⇒ G B = 7.48MHz
c
6.) Pdiss = 5x320µA = 1.6mW ⇒ P diss = 1.6mW
ECE 6412 - Spring 2005 Page 2

Problem 2 - (10 points)

Bias current calculation:
2 .I 8
VT 8 + VON 8 + I8 .R S = V dd − V ss or, VT 8 + = 5 − I 8 .R s . (1)
3.K /p
Solving for I 8 quadratically would give, I8 __
36µA , I5 __
36µA , and I7 __60µA
/ W
Using the formula, g m = 2.K .I and g ds = λI we get,
L
gm2 = 60 µS , g ds 2 = 0.9µS , g ds 4 = 0.72µS (2)
gm6 = 363µS , g ds 6 = 3µS , g ds 7 = 2.4µS (3)
Small-signal open-loop gain:
The small-signal voltage gain can be expressed as,
− g m2 − g m6
AV 1 = = − 37 and AV 2 = = − 67
( g ds 2 + g ds4 ) ( g ds6 + g ds7 )
Thus, total open-loop gain is,
A v = A v1·A v2 = 2489V/V (3)
Output resistance:
1
Rout = = 185KΩ (5)
( g ds 6 + g ds 7 )

Power dissipation:
Pdiss = 5(36 + 36 + 60)µW = 660µW (6)

ICMR:
Vin ,max = 2.5 − VT 1 − V ON1 − VON 5 = 0.51V (7)

Vin ,min = − 2.5 − VT1 + VT 3 + VON 3 = − 2.21V (8)

Output voltage swing:

V 0,max = 2.5 − VON 7 = 1.81V (9)

Slew Rate:
Slew rate under no load condition can be given as,
I
SR = 5 = 6V / µs
CC

In presence of a load capacitor of 20 pF, slew rate would be,

I 5 I7
SR = minC , C 
c L
ECE 6412 - Spring 2005 Page 3

Problem 6.3-7 - Continued

CMRR:
Under perfectly balanced condition where I1 = I 2 , if a small signal common-mode
variation occurs at the two input terminals, the small signal currents i1 = i 2 = i 3 = i 4 and the
differential output current at node (7) is zero. So, ideally, common-mode gain would be
zero and the value for CMRR would be infinity.
GBW:
Let us design M9 and M10 first. Both these transistors would operate in triode region and
will carry zero dc current. Thus, V ds9 = V ds10 ≅ 0 . The equation of drain current in triode
region is given as,
W
I D ≅ K / (VGS − VT ).V DS .
L
The on resistance of the MOS transistor in triode region of operation would be,
W
RON = K / (VGS − VT ) .
L
1
It is intended to make the effective resistance of M9 and M10 equal to .
g m6
W 9  W 10
So, K’ 9 L  (VGS9-VT9) + K’10 L  (VGS10-VT10) = gm6 (11)
9 10
V D 4 = V D 3 = − 2.5 + VT 3 + VON 3 = − 1.51V
Thus,
VGS 9 ≅ 4V and VGS10 ≅ − 1V .
Putting the appropriate values in (11), we can solve for the aspect ratios of M9 and M10.
One of the solutions could be,

W 9 1 W 10
K’9 L  = 1 and K’10 L  = very small (12)
9 10
The dominant pole could be calculated as,
(g g )
p1 = − ds4 + ds2 =640HZ .
2.π . AV2 .C C

And the load pole would be,

− gm6
p2 = = − 2.8MHz. for a 20 pF load.
2.π .C L

It can be noted that in this problem, the product of the open-loop gain and the
dominant pole is approximately equal to the load pole. Thus, the gain bandwidth is
approximately equal to 2.8 MHz and the phase margin would be close to 45 degrees.
ECE 6412 - Spring 2005 Page 4

Problem 6.3-7 - Continued

PSRR:
If a small ripple v S is applied at the V dd terminal, then the gain of this ripple from
this terminal to the output can be expressed as,
 1- RS 
vo  RS+(1/gm8) gm7
vs = gds6+gds7 = 2.8V/V
Thus, PSRR due to variations in V dd would be, AV 2.8 = 2489 / 2.8 = 889 .

SPICE file:
. modelnmos nmos vto=0.7 lambda=0.04 kp=110u
.model pmos pmos vto=-0.8 lambda=0.05 kp=50u

vdd 1 0 dc 2.5 ac 0
vss 10 0 dc -2.5 ac 0
vinp 5 0 dc 0 ac 1
*vinn 4 0 dc 0 ac 0

m8 2 2 1 1 pmos w=3u l=1u

rs 2 10 100k
m5 3 2 1 1 pmos w=3u l=1u
m1 6 8 3 3 pmos w=2u l=1u
m2 7 5 3 3 pmos w=2u l=1u
m3 6 6 10 10 nmos w=4u l=1u
m4 7 6 10 10 nmos w=4u l=1u
m7 8 2 1 1 pmos w=5u l=1u
m6 8 7 10 10 nmos w=10u l=1u
cc 7 9 6p
cl 8 0 20p
m9 8 1 9 9 nmos w=1u l=1u
m10 8 10 9 9 pmos w=1u l=100u

.op
.ac dec 10 1 100meg
.option post
.end

Operating points:

**** mosfets

subckt
element 0:m8 0:m5 0:m1 0:m2 0:m3 0:m4
model 0:pmos 0:pmos 0:pmos 0:pmos 0:nmos 0:nmos
region Cutoff Cutoff Cutoff Cutoff Saturati Saturati
id -35.3708u -34.8506u -17.4107u -17.4399u 17.4107u 17.4399u
ibs 0. 0. 0. 0. 0. 0.
ibd 14.6292f 11.4726f 28.7676f 28.3314f -9.7598f -10.1959f
ECE 6412 - Spring 2005 Page 5

Problem 6.3-7 - Continued

vgs -1.4629 -1.4629 -1.3517 -1.3527 975.9818m 975.9818m
vds -1.4629 -1.1473 -2.8768 -2.8331 975.9818m 1.0196
vbs 0. 0. 0. 0. 0. 0.
vth -800.0000m -800.0000m -800.0000m -800.0000m 700.0000m
700.0000m
vdsat -662.9217m -662.9217m -551.7476m -552.7377m 275.9818m
275.9818m
beta 160.9719u 158.6045u 114.3838u 114.1657u 457.1773u 457.9449u
gam eff 527.6252m 527.6252m 527.6252m 527.6252m 527.6252m 527.6252m
gm 106.7118u 105.1423u 63.1110u 63.1037u 126.1726u 126.3844u
gds 1.6480u 1.6480u 761.0636n 763.7975n 670.2604n 670.2604n
gmb 36.9704u 36.4266u 21.8648u 21.8623u 43.7126u 43.7860u
cdtot 2.021e-18 1.585e-18 2.649e-18 2.609e-18 1.797e-18 1.878e-18
cgtot 7.005e-16 7.000e-16 4.693e-16 4.692e-16 9.467e-16 9.467e-16
cstot 6.906e-16 6.906e-16 4.604e-16 4.604e-16 9.208e-16 9.208e-16
cbtot 7.806e-18 7.806e-18 6.216e-18 6.205e-18 2.402e-17 2.402e-17
cgs 6.906e-16 6.906e-16 4.604e-16 4.604e-16 9.208e-16 9.208e-16
cgd 2.021e-18 1.585e-18 2.649e-18 2.609e-18 1.797e-18 1.878e-18

subckt
element 0:m7 0:m6 0:m9 0:m10
model 0:pmos 0:nmos 0:nmos 0:pmos
region Cutoff Saturati Linear Cutoff
id -61.7971u 61.7971u 0. 0.
ibs 0. 0. 0. 0.
ibd 24.9901f -25.0099f 0. 0.
vgs -1.4629 1.0196 2.4990 -2.5010
vds -2.4990 2.5010 0. 0.
vbs 0. 0. 0. 0.
vth -800.0000m 700.0000m 700.0000m -800.0000m
vdsat -662.9217m 319.5939m 0. 0.
beta 281.2376u 1.2100m 110.0000u 500.0000n
gam eff 527.6252m 527.6252m 527.6252m 527.6252m
gm 186.4385u 386.7225u 0. 0.
gds 2.7467u 2.2471u 197.8911u 850.4951n
gmb 64.5917u 133.9802u 0. 0.
cdtot 5.753e-18 1.152e-17 1.727e-16 17.2658f
cgtot 1.1698f 2.3660f 3.463e-16 34.6349f
cstot 1.1511f 2.3021f 1.727e-16 17.2658f
cbtot 1.301e-17 5.233e-17 9.769e-19 1.033e-16
cgs 1.1511f 2.3021f 1.727e-16 17.2658f
cgd 5.753e-18 1.152e-17 1.727e-16 17.2658f

Results from SPICE simulation:

i. Unloaded output (load capacitor = 0)

GBW = 1.5 MHz., Phase Margin = 90 deg, 1% settling time = 0.39 us.
ii. Loaded output (load capacitor = 20 pF)
GBW = 1.5 MHz., Phase Margin = 65 deg, 1% settling time = 0.48 us.
ECE 6412 - Spring 2005 Page 6

Problem 6.3-7 - Continued

ECE 6412 - Spring 2005 Page 7

Problem 6.3-7 - Continued

ECE 6412 - Spring 2005 Page 8

Problem 3 - (10 points)

+5V
Small signal differential voltage gain: M4
By intuitive analysis methods, 2/1 1/1 10/1
vo1
vo1 -0.5gm1 M8 M3
vin = g ds1 + g ds3 M1 10µA v out
and
20µA
+
v in
4/1 M2 10µA5pF
vout -gm4 100µA
-
vo1 = g ds4 + g ds5 4/1

M7 M5
M6
1/1 1/1 5/1
vout 0.5gm1gm4
∴ vin = (gds1+gds3)(gds4+gds5)
-5V

2KNW1ID1
gm1 = L1 = 24·2·4·10 x10-6 = 43.82µS

gds1 = λNID1 = 0.01·10µA = 0.1µS, gds3 = λPID3 = 0.02·10µA = 0.2µS

2KPW4ID4
gm4 = L4 = 2·8·10·100 x10-6 = 126.5µS

gds4 = λPID4 = 0.02·100µA = 2µS, gds5 = λNID5 = 0.01·100µA = 1µS

v out 0.5·43.82·126.5
∴ vin = (0.1+0.2)(1+2) = 3,079V/V

Output resistance:
1 106
R o u t = g +g = 1+2 = 333kΩ
ds4 ds5

Dominant pole, p1:

1 1 106
|p1| = R C where R1 = g +g = 0.1+0.2 = 3.33MΩ
1 1 ds1 ds3
and
 gm4   126.5
C1 = Cc(1+|Av2|) = 5pF1 + gds4+gds5 = 51+ 3  = 215.8pF
106
∴ |p1| = 3.33·2.15.8 = 1,391 rads/sec → |p 1 | = 1,391 rads/sec = 221Hz
0.5·gm1 0.5·43.82x10-6
GB = Cc = = 4.382Mrads/sec
5x10-12
GB = 4.382 Mrads/sec = 0.697MHz
ID 6 1 0 µ A
SR = Cc = 5pF = 2V/µs P diss = 10V(140µA) = 1.4mW
ECE 6412 - Spring 2005 Page 9

Problem 4 - Design Problem 2 (50 points)

ECE 6412 - Spring 2006 Page 1

Homework Assignment No. 8 - Solutions

Problem 1 - (10 points)

This problem deals +3V
with the op amp M3 M4
shown in Fig.
P6.5-15. All M14
1.5I 1.5I
device lengths are
1µm, the slew rate M15
is ±8V/µs, the GB M6 M7
is 8MHz, the 0.5I 0.5I I
maximum output I I
v1 M1 vout
voltage is +2V, the
minimum output M8 M9
I v2 M2 10pF
voltage is -2V, and
the input common I
mode range is from M13 I
-1V to +2V. M12 M5 M10 M11
Design all W values
of all transistors in -3V
this op amp. Your
design must meet or Figure P6.5-15
exceed the specifications. When calculating the maximum or minimum output voltages,
divide the voltage drop across series transistors equally. Ignore bulk effects in this
problem. When you have completed your design, find the value of the small signal
differential voltage gain, Avd = vout/vid, where vid = v1-v2 and the small signal output
resistance, Rout.
Solution
1.) The slew rate will specify I. ∴ I = C·SR = 10-11x8x106 = 10-4 = 80µA.
2.) Use GB to define W1 and W2.
gm1
GB = C → gm1 = GB·C = 2πx8x106·10-11 = 502.4µS
gm12 (502.4)2
∴ W1 = 2K (0.5I) = 2·110·40 = 28.68 ⇒ W1 = W 2 = 29µm
N
3.) Design W15 to give VT+2VON bias for M6 and M7. VON = 0.5V will meet the desired
maximum output voltage specification. Therefore,
2I
VSG15 = VON15 + |VT| = 2(0.5V) + |VT| → VON15 = 1V = K PW 15
2I 2·80
∴ W15 = 2 = = 3.2µm ⇒ W 15 = 4µm
KPVON15 50·12
4.) Design W3, W4, W6 and W7 to have a saturation voltage of 0.5V with 1.5I current.
2(1.5I) 2·120
W3 =W 4 =W 6 =W 7 = 2 = = 19.2µm ⇒ W 3=W 4 =W 6 =W 7 = 20µm
KPVON 50·0.52
ECE 6412 - Spring 2005 Page 2

Problem 6.5-15 – Continued

5.) Next design W8, W9, W10 and W11 to meet the minimum output voltage specification.
Note that we have not taken advantage of smallest minimum output voltage because a
normal cascode current mirror is used which has a minimum voltage across it of VT +
2V ON . Therefore, setting VT + 2VON = 1V gives VON = 0.15V. Using worst case
current, we choose 1.5I. Therefore,
2(1.5I) 2·120
W 8 =W 9 =W 10 =W 11 = = = 96.8µm ⇒ W 8 =W 9 =W 10 =W 11 =
K NV ON2 110·0.152
97µm
6.) Check the maximum ICM voltage.
Vic(max) = VDD + VSD3(sat) + VTN = 3V – 0.5 + 0.7 = 3.2V which exceeds spec.
7.) Use the minimum ICM voltage to design W5.
 2·40 
Vic(min) = VSS + VDS5(sat) + VGS1 = -3 + VDS5(sat) +  110·29+0.7 = -1V
2I
∴ VDS5(sat) = 1.142 → W 5 = = 1.11µm = 1.2µm
K N V DS5 (sat)2
Also, let W12 =W13 =W5 ⇒ W 12 =W 13 =W 5 = 1.2µm
8.) W14 is designed as
I14 I
W 14 = W 3 I = 20µm 1.5I = 13.3µm ⇒ W 14 = 14µm
3
Now, calculate the op amp small-signal performance.
Rout ≈ rds11gm9rds9||gm7rds7(rds2||rds4)
25V
gm9 = 2KN·I·W9 = 1306µS, rds9 = rds11 = 80µA = 0.312MΩ,
20V 25V
gm7 = 2KP·I·W7 = 400µS, rds7 = 80µA = 0.25MΩ, rd2 = 40µA = 0.625MΩ
20V
rds4 = 120µA = 0.1667MΩ ∴ R out ≈ 127ΜΩ||13.16ΜΩ = 11.92ΜΩ

Avd=gm1 Rout gm1 = K N ·I·W1 = 505µS

∴ Avd = (505µS)(11.92MΩ) = 6,022V/V ⇒A vd = 6,022V/V
 1.5X as much

3.6

14.25 uA

3.6
14.25e3

9.12
14.25e3
0.54

7.2M 9.12 1.54

4.75

1.8 4.75

3.6

4.75 =2.59

2590
719
3.6

401,000
 is changed to 50ohm

+ x50ohm=11.8+251x0.05=24.35k

16.37
Req

377 16.37

4.487

97ohm
1+REgm17

(1+REgm17)

79.14
4.487 79.1

97

2703 78.4K
79.14 78.4K

0.097K

404,610
ECE 6412 - Spring 2005 Page 5

Problem 5 – (10 points)

A two-stage, BiCMOS op amp is shown. 1.2V
For the PMOS transistors, the model
parameters are KP’=50µA/V2, VTP = -0.7V
20/1 40/1
and λP = 0.05V-1. For the NPN BJTs, the 20/1
M8 M5 M7
model parameters are βF = 100, VCE(sat) = 25µA 25µA
50µA vout
0.2V, VA = 25V, Vt = 26mV, Is = 10fA and
n=1. (a.) Identify which input is positive v 1 v 2 C c=
and which input is negative. (b.) Find the 20/1 20/1 5pF
- +
numerical values of differential voltage gain M1 M2
magnitude, |Av(0)|, GB (in Hertz), the slew 12.5µA
W/L ratios Q6
rate, SR, and the location of the RHP zero.
(c.) Find the numerical value of the in microns
maximum and minimum input common Q3 Q4
mode voltages.
Solution S01E2P1 -1.2V
(a.) The plus and minus signs on the schematic show which input is positive and negative.
(b.) The differential voltage gain, Av(0), is given as
gm1 gm6
Av(0) = g · gm1 = gm2 = 50·25·20 = 158.1µS
ds2+go4+gπ6 gds7+go6
1 20 VA 25V IC 50µA
rds2 = = 12.5µA = 1.6MΩ,ro4= I = 12.5µA2=MΩ, gm6 = V = 26mV =1923µS
λPID C t

βF 1 20 VA 25V
rπ 6 = g = 52kΩ rds7 = = 50µA = 0.4MΩ and ro6 = I = 50µA = 0.5MΩ
m6 λPID C

∴ |Av(0)| = [158.1(1.6||2||0.052)][1923(0.4||0.5)] = 3319.3V/V

gm1 158.1µS
GB = C = 5pF = 31.62x106 rads/sec → GB = 5.0325MHz
c
25µA
SR = 5pF = 5V/µs
gm6 1.923mS
RHP zero = C = 5pF = 384.6x106 rads/sec=61MHz
c
(c.) The maximum input common mode voltage is given as
2·25 2x12.5
vicm+ = VCC-VDS5(sat) - VSG1 = 1.2 - 50·20 - 0.7 - 50·20 = 0.5 - 0.224-0.158 =
∴ vicm+ = 0.118V
12.5µA
vicm- = -1.2 + VBE3 - VT1 = -1.2 + Vt ln 10fA  - 0.7 = -1.9 + 0.545 = -1.3554V
ECE 6412 - Spring 2006 Page 1

Homework Assignment No. 9 Solutions

Problem 1 – (10 points)

Problem 2 – (10 points)
Problem 3 – (10 points)
Problem 4 – (10 points)
Problem 5 – (10 points)
Problem 6 – (10 points)
Problem 7 – (10 points)
Problem 8 – (10 points)
Problem 9– (10 points)
Problem 10– (10 points)
Homework Assignment No. 10 Solutions
Problem 4
Problem 6– P7.2-4
Use the technique of Ex. 7.2-2 to extend the GB of the cascode op amp of Ex. 6.5-2 as
much as possible that will maintain 60° phase margin. What is the minimum value of CL
for the maximum GB?

Solution

Assuming all channel lengths to be 1 µm , the total capacitance at the source of M7 is

C 7 = C gs 7 + Cbd 7 + C gd 6 + Cbd 6
or, C 7 = 75 + 51 + 9 + 51 = 186 fF
g m7 = 707 µS
Thus, the pole at the source of M7 is
g
p S 7 = ! m7 = !605 MHz.
C7
The total capacitance at the source of M12 is
C12 = C gs12 + Cbd12 + C gd11 + Cbd11
or, C12 = 34 + 29 + 4 + 29 = 96 fF
g m12 = 707 µS
Thus, the pole at the source of M12 is
g
p S12 = ! m12 = !1170 MHz.
C12
The total capacitance at the drain of M4 is
C 4 = C gs 4 + C gs 6 + Cbd 4 + C gd 2 + Cbd 2
or, C 4 = 43 + 75 + 21 + 3 + 19 = 161 fF
g m 4 = 283 µS
ECE 6412 - Spring 2006 Page 11

Problem 6 - Continued
Thus, the pole at the drain of M4 is
g
p D 4 = ! m 4 = !280 MHz.
C4
The total capacitance at the drain of M8 is
C8 = C gd 8 + Cbd 8 + C gs10 + C gs12
or, C8 = 9 + 51 + 34 + 34 = 128 fF
1
R2 + = 3.4 K!
g m10
Thus, the pole at the drain of M8 is
1
pD 8 = " = "366 MHz.
#% 1 &(
R + C
$ 2 gm10 ' 8
For a phase margin of 60 o , we have
/ ) # GB & # # # ,2
PM = 180 o " 190o " *tan"1 % ( + tan"1% GB &( + tan"1% GB &( + tan"1 % GB &( -
0 + $ pS7 ' $ pS12 ' $ pD4 ' $ pD 8 ' .43
Solving the above equation
GB ! 65 MHz.
And, Av = 6925 V/V
Thus, p1 = 9.39 KHz, and CL " 1.54 pF
ECE 6412 - Spring 2006 Page 1

Homework Assignment No. 11 Solutions

Problem 1 – (10 points)

Problem 2 – (10 points)
Common mode half circuit:
Vo1 = Vo 2 = VDD − VGS 3
2I D
VGS 3 = + VTP = Vov + VTP = 0.8V
' w
kp
L
⇒ Vo1 = Vo 2 = 2.5 − 0.8 = 1.7V
adm = − g m1 (ro1 ro 3 20 K ) = −1(100 200 20) = −15.38, where :
w w
g m1 = 2kn ' I D = kn ' vov = 5000 × 0.2 = 1mS
L L
⎧ ' ⎛w⎞
⎪ k p ⎜ L ⎟ = 5000 µ
2I D3 2 ×100 µ ⎪ ⎝ ⎠3
vov = ⇒ 0.2 = ⇒⎨
⎛w⎞ ⎛w⎞ ⎪ k ' ⎛ w ⎞ = 5000 µ
k p' ⎜ ⎟ k p' ⎜ ⎟
⎝ L ⎠3 ⎝ L ⎠3 ⎪⎩ n ⎜⎝ L ⎟⎠1
ro1 = 100 K , ro 3 = 200 K

g m1 1 1
acm = − (ro1 (1 + 2 g m1ro 5 ) ro 3 )= = 0.01, where :
1 + 2 g m1ro 5 g m 3 1 + 2m × 50 K
g m 3 = 5000 × 0.2 = 1mS
ro5 = 50 K
Because of adding the 20Kresistors, the adm becomes smaller but acm becomes much
smaller. The effective impedance of M3 and M4 is now 1/gm, which is much smaller than
roÆ adm/acm=1538 which is much higher than 100 in 12.4.1

Problem 3 – (10 points)

Without Ccs:
1
( Rcs )
C1s
vcms = (vov1 + vov 2 )
1
( Rcs ) + Rcs
C1s
vov1 + vov 2
voc =
2
vcms Rcs 1
=2 ⇒ acms =
voc Rcs + Rcs ( Rcs C1s + 1) R Cs
1 + cs 1
2
Gain starts to drop at frequencies higher than the pole. In Other words the CM detector
cannot follow the signal at the same rate.
With Ccs:
1
( Rcs )
(Ccs + C1 ) s
vcms = (vov1 + vov 2 )
1 1
( Rcs ) + ( Rcs )
(Ccs + C1 ) s Ccs s
vov1 + vov 2
voc =
2
vcms Rcs Ccs s + 1 1 + Rcs Ccs s
=2 ⇒ acms =
voc Rcs Ccs s + 1 + 1 + Rcs (C1s + Ccs s ) C
1 + Rcs (Ccs + 1 ) s
2
C1
If Ccs >> Æ gain stays constant over the entire frequency range.
2
Problem 4 – (10 points)
w
( )12
L = 20 ⇒ ( w ) = 19.2 ⇒ w = 19.2 µ m
12 12
w
( )11 100 L
L
I D 51 = 120 µ
w
( )51
L = 120 ⇒ ( w ) = 1.2 × 16 × 0.8 = 19.2 ⇒ w = 19.2µ m
51 51
w
( )14 100 L 0.8
L
100µ A
SR = = 25 V
4 pF µ sec

vo1 min = max(−1.65 + vov 51 + vov1 + vov1C , vi − vt + vov1C )

vo1 max = 1.65 − vov 27 − vgs 24
Problem 5 – (10 points)
v + o = vDD − vds 3 − vgs1
v − o = vDD − vds 6 − vgs 2
kn ' = µn Cox = 126, k p ' = µ p Cox = 57
20 µ
vov 6 = = 0.079V
kn ' (25)
20µ
vov 3 = = 0.083V
k p ' (50)
Vtn = Vt 0 + 0.16( 3.5 + 0.65 − 0.65) = 0.897V
⇒ vgs1 = 2.5 − 1 − 0.083 = 1.41V
⎛w⎞ 2 × 1mA ⎛w⎞
⇒⎜ ⎟ = = 60, ⎜ ⎟ = 0.1× 60 = 6
⎝ L ⎠1 126 µ × (1.41 − 0.897) ⎝ L ⎠4
2

Vtp = Vt 0 − 0.44( 3.5 + 0.65 − 0.65) = −1.242V

⇒ vgs 2 = −2.5 + 1 + 0.079 = 1.421V
⎛w⎞ 2 ×1mA ⎛w⎞
⇒⎜ ⎟ = = 1095, ⎜ ⎟ = 0.1× 1095 = 109.5
⎝ L ⎠ 2 57 µ × (1.421 − 1.242) ⎝ L ⎠4
2
ECE 6412 - Spring 2006 Page 1

Homework Assignment No. 12 Solutions

Problem 1 – (10 points)
Problem 2 – (10 points)

Applying the half-circuit principle, it can be seen that each ½ circuit consists of a cascade of two
common-source (CS) stages – the first with a diode connected PMOS load and the other with an
NMOS load.

The half circuit representation is shown along-side.

The gain of the first stage is:

g m1
Av1 = Gm Rout =
g m3

In general for a CS stage with an active load, the primary noise

contributors can be represented as shown below (for the second
CS stage in the problem). From the figure along-side, we have:

2 ⎛2⎞ K P g m2 5
i n 5 = 4kT ⎜ ⎟ g m 5 +
⎝3⎠ COX (WL )5 f

2 ⎛2⎞ K N g m2 7
i n 7 = 4kT ⎜ ⎟ g m 7 +
⎝3⎠ COX (WL )7 f

Therefore the input referred noise at the gate of M5 is given by:

2 in25 + in27
v o1 =
g m2 5

Similarly, the noise at the gate of M1 due to M1 and diode connected M3 can be expressed as:

2 in21 + in23
v in (1,3) =
g m2 1
2 ⎛2⎞ K N g m2 1 2 ⎛2⎞ K P g m2 3
Where, i n1 = 4kT ⎜ ⎟ g m1 + and i n 3 = 4kT ⎜ ⎟ g m 3 +
⎝3⎠ COX (WL )1 f ⎝3⎠ COX (WL )3 f

Therefore the total noise referred to the input (gate of M1) is:

2 2
v in = v in (1,3) +
vo21
=
( ) (
in21 + in23
+
)
in25 + in27 × g m2 3
. Therefore for one half-circuit,
Av21 g m2 1 g m2 5 × g m2 1
2
v in =
( ) ( )
g m2 5 × in21 + in23 + in25 + in27 × g m2 3
g m2 5 × g m2 1

Considering only the thermal noise, the total input referred noise is:
 ⎡ ⎛2⎞ ⎤ ⎡ ⎛2⎞ ⎤
g m2 5 ⎢4kT ⎜ ⎟( g m1 + g m3 )⎥ + g m2 3 ⎢4kT ⎜ ⎟( g m5 + g m 7 )⎥
2 ⎣ ⎝3⎠ ⎦ ⎣ ⎝3⎠ ⎦
v in (THERMAL ) = 2×
g m 5 × g m1
2 2

Considering only the flicker noise, the total input referred noise is:

⎡ K N g m2 1 K P g m2 3 ⎤ 2 ⎡ K P g m2 5 K N g m2 7 ⎤
g m2 5 ⎢ + ⎥ + g m3 ⎢ + ⎥
2
v in ( FLICKER ) = 2× ⎣ COX (WL )1 f COX (WL )3 f⎦ ⎣ COX (WL )5 f COX (WL )7 f⎦
g m 5 × g m1
2 2

Equating the thermal noise and flicker noise to find the flicker noise corner frequency (fC), we
have:

⎧⎪ 2 ⎡ K N g m2 1 K P g m2 3 ⎤ 2 ⎡ K P g m5
2
K N g m2 7 ⎤ ⎫⎪ 1
⎨ g m5 ⎢ + ⎥ + g m3 ⎢ + ⎥⎬ =
⎪⎩ ⎣ COX (WL )1 COX (WL )3 ⎦ ⎣ COX (WL )5 COX (WL )7 ⎦ ⎪⎭ f C
⎡ ⎛2⎞ ⎤ ⎡ ⎛2⎞ ⎤
g m2 5 ⎢4kT ⎜ ⎟( g m1 + g m3 )⎥ + g m2 3 ⎢4kT ⎜ ⎟( g m5 + g m 7 )⎥
⎣ ⎝3⎠ ⎦ ⎣ ⎝3⎠ ⎦

Numerical Calculations:

All transistors in saturation,

(W/L)1,2 = 50/0.6, (W/L)3,4 = 10/0.6, (W/L)5,6 = 20/0.6 and (W/L)7,8 = 56/0.6
µnCOX = 75 µA/V2 and µpCOX = 30 µA/V2 and ISS = 0.5 mA
Therefore Æ I1 = I2 = I3 = I4 = 0.25 mA and I5 = I6 = I7 = I8 = 0.5mA

⎛W ⎞
Using g m = 2 µCOX ⎜ ⎟ I D , we obtain:
⎝L ⎠
gm1 = gm2 = 1.768 mS
gm3 = gm4 = 0.5 mS
gm5 = gm6 = 1 mS
gm7 = gm8 = 2.646 mS

Using the above, we obtain, the following values for the thermal and flicker noise powers
2 2
v in (THERMAL ) = 2.247 ×10 −17 V
Hz

Assuming tox= 100A°, we obtain COX = 34.53 x 10-4. Therefore the total flicker noise is given by:

2 3.2417 ×10−8 V 2
v in ( FLICKER ) =
f Hz

Equating the noise powers to find the flicker noise corner frequency, we obtain: fC = 1.44 GHz.
Problem 3 – (10 points)

Assumptions:
• VOD = VGS – VTH
• Only thermal noise of drain current considered

Also, we know for a MOS transistor, we have:

2I D 2I 1
gm = = D and ro =
VGS − VTH VOD λI D

Dynamic range of the circuit is defined as: VDD

Vout − swing M5 Vb5

DR =
Vnoise −out
where Vout-swing is the maximum output voltage swing of the M4 Vb4
amplifier and Vnoise-out is the total output referred voltage VDD
noise. vout
We know for a folded cascode amplifier, vin M1 M2 Vb2
Gm = g m1
and
Rout = g m 4 ro 4 r05 g m 2 ro 2 (ro1 ro 3 ) ,
M3 Vb3
which on expansion, yields
g m 2 g m 4 ro1ro 2 ro 3 ro 4 ro 5
Rout =
g m 4 ro 4 ro 5 (ro1 + ro 3 ) + g m 2 ro1ro 2 ro 3

Since from the above, we see that both Gm and Rout are dependent on the over-drive voltage, we
need to consider the effect of variation of VOD on both. Substituting for gm and Rout in terms of
VOD, we obtain the following expressions for Gm and Rout

2I D
Gm = g m1 =
VOD
2 1
Rout = ×
5 VOD λ2 I D

Expression for output swing in terms of the over-drive voltage:

Output swing of a folded cascode amplifier:

Vout − swing = VDD − 4VOD

Expression for the output referred noise as a function of over-drive voltage:

The major noise contributors in the folded cascode amplifier are: M1, M3 and M5. Therefore we
first obtain the noise contributions of each of these noise sources at the output.
 2 ⎡ ⎛ 2 ⎞⎤ 2 2
v n−out (1) = ⎢4kT ⎜⎜ ⎟⎟⎥ × g m1 Rout
⎣ ⎝ 3 g m1 ⎠⎦
2 ⎡ ⎛ 2 ⎞⎤ 2 2
v n−out ( 3) = ⎢4kT ⎜⎜ ⎟⎟⎥ × g m3 Rout
⎣ ⎝ 3 g m 3 ⎠⎦
2 ⎡ ⎛ 2 ⎞⎤
v n − out ( 5 ) = ⎢ 4 kT ⎜⎜ ⎟⎟ ⎥ × g m2 5 Rout
2

⎣ ⎝ m 5 ⎠⎦
3 g
Therefore taking the superposition of these noise sources, we have the output referred noise given
by:
⎛ 2⎞
v n−out = 4kT ⎜ ⎟ × [g m1 + g m3 + g m5 ]× Rout
2 2

⎝ 3⎠
Therefore substituting expressions for gm and Rout into the above, we obtain the total output
referred noise power as:

2 ⎛ 2 ⎞ ⎛ 32 ⎞ 1
v n−out = 4kT × ⎜ ⎟ × ⎜ ⎟ × 3 4
⎝ 3 ⎠ ⎝ 25 ⎠ VOD λ I D
Therefore the output referred noise voltage can be expressed as a function of VOD as:
1
vn−out = B ×
(VOD ) 2
3

Dynamic Range calculations:

Initial expression for the dynamic range (DR1):

(V − 4VOD )(VOD ) 2
3

DR1 = DD
B
After the over-drive voltage changes to 75% of its original value, the new dynamic range (DR2) is
given by:
3
⎛3 ⎞
(VDD − 3VOD )⎜ VOD ⎟
2

DR2 = ⎝4 ⎠
B
Therefore, finding the difference between the initial and final dynamic ranges, we can find the
variation in the dynamic range caused by 25% reduction in VOD

(V ) 2 ⎡VDD − 7VOD ⎤
3

∆DR = DR1 − DR2 = OD ⎢ ⎥

B ⎣ 4 ⎦
Problem 4 – (10 points)
Problem 5 – (10 points)
ECE 6412 - Spring 2006 Page 1

Homework Assignment No. 13 Solutions

Problem 1 – (10 points)
Problem 2 – (10 points)
Problem 3 – (10 points)
Problem 4 – (10 points)