Exp No 8

ASYNCHRONOUS & SYNCHRONOUS COUNTERS

Aim : To design and set up a 4-bit ripple counter, Johnson counter, Ring counter & Synchronous counter.

Components Required : IC 7476,7400,7408,7432,7473,7404

Principle:

Ripple Counter :

Ripple counter is an asynchronous counter. So clock pulse is given to any one of the flip flop and
output of the flip flop is from 0000 to 1111.

In order to make a mod 10 counter, the counter should be reset to 0000 after reaching 1001. To
achieve this, we can use a NAND gate whose inputs are the outputs of third and first flip flop so that
when both of them are ‘1’, flip flops will be cleared.

Then by using the BCD 7 segment decoder IC, we will produce the outputs, which are the inputs
of 7-segment display.

Vcc

SET SET SET SET

J Q J Q J Q J Q

Clk
K CLR Q K CLR Q K CLR Q K CLR Q

Q0 Q1 Q2 Q3

Ring Counter:

Here four D flip flops are used and they are all triggered simultaneously. The output of D flip
dlop is connected to D input of the next and Q output of the last is connected to the D input of the first.
One of the Flip Flops is preset to 1. So the output sequence is 1000, 0100, 0001, 1000, ….
 SET SET SET SET
D Q D Q D Q D Q
Clk
CLR Q CLR Q CLR Q CLR Q

Q0 Q1 Q2 Q3

Johnson Counter :

Design is similar to ring counter except fot the fact that Qbar output of the fourth D flip flop is
connected to the D input of the first flip flop. The count sequence is 0000, 1000, 1100, 1110, 1111, 0111,
…. Initially all flip flops are cleared.

SET SET SET SET

D Q D Q D Q D Q
Clk
CLR Q CLR Q CLR Q CLR Q

Q0 Q1 Q2 Q3
Synchronous Counters :

Synchronous counters and synchronous counters provide same outputs. The difference is that in
the synchronous counters, all flip flops are working in synchronization with the input clock pulses. The
additive propagation delay appears in the asynchronous counters is avoided here, yielding to a trade off
with the circuit complexity and comparatively tedious design process. Also an up down counter is capable
of progressing the counter in either direction through a certain sequence.

For designing any counter it is basically important to know about the excitation of the flip flops
we use.

J3=K3=Q2Q1Q0

J2=K2=Q1Q0

J1=K1=Q0
J0=K0=1

SET SET SET SET

J Q J Q J Q J Q
Clk
K CLR Q K CLR Q K CLR Q K CLR Q

MODE

Q0 Q1 Q2 Q3

Procedure:

The connections are made as shown in fig. and pulses are applied and out is verified.

Viva Questions :

1. Design a decade counter.

2. Difference between asynchronous and synchronous counters.
3. Draw and explain the working of 4-bit UP/DOWN synchronous counter.

Result: