A B C D E

1 1

BMWQ1/Q2 UMA M/B Schematics Document

Intel Skylake U22 with DDRIIIL
2 2

2015-07-12

REV:1.0

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Friday, July 31, 2015 Sheet 1 of 60
A B C D E
 A B C D E

Memory BUS (DDR3L)

Dual Channel DDR3L-SO-DIMM X2
Page 14,15

1 1.35V DDR3L 1600 MT/s 1

UP TO 8G x 2
Page 25~26

HDMI (DDI0) USB3.0 Left CONN1

HDMI Conn. USB 3.0 1x
Page 34 USB 2.0 1x USB 3.0 Port1
USB 2.0 Port1
Page 41

DP to VGA DPx2 Lane (DDI1)

VGA Conn.
Page 36 Page 35 IT6515FN Intel MCP
eDP x2 Lane USB2.0 2x USB2.0 Right CONN
eDP Conn
SKL-U22 15W USB2.0 Port2, Port3

USB2.0 1x USB Board

Int. Camera
USB2.0 Port6
BGA-1356
2 Int. MIC Conn. 42mm*24mm USB 2.0 1x Touch Screen 2

(optionanl)
Page 33 USB2.0 Port5 Page 33

SATA HDD SATA Gen3

Page 42 SATA Port0
USB2.0 1x
Cardreader Realtek SD/MMC Conn.
SATA ODD SATA Gen1 RTS5170
USB2.0 Port4 Page 30
Page 42 SATA Port1A

USB 2.0 1x NGFF slot WLAN&BT

RJ45 Conn. LAN Realtek PCIe 1x PCIe 1x USB2.0 Port7
Page 38 RTL8111H_CG PCIe Port6 Page 40
Sub-board ( for 14")
Page 37 PCIe Port5

3 HD Audio SPI BUS SPI ROM POWER BOARD 3

Page 3~13
8MB Page 07

LCP BUS SPI ROM 4MB USB Board 

Codec SPK Conn. for reserve
Conexant_CX11802_33Z Page 07
Page 43
Page 43

EC TPM (reserved) Sub-board ( for 15")

ITE IT8586E-LQFP ST33ZP24AR28PVSP
Page 44
POWER  BOARD 
HP&Mic Combo Conn.
USB Board 
Touch Pad Int.KBD Thermal Sensor
Page 45 Page 45 NCT7718W ODD  Board
Page 39

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

WWW.AliSaler.Com
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 2 of 60
A B C D E
 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )

SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Power Plane Full ON HIGH HIGH HIGH ON ON ON ON

+5VS
+3VALW +1.35V S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
+3VS
1 +5VALW +VCCST +VCCIO S4 (Suspend to Disk) LOW LOW LOW ON OFF OFF OFF 1

+VCCSTG
+3VALW_PCH S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
+VCCSA
B+ +1.8VALW +VCC_GT
+CPU_CORE
+1.0VALW
+0.675VS
State
HSIO PORT Function BOM Structure BTO Item
1 USB3.0 CONN left @ Not stuff
2 NC 14@ For 14" part
3 NC 15@ For 15" part
USB3.0 4 NC For 14" or 15" part
14or15@
S0 O O O O 5 NC 14or17@ For 14" or 17" part
6 NC AOAC@ AOAC support part
1 USB3.0 CONN Left BCD@ For C cost down (BDW)
S3 O O O X 2 USB2.0 CONN1 Right Cannonlake@ For Cannonlake part
2
3 USB2.0 CONN2 Right CD@ For C cost down 2

4 Camera DUALMIC@ For Dual MIC part

S3
Battery only O O O X USB2.0 5 Cardreader EMC@ For EMC part
6 Touch Panel EMC_15@ For EMC 15" part
7 BT EMC_NS@ For EMC nu-stuff part

S5 S4/AC Only O O X X 8 NC EMC_PX@ For EMC PX part

9 NC EMC_PXNS@ For EMC PX nu-stuff part
10 NC ES@ For ES CPU
S5 S4 X 1 NC EXO@ For EXO GPU
Battery only O X X 2 NC GCLK@ For GreenCLK part
3 NC ME@ For ME part
S5 S4 4 NC NTS@ For nu-touch part
AC & Battery X X X X 5 LAN PCH_SDIO@ For PCH SDIO part
don't exist PCIE 6 WLAN PCH_SDIO1@ For PCH SDIO path1
7 used as SATA PCH_SDIO2@ For PCH SDIO path2
8 used as SATA PX@ For PX part
SMBUS Control Table
3 RANKA@ For VRAM rank A part 3

WLAN Thermal PCH TP X4 PCIE RANKB@ For VRAM rank B part

SOURCE BATT IT8586E SODIMM WiMAX Sensor Module charger DGPU DGPU
(9-12) Realtek_SD@ For Realtek SD part
SINGLEMIC@ For single MIC part
EC_SMB_CK1 IT8586E V 0 HDD SINGLERANK@ For single VRAN rank part
+3VALW V +3VALW X X X X X V X 1A ODD DUALRANK@ For dual VRAN rank part
EC_SMB_DA1 SATA 1B used as PCIE TS@ For touch screen part
EC_SMB_CK2 IT8586E V 2 used as PCIE TPM@ For TPM part
X X V V X X V
EC_SMB_DA2 +3VS X +3VS +3VS +3VALW_PCH UMA@ For UMA part
+3VGS

PCH_SMB_CLK PCH
PCH_SMB_DATA +3VALW_PCH X X V V X V X X X
+3VS +3VS +3VALW_PCH

EC SM Bus1 address EC SM Bus2 address PCH SM Bus address

Device Address
Device Device Address DDR DIMMA 1010 000Xb
4 4
Smart Battery 0X16 Thermal Sensor NCT7718W 1001_100xb DDR DIMMB 1010 010Xb
Charger 0001 0010 b PCH need to update Wlan Rsvd
DGPU need to update

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 3 of 60
A B C D E
 5 4 3 2 1

SKL_ULT ?
UC1A

HDMI_TX2- E55 C47 CPU_EDP_TX0-

{34} HDMI_TX2- HDMI_TX2+ DDI1_TXN[0] EDP_TXN[0] CPU_EDP_TX0+ CPU_EDP_TX0- {33}
HDMI D2 F55 C46 confirmed with ITE, the HPD
D {34} HDMI_TX2+ HDMI_TX1- DDI1_TXP[0] EDP_TXP[0] CPU_EDP_TX1- CPU_EDP_TX0+ {33} D
E58 D46 pull down resistor should follow
{34} HDMI_TX1- HDMI_TX1+ DDI1_TXN[1] EDP_TXN[1] CPU_EDP_TX1+ CPU_EDP_TX1- {33}
HDMI D1 F58 C45 ITE recommended resistor 4.7k~10Kohm
{34} HDMI_TX1+ HDMI_TX0- DDI1_TXP[1] EDP_TXP[1] CPU_EDP_TX1+ {33}
F53 A45
{34} HDMI_TX0- HDMI_TX0+ DDI1_TXN[2] EDP_TXN[2]
HDMI D0 G53 B45
{34} HDMI_TX0+ HDMI_CLK- DDI1_TXP[2] EDP_TXP[2]
F56 A47
{34} HDMI_CLK- HDMI_CLK+ DDI1_TXN[3] EDP_TXN[3]
HDMI CLK G56 B47
{34} HDMI_CLK+ DDI1_TXP[3] EDP_TXP[3] +3VS
VGA_TX0- C50 E45 CPU_EDP_AUX#
{35} VGA_TX0- VGA_TX0+ DDI2_TXN[0] DDI EDP_AUXN CPU_EDP_AUX CPU_EDP_AUX# {33}
D50 EDP F45
{35} VGA_TX0+ VGA_TX1- DDI2_TXP[0] EDP_AUXP CPU_EDP_AUX {33}
DP TO VGA Converter C52
{35} VGA_TX1- VGA_TX1+ DDI2_TXN[1] GPP_E15
D52 B52 RC1601 1 2 10K_0402_5%
{35} VGA_TX1+ DDI2_TXP[1] EDP_DISP_UTIL
A50
B50 DDI2_TXN[2] G50 @
D51 DDI2_TXP[2] DDI1_AUXN F50
DDI2_TXN[3] DDI1_AUXP

2
C51 E48 VGA_AUX#
DDI2_TXP[3] DDI2_AUXN VGA_AUX VGA_AUX# {35}
F48 RC37
DDI2_AUXP G46 VGA_AUX {35}
DDI3_AUXN 4.7K_0402_5%
DISPLAY SIDEBANDS F46
DDPB_CLK L13 DDI3_AUXP

1
{34} DDPB_CLK DDPB_DATA L12 GPP_E18/DDPB_CTRLCLK L9 HDMI_HPD
{34} DDPB_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 DP_VGA_HPD HDMI_HPD {34}
L7
DDPC_CLK GPP_E14/DDPC_HPD1 GPP_E15 DP_VGA_HPD {35}
N7 L6 RC181 1 2 0_0402_5%
DDPC_DATA GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 EC_SCI# {8,44}
N8 N9
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 CPU_EDP_HPD
GPP_E17/EDP_HPD CPU_EDP_HPD {33}
N11
GPP_E22/DDPD_CTRLCLK

1
+VCCIO N12 R12 PCH_ENBKL
GPP_E23/DDPD_CTRLDATA EDP_BKLTEN PCH_EDP_PWM PCH_ENBKL {33}
R11 RC13
RC4 2 1 24.9_0402_1% EDP_COMP E52 EDP_BKLTCTL U13 PCH_ENVDD PCH_EDP_PWM {33} 100K_0402_5%
EDP_RCOMP EDP_VDDEN PCH_ENVDD {33}
1 OF 20
+VCCIO&EDP_COMP : SKYLAKE-U_BGA1356

2
Trace Width: 20mil REV = 1 ?
+VCCST_CPU
C
Isolation Spacing: 25mil @
C
Max length: 100mil

1
+VCCSTG
RC1625
@ 49.9_0402_1%
1

RC19 UC1D SKL_ULT ?

2
1K_0402_5% XDP_TCK RC15461 2 0_0402_5% JTAGX RC1551 1 2 51_0402_5%
check PROCHOT# circuit with PWR CATERR# D63
H_PECI A54 CATERR# XDP_TDO RC1547 1 2 0_0402_5% PCH_JTAG_TDO RC1543 1 2 51_0402_5%
{44} H_PECI +VCCSTG
2

RC20 1 2 499 +-1% 0402 H_PROCHOT#_R C65 PECI

{44} H_PROCHOT# PROCHOT# JTAG
H_THRMTRIP# C63
A65 THERMTRIP# B61 XDP_TCK 1 PAD @ XDP_TDI RC1548 1 2 0_0402_5% PCH_JTAG_TDI
SKTOCC# PROC_TCK XDP_TDI TC15
CPU MISC
D60 1 PAD @
PROC_TDI TC16
1

PAD @ TC11 1 XDP_BPM0# C55 A61 XDP_TDO 1 PAD @ XDP_TMS RC1549 1 2 0_0402_5% PCH_JTAG_TMS
XDP_BPM1# BPM#[0] PROC_TDO XDP_TMS TC17
RC143 PAD @ TC12 1 D55 C60 1 PAD @
XDP_BPM2# BPM#[1] PROC_TMS XDP_TRST# TC18 XDP_TRST# RC1550 1
1K_0402_5% PAD @ TC13 1 B54 B59 1 PAD @ 2 0_0402_5% PCH_JTAG_TRST#
XDP_BPM3# BPM#[2] PROC_TRST# TC27
PAD @ TC14 1 C56
BPM#[3] B56 PCH_JTAG_TCK 1 PAD @
TC29
2

PAD @ TC162 1 GPP_E3 A6 PCH_JTAG_TCK D59 PCH_JTAG_TDI 1 PAD @

GPP_E3/CPU_GP0 PCH_JTAG_TDI TC31 check JTAG circuit?
+VCCST_CPU PAD @ TC163 1 GPP_E7 A7 A56 PCH_JTAG_TDO 1 PAD @
GPP_B3 GPP_E7/CPU_GP1 PCH_JTAG_TDO PCH_JTAG_TMS TC35
PAD @ TC164 1 BA5 C59 1 PAD @
GPP_B4 GPP_B3/CPU_GP2 PCH_JTAG_TMS PCH_JTAG_TRST# TC36
check H_THRMTRIP# if need to connector to EC PAD @ TC165 1 AY5 C61 1 PAD @
GPP_B4/CPU_GP3 PCH_TRST# TC42
A59 JTAGX 1 PAD @
PROC_OPI_RCOMP JTAGX TC43
RC155 1 2 49.9_0402_1% AT16
RC156 1 2 49.9_0402_1% PCH_OPI_RCOMP AU16 PROC_POPIRCOMP
RC157 1 2 49.9_0402_1% EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
RC170 1 2 49.9_0402_1% EOPIO_RCOMP H65 OPCE_RCOMP
OPC_RCOMP
@
@
1 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
B B
@

check DDPC_CLK pull high or not?

+3VS

RPC19
8 1 DDPC_CLK
7 2 DDPC_DATA
6 3 DDPB_CLK
5 4 DDPB_DATA

2.2K_0804_8P4R_5%

DDP*_CTRLDATA strapping sampled on the rising edge of PWROK

Port Strap Enable Disable

Pull up to 3.3 V
Port 1 DDPB_CTRLDATA with 2.2Kohm NC
Pull up to 3.3 V
Port 2 DDPC_CTRLDATA with 2.2Kohm NC

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (DDI,EDP)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 4 of 60
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

?
SKL_ULT
UC1B

AU53
{17} DDRA_DQ[0..63] DDRA_DQ0 AL71 DDR0_CKN[0] DDRA_CLK0# {17}
AT53
DDRA_DQ1 AL68 DDR0_DQ[0] DDR0_CKP[0] DDRA_CLK0 {17}
AU55
DDRA_DQ2 AN68 DDR0_DQ[1] DDR0_CKN[1] DDRA_CLK1# {17}
AT55
DDRA_DQ3 AN69 DDR0_DQ[2] DDR0_CKP[1] DDRA_CLK1 {17}
DDRA_DQ4 AL70 DDR0_DQ[3] BA56
DDRA_DQ5 AL69 DDR0_DQ[4] DDR0_CKE[0] DDRA_CKE0 {17}
BB56
DDRA_DQ6 AN70 DDR0_DQ[5] DDR0_CKE[1] DDRA_CKE1 {17}
AW56
DDRA_DQ7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56
DDRA_DQ8 AR70 DDR0_DQ[7] DDR0_CKE[3]
D DDRA_DQ9 AR68 DDR0_DQ[8] AU45 D
DDRA_DQ10 AU71 DDR0_DQ[9] DDR0_CS#[0] DDRA_CS0# {17}
AU43
DDRA_DQ11 AU68 DDR0_DQ[10] DDR0_CS#[1] DDRA_CS1# {17}
AT45
DDRA_DQ12 AR71 DDR0_DQ[11] DDR0_ODT[0] DDRA_ODT0 {17}
AT43
DDRA_DQ13 AR69 DDR0_DQ[12] DDR0_ODT[1] DDRA_ODT1 {17}
DDRA_DQ14 AU70 DDR0_DQ[13] BA51
DDRA_DQ15 AU69 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDRA_MA5 {17}
BB54
DDRA_DQ16 BB65 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDRA_MA9 {17}
BA52
DDRA_DQ17 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDRA_MA6 {17}
AY52
DDRA_DQ18 AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDRA_MA8 {17}
AW52
DDRA_DQ19 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDRA_MA7 {17}
AY55
DDRA_DQ20 BA65 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDRA_BS2# {17}
AW54
DDRA_DQ21 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDRA_MA12 {17}
BA54
DDRA_DQ22 BA63 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDRA_MA11 {17}
BA55
DDRA_DQ23 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDRA_MA15 {17}
AY54
DDRA_DQ24 BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDRA_MA14 {17}
DDRA_DQ25 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46
DDRA_DQ26 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDRA_MA13 {17}
AU48
DDRA_DQ27 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDRA_CAS# {17}
AT46
DDRA_DQ28 BB61 DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDRA_WE# {17}
AU50
DDRA_DQ29 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDRA_RAS# {17}
AU52
DDRA_DQ30 BA59 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDRA_BS0# {17}
AY51
DDRA_DQ31 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDRA_MA2 {17}
AT48
DDRA_DQ32 AY39 DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDRA_BS1# {17}
AT50
DDRA_DQ33 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDRA_MA10 {17}
BB50
DDRA_DQ34 AY37 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDRA_MA1 {17}
AY50
DDRA_DQ35 AW37 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDRA_MA0 {17}
BA50
DDRA_DQ36 BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] DDRA_MA3 {17}
BB52
DDRA_DQ37 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDRA_MA4 {17}
DDRA_DQ38 BA37 DDR0_DQ[37]/DDR1_DQ[5] AM70 DDRA_DQS#0
DDRA_DQ39 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 DDRA_DQS0
DDRA_DQ40 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 DDRA_DQS#1 DDRA_DQS#[0..7]
C DDRA_DQ41 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] DDRA_DQS1 DDRA_DQS#[0..7] {17} C
AT70
DDRA_DQ42 AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] BA64 DDRA_DQS#2 DDRA_DQS[0..7]
DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4]
CHECK DDRA_DQS[0..7] {17}
DDRA_DQ43 AW33 AY64 DDRA_DQS2
DDRA_DQ44 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 DDRA_DQS#3
DDRA_DQ45 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDRA_DQS3
DDRA_DQ46 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] BA38 DDRA_DQS#4
DDRA_DQ47 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDRA_DQS4
DDRA_DQ48 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDRA_DQS#5
DDRA_DQ49 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDRA_DQS5
DDRA_DQ50 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDRA_DQS#6
DDRA_DQ51 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDRA_DQS6
DDRA_DQ52 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDRA_DQS#7
DDRA_DQ53 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDRA_DQS7
DDRA_DQ54 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5]
DDR0_DQ[54]/DDR1_DQ[38]
SMVREF
DDRA_DQ55 BB29 AW50 WIDTH:20MIL
DDRA_DQ56 AY27 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# AT52
DDRA_DQ57 AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR SPACING: 20MIL
DDRA_DQ58 AY25 DDR0_DQ[57]/DDR1_DQ[41] AY67
DDRA_DQ59 AW25 DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA DDR_SM_VREFCA {17}
AY68
DDRA_DQ60 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR0_VREF_DQ DDR_SA_VREFDQ {17}
DDR CH - A BA67
DDRA_DQ61 BA27 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ DDR_SB_VREFDQ {18}
DDRA_DQ62 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_VTT_CNTL
DDRA_DQ63 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL
DDR0_DQ[63]/DDR1_DQ[47]
1 OF 20

SKYLAKE-U_BGA1356
REV = 1 ?
@

B B

+3VALW

RC30
100K_0402_5%
2

CPU_DRAMPG_CNTL {55}
+1.35V
1

C
RC3 1 2 2 QC18
1K_0402_5% B
E
3

MMBT3904WH_SOT323-3

DDR_VTT_CNTL
2

RC29
10K_0402_5%
@
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (DDR3LA)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 5 of 60
5 4 3 2 1
 5 4 3 2 1

?
SKL_ULT
UC1C
{18} DDRB_DQ[0..63]

DDRB_DQ0 AF65 AN45

DDRB_DQ1 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] DDRB_CLK0# {18}
AF64 AN46
DDRB_DQ2 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] DDRB_CLK1# {18}
AK65 AP45
DDRB_DQ3 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] DDRB_CLK0 {18}
AK64 AP46
DDRB_DQ4 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDRB_CLK1 {18}
AF66
D DDRB_DQ5 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 D
DDRB_DQ6 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] DDRB_CKE0 {18}
AK67 AP55
DDRB_DQ7 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] DDRB_CKE1 {18}
AK66 AN55
DDRB_DQ8 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53
DDRB_DQ9 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
DDRB_DQ10 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42
DDRB_DQ11 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] DDRB_CS0# {18}
AH68 AY42
DDRB_DQ12 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] DDRB_CS1# {18}
AF71 BA42
DDRB_DQ13 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] DDRB_ODT0 {18}
AF69 AW42
DDRB_DQ14 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDRB_ODT1 {18}
AH70
DDRB_DQ15 AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48
DDRB_DQ16 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDRB_MA5 {18}
AT66 AP50
DDRB_DQ17 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDRB_MA9 {18}
AU66 BA48
DDRB_DQ18 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDRB_MA6 {18}
AP65 BB48
DDRB_DQ19 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDRB_MA8 {18}
AN65 AP48
DDRB_DQ20 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDRB_MA7 {18}
AN66 AP52
DDRB_DQ21 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDRB_BS2# {18}
AP66 AN50
DDRB_DQ22 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDRB_MA12 {18}
AT65 AN48
DDRB_DQ23 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDRB_MA11 {18}
AU65 AN53
DDRB_DQ24 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDRB_MA15 {18}
AT61 AN52
DDRB_DQ25 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDRB_MA14 {18}
AU61
DDRB_DQ26 AP60 DDR1_DQ[25]/DDR0_DQ[57] BA43
DDRB_DQ27 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDRB_MA13 {18}
AN60 AY43
DDRB_DQ28 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDRB_CAS# {18}
AN61 AY44
DDRB_DQ29 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDRB_WE# {18}
AP61 AW44
DDRB_DQ30 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDRB_RAS# {18}
AT60 BB44
DDRB_DQ31 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDRB_BS0# {18}
AU60 AY47
DDRB_DQ32 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDRB_MA2 {18}
AU40 BA44
DDRB_DQ33 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDRB_BS1# {18}
AT40 AW46
DDRB_DQ34 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDRB_MA10 {18}
AT37 AY46
DDRB_DQ35 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDRB_MA1 {18}
AU37 BA46
DDRB_DQ36 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDRB_MA0 {18}
AR40 BB46
C DDRB_DQ37 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] DDRB_MA3 {18} C
AP40 BA47
DDRB_DQ38 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4] DDRB_MA4 {18}
AP37
DDRB_DQ39 AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66 DDRB_DQS#0
DDRB_DQ40 AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDRB_DQS0
DDRB_DQ41 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 DDRB_DQS#1
DDRB_DQ42 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 DDRB_DQS1
DDRB_DQ43 AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDRB_DQS#2
DDRB_DQ44 AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDRB_DQS2
DDRB_DQ45 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDRB_DQS#3 DDRB_DQS#[0..7]
DDRB_DQ46 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] DDRB_DQS3 DDRB_DQS#[0..7] {18}
AR30 AR60
DDRB_DQ47 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDRB_DQS#4 DDRB_DQS[0..7]
DDRB_DQ48 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] DDRB_DQS4 DDRB_DQS[0..7] {18}
AU27 AR38
DDRB_DQ49 AT27 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDRB_DQS#5
DDRB_DQ50 AT25 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] AR32 DDRB_DQS5
DDRB_DQ51 AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25 DDRB_DQS#6
DDRB_DQ52 AP27 DDR1_DQ[51] DDR1_DQSN[6] AR27 DDRB_DQS6
DDRB_DQ53 AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22 DDRB_DQS#7
DDRB_DQ54 AN25 DDR1_DQ[53] DDR1_DQSN[7] AR21 DDRB_DQS7
DDRB_DQ55 AP25 DDR1_DQ[54] DDR1_DQSP[7]
DDRB_DQ56 AT22 DDR1_DQ[55] AN43
DDRB_DQ57 AU22 DDR1_DQ[56] DDR1_ALERT# AP43
DDRB_DQ58 AU21 DDR1_DQ[57] DDR1_PAR AT13 CPU_DRAMRST#_R
DDRB_DQ59 AT21 DDR1_DQ[58] DRAM_RESET# AR18 SM_RCOMP_0 RC24 1 2 121_0402_1%
DDRB_DQ60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP_1 RC25 1 2 80.6_0402_1%
DDRB_DQ61 AP22 DDR1_DQ[60] DDR_RCOMP[1] AU18 SM_RCOMP_2 RC26 1 2 100_0402_1%
DDRB_DQ62 AP21 DDR1_DQ[61] DDR_RCOMP[2]
DDRB_DQ63 AN21 DDR1_DQ[62] DDR CH - B
DDR1_DQ[63]

1 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
B @ B

Need to check the resistor value

+1.35V

1
RC22
2 470_0402_5%

RC23 @ 0_0402_5%
1 2 CPU_DRAMRST#_R
{17,18} CPU_DRAMRST#
1
EMC_NS@
CC1
0.01U_0402_25V7K
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (DDR3LB)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

WWW.AliSaler.Com
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 6 of 60
5 4 3 2 1
 5 4 3 2 1

?
SKL_ULT
UC1E
+3VALW_PCH +3VS +3VS
SPI - FLASH
SMBUS, SMLINK
SPI_CLK RC1539 1 2 15_0402_5% SPI_CLK_R SPI_CLK_R AV2 R7 PCH_SMB_CLK
{44} SPI_CLK SPI_CLK_1 SPI_SO_R SPI0_CLK GPP_C0/SMBCLK PCH_SMB_DATA
RC1538 1 @ 2 33_0402_5% AW3 R8 DIMM1, DIMM2, NGFF
SPI_SI_R AV3 SPI0_MISO GPP_C1/SMBDATA R10 SMB_ALERT#
SPI0_MOSI GPP_C2/SMBALERT#

3
4

4
3
SPI_WP#_R AW2 RPC20
SPI_SO RC53 1 2 15_0402_5% SPI_SO_R SPI_HOLD#_R AU4 SPI0_IO2 R9 SML0_CLK RPC24
{44} SPI_SO SPI0_IO3 GPP_C3/SML0CLK

2
SPI_SO_1 RC177 1 @ 2 33_0402_5% SPI_CS0#_R AU3 W2 SML0_DATA 2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5%

G
D SPI_CS1#_R AU2 SPI0_CS0# GPP_C4/SML0DATA W1 SML0_ALERT# D
AU1 SPI0_CS1# GPP_C5/SML0ALERT#

2
1

1
2
SPI0_CS2# W3 PCH_SML1_CLK
SPI_SI RC52 1 2 15_0402_5% SPI_SI_R GPP_C6/SML1CLK V3 PCH_SML1_DAT PCH_SMB_CLK QC2A 6 1
GPU, EC, Thermal Sensor

S
{44} SPI_SI SPI_SI_1 SPI - TOUCH GPP_C7/SML1DATA SML1_ALERT# SMB_CLK_S3 {17,18,40}
RC1751 @ 2 33_0402_5% AM7

D
M2 GPP_B23/SML1ALERT#/PCHHOT# 2N7002KDWH_SOT363-6
GPP_D1/SPI1_CLK

5
M3

G
@ J4 GPP_D2/SPI1_MISO
SPI_CS0# RC51 1 2 0_0402_5% SPI_CS0#_R V1 GPP_D3/SPI1_MOSI
{44} SPI_CS0# SPI_CS1# SPI_CS1#_R GPP_D21/SPI1_IO2
RC1741 @ 2 0_0402_5% V2
BOARD_ID4 M1 GPP_D22/SPI1_IO3 AY13 PCH_SMB_DATA QC2B 3 4
LPC

S
{8} BOARD_ID4 GPP_D0/SPI1_CS# GPP_A1/LAD0/ESPI_IO0 LPC_AD0 {32,44} SMB_DATA_S3 {17,18,40}
BA13

D
GPP_A2/LAD1/ESPI_IO1 LPC_AD1 {32,44}
BB13 2N7002KDWH_SOT363-6
C LINK GPP_A3/LAD2/ESPI_IO2 LPC_AD2 {32,44}
AY12
GPP_A4/LAD3/ESPI_IO3 LPC_AD3 {32,44}
G3 BA12
CL_CLK GPP_A5/LFRAME#/ESPI_CS# SUS_STAT# LPC_FRAME# {32,44}
G2 BA11 1
G1 CL_DATA GPP_A14/SUS_STAT#/ESPI_RESET# TC81@
CL_RST#
AW9 CLK_PCI_EC_R RC173 2 1 22_0402_5% +3VALW_PCH
+3V_SPI GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_PCI_TPM_R CLK_PCI_EC {44}
KBRST# AW13 AY9 RC1541 2 1 22_0402_5%
{44} KBRST# GPP_A0/RCIN# GPP_A10/CLKOUT_LPC1 PM_CLKRUN# CLK_PCI_TPM {32}
AW11 TPM@
SERIRQ AY11 GPP_A8/CLKRUN# SMB_ALERT# 2.2K_0402_5% 2 1 RC1562
{32,44} SERIRQ GPP_A6/SERIRQ

1 OF 20
1

SKYLAKE-U_BGA1356
RC60 RC61 REV = 1
?
1K_0402_5% 1K_0402_5%
Check with BIOS, SPI is Dual mode or quad mode @
2

SPI_WP#_R RC54 1 2 15_0402_5% SPI_WP#

+3VALW_PCH
C @ +3V_SPI check CLKRUN# / SUS_STAT# signal if need to connect +3VS C
SPI_HOLD#_R RC55 1 2 15_0402_5% SPI_HOLD# RPC23
+3VS +3VALW_PCH SML0_CLK 4 1
@ SML0_DATA 3 2
RC1711 @ 2 0_0402_5% PM_CLKRUN# RC11 1 2 8.2K_0402_5%
2.2K_0404_4P2R_5%
RC1721 @ 2
0_0402_5% SERIRQ RC12 1 2 10K_0402_5%
+3V_SPI +3V_SPI
* +3VALW_PCH
1. If support DS3, connect to +3VS and don't support EC mirror code; KBRST# RC10 1 2 10K_0402_5%
2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.
@
1

SML0_ALERT# RC1564 2 1 2.2K_0402_5%

RC179 RC180
1K_0402_5% 1K_0402_5% KBRST# CC1255 1 2 EMC_NS@ 1000P_0402_50V7K
@ @ This signal has a weak internal pull-down.
0 = LPC Is selected for EC. (Default)
2

SPI_WP#_R SPI_WP#_1 1 = eSPI Is selected for EC.

RC176 1 @ 2 33_0402_5%
Notes:
1. The internal pull-down is disabled after RSMRST#
SPI_HOLD#_R RC178 1 @ 2 33_0402_5% SPI_HOLD#_1 de-asserts.
2. This signal is in the primary wel
+3V_SPI Rising edge of RSMRST#
+3VALW_PCH
UC3
SPI_CS0# 1 8
CS# VCC SML1_ALERT# RC1569 1 2150K_0402_5%
SPI_SO 2 7 SPI_HOLD#
DO HOLD# 1
CC8
+3VALW_PCH Follow CRB, need to check the strap ? SPI_WP# 3 6 SPI_CLK .1U_0402_10V6-K
B WP# CLK B
@ 4 5 SPI_SI 2
RC1568 2 1 20K_0402_5% SPI_SO_R GND DI +3VALW_PCH +3VS To enable Direct Connect Interface (DCI), a 150K pull up resistor will need to be
@ added to PCHHOT# pin. This pin must be low during the rising edge of RSMRST#.
RC1565 2 1 20K_0402_5% SPI_SI_R W25Q64FVSSIQ_SO8 (Refer to WW52_MOW)
@
RC1578 2 1 20K_0402_5% SPI_WP#_R

4
3
@
RC1580 2 1 20K_0402_5% SPI_HOLD#_R RPC25

2
+3V_SPI 2.2K_0404_4P2R_5%

G
UC6

1
2
SPI_CS1# 1 8
SPI_SO_1 2 CS# VCC 7 SPI_HOLD#_1 PCH_SML1_CLK QC10A 6 1

S
SPI_WP#_1 DO HOLD# SPI_CLK_1 EC_SMB_CK2 {39,44}
3 6

D
WP# CLK 1
Follow CRB, need to check the strap ? 4 5 SPI_SI_1 CC97 2N7002KDWH_SOT363-6
GND DI

5
.1U_0402_10V6-K @

G
@ W25Q32FVSSIQ_SO8 @
RC1567 2 1 4.7K_0402_5% SPI_SO_R 2
@
@
RC1566 2 1 4.7K_0402_5% SPI_SI_R PCH_SML1_DAT QC10B 3 4

S
EC_SMB_DA2 {39,44}
@

D
RC1581 2 1 4.7K_0402_5% SPI_WP#_R 2N7002KDWH_SOT363-6
@
RC64 1 2 1K_0402_5% SPI_HOLD#_R

Based on WW36 SKL U&Y WOM, RC64 populated,

and RC61 de-populated for SKL U ES sample.
In this case, customers must ensure that the
A SPI flash device on the platform A
has HOLD functionality disabled by default.

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MPC (MISC,JTAG,SPI,LPC,SMB)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 7 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS

@
RC1561 1 2 2.2K_0402_5% GPP_B18
+3VS
DUALRANK@ DUALMIC@
SKL_ULT ?
UC1F

1 RC1615 2

1 RC1613 2

1 RC1611 2

1 RC1609 2

1 RC1606 2
RC1602 1 2 10K_0402_5% EC_SCI#_R

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
17@ 15@ TS@ PX@
LPSS ISH
@

RC1608
@ AN8 P2 BOARD_ID0
RC1563 1 2 2.2K_0402_5% GPP_B22 AP7 GPP_B15/GSPI0_CS# GPP_D9 P3 BOARD_ID1

1
AP8 GPP_B16/GSPI0_CLK GPP_D10 P4
GPP_B18 AR7 GPP_B17/GSPI0_MISO GPP_D11 P1 BOARD_ID3 BOARD_ID0
GPP_B18/GSPI0_MOSI GPP_D12 BOARD_ID1
D AM5 M4 BOARD_ID2 D
CMOS_ON# GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA BOARD_ID5 {9} BOARD_ID2 BOARD_ID3
AN7 N3
{33} CMOS_ON# EC_SCI#_R GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL BOARD_ID4
RC183 1 2 0_0402_5% AP5
{4,44} EC_SCI# GPP_B22 GPP_B21/GSPI1_MISO {7} BOARD_ID4 BOARD_ID5
AN5 N1
GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2
@
AB1 GPP_D8/ISH_I2C1_SCL
{40} UART_RX_DEBUG GPP_C8/UART0_RXD
AB2 AD11

10K_0402_5%
SINGLERANK@
SINGLEMIC@
{40} UART_TX_DEBUG GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA

1 RC1616 2

1 RC1614 2

1 RC1612 2

1 RC1610 2

1 RC1607 2

1 RC123 2
RC1558 1 UMA@ 2 10K_0402_5% VGA_PWRGD W4 AD12

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
14or15@ 14or17@ NTS@ UMA@
AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_C11/UART0_CTS#
AD1 U1
{40} UART2_RXD GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
AD2 U2
{40} UART2_TXD VGA_PWRGD GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
AD3 U3
AD4 GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# U4
GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
AC1
ODD_EN U7 GPP_C12/UART1_RXD/ISH_UART1_RXD AC2
U6 GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD AC3
+3VALW_PCH GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4
PCH_WLAN_OFF# U8 GPP_C15/UART1_CTS#/ISH_UART1_CTS#
{40} PCH_WLAN_OFF# PCH_BT_OFF# GPP_C18/I2C1_SDA
U9 AY8
{40} PCH_BT_OFF# GPP_C19/I2C1_SCL GPP_A18/ISH_GP0
@ BA8
RC1593 2 1 10K_0402_5% ODD_EN AH9 GPP_A19/ISH_GP1 BB7
AH10 GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BA7
GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 AY7
AH11 GPP_A22/ISH_GP4 AW7
+3VS AH12 GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 AP13 GPP_A12 1 TC82 @
GPP_F7/I2C3_SCL GPP_A12/BM_BUSY#/ISH_GP6
AF11 check GPP_A12
AF12 GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL
Board ID Description Stuff R
@ 00 14" RC1616 RC1614
C RC1595 2 1 10K_0402_5% CMOS_ON# 1 OF 20 C
PCH_WLAN_OFF# SKYLAKE-U_BGA1356
RC1596 2 1 10K_0402_5% REV = 1 ? Board_ID[0:1] 01 15" RC1616 RC1613
RC1597 2 1 10K_0402_5% PCH_BT_OFF#
@ UC1G SKL_ULT ? 10 17" RC1615 RC1614
double check if need the pull up resisor
AUDIO 11 Reserved
RC43 1 2 33_0402_5% HDA_SYNC BA22 Board_ID2 0 Non-touch RC1612
{43} HDA_SYNC_AUDIO HDA_BCLK HDA_SYNC/I2S0_SFRM
RC42 1 2 33_0402_5% AY22
+3VALW_PCH +3VS {43} HDA_BITCLK_AUDIO HDA_SDOUT HDA_BLK/I2S0_SCLK
BB22 SDIO/SDXC 1 Touch RC1611
HDA_SDIN0 BA21 HDA_SDO/I2S0_TXD
{43} HDA_SDIN0 HDA_SDI0/I2S0_RXD SD_CMD_PCH
RC1600 1 @ 2 1K_0402_5% AY21 AB11 Board_ID3 0 UMA RC1610
HDA_RST# HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD SD_D0_PCH SD_CMD_PCH {30}
RC44 1 2 33_0402_5% AW22 AB13
HDA_SDOUT {43} HDA_RST_AUDIO# HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 SD_D1_PCH SD_D0_PCH {30}
RC47 1 @ 2 1K_0402_5% J5 AB12 1 DIS RC1609
GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 SD_D2_PCH SD_D1_PCH {30}
AY20 W12
* AW20 I2S1_SFRM
I2S1_TXD
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
W11 SD_D3_PCH
SD_CD#_PCH
SD_D2_PCH
SD_D3_PCH
{30}
{30} Board_ID4 0 SingleRankRC1607
HDA_SDO This signal has a weak internal pull-down. W10
GPP_G5/SD_CD# SD_CLK_PCH SD_CD#_PCH {30}
0 = Enable security measures defined in the Flash Descriptor. AK7 W8 1 DualRank RC1608
GPP_F1/I2S2_SFRM GPP_G6/SD_CLK SD_WP_PCH SD_CLK_PCH {30}
AK6 W7
1 = Disable Flash Descriptor Security(override). This strap GPP_F0/I2S2_SCLK GPP_G7/SD_WP SD_WP_PCH {30}
AK9 Board_ID5 0 SingleMIC RC123
should only be asserted high during external pull-up in AK10 GPP_F2/I2S2_TXD BA9 SD_PWR_EN#
manufacturing/debug environments ONLY. GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 SD_1P8_SEL SD_PWR_EN# {44}
BB9 1 DualMIC RC1606
GPP_A16/SD_1P8_SEL SD_1P8_SEL {30}
H5 AB7 SD_RCOMP RC49 1 2 200_0402_1%
D7 GPP_D19/DMIC_CLK0 SD_RCOMP
GPP_D20/DMIC_DATA0
For EMI D8 AF13
HDA_SDIN0 C8 GPP_D17/DMIC_CLK1 GPP_F23
GPP_D18/DMIC_DATA1
PCH_BEEP AW5
{43} PCH_BEEP GPP_B14/SPKR
1
EMC_NS@
B CC7 B
10P_0402_50V8J 1 OF 20
2 SKYLAKE-U_BGA1356
REV = 1 ?
@

+3VS
RC45 1 2 33_0402_5% HDA_SDOUT
{43} HDA_SDOUT_AUDIO +3VALW_PCH
RC46 1 2 0_0402_5% @
{44} ME_FLASH PCH_BEEP
RC14 1 2 2.2K_0402_5%
@

PCH_SDIO@
SD_PWR_EN# RC1603 1 2 49.9K_0402_1%
Default When
Pin Name Strap Description Configuration Value Sampled
Internal PD
0 = Disable “ Top Swap”
SPKR / Top Swap mode. (Default) 0 Rising edge
GPP_B14 Override 1 = Enable “ Top Swap” * of PCH_PWROK
mode.

Internal PD
0 = Disable “ No Reboot”
GSPI0_MOSINo Reboot mode. (Default)
A
/GPP_B18 1 = Enable “ No Reboot” * 0 Rising edge A

mode of PCH_PWROK

Internal PD
0 = SPI (Default) Security Classification LC Future Center Secret Data Title
GSPI1_MOSIBoot BIOS Rising edge
/GPP_B22 Strap Bit
1 = LPC * 0 of PCH_PWROK Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (LPSS,ISH,AUDIO,SDIO)
BBS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 8 of 60
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

PCIE1
D D

SKL_ULT
?
UC1H

SSIC / USB3
PCIE/USB3/SATA
H8 USB30_RX_N1
USB3_1_RXN USB30_RX_P1 USB30_RX_N1 {41}
G8
H13 USB3_1_RXP C13 USB30_TX_N1 USB30_RX_P1 {41} LEFT USB (3.0)
PCIE1_RXN/USB3_5_RXN USB3_1_TXN USB30_TX_P1 USB30_TX_N1 {41}
G13 D13
PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB30_TX_P1 {41}
B17
A17 PCIE1_TXN/USB3_5_TXN J6
PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN H6
G11 USB3_2_RXP/SSIC_1_RXP B13
F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13
D16 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP
C16 PCIE2_TXN/USB3_6_TXN J10
PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN H10
H16 USB3_3_RXP/SSIC_2_RXP B15
G16 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN A15
D17 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP
C17 PCIE3_TXN E10
PCIE3_TXP USB3_4_RXN F10
G15 USB3_4_RXP C15
F15 PCIE4_RXN USB3_4_TXN D15
B19 PCIE4_RXP USB3_4_TXP
A19 PCIE4_TXN AB9 USB20_N1
PCIE4_TXP USB2N_1 USB20_P1 USB20_N1 {41}
AB10
PCIE_PRX_DTX_N5 F16 USB2P_1 USB20_P1 {41} LEFT USB (3.0)
{37} PCIE_PRX_DTX_N5 PCIE5_RXN
PCIE_PRX_DTX_P5 E16 AD6 USB20_N2
LAN PCIE5
{37} PCIE_PRX_DTX_P5
CC22 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_N5 C19 PCIE5_RXP USB2N_2 AD7 USB20_P2 USB20_N2 {45} RIGHT USB (2.0)
{37} PCIE_PTX_C_DRX_N5 PCIE5_TXN USB2P_2 USB20_P2 {45}
CC23 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_P5 D19
C {37} PCIE_PTX_C_DRX_P5 PCIE5_TXP USB20_N3 C
AH3
PCIE_PRX_DTX_N6 USB2N_3 USB20_P3 USB20_N3 {45}
G18 AJ3
{40} PCIE_PRX_DTX_N6
PCIE_PRX_DTX_P6 F18 PCIE6_RXN USB2P_3 USB20_P3 {45} RIGHT USB (2.0)
{40} PCIE_PRX_DTX_P6 PCIE6_RXP
WLAN PCIE6 CC24 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_N6 D20 AD9 USB20_N4
{40} PCIE_PTX_C_DRX_N6 PCIE6_TXN USB2N_4 USB20_N4 {33}
CC25 1 2 .1U_0402_10V6-K PCIE_PTX_DRX_P6 C20 AD10 USB20_P4
{40} PCIE_PTX_C_DRX_P6 PCIE6_TXP USB2P_4 USB20_P4 {33} Camera
SATA_PRX_DTX_N0 F20 AJ1 USB20_N5
{42} SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 PCIE7_RXN/SATA0_RXN USB2N_5 USB20_P5 USB20_N5 {30}
E20 AJ2
{42} SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 B21 PCIE7_RXP/SATA0_RXP
USB2
USB2P_5 USB20_P5 {30} Card reader
{42} SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 A21 PCIE7_TXN/SATA0_TXN AF6 USB20_N6
{42} SATA_PTX_DRX_P0 PCIE7_TXP/SATA0_TXP USB2N_6 AF7 USB20_P6 USB20_N6 {33} Touch panel
SATA_PRX_DTX_N1 USB2P_6 USB20_P6 {33}
G21
{42} SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 F21 PCIE8_RXN/SATA1A_RXN AH1 USB20_N7
{42} SATA_PRX_DTX_P1 SATA_PTX_DRX_N1 D21 PCIE8_RXP/SATA1A_RXP USB2N_7 AH2 USB20_P7 USB20_N7 {40} BT
{42} SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 {40}
C21
{42} SATA_PTX_DRX_P1 PCIE8_TXP/SATA1A_TXP AF8
E22 USB2N_8 AF9
E23 PCIE9_RXN USB2P_8
B23 PCIE9_RXP AG1
A23 PCIE9_TXN USB2N_9 AG2
PCIE9_TXP USB2P_9
F25 AH7
E25 PCIE10_RXN USB2N_10 AH8
D23 PCIE10_RXP USB2P_10
C23 PCIE10_TXN AB6 USB2_COMP RC118 2 1 113_0402_1%
PCIE10_TXP USB2_COMP
USBRBIAS
AG3 USB2_ID RC1635 1 2 0_0402_5% Width 20Mil
RC119 1 2 100_0402_1% PCIE_RCOMPN F5 USB2_ID AG4USB2_VBUSSENSE RC1634 1 2 1K_0402_5%
PCIE_RCOMPN USB2_VBUSSENSE Space 15Mil
PCIE_RCOMPP E5
PCIE_RCOMPP A9 USB_OC0# Length 500Mil
PAD @ TC20 1 XDP_PRDY# D56 GPP_E9/USB2_OC0# C9 USB_OC1#
XDP_PREQ# PROC_PRDY# GPP_E10/USB2_OC1# USB_OC2# USB_OC1# {41}
PAD @ TC19 1 D61 D9
PROC_PREQ# GPP_E11/USB2_OC2# USB_OC3# USB_OC2# {45}
PIRQA# BB11 B9
B GPP_A7/PIRQA# GPP_E12/USB2_OC3# B
E28 J1 GPP_E4 RC1636 1 2 0_0402_5%
PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 GPP_E5 EC_SMI# {44}
E27 J2 1
D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3 @ PAD TC202
@
C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
E30 PCIE11_TXP/SATA1B_TXP H2 SATA0GP
F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3 ODD_DETECT#
PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 ODD_DETECT#
A25 G4 SATA2GP
B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2
PCIE12_TXP/SATA2_TXP H1 BOARD_ID2
GPP_E8/SATALED# BOARD_ID2 {8}

1 OF 20 +3VS
SKYLAKE-U_BGA1356
REV = 1 ?
@
@
GPP_E4 RC1617 2 1 10K_0402_5%
+3VALW_PCH

+3VS
RPC2 RPC17
1 8 ODD_DETECT# USB_OC0# 8 1
2 7 SATA0GP USB_OC1# 7 2
3 6 SATA2GP USB_OC3# 6 3
4 5 PIRQA# USB_OC2# 5 4

10K_0804_8P4R_5% 10K_0804_8P4R_5%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (PCIE,SATA,USB3,USB2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 9 of 60
5 4 3 2 1
 5 4 3 2 1

UC1I
SKL_ULT ?

CSI-2

A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D D36 CSI2_DN2 CSI2_CLKN2 D29 D
A38 CSI2_DP2 CSI2_CLKP2 B26
B38 CSI2_DN3 CSI2_CLKN3 A26
CSI2_DP3 CSI2_CLKP3
C31 E13 CSI2_COMP RC73 1 2 100_0402_1%
D31 CSI2_DN4 CSI2_COMP B7
C33 CSI2_DP4 GPP_D4/FLASHTRIG
D33 CSI2_DN5
A31 CSI2_DP5 EMMC
check the Pull up resistor CSI2_DN6
B31 AP2
A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
+3VS B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
RPC3 @ A29 GPP_F16/EMMC_DATA3 AN1
1 8 PCIE_CLKREQ2# B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
2 7 PCIE_CLKREQ3# C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
3 6 PCIE_CLKREQ1# D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
4 5 A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
10K_0804_8P4R_5% C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
RPC4 D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
1 8 GPU_CLKREQ# CSI2_DP11 GPP_F12/EMMC_CMD
2 7 LAN_CLKREQ# AT1 EMMC_RCOMP RC50 1 2 200_0402_1%
3 6 EMMC_RCOMP
4 5 WLAN_CLKREQ# 1 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
10K_0804_8P4R_5%
@

SUSCLK RC95 1 @ 2 1K_0402_5%

UC1J SKL_ULT ?

C CLOCK SIGNALS C

D42
C42 CLKOUT_PCIE_N0
GPU_CLKREQ# AR10 CLKOUT_PCIE_P0
GPP_B5/SRCCLKREQ0#
B42
A42 CLKOUT_PCIE_N1 F43
PCIE_CLKREQ1# AT7 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N E43
GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
D41 BA17 SUSCLK
CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK {40}
C41
PCIE_CLKREQ2# AT8 CLKOUT_PCIE_P2 E37 XTAL24_IN
GPP_B7/SRCCLKREQ2# XTAL24_IN E35 XTAL24_OUT +VCCCLK5
D40 XTAL24_OUT
C40 CLKOUT_PCIE_N3 E42 DIFFCLK_BIASREF RC72 1 2 2.7K_0402_1% RC1555
PCIE_CLKREQ3# AT10 CLKOUT_PCIE_P3 XCLK_BIASREF DIFFCLK_BIASREF 1 2 60.4_0402_1%
GPP_B8/SRCCLKREQ3# AM18 RTC_X1 Cannonlake@
CLK_PCIE_LAN# B40 RTCX1 AM20 RTC_X2
{37} CLK_PCIE_LAN# CLK_PCIE_LAN CLKOUT_PCIE_N4 RTCX2
PCIE CLK5 LAN A40
{37} CLK_PCIE_LAN LAN_CLKREQ# CLKOUT_PCIE_P4 SRTC_RST#
AU8 AN18
{37} LAN_CLKREQ# GPP_B9/SRCCLKREQ4# SRTCRST# RTC_RST#
AM16
CLK_PCIE_WLAN# E40 RTCRST#
{40} CLK_PCIE_WLAN# CLK_PCIE_WLAN CLKOUT_PCIE_N5
PCIE CLK6 WLAN E38
{40} CLK_PCIE_WLAN WLAN_CLKREQ# CLKOUT_PCIE_P5
AU7
{40} WLAN_CLKREQ# GPP_B10/SRCCLKREQ5#
1
CC3
VCCRTC 1U_0402_10V6K
1 OF 20
SKYLAKE-U_BGA1356 2
REV = 1 ?
RC33 1 2 20K_0402_1% SRTC_RST#
B @ RC34 1 2 20K_0402_1% RTC_RST# RC16241 2 0_0402_5% B
EC_RTC_RST# {44}
1 @

1
CC6 JCMOS1
1U_0402_10V6K SHORT PADS
@

2
2

change to SJ10000LM00 RTC_X1

check if need to change to 1M_0402_1% follow PDG,
RC71 2 1 1M_0402_5%
CRB is 1M_0402_5%
RC32 2 1 10M_0402_5% RTC_X2

2 3 XTAL24_OUT YC1
GND1 OSC2 1 2
XTAL24_IN 1 4
OSC1 GND2 X1A000141000200
2 2
1
1 YC2 CC11 CC4 CC5
CC12 2.7P_0402_50V9-B 7P_0402_50V8J 7P_0402_50V8J
2.7P_0402_50V9-B 24MHZ_6PF_X1E000021088000 1 1
2
2
when single end external clock generator used,
this pin should be grounded

need to use 38.4MHz (30ohm) for Cannonlake-u

GCLK@
{31} RTC_CLK RC121 1 2 0_0402_5% RTC_X1
A GCLK@ A

{31} 24M_CLK RC122 1 2 0_0402_5% XTAL24_IN

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (CSI2,EMMC,CLOCK)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

WWW.AliSaler.Com
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 10 of 60
5 4 3 2 1
 5 4 3 2 1

SKL_ULT
?
UC1K
SYSTEM POWER MANAGEMENT
check if need one buffer PM_SLP_S0#_R
AT11 1 TC204 PAD @
@ GPP_B12/SLP_S0# AP15 PM_SLP_S3#_R RC96 1 @ 2 0_0402_5%
PLT_RST#_R GPD4/SLP_S3# PM_SLP_S4#_R PM_SLP_S3# {11,13,44}
RC84 1 2 0_0402_5% AN10 BA16 RC97 1 @ 2 0_0402_5%
{32,37,40,44} PLT_RST# SYS_RESET# GPP_B13/PLTRST# GPD5/SLP_S4# PM_SLP_S5# PM_SLP_S4# {44}
@ B5 AY16
D PCH_RSMRST#_R SYS_RESET# GPD10/SLP_S5# PM_SLP_S5# {44} D
RC85 1 2 0_0402_5% AY17
{44} EC_RSMRST# RSMRST# PM_SLP_SUS#_R
AN15 RC89 1 @ 2 0_0402_5%
CPU_PROCPWRGD SLP_SUS# PM_SLP_SUS# {44}
PAD @ TC21 1 A68 AW15 1
VCCST_PWRGD_R RC93 1 2 60.4_0402_1% VCCST_PWRGD B65 PROCPWRGD SLP_LAN# BB17 1 TC40 PAD @ Reserve for DS3
VCCST_PWRGD GPD9/SLP_WLAN# AN16 1 TC41 PAD @
RC139 1 @ 2 0_0402_5% SYS_PWROK_R B6 GPD6/SLP_A# TC44 PAD @
{44} SYS_PWROK PCH_PWROK_R SYS_PWROK PBTN_OUT#_R PBTN_OUT# {44}
RC126 1 @ 2 0_0402_5% BA20 BA15 RC87 1 @ 2 0_0402_5%
{44} PCH_PWROK PCH_DPWROK_R PCH_PWROK GPD3/PWRBTN# AC_PRESENT_R
BB20 AY15
DSW_PWROK GPD1/ACPRESENT AU13 BATLOW#
RC86 1 @ 2 0_0402_5% SUSWARN#_R AR13 GPD0/BATLOW#
{44} SUSWARN# SUSACK#_R GPP_A13/SUSWARN#/SUSPWRDNACK
RC79 1 @ 2 0_0402_5% AP11 VCCRTC
{44} SUSACK# GPP_A15/SUSACK#
Reserve for DS3 AU11 PME# 1 TC89 @
RC91 1 @ 2 0_0402_5% WAKE# BB15 GPP_A11/PME# AP16 INTVRMEN RC41 2 1 330K_0402_5%
{37,40,44} PCIE_WAKE# PCH_LAN_WAKE# AM15 WAKE# INTRUDER#
PAD @ TC203 1 GPD11 AW17 GPD2/LAN_WAKE# AM10 1 TC93 @
AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 1 TC96 @
GPD7/RSVD GPP_B2/VRALERT#

1 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
@
+3VALW +3VS

RC74 1 2 10K_0402_5% AC_PRESENT_R RC80 1 2 10K_0402_5% SYS_RESET#

RC88 1 @ 2 0_0402_5% AC_PRESENT_R
{44} AC_PRESENT
RC75 1 2 8.2K_0402_5% BATLOW#

RC76 2 1 1K_0402_5% WAKE# Follow CRB change to 1kohm

1
RC90 1 2 10K_0402_5% PCH_LAN_WAKE# D @
C 2 QC8 C
{44} ACIN# G 2N7002KW_SOT323-3

3
+3VALW_PCH

+VCCST_CPU +VCCSTG

RC78 @1 2 10K_0402_5% SUSWARN#_R

2
@
CC1254 EMC_NS@ +3VALW RC137 RC1554
1 2 PCH_RSMRST#_R 1K_0402_5% 1K_0402_5%
1000P_0402_50V7K

2
CC104 EMC_NS@

1
1 2 PCH_PWROK RC136
1000P_0402_50V7K 10K_0402_5% VCCST_PWRGD_R
CC103 EMC_NS@

3
1 2 PCH_DPWROK_R D

1
1000P_0402_50V7K 5 QC6B 2
@ G
EMC_NS@
CC1011 2 SYS_PWROK 2N7002KDWH_SOT363-6 CC140

6
1000P_0402_50V7K D S 1000P_0402_50V7K

4
RC138 1 2 0_0402_5% 2 QC6A 1
{44} EC_VCCST_PWRGD @ EMC_NS@
G
@ 1 2N7002KDWH_SOT363-6
CC46 S

1
0.01U_0402_16V7K
@
RPC21 EMC_NS@
1 8 PCH_RSMRST#_R 2
2 7 PCH_PWROK
3 6 SYS_PWROK
B 4 5 B

10K_0804_8P4R_5%

RC1599 1 @ 2 0_0402_5%

DC4 1 2 @
{11,13,44} PM_SLP_S3#
RB751V-40_SOD323-2

100K_0402_5% 2 1 RC92 PLT_RST#_R RC1821 @ 2 0_0402_5% EC_RSMRST#

100K_0402_1% 2 @ 1 RC94 PCH_DPWROK_R Reserve for DS3

PCH_DPWROK_R RC81 1 @ 2 0_0402_5% DPWROK_EC {44}

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (SYSTEM PWR MANAGEMENT)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 11 of 60
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE ? +CPU_CORE +VCC_GT

SKL_ULT SKL_ULT ?
UC1L +VCC_GT UC1M
CPU POWER 1 OF 4
CPU POWER 2 OF 4
A30 G32 +CPU_CORE +VCC_GT N70
A34 VCC_A30 VCC_G32 G33 A48 VCCGT_N70 N71
A39 VCC_A34 VCC_G33 G35 A53 VCCGT_A48 VCCGT_N71 R63
A44 VCC_A39 VCC_G35 G37 A58 VCCGT_A53 VCCGT_R63 R64
AK33 VCC_A44 VCC_G37 G38 VCORE_VCC_SEN RC77 1 2 100_0402_1% VCCGT_VCC_SEN RC83 1 2 100_0402_1% A62 VCCGT_A58 VCCGT_R64 R65
AK35 VCC_AK33 VCC_G38 G40 A66 VCCGT_A62 VCCGT_R65 R66
AK37 VCC_AK35 VCC_G40 G42 AA63 VCCGT_A66 VCCGT_R66 R67
AK38 VCC_AK37 VCC_G42 J30 VCORE_VSS_SEN RC82 1 2 100_0402_1% VCCGT_VSS_SEN RC98 1 2 100_0402_1% AA64 VCCGT_AA63 VCCGT_R67 R68
AK40 VCC_AK38 VCC_J30 J33 AA66 VCCGT_AA64 VCCGT_R68 R69
AL33 VCC_AK40 VCC_J33 J37 AA67 VCCGT_AA66 VCCGT_R69 R70
AL37 VCC_AL33 VCC_J37 J40 AA69 VCCGT_AA67 VCCGT_R70 R71
AL40 VCC_AL37 VCC_J40 K33 AA70 VCCGT_AA69 VCCGT_R71 T62
D VCC_AL40 VCC_K33 VCCGT_AA70 VCCGT_T62 D
AM32 K35 AA71 U65
AM33 VCC_AM32 VCC_K35 K37 AC64 VCCGT_AA71 VCCGT_U65 U68
AM35 VCC_AM33 VCC_K37 K38 AC65 VCCGT_AC64 VCCGT_U68 U71
AM37 VCC_AM35 VCC_K38 K40 AC66 VCCGT_AC65 VCCGT_U71 W63
AM38 VCC_AM37 VCC_K40 K42 AC67 VCCGT_AC66 VCCGT_W63 W64
G30 VCC_AM38 VCC_K42 K43 AC68 VCCGT_AC67 VCCGT_W64 W65
@ VCC_G30 VCC_K43 AC69 VCCGT_AC68 VCCGT_W65 W66
TC90 1 K32 E32 VCORE_VCC_SEN AC70 VCCGT_AC69 VCCGT_W66 W67
RSVD_K32 VCC_SENSE VCORE_VSS_SEN VCORE_VCC_SEN {59} VCCGT_AC70 VCCGT_W67
E33 AC71 W68
VSS_SENSE VCORE_VSS_SEN {59} VCCGT_AC71 VCCGT_W68
TC91 1 AK32 J43 W69
@ RSVD_AK32 B63 CPU_SVID_ALERT#_R J45 VCCGT_J43 VCCGT_W69 W70
AB62 VIDALERT# A63 CPU_SVID_CLK_R J46 VCCGT_J45 VCCGT_W70 W71
2.5A P62 VCCOPC_AB62 VIDSCK D64 CPU_SVID_DAT_R J48 VCCGT_J46 VCCGT_W71 Y62
V62 VCCOPC_P62 VIDSOUT J50 VCCGT_J48 VCCGT_Y62 +VCC_GT
+VCCOPC_1.0V VCCOPC_V62 VCCGT_J50
G20 +VCCSTG J52
+V1.8S_EDRAM H63 VCCSTG_G20 J53 VCCGT_J52 AK42
U23E@ 0.05A VCC_OPC_1P8_H63 J55 VCCGT_J53 VCCGTX_AK42 AK43
1 2 G61 +VCCEOPIO J56 VCCGT_J55 VCCGTX_AK43 AK45
+1.8VALW VCC_OPC_1P8_G61 +VCCOPC_1.0V VCCGT_J56 VCCGTX_AK45
RC1626 0_0402_5% J58 AK46
VCCOPC_SENSE AC63 J60 VCCGT_J58 VCCGTX_AK46 AK48
{57} VCCOPC_SENSE VSSOPC_SENSE VCCOPC_SENSE RC1631 VCCGT_J60 VCCGTX_AK48
AE63 K48 AK50
{57} VSSOPC_SENSE VSSOPC_SENSE VCCGT_K48 VCCGTX_AK50
1 2 K50 AK52
2.0A AE62 K52 VCCGT_K50 VCCGTX_AK52 AK53
AG62 VCCEOPIO_AE62 K53 VCCGT_K52 VCCGTX_AK53 AK55
+VCCEOPIO VCCEOPIO_AG62 0_0805_5% VCCGT_K53 VCCGTX_AK55
K55 AK56
VCCEOPIO_SENSE AL63 U23E@ +VCCEOPIO K56 VCCGT_K55 VCCGTX_AK56 AK58
VSSEOPIO_SENSE AJ62 VCCEOPIO_SENSE +VCCOPC_1.0V K58 VCCGT_K56 VCCGTX_AK58 AK60
VSSEOPIO_SENSE K60 VCCGT_K58 VCCGTX_AK60 AK70
L62 VCCGT_K60 VCCGTX_AK70 AL43
1 OF 20 L63 VCCGT_L62 VCCGTX_AL43 AL46
SKYLAKE-U_BGA1356 ? VCCEOPIO_SENSE VCCGT_L63 VCCGTX_AL46
REV = 1 RC1629 1 2 100_0402_1% L64 AL50
VCCOPC_SENSE RC1627 1 2 100_0402_1% L65 VCCGT_L64 VCCGTX_AL50 AL53
@ VCCGT_L65 VCCGTX_AL53
U23E@ L66 AL56
VSSEOPIO_SENSE RC1630 1 2 100_0402_1% L67 VCCGT_L66 VCCGTX_AL56 AL60
U23E@
VSSOPC_SENSE RC1628 1 2 100_0402_1% L68 VCCGT_L67 VCCGTX_AL60 AM48
L69 VCCGT_L68 VCCGTX_AM48 AM50
U23E@
L70 VCCGT_L69 VCCGTX_AM50 AM52
C U23E@ C
L71 VCCGT_L70 VCCGTX_AM52 AM53
M62 VCCGT_L71 VCCGTX_AM53 AM56
+VCCEOPIO N63 VCCGT_M62 VCCGTX_AM56 AM58
+VCCOPC_1.0V +V1.8S_EDRAM N64 VCCGT_N63 VCCGTX_AM58 AU58
N66 VCCGT_N64 VCCGTX_AU58 AU63
N67 VCCGT_N66 VCCGTX_AU63 BB57
N69 VCCGT_N67 VCCGTX_BB57 BB66
VCCGT_N69 VCCGTX_BB66 TC133
10U_0402_6.3V6-M

10U_0402_6.3V6-M

VCCGT_VCC_SEN VCCGTX_SENSE TC134

10U_0402_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1 1 J70 AK62 1
{59} VCCGT_VCC_SEN VCCGT_VSS_SEN VCCGT_SENSE VCCGTX_SENSE VSSGTX_SENSE

1U_0402_10V6K
CC1266

CC1267

1 1 1 1 1 1 1 J69 AL61 1
VCCOPC_SENSE {59} VCCGT_VSS_SEN VSSGT_SENSE VSSGTX_SENSE
2 0_0402_5% VCCEOPIO_SENSE
CC1265

CC1264

CC1259

CC1260

CC1261

CC1262

CC1263

1 RC1632 1
@
CC1268
@
2 2 1 OF 20 @
@ SKYLAKE-U_BGA1356
2 2 2 2 2 2 2 VSSOPC_SENSE RC1633 1 2 0_0402_5% VSSEOPIO_SENSE
2 REV = 1 ?
@
U23E@ U23E@ @
U23E@ U23E@ U23E@ U23E@ U23E@ U23E@ U23E@

+VCC_GT Backside Cap 8x10uF 0402, SIT update

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M
1 1 1 1 1 1 1 1

CC1122

CC1123

CC1124

CC1125

CC1126

CC1127

CC1128

CC1129
2 2 2 2 2 2 2 2
SVID
+VCCST_CPU
@ @ @ @

+CPU_CORE

13x10uF 0402, SIT update to 0603 package +VCC_GT

.1U_0402_10V6-K
B @ Backside Cap 12x1uF 0201, SIT update B

1
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0402_6.3V6-M

10U_0402_6.3V6-M

CC42
2

1
56_0402_5%

100_0402_1%

100_0402_1%

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1

2
CC1086

CC1085

CC1080

CC1236

CC1237

CC1093

CC1092

CC1091

CC1089

CC1238

RC131

RC1544

RC132
1 1 1 1 1 1 1 1

CC1111

CC1114

CC1115

CC1116

CC1118

CC1119

CC1240

CC1241
2 2 2 2 2 2 2 2 2 2

2
@ 2 2 2 2 2 2 2 2

RC133 1 2 220_0402_1% CPU_SVID_ALERT#_R

{59} VR_SVID_ALRT#

RC134 1 @ 2 0_0402_5% CPU_SVID_CLK_R +VCC_GT Backside Cap 8x10uF 0402

{59} VR_SVID_CLK

+CPU_CORE RC1545 1 @ 2 0_0402_5% CPU_SVID_DAT_R

{59} VR_SVID_DAT

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M
15x1uF 0201, SIT update to 0402 package
1 1 1 1 1 1 1 1

CC1269

CC1270

CC1271

CC1272

CC1273

CC1274

CC1275

CC1276
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0201_6.3V6-K

1U_0201_6.3V6-K

1 1 1 1 1 1 1 1 1 1 1 1 1, Alert# Route Between CLK and Data 2 2 2 2 2 2 2 2

CC1095

CC1096

CC1097

CC1098

CC1099

CC1100

CC1101

CC1102

CC1104

CC1105

CC1108

CC1109

2 2 2 2 2 2 2 2 2 2 2 2
U23E@ U23E@ U23E@ U23E@ U23E@ U23E@ U23E@ U23E@

@ @

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (CPU PWR1)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 12 of 60
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

+VCCIO
3.1A 2x10uF, 4x1uF
+1.35V Need short +1.35V_CPU

10U_0402_6.3V6-M

10U_0402_6.3V6-M

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K
1U_0201_6.3V6-K

1U_0201_6.3V6-K

1U_0201_6.3V6-K

1U_0201_6.3V6-K
JC1 @

CC1218

CC1230

CC1231

@ CC1232
1 2 +VCCIO 1 1 1 1 1 1 1 1 1 1
1 2

CC1152

CC1153

CC1158

CC1159

CC1160

CC1161
@ 1 +1.35V_CPU
?
UC1N SKL_ULT
JUMP_43X79
CC1170 CPU POWER 3 OF 4
0.1u_0201_10V6K 2 2 2 2 2 2 2 2 2 2
2 AU23 AK28
AU28 VDDQ_AU23 VCCIO_AK28 AK30
+1.35V_CPU AU35 VDDQ_AU28 VCCIO_AK30 AL30 @ @ @ @
2A , 3x22uF, 6x10uF, 4x1uF, SIT update VDDQ_AU35 VCCIO_AL30
AU42 AL42
BB23 VDDQ_AU42 VCCIO_AL42 AM28
BB32 VDDQ_BB23 VCCIO_AM28 AM30 +VCCSA
VDDQ_BB32 VCCIO_AM30
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

10U_0603_6.3V6M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

1U_0201_6.3V6-M
1U_0201_6.3V6-K

1U_0201_6.3V6-K

1U_0201_6.3V6-K
BB41 AM42
BB47 VDDQ_BB41 VCCIO_AM42
D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VDDQ_BB47 D
CC1256

CC1257

CC1258

CC1168

CC1169

CC1171

CC1222

CC1223

CC1243

CC1244

CC1224

CC1225

CC1226

CC1227
BB51 AK23 +VCCSA
VDDQ_BB51 VCCSA_AK23 AK25
@ @ VCCSA_AK25 G23
VCCSA_G23
4.5A 10x10uF, 7x1uF, SIT update
2 2 2 2 2 2 2 2 2 2 2 2 2 2 AM40 G25
+VDDQ_CPU_CLK VDDQC VCCSA_G25 G27
VCCSA_G27

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
+VCCST_CPU A18 G28
@ @ VCCST VCCSA_G28 J22
VCCSA_J22 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CC1133

CC1134

CC1135

CC1136

CC1137

CC1251

CC1252

CC1253

CC1139

CC1140

CC1142

CC1145

CC1141

CC1143

CC1144
+VCCSTG A22 J23
VCCSTG_A22 VCCSA_J23

CC1132
J27
AL23 VCCSA_J27 K23
+VCCSFR_OC VCCPLL_OC VCCSA_K23 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
K25
K20 VCCSA_K25 K27
K21 VCCPLL_K20 VCCSA_K27 K28
+VCCPLL_CPU VCCPLL_K21 VCCSA_K28 K30 @ @ @ @
+VCCSTG +VCCST_CPU VCCSA_K30
+VDDQ_CPU_CLK AM23 VCCIO_SENSE 1 TC136 @
VCCIO_SENSE AM22 VSSIO_SENSE 1 TC137 @
120mA VSSIO_SENSE
VCCSA_VSS_SEN

1U_0402_10V6K
+1.35V_CPU 1
RC1497 2 0_0402_5% +VCCIO RC103 1 2 0_0402_5% H21
VSSSA_SENSE VCCSA_VCC_SEN VCCSA_VSS_SEN {59}
10U_0402_6.3V6-M
1U_0201_6.3V6-K

1 H20
VCCSA_SENSE VCCSA_VCC_SEN {59}

1U_0402_10V6K

CC86
1@ 1 +VCCST_CPU RC1604 1 2 0_0402_5%
CC1229

CC1228

1
1 OF 20

CC87
@ SKYLAKE-U_BGA1356
2 REV =1 ?
2 2 @
2 +VCCSA

Reserved for VCCST/VCCSTG/VCCPLL power optimized

+VCCSFR_OC

VCCSA_VCC_SEN RC101 1 2 100_0402_1%

+VCCPLL_CPU
RC104 1 2 0_0402_5%
VCCSA_VSS_SEN
1U_0201_6.3V6-M

RC102 1 2 100_0402_1%
1 120mA
CC85

C +VCCST_CPU RC105 1 2 0_0402_5% C

1U_0402_10V6K
0.1U_0402_10V7K
+1.0VALW +VCCST_CPU
2 1 1

CC1249

CC84
@

RC1605 1 2 0_0402_5%
2 2
Reserved for VCCST/VCCSTG/VCCPLL power optimized

+1.0VALW +VCCST_CPU_R +VCCST_CPU

+1.0VALW +VCCIO_R +VCCIO
need to open UC7 @
JC2 @ 2 6 RC1592 1 2 0_0402_5%
1 2 VIN VOUT
UC8 1 2 EC_VCCST_EN 1 3
EN VBIAS +5VALW

1U_0402_10V6K
2 6
VIN VOUT JUMP_43X79
5 4 1
VCCIO_EN DC3 GATE GND

CC1246
1 3 +5VALW RC1590
EN VBIAS

1U_0402_10V6K
1 2 2 1 M5938CTB1U_SOT23-6
5 4 1 40.2K_0402_1% 2 @
DC2 GATE GND 2

CC1248
RC1591 @ SDM10U45LP-7_DFN1006-2-2
1 2 2 1 M5938CTB1U_SOT23-6 @ CC1245
40.2K_0402_1% 2 @ 0.01U_0402_25V7K @
SDM10U45LP-7_DFN1006-2-2 2 1
@ @
@ CC1247
0.01U_0402_25V7K @
1
@
Reserved for +VCCST_CPU switch

Reserved for +VCCIO switch +1.0VALW +VCCST_CPU

QC19
AO3402_SOT-23-3
B B

+1.0VALW AON7408L_DFN8-5 +VCCIO 1 3

D S
QC11

10U_0603_6.3V6M

10U_0603_6.3V6M
CC79

1
G
1 1

CC80
1 @ RC135

2
5 S1 2 470_0603_5%
D S2
22U_0603_6.3V6-M

10U_0603_6.3V6M

3
S3 2 2
10U_0603_6.3V6M

22U_0603_6.3V6-M

@ 1 1 @

2
G
CC72
CC71

1 1

1
CC1250

C1102
4

RC124
2 2 @ 470_0603_5%

1
2 2 D
@ +20VSB VCCST_EN# 2 QC14

2
G 2N7002KW_SOT323-3
+3VALW
+20VSB 1 2 RC142 S

3
100K_0402_5% @

1
+3VALW

0.01U_0402_25V7K
D

100K_0402_5%
RC1621 2 1 100K_0402_5% VCCIO_EN# 2 QC13 1

CC81

RC1584
G 2N7002KW_SOT323-3 D
VCCST_EN#
0.01U_0402_25V7K

RC1411 2 2 QC16A
1

1 S 47K_0402_5% G 2N7002KDWH_SOT363-6
3
6

2
CC77

D RC125 @

1
RC128 1 2VCCIO_EN# 2 QC12A 470K_0402_5% S

1
47K_0402_5% G 2N7002KDWH_SOT363-6
2

@ 2
2

3
RC1575 S D
1

47K_0402_5% EC_VCCST_EN 5 QC16B

{44} EC_VCCST_EN G 2N7002KDWH_SOT363-6
1

4
+VCCST_CPU switch
3

D
RC1577 1 @ 2 0_0402_5% VCCIO_EN 5 QC12B
{44} EC_VCCIO_EN G
A 2N7002KDWH_SOT363-6 A
DC1 1 2 @
{11,44} PM_SLP_S3# S
4

RB751V-40_SOD323-2

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (CPU PWR2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1
Date: Monday, July 27, 2015 Sheet 13 of 60
5 4 3 2 1
 5 4 3 2 1

+VCCPGPPG

+1.0VALW RC1503 1 @ 2 0_0603_5% +VCCAMPHY

RC1622 1 @ 2 0_0402_5%
+3VALW_PCH
+1.0VALW 1
BLM15GG471SN1D 2 RC1504 +VCCAPLL_1P0
EMC@ +VCCPGPPG_SDIO RC1623 1 2 0_0402_5%
D +VCCHDA D
@
+3VS RC1585 1 2 0_0402_5% @

+3VALW_PCH RC1586 1 2 BLM15GG471SN1D

EMC@

RC1620 1 2 0_0402_5% VCCMPHYON_1P0_L1

+1.0VALW

1U_0402_10V6K
@
1

CC144
2

+3VALW_PCH

0.696A
+1.0VALW

1U_0402_10V6K
Near AB19
1

CC141
@ @ @ @ @

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K
22mA 2.574A +VCCPGPPG
+1.0VALW +1.0VALW ? 1 1 1 1 1

CC156

CC164

CC172

CC173

CC174
1U_0402_10V6K
22U_0603_6.3V6-M
1 1 2 SKL_ULT

CC158
UC1O

CC153
CPU POWER 4 OF 4 2 2 2 2 2
+VCCDSW_1P0 2 2 AB19

1U_0402_10V6K

1U_0402_10V6K
@
AB20 VCCPRIM_1P0_AB19 AK15 20mA
1 VCCPRIM_1P0_AB20 VCCPGPPA
Near Y15 1 +3VALW_PCH
P18 AG15 4mA

CC145

CC175

1U_0402_10V6K
@
1.5A VCCPRIM_1P0_P18 VCCPGPPB Y16 6mA
+1.0VALW Near AF18 VCCPGPPC 1
AF18 Y15 8mA

CC176
@ VCCPRIM_CORE_AF18 VCCPGPPD
2 AF19 T16 6mA 2
VCCPRIM_CORE_AF19 VCCPGPPE 161mA +1.8VALW
V20 AF16
47U_0805_4V6-M

1U_0402_10V6K
1U_0201_6.3V6-M

C C
VCCPRIM_CORE_V20 VCCPGPPF 61mA +1.8VALW 2
1 1 PCH Internal VRM V21 AD15 1
VCCPRIM_CORE_V21 VCCPGPPG
CC148

CC147

CC142
@ +3VALW_PCH
Near N15 AL1 V19

1U_0402_10V6K
.1U_0402_10V6-K
DCPDSW_1P0 VCCPRIM_3P3_V19
2 2 2 1 1
K17 T1

CC143
+1.0VALW CC149
88mA VCCMPHYON_1P0_L1 L1 VCCMPHYAON_1P0_K17 VCCPRIM_1P0_T1
+VCCAMPHY VCCMPHYAON_1P0_L1 6mA
AA1
N15 VCCATS_1P8 2 2
1U_0402_10V6K
22U_0603_6.3V6-M

@ N16 VCCMPHYGT_1P0_N15 AK17 1mA

1 1 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3
C1096

N17
CC151

P15 VCCMPHYGT_1P0_N17 AK19 1mA

VCCMPHYGT_1P0_P15 VCCRTC_AK19 VCCRTC
P16 BB14

1U_0402_10V6K
Near K15

.1U_0402_10V6-K
2 2 VCCMPHYGT_1P0_P16 VCCRTC_BB14
1 1
K15 BB10 VCCRTCEXT

CC1242
CC146
L15 VCCAMPHYPLL_1P0_K15 DCPRTC

0.1U_0402_10V7K
VCCAMPHYPLL_1P0_L15 A14 35mA
22mA VCCCLK1 +1.0VALW 2 2
V15
1U_0402_10V6K

+VCCAPLL_1P0 VCCAPLL_1P0 1
29mA

CC55
K19 0_0603_5%1 2 RC1587 +1.0VALW

1U_0402_10V6K
.1U_0402_10V6-K

1 VCCCLK2
AB17
CC154

1 +1.0VALW VCCPRIM_1P0_AB17 1
C1097

Y18 L21 24mA

CC56

22U_0603_6.3V6-M
VCCPRIM_1P0_Y18 VCCCLK3 +1.0VALW 2
@
.1U_0402_10V6-K

2 +VCCHDA 1

C1098
0.118A AD17 N20 33mA
2 1 +3VALW VCCDSW_3P3_AD17 VCCCLK4 +VCCCLK4 2
AD18
CC165

AJ17 VCCDSW_3P3_AD18 L19 4mA

VCCDSW_3P3_AJ17 VCCCLK5 +VCCCLK5 2
2 68mA AJ19 A10 10mA
VCCHDA VCCCLK6 +1.0VALW

1U_0402_10V6K
11mA AJ16 AN11 1 TC179 @ PAD
+3VALW_PCH VCCSPI GPP_B0/CORE_VID0 1

CC57
AN13 1 TC180 @ PAD
0.642A AF20 GPP_B1/CORE_VID1
+1.0VALW VCCSRAM_1P0_AF20
AF21
1U_0402_10V6K

1 VCCSRAM_1P0_AF21 2
T19
CC159

Near AF20 VCCSRAM_1P0_T19

T20
VCCSRAM_1P0_T20
2 75mA AJ21
+3VALW_PCH VCCPRIM_3P3_AJ21
1U_0402_10V6K

1
AK20
CC171

+1.0VALW VCCPRIM_1P0_AK20
N18 +VCCCLK4 0_0603_5%1 2 RC1588 +1.0VALW
B 2 VCCAPLLEBB B
1U_0402_10V6K

1
CC169

22U_0603_6.3V6-M
1 OF 20 @
SKYLAKE-U_BGA1356 1

C1099
2 REV = 1 ?
@
2
33mA
+1.0VALW
Near A18

+VCCCLK5 0_0603_5%1 2 RC1589 +1.0VALW

22U_0603_6.3V6-M
@ 1

C1100
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (PCH PWR)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

WWW.AliSaler.Com
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 14 of 60
5 4 3 2 1
 5 4 3 2 1

SKL_ULT
UC1Q ?
SKL_ULT
UC1P ?
SKL_ULT ?
GND 2 OF 3 UC1R
GND 1 OF 3
AT63 BA49 GND 3 OF 3
A5 AL65 AT68 VSS_AT63 VSS_BA49 BA53 F8 L18
A67 VSS_A5 VSS_AL65 AL66 AT71 VSS_AT68 VSS_BA53 BA57 G10 VSS_F8 VSS_L18 L2
A70 VSS_A67 VSS_AL66 AM13 AU10 VSS_AT71 VSS_BA57 BA6 G22 VSS_G10 VSS_L2 L20
D AA2 VSS_A70 VSS_AM13 AM21 AU15 VSS_AU10 VSS_BA6 BA62 G43 VSS_G22 VSS_L20 L4 D
AA4 VSS_AA2 VSS_AM21 AM25 AU20 VSS_AU15 VSS_BA62 BA66 G45 VSS_G43 VSS_L4 L8
AA65 VSS_AA4 VSS_AM25 AM27 AU32 VSS_AU20 VSS_BA66 BA71 G48 VSS_G45 VSS_L8 N10
AA68 VSS_AA65 VSS_AM27 AM43 AU38 VSS_AU32 VSS_BA71 BB18 G5 VSS_G48 VSS_N10 N13
AB15 VSS_AA68 VSS_AM43 AM45 AV1 VSS_AU38 VSS_BB18 BB26 G52 VSS_G5 VSS_N13 N19
AB16 VSS_AB15 VSS_AM45 AM46 AV68 VSS_AV1 VSS_BB26 BB30 G55 VSS_G52 VSS_N19 N21
AB18 VSS_AB16 VSS_AM46 AM55 AV69 VSS_AV68 VSS_BB30 BB34 G58 VSS_G55 VSS_N21 N6
AB21 VSS_AB18 VSS_AM55 AM60 AV70 VSS_AV69 VSS_BB34 BB38 G6 VSS_G58 VSS_N6 N65
AB8 VSS_AB21 VSS_AM60 AM61 AV71 VSS_AV70 VSS_BB38 BB43 G60 VSS_G6 VSS_N65 N68
AD13 VSS_AB8 VSS_AM61 AM68 AW10 VSS_AV71 VSS_BB43 BB55 G63 VSS_G60 VSS_N68 P17
AD16 VSS_AD13 VSS_AM68 AM71 AW12 VSS_AW10 VSS_BB55 BB6 G66 VSS_G63 VSS_P17 P19
AD19 VSS_AD16 VSS_AM71 AM8 AW14 VSS_AW12 VSS_BB6 BB60 H15 VSS_G66 VSS_P19 P20
AD20 VSS_AD19 VSS_AM8 AN20 AW16 VSS_AW14 VSS_BB60 BB64 H18 VSS_H15 VSS_P20 P21
AD21 VSS_AD20 VSS_AN20 AN23 AW18 VSS_AW16 VSS_BB64 BB67 H71 VSS_H18 VSS_P21 R13
AD62 VSS_AD21 VSS_AN23 AN28 AW21 VSS_AW18 VSS_BB67 BB70 J11 VSS_H71 VSS_R13 R6
AD8 VSS_AD62 VSS_AN28 AN30 AW23 VSS_AW21 VSS_BB70 C1 J13 VSS_J11 VSS_R6 T15
AE64 VSS_AD8 VSS_AN30 AN32 AW26 VSS_AW23 VSS_C1 C25 J25 VSS_J13 VSS_T15 T17
AE65 VSS_AE64 VSS_AN32 AN33 AW28 VSS_AW26 VSS_C25 C5 J28 VSS_J25 VSS_T17 T18
AE66 VSS_AE65 VSS_AN33 AN35 AW30 VSS_AW28 VSS_C5 D10 J32 VSS_J28 VSS_T18 T2
AE67 VSS_AE66 VSS_AN35 AN37 AW32 VSS_AW30 VSS_D10 D11 J35 VSS_J32 VSS_T2 T21
AE68 VSS_AE67 VSS_AN37 AN38 AW34 VSS_AW32 VSS_D11 D14 J38 VSS_J35 VSS_T21 T4
AE69 VSS_AE68 VSS_AN38 AN40 AW36 VSS_AW34 VSS_D14 D18 J42 VSS_J38 VSS_T4 U10
AF1 VSS_AE69 VSS_AN40 AN42 AW38 VSS_AW36 VSS_D18 D22 J8 VSS_J42 VSS_U10 U63
AF10 VSS_AF1 VSS_AN42 AN58 AW41 VSS_AW38 VSS_D22 D25 K16 VSS_J8 VSS_U63 U64
AF15 VSS_AF10 VSS_AN58 AN63 AW43 VSS_AW41 VSS_D25 D26 K18 VSS_K16 VSS_U64 U66
AF17 VSS_AF15 VSS_AN63 AP10 AW45 VSS_AW43 VSS_D26 D30 K22 VSS_K18 VSS_U66 U67
AF2 VSS_AF17 VSS_AP10 AP18 AW47 VSS_AW45 VSS_D30 D34 K61 VSS_K22 VSS_U67 U69
AF4 VSS_AF2 VSS_AP18 AP20 AW49 VSS_AW47 VSS_D34 D39 K63 VSS_K61 VSS_U69 U70
AF63 VSS_AF4 VSS_AP20 AP23 AW51 VSS_AW49 VSS_D39 D44 K64 VSS_K63 VSS_U70 V16
AG16 VSS_AF63 VSS_AP23 AP28 AW53 VSS_AW51 VSS_D44 D45 K65 VSS_K64 VSS_V16 V17
AG17 VSS_AG16 VSS_AP28 AP32 AW55 VSS_AW53 VSS_D45 D47 K66 VSS_K65 VSS_V17 V18
AG18 VSS_AG17 VSS_AP32 AP35 AW57 VSS_AW55 VSS_D47 D48 K67 VSS_K66 VSS_V18 W13
C AG19 VSS_AG18 VSS_AP35 AP38 AW6 VSS_AW57 VSS_D48 D53 K68 VSS_K67 VSS_W13 W6 C
AG20 VSS_AG19 VSS_AP38 AP42 AW60 VSS_AW6 VSS_D53 D58 K70 VSS_K68 VSS_W6 W9
AG21 VSS_AG20 VSS_AP42 AP58 AW62 VSS_AW60 VSS_D58 D6 K71 VSS_K70 VSS_W9 Y17
AG71 VSS_AG21 VSS_AP58 AP63 AW64 VSS_AW62 VSS_D6 D62 L11 VSS_K71 VSS_Y17 Y19
AH13 VSS_AG71 VSS_AP63 AP68 AW66 VSS_AW64 VSS_D62 D66 L16 VSS_L11 VSS_Y19 Y20
AH6 VSS_AH13 VSS_AP68 AP70 AW8 VSS_AW66 VSS_D66 D69 L17 VSS_L16 VSS_Y20 Y21
AH63 VSS_AH6 VSS_AP70 AR11 AY66 VSS_AW8 VSS_D69 E11 VSS_L17 VSS_Y21
AH64 VSS_AH63 VSS_AR11 AR15 B10 VSS_AY66 VSS_E11 E15
AH67 VSS_AH64 VSS_AR15 AR16 B14 VSS_B10 VSS_E15 E18
AJ15 VSS_AH67 VSS_AR16 AR20 B18 VSS_B14 VSS_E18 E21
AJ18 VSS_AJ15 VSS_AR20 AR23 B22 VSS_B18 VSS_E21 E46 1 OF 20
VSS_AJ18 VSS_AR23 VSS_B22 VSS_E46 SKYLAKE-U_BGA1356
AJ20 AR28 B30 E50 REV = 1 ?
AJ4 VSS_AJ20 VSS_AR28 AR35 B34 VSS_B30 VSS_E50 E53
AK11 VSS_AJ4 VSS_AR35 AR42 B39 VSS_B34 VSS_E53 E56 @
AK16 VSS_AK11 VSS_AR42 AR43 B44 VSS_B39 VSS_E56 E6
AK18 VSS_AK16 VSS_AR43 AR45 B48 VSS_B44 VSS_E6 E65
AK21 VSS_AK18 VSS_AR45 AR46 B53 VSS_B48 VSS_E65 E71
AK22 VSS_AK21 VSS_AR46 AR48 B58 VSS_B53 VSS_E71 F1
AK27 VSS_AK22 VSS_AR48 AR5 B62 VSS_B58 VSS_F1 F13
AK63 VSS_AK27 VSS_AR5 AR50 B66 VSS_B62 VSS_F13 F2
AK68 VSS_AK63 VSS_AR50 AR52 B71 VSS_B66 VSS_F2 F22
AK69 VSS_AK68 VSS_AR52 AR53 BA1 VSS_B71 VSS_F22 F23
AK8 VSS_AK69 VSS_AR53 AR55 BA10 VSS_BA1 VSS_F23 F27
AL2 VSS_AK8 VSS_AR55 AR58 BA14 VSS_BA10 VSS_F27 F28
AL28 VSS_AL2 VSS_AR58 AR63 BA18 VSS_BA14 VSS_F28 F32
AL32 VSS_AL28 VSS_AR63 AR8 BA2 VSS_BA18 VSS_F32 F33
AL35 VSS_AL32 VSS_AR8 AT2 BA23 VSS_BA2 VSS_F33 F35
AL38 VSS_AL35 VSS_AT2 AT20 BA28 VSS_BA23 VSS_F35 F37
AL4 VSS_AL38 VSS_AT20 AT23 BA32 VSS_BA28 VSS_F37 F38
AL45 VSS_AL4 VSS_AT23 AT28 BA36 VSS_BA32 VSS_F38 F4
AL48 VSS_AL45 VSS_AT28 AT35 F68 VSS_BA36 VSS_F4 F40
AL52 VSS_AL48 VSS_AT35 AT4 BA45 VSS_F68 VSS_F40 F42
B AL55 VSS_AL52 VSS_AT4 AT42 VSS_BA45 VSS_F42 BA41 B
AL58 VSS_AL55 VSS_AT42 AT56 VSS_BA41
AL64 VSS_AL58 VSS_AT56 AT58
VSS_AL64 VSS_AT58
1 OF 20

1 OF 20 SKYLAKE-U_BGA1356
SKYLAKE-U_BGA1356 REV = 1 ?
REV = 1 ?
@
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (VSS)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 15 of 60
5 4 3 2 1
 5 4 3 2 1

?
SKL_ULT
UC1S

RESERVED SIGNALS-1

CPU_CFG0 E68 BB68 1 TC173 @ PAD

D PAD @ TC142 1 CPU_CFG1 B67 CFG[0] RSVD_TP_BB68 BB69 1 TC174 @ PAD D
PAD @ TC143 1 CPU_CFG2 D65 CFG[1] RSVD_TP_BB69
PAD @ TC144 1 XDP_CPU_CFG3 D67 CFG[2] AK13 1 TC175 @ PAD
CFG[3] RSVD_TP_AK13
2

CPU_CFG4 E70 AK12 1 TC176 @ PAD

RC1618 PAD @ TC146 1 CPU_CFG5 C68 CFG[4] RSVD_TP_AK12 +VCCST_CPU
1K_0402_5% PAD @ TC147 1 CPU_CFG6 D68 CFG[5] BB2 1 TC196 @ PAD UC1T SKL_ULT ?
PAD @ TC148 1 CPU_CFG7 C67 CFG[6] RSVD_BB2 BA3 1 TC200 @ PAD
CFG[7] RSVD_BA3

2
PAD @ TC153 1 CPU_CFG8 F71 SPARE
1

RC106 CPU_CFG9 G69 CFG[8] +1.8VALW

@ CFG[9]

1
1K_0402_5% PAD @ TC151 1 CPU_CFG10 F70 AU5 AW69 F6
PAD @ TC152 1 CPU_CFG11 G68 CFG[10] TP5 AT5 AW68 RSVD_AW69 RSVD_F6 E3 RC1619
CPU_CFG12 H70 CFG[11] TP6 AU56 RSVD_AW68 RSVD_E3 C11 150_0402_5%
1

PAD @ TC154 1 CPU_CFG13 G71 CFG[12] AW48 RSVD_AU56 RSVD_C11 B11 @

CPU_CFG14 H69 CFG[13] D5 Cannonlake@ C7 RSVD_AW48 RSVD_B11 A11

2
PAD @ TC156 1 CPU_CFG15 G70 CFG[14] RSVD_D5 D4 RC1582 2 1 0_0402_5% RSVD_U12 U12 RSVD_C7 RSVD_A11 D12
CFG[15] RSVD_D4 B2 1 TC183 @ PAD RC1583 2 1 0_0402_5% RSVD_U11 U11 RSVD_U12 RSVD_D12 C12
PAD @ TC159 1 CPU_CFG16 E63 RSVD_B2 C2 1 TC185 @ PAD Cannonlake@ H11 RSVD_U11 RSVD_C12 F52 RSVD_F52
PAD @ TC158 1 CPU_CFG17 F63 CFG[16] RSVD_C2 RSVD_H11 RSVD_F52
CFG[17] B3 1 TC184 @ PAD
PAD @ TC161 1 CPU_CFG18 E66 RSVD_B3 A3 1 TC181 @ PAD
CFG[18] RSVD_A3 1 OF 20
PAD @ TC160 1 CPU_CFG19 F66
CFG[19] SKYLAKE-U_BGA1356
AW1 1 TC194 @ PAD REV = 1 ?
C CFG_RCOMP E60 RSVD_AW1 C
CFG_RCOMP @
E1 1 TC187 @ PAD
PAD @ TC166 1 XDP_ITP_PMODE E8 RSVD_E1 E2
ITP_PMODE RSVD_E2
2

RC162 PAD @ TC201 1 AY2 BA4

PAD @ TC195 1 AY1 RSVD_AY2 RSVD_BA4 BB4 1 TC198 @ PAD
49.9_0402_1% RSVD_AY1 RSVD_BB4
PAD @ TC186 1 D1 A4 1 TC182 @ PAD
1

D3 RSVD_D1 RSVD_A4 C4
RSVD_D3 RSVD_C4
K46 BB5 1 TC199 @ PAD
K45 RSVD_K46 TP4
RSVD_K45 A69 1 TC188 @ PAD
AL25 RSVD_A69 B69 1 TC193 @ PAD
AL27 RSVD_AL25 RSVD_B69 need to check with Intel
RSVD_AL27 AY3 RSVD_AY3
PAD @ TC189 1 C71 RSVD_AY3
RSVD_C71

2
PAD @ TC191 1 B70 D71 1 TC190 @ PAD
RSVD_B70 RSVD_D71 C70 1 TC192 @ PAD RC107
F60 RSVD_C70
RSVD_F60 0_0402_5%
C54
A52 RSVD_C54 D54

1
B RSVD_A52 RSVD_D54 B
PAD @ TC171 1 BA70 AY4
PAD @ TC172 1 BA68 RSVD_TP_BA70 TP1 BB3 1 TC197 @ PAD
RSVD_TP_BA68 TP2 need to check with Intel
J71 AY71 VSS_AY71
J68 RSVD_J71 VSS_AY71 AR56 ZVM#
RSVD_J68 ZVM# ZVM# {57}

2
PAD @ TC169 1 F65 AW71 1 TC177 @ PAD
PAD @ TC170 1 G65 VSS_F65 RSVD_TP_AW71 AW70 1 TC178 @ PAD RC108
VSS_G65 RSVD_TP_AW70
0_0402_5%
F61 AP56 1 TC168 @ PAD
E61 RSVD_F61 MSM# C64 PROC_SELECT# 1 2 +VCCST_CPU

1
RSVD_E61 PROC_SELECT# R22 100K_0402_5%
Cannonlake@
1 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
@
Default
Pin Name Strap Description Configuration Value

A A
CFG[4] Display Port — 1 = eDP Disabled 1
Presence strap — 0 = eDP Enabled * Security Classification LC Future Center Secret Data Title
Issued Date 2014/12/11 Deciphered Date 2015/12/11 MCP (CFG,RESERVED)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 16 of 60
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

Swap Table
Pin Pin
DDR_SA_VREFDQ {5} DDR3 SO-DIMM A DDRA_DQ[0..63] {5}
Number Pin Name Net Name Number Pin Name Net Name
DDRA_DQS[0..7] {5}
5 DQ0 DDRA_DQ1 5 DQ32 DDRA_DQ33
+1.35V 7 DQ1 DDRA_DQ5 7 DQ33 DDRA_DQ36
DDRA_DQS#[0..7] {5}
+1.35V +1.35V 15 DQ2 DDRA_DQ6 15 DQ34 DDRA_DQ39
DDRA_MA[0..15] {5} 17 DQ3 DDRA_DQ7 17 DQ35 DDRA_DQ38

1
RD5 4 DQ4 DDRA_DQ0 4 DQ36 DDRA_DQ37
1.82K_0402_1% 3A@1.5V 6 DQ5 DDRA_DQ4 6 DQ37 DDRA_DQ32
RD6 For RF 16 DQ6 DDRA_DQ2 16 DQ38 DDRA_DQ34
JDDR1 18 DQ7 DDRA_DQ3 18 DQ39 DDRA_DQ35
2

1 2 +VREF_DQ_DIMMA 1 2
D VREF_DQ VSS_2 DDRA_DQ0
10 DQS#0 DDRA_DQS#0 10 DQS#4 DDRA_DQS#4 D
2_0402_5% 3 4
VSS_1 DQ4 12 DQS0 DDRA_DQS0 12 DQS4 DDRA_DQS4
1
0.022U_0402_16V7-K

1.82K_0402_1%

2.2U_0603_6.3V6K

.1U_0402_10V6-K
DDRA_DQ1 DDRA_DQ4

47P_0402_50V8J

47P_0402_50V8J

47P_0402_50V8J
5 6
DDRA_DQ5 7 DQ0 DQ5 8
1 1 DQ1 VSS_4 1 1 1
RD7

DDRA_DQS#0

CD5

CD6

CD7
1 CD4 CD2 9 10 21 DQ8 DDRA_DQ12 21 DQ40 DDRA_DQ44
VSS_3 DQS0#
CD3

11 12 DDRA_DQS0 23 DQ9 DDRA_DQ9 23 DQ41 DDRA_DQ41

13 DM0 DQS0 14 33 DQ10 DDRA_DQ14 33 DQ42 DDRA_DQ46
2

CD@2 2 DDRA_DQ6 15 VSS_5 VSS_6 16 DDRA_DQ2 2 2 2

2 DDRA_DQ7 17 DQ2 DQ6 18 DDRA_DQ3 35 DQ11 DDRA_DQ10 35 DQ43 DDRA_DQ47
19 DQ3 DQ7 20 22 DQ12 DDRA_DQ13 22 DQ44 DDRA_DQ45
DDRA_DQ12 21 VSS_7 VSS_8 22 DDRA_DQ13 24 DQ13 DDRA_DQ8 24 DQ45 DDRA_DQ40
DQ8 DQ12
1

DDRA_DQ9 23 24 DDRA_DQ8 34 DQ14 DDRA_DQ11 34 DQ46 DDRA_DQ43

RD8 25 DQ9 DQ13 26
VSS_9 VSS_10 36 DQ15 DDRA_DQ15 36 DQ47 DDRA_DQ42
24.9_0402_1% DDRA_DQS#1 27 28
DDRA_DQS1 DQS1# DM1 CPU_DRAMRST#
27 DQS#1 DDRA_DQS#1 27 DQS#5 DDRA_DQS#5
29 30
31 DQS1 RESET# 32
CPU_DRAMRST# {6,18} 29 DQS1 DDRA_DQS1 29 DQS5 DDRA_DQS5
2

VSS_11 VSS_12

.1U_0402_10V6-K
DDRA_DQ14 33 34 DDRA_DQ11
DDRA_DQ10 35 DQ10 DQ14 36 DDRA_DQ15
DQ11 DQ15
39 DQ16 DDRA_DQ20 39 DQ48 DDRA_DQ48
37 38 @ 1 41 DQ17 DDRA_DQ21 41 DQ49 DDRA_DQ53
VSS_13 VSS_14

CD70
DDRA_DQ20 39 40 DDRA_DQ17 Layout Note:
DDRA_DQ21 41 DQ16 DQ20 42 DDRA_DQ16 51 DQ18 DDRA_DQ18 51 DQ50 DDRA_DQ55
43 DQ17 DQ21 44 Place near DIMM (10uF_0603_6.3V)*8 53 DQ19 DDRA_DQ23 53 DQ51 DDRA_DQ54
DDRA_DQS#2 45 VSS_15 VSS_16 46 2 40 DQ20 DDRA_DQ17 40 DQ52 DDRA_DQ52
DDRA_DQS2 47 DQS2# DM2 48 (1U_0402_6.3V)*8 42 DQ21 DDRA_DQ16 42 DQ53 DDRA_DQ49
49 DQS2 VSS_18 50 DDRA_DQ22 50 DQ22 DDRA_DQ22 50 DQ54 DDRA_DQ51
DDRA_DQ18 51 VSS_17 DQ22 52 DDRA_DQ19
DQ18 DQ23 52 DQ23 DDRA_DQ19 52 DQ55 DDRA_DQ50
DDRA_DQ23 53 54
DQ19 VSS_20 DDRA_DQ24
45 DQS#2 DDRA_DQS#2 45 DQS#6 DDRA_DQS#6
55 56
DDRA_DQ29 57 VSS_19 DQ28 58 DDRA_DQ28 +1.35V
47 DQS2 DDRA_DQS2 47 DQS6 DDRA_DQS6
DDRA_DQ25 59 DQ24 DQ29 60
61 DQ25 VSS_22 62 DDRA_DQS#3
VSS_21 DQS3#
57 DQ24 DDRA_DQ29 57 DQ56 DDRA_DQ61

CD8

CD9

CD10

CD11

CD12

CD13

CD14

CD15
63 64 DDRA_DQS3 59 DQ25 DDRA_DQ25 59 DQ57 DDRA_DQ60
65 DM3 DQS3 66
VSS_23 VSS_24 67 DQ26 DDRA_DQ26 67 DQ58 DDRA_DQ59

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
C DDRA_DQ26 67 68 DDRA_DQ31 C
DDRA_DQ30 69 DQ26 DQ30 70 DDRA_DQ27 69 DQ27 DDRA_DQ30 69 DQ59 DDRA_DQ63
DQ27 DQ31 1 1 1 1 1 1 1 1 56 DQ28 DDRA_DQ24 56 DQ60 DDRA_DQ56
71 72
VSS_25 VSS_26 58 DQ29 DDRA_DQ28 58 DQ61 DDRA_DQ57
68 DQ30 DDRA_DQ31 68 DQ62 DDRA_DQ62
DDRA_CKE0 73 74 DDRA_CKE1 2 2 2 2 2 2 2 2
{5} DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 {5} 70 DQ31 DDRA_DQ27 70 DQ63 DDRA_DQ58
75 76 62 DQS#3 DDRA_DQS#3 62 DQS#7 DDRA_DQS#7
77 VDD_1 VDD_2 78 DDRA_MA15
DDRA_BS2# 79 NC_1 A15 80 DDRA_MA14 64 DQS3 DDRA_DQS3 64 DQS7 DDRA_DQS7
{5} DDRA_BS2# BA2 A14
81 82 CD@ CD@
DDRA_MA12 83 VDD_3 VDD_4 84 DDRA_MA11
DDRA_MA9 85 A12/BC# A11 86 DDRA_MA7
87 A9 A7 88
DDRA_MA8 89 VDD_5 VDD_6 90 DDRA_MA6
DDRA_MA5 91 A8 A6 92 DDRA_MA4
93 A5 A4 94
VDD_7 VDD_8

CD16

CD17

CD18

CD19

CD56

CD57

CD58

CD59
DDRA_MA3 95 96 DDRA_MA2
DDRA_MA1 97 A3 A2 98 DDRA_MA0
A1 A0

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
99 100
DDRA_CLK0 101 VDD_9 VDD_10 102 DDRA_CLK1
{5} DDRA_CLK0 CK0 CK1 DDRA_CLK1 {5} 1 1 1 1 1 1 1 1
DDRA_CLK0# 103 104 DDRA_CLK1#
{5} DDRA_CLK0# CK0# CK1# DDRA_CLK1# {5}
105 106
DDRA_MA10 107 VDD_11 VDD_12 108 DDRA_BS1#
DDRA_BS0# A10/AP BA1 DDRA_RAS# DDRA_BS1# {5} 2 2 2 2 2 2 2 2
{5} DDRA_BS0# 109 110
BA0 RAS# DDRA_RAS# {5}
111 112
DDRA_WE# 113 VDD_13 VDD_14 114 DDRA_CS0#
{5} DDRA_WE# WE# S0# DDRA_CS0# {5}
DDRA_CAS# 115 116 DDRA_ODT0
{5} DDRA_CAS# CAS# ODT0 DDRA_ODT0 {5}
117 118 CD@
DDRA_MA13 119 VDD_15 VDD_16 120 DDRA_ODT1 CD@ CD@ CD@
DDRA_CS1# A13 ODT1 DDRA_ODT1 {5}
{5} DDRA_CS1# 121 122
123 S1# NC_2 124
125 VDD_17 VDD_18 126 +VREF_CA_DIMMA RD22 1 @ 2 0_0402_5% +VREF_CA
B 127 TEST VREF_CA 128 B
VSS_27 VSS_28
.1U_0402_10V6-K

DDRA_DQ33 129 130 DDRA_DQ37

DDRA_DQ36 131 DQ32 DQ36 132 DDRA_DQ32
DQ33 DQ37 1 1
CD22

133 134 CD23

DDRA_DQS#4 135 VSS_29 VSS_30 136 2.2U_0603_6.3V6K
DDRA_DQS4 137 DQS4# DM4 138
139 DQS4 VSS_32 140 DDRA_DQ34 2 2
DDRA_DQ39 141 VSS_31 DQ38 142 DDRA_DQ35
DDRA_DQ38 143 DQ34 DQ39 144
145 DQ35 VSS_34 146 DDRA_DQ45
DDRA_DQ44 147 VSS_33 DQ44 148 DDRA_DQ40
DDRA_DQ41 DQ40 DQ45 Layout Note: (10U_0603_6.3V)*2
149 150
151 DQ41 VSS_35 152 DDRA_DQS#5 Place near DIMM
153 VSS_36 DQS5# 154 DDRA_DQS5 (.1U_0402_10V)*4
155 DM5 DQS5 156
DDRA_DQ46 157 VSS_37 VSS_38 158 DDRA_DQ43 +1.35V
DDRA_DQ47 159 DQ42 DQ46 160 DDRA_DQ42
161 DQ43 DQ47 162
Note:
VSS_39 VSS_40 VREF trace width:20 mils at least

1
DDRA_DQ48 163 164 DDRA_DQ52 +0.675VS
DDRA_DQ53 165 DQ48 DQ52 166 DDRA_DQ49 RD9 Spacing:20mils to other signal/planes
167 DQ49 DQ53 168
VSS_41 VSS_42 Trace  width:20  mils 1.82K_0402_1% Place near DIMM scoket
CD24

CD25

CD26

CD27

CD64

CD65
DDRA_DQS#6 169 170
DDRA_DQS6 171 DQS6# DM6 172
Space:20mils 

2
DQS6 VSS_44
.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

10U_0603_6.3V6M

10U_0603_6.3V6M
173 174 DDRA_DQ51
DDRA_DQ55 175 VSS_43 DQ54 176 DDRA_DQ50 +VREF_CA RD10 1 2 2_0402_5%
DQ50 DQ55 1 1 1 1 1 1 {18} +VREF_CA DDR_SM_VREFCA {5}
DDRA_DQ54 177 178 1
179 DQ51 VSS_46 180 DDRA_DQ56 CD21
VSS_45 DQ60

1
DDRA_DQ61 181 182 DDRA_DQ57 0.022U_0402_16V7-K
DDRA_DQ60 183 DQ56 DQ61 184 2 2 2 2 2 2 RD11
185 DQ57 VSS_48 186 DDRA_DQS#7 1.82K_0402_1% 2
VSS_47 DQS7#

1
187 188 DDRA_DQS7
189 DM7 DQS7 190 CD@ CD@ CD@

2
A DDRA_DQ59 191 VSS_49 VSS_50 192 DDRA_DQ62 RD12 A
DDRA_DQ63 193 DQ58 DQ62 194 DDRA_DQ58 24.9_0402_1%
195 DQ59 DQ63 196

2
1 @ 2 0_0402_5%197 VSS_51 VSS_52 198
RD13 199 SA0 EVENT# 200 SMB_DATA_S3
+3VS VDDSPD SDA SMB_CLK_S3 SMB_DATA_S3 {7,18,40}
201 202
SA1 SCL SMB_CLK_S3 {7,18,40}
1 1 203 204 +0.675VS
VTT_1 VTT_2
1

47P_0402_50V8J

@ LC Future Center Secret Data Title

CD28 CD29
0_0402_5%
205
GND1 GND2
206 1 0 . 6 5 A @ 0 . 7 5 V Security Classification
CD68

2.2U_0603_6.3V6K .1U_0402_10V6-K 207 208

@ 2 2 RD14 BOSS1 BOSS2 Issued Date 2014/12/11 Deciphered Date 2015/12/11 DDRIII SO-DIMM A
2

2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
LCN_DAN06-K4406-0103 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
ME@ For RF DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Friday, July 31, 2015 Sheet 17 of 60
5 4 3 2 1
 5 4 3 2 1

DDR_SB_VREFDQ {5}

+1.35V
DDR3 SO-DIMM B Swap Table
Pin
+1.35V +1.35V Pin Name Net Name
Number

1
DDRB_DQ[0..63] {6}
RD15 5 DQ0 DDRB_DQ12
1.82K_0402_1% 3A@1.5V 7 DQ1 DDRB_DQ8
DDRB_DQS[0..7] {6}
RD16 For RF 15 DQ2 DDRB_DQ10
JDDR2
DDRB_DQS#[0..7] {6} 17 DQ3 DDRB_DQ11

2
1 2 +VREF_DQ_DIMMB 1 2
2_0402_5% 3 VREF_DQ VSS1 4 DDRB_DQ9 4 DQ4 DDRB_DQ9
VSS2 DQ4 DDRB_MA[0..15] {6} 6 DQ5 DDRB_DQ13

1.82K_0402_1%

CD30

2.2U_0603_6.3V6K

CD31

.1U_0402_10V6-K
DDRB_DQ12 DDRB_DQ13

47P_0402_50V8J

47P_0402_50V8J

47P_0402_50V8J
5 6
DQ0 DQ5
1
0.022U_0402_16V7-K

1 1 DDRB_DQ8 7 8 1 1 1 16 DQ6 DDRB_DQ14

DQ1 VSS3

RD17
DDRB_DQS#1

CD33

CD34

CD35
D 9 10 D
VSS4 DQS#0 18 DQ7 DDRB_DQ15
11 12 DDRB_DQS1
1 DM0 DQS0 10 DQS#0 DDRB_DQS#1
CD32

13 14
2 2 DDRB_DQ10 15 VSS5 VSS6 16 DDRB_DQ14 2 2 2 12 DQS0 DDRB_DQS1
2

DDRB_DQ11 17 DQ2 DQ6 18 DDRB_DQ15

2 19 DQ3 DQ7 20
VSS7 VSS8
21 DQ8 DDRB_DQ4
CD@ DDRB_DQ4 21 22 DDRB_DQ1 23 DQ9 DDRB_DQ5
DDRB_DQ5 23 DQ8 DQ12 24 DDRB_DQ0
DQ9 DQ13 33 DQ10 DDRB_DQ7
1

25 26
RD18 DDRB_DQS#0 27 VSS9 VSS10 28 35 DQ11 DDRB_DQ3
24.9_0402_1% DDRB_DQS0 29 DQS#1 DM1 30 CPU_DRAMRST# 22 DQ12 DDRB_DQ1
DQS1 RESET# CPU_DRAMRST# {6,17} 24 DQ13 DDRB_DQ0
31 32
VSS11 VSS12

.1U_0402_10V6-K
DDRB_DQ7 33 34 DDRB_DQ6 34 DQ14 DDRB_DQ6
2

DDRB_DQ3 35 DQ10 DQ14 36 DDRB_DQ2

DQ11 DQ15 (10uF_0603_6.3V)*8 36 DQ15 DDRB_DQ2
37 38 @ 1 Layout Note: 27 DQS#1 DDRB_DQS#0
VSS13 VSS14

CD71
DDRB_DQ16 39 40 DDRB_DQ20
DDRB_DQ18 41 DQ16 DQ20 42 DDRB_DQ21 Place near DIMM (1U_0402_6.3V)*8 29 DQS1 DDRB_DQS0
43 DQ17 DQ21 44
DDRB_DQS#2 45 VSS15 VSS16 46 2
DQS#2 DM2
39 DQ16 DDRB_DQ16
DDRB_DQS2 47 48 41 DQ17 DDRB_DQ18
49 DQS2 VSS17 50 DDRB_DQ17
DDRB_DQ19 51 VSS18 DQ22 52 DDRB_DQ22 51 DQ18 DDRB_DQ19
DDRB_DQ23 53 DQ18 DQ23 54 53 DQ19 DDRB_DQ23
55 DQ19 VSS19 56 DDRB_DQ27 +1.35V 40 DQ20 DDRB_DQ20
DDRB_DQ29 57 VSS20 DQ28 58 DDRB_DQ28 42 DQ21 DDRB_DQ21
DDRB_DQ24 59 DQ24 DQ29 60 50 DQ22 DDRB_DQ17
DQ25 VSS21

CD36

CD37

CD38

CD39

CD40

CD41

CD42

CD43
61 62 DDRB_DQS#3 52 DQ23 DDRB_DQ22
63 VSS22 DQS#3 64 DDRB_DQS3
DM3 DQS3 45 DQS#2 DDRB_DQS#2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
65 66
DDRB_DQ31 67 VSS23 VSS24 68 DDRB_DQ25 47 DQS2 DDRB_DQS2
DQ26 DQ30 1 1 1 1 1 1 1 1
DDRB_DQ30 69 70 DDRB_DQ26
71 DQ27 DQ31 72
VSS25 VSS26
57 DQ24 DDRB_DQ29
C C
2 2 2 2 2 2 2 2 59 DQ25 DDRB_DQ24
67 DQ26 DDRB_DQ31
DDRB_CKE0 73 74 DDRB_CKE1 69 DQ27 DDRB_DQ30
{6} DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 {6} 56 DQ28 DDRB_DQ27
75 76
77 VDD1 VDD2 78 DDRB_MA15 CD@ CD@ 58 DQ29 DDRB_DQ28
DDRB_BS2# 79 NC1 A15 80 DDRB_MA14 68 DQ30 DDRB_DQ25
{6} DDRB_BS2# BA2 A14
81 82 70 DQ31 DDRB_DQ26
DDRB_MA12 83 VDD3 VDD4 84 DDRB_MA11
A12/BC# A11 62 DQS#3 DDRB_DQS#3

CD44

CD45

CD46

CD47

CD60

CD61

CD62

CD63
DDRB_MA9 85 86 DDRB_MA7
87 A9 A7 88
64 DQS3 DDRB_DQS3
VDD5 VDD6

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
DDRB_MA8 89 90 DDRB_MA6
DDRB_MA5 91 A8 A6 92 DDRB_MA4
A5 A4 1 1 1 1 1 1 1 1 129 DQ32 DDRB_DQ36
93 94 131 DQ33 DDRB_DQ37
DDRB_MA3 95 VDD7 VDD8 96 DDRB_MA2
DDRB_MA1 97 A3 A2 98 DDRB_MA0 141 DQ34 DDRB_DQ38
99 A1 A0 100 2 2 2 2 2 2 2 2 143 DQ35 DDRB_DQ39
DDRB_CLK0 101 VDD9 VDD10 102 DDRB_CLK1 130 DQ36 DDRB_DQ33
{6} DDRB_CLK0 CK0 CK1 DDRB_CLK1 {6}
{6} DDRB_CLK0#
DDRB_CLK0# 103 104 DDRB_CLK1# CD@ CD@ CD@ CD@ 132 DQ37 DDRB_DQ32
CK0# CK1# DDRB_CLK1# {6}
105
VDD11 VDD12
106 140 DQ38 DDRB_DQ35
DDRB_MA10 107 108 DDRB_BS1# 142 DQ39 DDRB_DQ34
DDRB_BS0# A10/AP BA1 DDRB_RAS# DDRB_BS1# {6}
{6} DDRB_BS0# 109 110 135 DQS#4 DDRB_DQS#4
BA0 RAS# DDRB_RAS# {6}
111 112
DDRB_WE# 113 VDD13 VDD14 114 DDRB_CS0# 137 DQS4 DDRB_DQS4
{6} DDRB_WE# WE# S0# DDRB_CS0# {6}
DDRB_CAS# 115 116 DDRB_ODT0
{6} DDRB_CAS# CAS# ODT0 DDRB_ODT0 {6}
117 118 147 DQ40 DDRB_DQ44
DDRB_MA13 119 VDD15 VDD16 120 DDRB_ODT1
A13 ODT1 DDRB_ODT1 {6} 149 DQ41 DDRB_DQ45
DDRB_CS1# 121 122
{6} DDRB_CS1#
123 S1# NC2 124
157 DQ42 DDRB_DQ47
125 VDD17 VDD18 126 +VREF_CA_DIMMB RD19 1 @ 2 0_0402_5% 159 DQ43 DDRB_DQ46
NCTEST VREF_CA +VREF_CA {17} 146 DQ44 DDRB_DQ41
127 128
VSS27 VSS28 148 DQ45 DDRB_DQ40
.1U_0402_10V6-K
DDRB_DQ36 129 130 DDRB_DQ33
B DDRB_DQ37 131 DQ32 DQ36 132 DDRB_DQ32 158 DQ46 DDRB_DQ42 B
DQ33 DQ37 1 1
133 134 CD48 CD49 160 DQ47 DDRB_DQ43
DDRB_DQS#4 135 VSS29 VSS30 136 2.2U_0603_6.3V6K
DDRB_DQS4 DQS#4 DM4 152 DQS#5 DDRB_DQS#5
137 138
139 DQS4 VSS31 140 DDRB_DQ35 2 2 154 DQS5 DDRB_DQS5
DDRB_DQ38 141 VSS32 DQ38 142 DDRB_DQ34
DDRB_DQ39 143 DQ34 DQ39 144
DQ35 VSS33
163 DQ48 DDRB_DQ52
145 146 DDRB_DQ41 165 DQ49 DDRB_DQ53
DDRB_DQ44 147 VSS34 DQ44 148 DDRB_DQ40
DDRB_DQ45 DQ40 DQ45 Layout Note: (10U_0603_6.3V)*2 175 DQ50 DDRB_DQ54
149 150
151 DQ41 VSS35 152 DDRB_DQS#5 Place near DIMM 177 DQ51 DDRB_DQ51
153 VSS36 DQS#5 154 DDRB_DQS5 (.1U_0402_10V)*4 164 DQ52 DDRB_DQ49
155 DM5 DQS5 156 166 DQ53 DDRB_DQ48
DDRB_DQ47 157 VSS37 VSS38 158 DDRB_DQ42 174 DQ54 DDRB_DQ50
DDRB_DQ46 159 DQ42 DQ46 160 DDRB_DQ43
DQ43 DQ47 176 DQ55 DDRB_DQ55
161 162 169 DQS#6 DDRB_DQS#6
DDRB_DQ52 163 VSS39 VSS40 164 DDRB_DQ49 +0.675VS
DDRB_DQ53 165 DQ48 DQ52 166 DDRB_DQ48 171 DQS6 DDRB_DQS6
167 DQ49 DQ53 168
VSS41 VSS42
CD50

CD51

CD52

CD53

CD66

CD67
DDRB_DQS#6 169 170 181 DQ56 DDRB_DQ57
DDRB_DQS6 171 DQS#6 DM6 172
DQS6 VSS43 183 DQ57 DDRB_DQ60
.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

10U_0603_6.3V6M

10U_0603_6.3V6M
173 174 DDRB_DQ50
DDRB_DQ54 175 VSS44 DQ54 176 DDRB_DQ55 191 DQ58 DDRB_DQ58
DQ50 DQ55 1 1 1 1 1 1 193 DQ59 DDRB_DQ59
DDRB_DQ51 177 178
179 DQ51 VSS45 180 DDRB_DQ56 180 DQ60 DDRB_DQ56
DDRB_DQ57 181 VSS46 DQ60 182 DDRB_DQ61 182 DQ61 DDRB_DQ61
DDRB_DQ60 183 DQ56 DQ61 184 2 2 2 2 2 2 192 DQ62 DDRB_DQ62
185 DQ57 VSS47 186 DDRB_DQS#7 CD@
VSS48 DQS#7 194 DQ63 DDRB_DQ63
187 188 DDRB_DQS7
DM7 DQS7 186 DQS#7 DDRB_DQS#7
189 190 CD@ CD@
DDRB_DQ58 191 VSS49 VSS50 192 DDRB_DQ62 188 DQS7 DDRB_DQS7
DDRB_DQ59 193 DQ58 DQ62 194 DDRB_DQ63
A 195 DQ59 DQ63 196 A
RD20 1 2 @ 197 VSS51 VSS52 198
0_0402_5% 199 SA0 EVENT# 200 SMB_DATA_S3
VDDSPD SDA SMB_CLK_S3 SMB_DATA_S3 {7,17,40}
1 2 201 202
+3VS SA1 SCL SMB_CLK_S3 {7,17,40}
RD21 10K_0402_5% 203 204 +0.675VS
VTT1 VTT2
0.65A@0.75V
47P_0402_50V8J

1 1
205 206 1
G1 G2
CD69

CD54 CD55 Title

2.2U_0603_6.3V6K .1U_0402_10V6-K LCN_DAN06-K4406-0102 Security Classification LC Future Center Secret Data
@ 2 2
ME@ 2 Issued Date 2014/12/11 Deciphered Date 2015/12/11 DDRIII SO-DIMM B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

WWW.AliSaler.Com For RF DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 18 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 19 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 ATI_JET-LE_PCIE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A3 0.2

WWW.AliSaler.Com
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 20 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 ATI_JET-LE_Main_MSIC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 21 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 ATI_JET-LE_TMDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 22 of 60
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 ATI_JET-LE_DP Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 23 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 ATI_JET-LE_Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

WWW.AliSaler.Com
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 24 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 ATI_JET-LE_MEM IF
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 25 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 ATI_JET-LE_VRAM_A

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 26 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 ATI_JET-LE_VRAM_B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 27 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 28 of 60
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 29 of 60
5 4 3 2 1
 5 4 3 2 1

FOR ESD Close to Connector

LW1 UW1
USB20_N5 1 2 USB20_N5_R
1 2 Realtek_SD@ CARD_3V3 SD_CD# SD_CMD
RW2 1 2 6.2K_0402_1% RREF 1 24 VDD18 1U_0402_6.3V6K 2 1 CW1
USB20_P5 4 3 USB20_P5_R USB20_N5 RW9 1 2 0_0402_5% USB20_N5_R 2 RREF V18 23

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2
4 3 {9} USB20_N5 DM XD_D7

1
USB20_P5 RW10 1 @ 2 0_0402_5% USB20_P5_R 3 22 Realtek_SD@
{9} USB20_P5 DP SP14 SD_D2_R
EXC24CH900U_4P @ 4 21 DW1 DW2 DW3

1
+3VS 3V3_IN SP13
FOR EMI CARD_3V3_R 5 20 SD_D3_R EMC_NS@ EMC_NS@ EMC_NS@
EMC_NS@ CARD_3V3 SP12

0.1U_0402_10V7K
SDREG 6 19

4.7U_0603_6.3V6K
7 SDREG SP11 18 SD_CMD_R
1 1 XD_CD# SP10
SD_WP_R

1U_0402_6.3V6K
CW2 CW3 8 17
SP1 GPIO0

2
Realtek_SD@ 1 9 16
Realtek_SD@ CW4 SD_D1_R 10 SP2 SP9 15 SD_CLK_R

2
2 2 SD_D0_R 11 SP3 SP8 14
12 SP4 SP7 13 SD_CD#_R
2 SP5 SP6
D D
Realtek_SD@ 25 CARD_3V3
GND

RTS5170-GRT_QFN24_4X4 CARD_3V3_R RW28 1 @ 2 0_0603_5%

Realtek_SD@

F2 JREAD1
CARD_3V3_PCH 1 2 4
VDD

.1U_0402_10V6-K
4.7U_0603_6.3V6K
0.5A_8V_KMC3S050RY SD_D0 7
1 1 DAT0
+VCCPGPPG_SDIO_PU SD_D1 8
@ DAT1
CW9 CW17 SD_D2 9
SD_D3 1 DAT2
2 2 CD/DAT3
SD_D0 RW30 @1 2 49.9K_0402_1% SD_CD# 11
SD_WP 10 C/D
SD_D1 RW31 @1 2 49.9K_0402_1% W/P
Close to Connector SD_CMD 2
SD_D2 RW32 @1 2 49.9K_0402_1% SD_CLK 5 CMD
CLK
SD_D3 RW33 @1 2 49.9K_0402_1% 3 12
6 VSS1 GND_1 13
SD_D0_R RW3 1 2 0_0402_5% SD_D0 SD_CMD RW34 @1 2 49.9K_0402_1% VSS2 GND_2
@ CW5 1 2 5.6P_0402_50V8-D DEREN_404232501111RHF_NR
SD_D0_PCH_R3 RW19 1 2 0_0402_5% SD_WP RW38 @1 2 49.9K_0402_1% ME@
@ EMC@
+VCCPGPPG_SDIO

SD_D1_R RW4 1 2 0_0402_5% SD_D1

@ CW6 1 2 5.6P_0402_50V8-D PCH_SDIO@
SD / MMC
SD_D1_PCH_R3 RW18 1 2 0_0402_5% SD_CD#_PCH RW132 1 2 49.9K_0402_1%
@ EMC@

SD_D2_R RW5 1 2 0_0402_5% SD_D2 SD_WP pull-up or pull-down reserved

C @ CW7 1 2 5.6P_0402_50V8-D C
SD_D2_PCH_R3 RW21 1 2 0_0402_5% SD_CLK RW35 @1 2 49.9K_0402_1%
@ EMC@ SD_WP RW39 @1 2 49.9K_0402_1%

SD_D3_R RW6 1 2 0_0402_5% SD_D3

@ CW8 1 2 5.6P_0402_50V8-D
SD_D3_PCH_R3 RW20 1 2 0_0402_5%
@ EMC@ +3VALW
+3VS CARD_3V3_PCH +VCCPGPPG_SDIO +VCCPGPPG_SDIO_PU

SD_CMD_R RW7 1 2 0_0402_5% SD_CMD

@ CW11 1 2 5.6P_0402_50V8-D
SD_CMD_PCH_R3 RW23 1 2 0_0402_5%

D
@ EMC@ QW1 3 1 PCH_SDIO@ QW15 3 1 PCH_SDIO@
RW133 LP2301ALT1G_SOT23-3 1 LP2301ALT1G_SOT23-3

1
PCH_SDIO@ 10K_0402_5%
SD_CLK_R RW8 1 2 0_0402_5% SD_CLK @ CW24 CW23

G
2

2
@ CW12 1 2 5.6P_0402_50V8-D 10U_0603_6.3V6M
1U_0402_6.3V6K

2
SD_CLK_PCH_R3 RW22 1 2 0_0402_5% 2
@ EMC@

SD_CD#_R RW25 1 2 0_0402_5% SD_CD# EC_SD_PWR_EN# EC_SD_PWR_EN#

{44} EC_SD_PWR_EN#
@ 1 1
SD_CD#_PCH RW27 1 2 0_0402_5% CW19 CW22
{8} SD_CD#_PCH
@ 0.1U_0402_16V4Z 0.1U_0402_16V4Z
PCH_SDIO@ PCH_SDIO@
2 2
SD_WP_R RW24 1 2 0_0402_5% SD_WP
@
SD_WP_PCH RW26 1 2 0_0402_5%
{8} SD_WP_PCH
@

B B
+3VALW +3VALW
+3VALW

2
RW128 PCH_SDIO@
10K_0402_5%

2
@ @ PCH_SDIO@

3
S
SD_D0_PCH RW40 1 2 0_0201_5% SD_D0_PCH_R1 RW47 1 2 0_0201_5% SD_D0_PCH_R3 RW127
{8} SD_D0_PCH

1
SD_1P8_SEL_3.3V_EN
G
PCH_SDIO@ 10K_0402_5% 2 1 RW130 CW21 2 QW14
SD_D0_PCH_R2

0.1U_0402_10V7K
RW46 1 2 0_0201_5% RW48 1 2 0_0201_5% 10K_0402_5% LP2301ALT1G_SOT23-3
PCH_SDIO@ PCH_SDIO@ 1
D

1
@ @ PCH_SDIO@ PCH_SDIO@

D2 3
SD_D1_PCH RW49 1 2 0_0201_5% SD_D1_PCH_R1 RW51 1 2 0_0201_5% SD_D1_PCH_R3
{8} SD_D1_PCH 2
QW12B
RW50 1 2 0_0201_5% SD_D1_PCH_R2 RW52 1 2 0_0201_5% SD_1P8_SEL_1.8V_EN 5 G2 PJT138K_SOT363-6
PCH_SDIO@ PCH_SDIO@ PCH_SDIO@ +VCCPGPPG_SDIO

4 S2
@ @
SD_D2_PCH SD_D2_PCH_R1 SD_D2_PCH_R3

D1 6
RW53 1 2 0_0201_5% RW55 1 2 0_0201_5%
{8} SD_D2_PCH
QW12A
RW54 1 2 0_0201_5% SD_D2_PCH_R2 RW56 1 2 0_0201_5% SD_1P8_SEL 2 G1 PJT138K_SOT363-6
{8} SD_1P8_SEL
PCH_SDIO@ PCH_SDIO@ PCH_SDIO@

1 S1
@ @
1

3
S
SD_D3_PCH RW57 1 2 0_0201_5% SD_D3_PCH_R1 RW59 1 2 0_0201_5% SD_D3_PCH_R3
{8} SD_D3_PCH SD_1P8_SEL_1.8V_EN
G
RW131 2 1 RW129 CW20 2 QW2
SD_D3_PCH_R2

0.1U_0402_10V7K
RW58 1 2 0_0201_5% RW60 1 2 0_0201_5% 49.9K_0402_1% 10K_0402_5% LP2301ALT1G_SOT23-3
PCH_SDIO@ PCH_SDIO@ PCH_SDIO@ PCH_SDIO@ 1
D

1
2

@ @ @ PCH_SDIO@
SD_CMD_PCH RW61 1 2 0_0201_5% SD_CMD_PCH_R1RW63 1 2 0_0201_5% SD_CMD_PCH_R3
{8} SD_CMD_PCH 2
RW62 1 2 0_0201_5% SD_CMD_PCH_R2RW64 1 2 0_0201_5%
A PCH_SDIO@ PCH_SDIO@ A

@ @ +1.8VALW
SD_CLK_PCH RW65 1 2 0_0201_5% SD_CLK_PCH_R1 RW67 1 2 0_0201_5% SD_CLK_PCH_R3
{8} SD_CLK_PCH
RW66 1 2 0_0201_5% SD_CLK_PCH_R2 RW68 1 2 0_0201_5%
PCH_SDIO@ PCH_SDIO@

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 Cardreader

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 30 of 60
5 4 3 2 1
 5 4 3 2 1

VCCRTC

1
CG16
390_0402_5%
D GCLK@ D
UG1

2
GCLK@
10 14 CG3 1 2
VRTC VOUT

+3VL 15 2.2U_0402_6.3V6M
V3.3A
1
+3VALW 2
CG9 VDD 9
32.768K RTC_CLK {10}
22U_0603_6.3V6-M
2
GCLK@
11 12
VIOE_27M 27M
8 6 CLK_25M RG3 1 2 33_0402_5%
+3VALW_LAN VIO_25M 25M 25M_CLK {37}
GCLK@
VIOE_24 3 5 CLK_24M RG4 1 2 33_0402_5%
VIOE_24M 24M 24M_CLK {10}
GCLK@
GCLK_XTALI 1
+1.0VALW GCLK_XTALO 16 X1
1 X2

GND1
GND2
GND3

GND4
CG8
.1U_0402_10V6-K
C 2 C

4
7
13

17
GCLK@ SLG3NB3377VTR_TQFN16_2X3
1

GCLK@
RG7
0_0402_5%
2

GCLK@
VIOE_24

+3VL

1
CG5 GCLK_XTALI
.1U_0402_10V6-K YG1
2 GCLK_XTALO
B GCLK@ B
1 4
OSC1 GND2 EMC_NS@
2 3 CLK_25M CG13 1 2 6P_0402_50V8D
GND1 OSC2
1 1
CG1 CG2
18P_0402_50V8J 25MHZ_10PF_X1E000021013300 15P_0402_50V8J
GCLK@ GCLK@ GCLK@
+3VALW +3VALW_LAN 2 2 EMC_NS@
CLK_24M CG15 1 2 6P_0402_50V8D

1 1
For EMC
CG4 CG6
.1U_0402_10V6-K .1U_0402_10V6-K
2 2
GCLK@ GCLK@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 Greenclk
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 31 of 60
5 4 3 2 1
 5 4 3 2 1

D D

+3VS
+3VS_TPM
1A RTPM11 TPM@ 2 0_0603_5%
1 1
1 CTPM3
CTPM4 CTPM1 .1U_0402_10V6-K
TPM .1U_0402_10V6-K 10U_0603_6.3V6M TPM@
TPM@ 2 TPM@ 2
2

+3VS_TPM
UTPM1
1 24
2 NC_1 VDD3 10
C 3 NC_2 VDD1 C
7 NC_3 28 RTPM2 1 TPM@ 2 4.7K_0402_5%
PP LPCPD# 27 SERIRQ_TPM RTPM5 1 TPM@ 2 0_0402_5%
SERIRQ LPC_AD0_TPM SERIRQ {7,44}
6 26 RTPM6 1 TPM@ 2 0_0402_5%
NC_4 LAD0 LPC_AD1_TPM LPC_AD0 {7,44}
9 23 RTPM7 1 TPM@ 2 0_0402_5%
NC_7 LAD1 LPC_FRAME#_TPM LPC_AD1 {7,44}
22 RTPM8 1 TPM@ 2 0_0402_5%
LFRAME# LPC_AD2_TPM LPC_FRAME# {7,44}
4 20 RTPM9 1 TPM@ 2 0_0402_5%
GND_1 LAD2 LPC_AD3_TPM LPC_AD2 {7,44}
11 17 RTPM10 1 TPM@ 2 0_0402_5%
GND_2 LAD3 LPC_AD3 {7,44}
18
+3VS_TPM GND_3 25 +3VS_TPM
5 GND_4 21
NC_5 LCLK CLK_PCI_TPM {7}
8 19
12 NC_6 VDD2 15 RTPM4 1 TPM@ 2 0_0402_5%
13 NC_8 CLK_RUN#
14 NC_9 16
NC_10 LRESET# PLT_RST# {11,37,40,44}

Z32H320TC_TSSOP28
TPM@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 TPM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 32 of 60
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

LCD POWER CIRCUIT CMOS Camera

+3VS +3VS Need  short +3VS_CMOS_R
+LCDVDD_CON J1 @
1 2
U5 1 2
5 1 W=60mils JUMP_43X39
IN OUT +3VS_CMOS

C121

C122

C123
33P_0402_50V8J
2

.1U_0402_10V6-K
4.7U_0603_6.3V6K
1 GND
1 1 1 LP2301ALT1G_SOT23-3
C1 PCH_ENVDD 4 3 W=40 mils W=40mils
EN FLG

D
.1U_0402_10V6-K Q7 3 1 R3 1 @ 2
2

.01U_0402_16V7-K
D 0_0603_5% D

EMC_NS@
2 2 2

C6
AP22802AW5-7_SOT25-5 @ 1 1
C3 C4

G
1 1

2
U5 EN PIN VIH MIN 1.5V @
C5
.1U_0402_10V6-K
.1U_0402_10V6-K
CD@
10U_0603_6.3V6M
@
@ 2 2
2 @2

PCH_ENVDD For RF R5 1 @ 2
{4} PCH_ENVDD {8} CMOS_ON#
100K_0402_5%

1
1 1
R1 C9 C10
100K_0402_5% 0.01U_0402_25V7K For EMI .1U_0402_10V6-K
EMC_NS@ Close to R5 @
2 2

2
+3VS

+3VS
EMI request

2
R8 R9
2

100K_0402_1% 100K_0402_1% DMIC_CLK DISPOFF# INVT_PWM

470P_0402_50V7K
R10
PCH_ENBKL

C11

C12

C13
470P_0402_50V7K
1 2

100P_0402_50V8J
R11 @ 4.7K_0402_5% @ @

1
0_0402_5% @ 1 1 1
EMC_NS@ EMC_NS@
1

EDP_AUX EMC@
R12 1 @ 2 0_0402_5% DISPOFF# B+ +LEDVDD EDP_AUX#
{44} BKOFF# 2 2 2
2A 80 mil R17 0_0805_5% 2A 80 mil

2
R14 1 @ 2 0_0402_5% ENBKL 2 1
{4} PCH_ENBKL ENBKL {44}

4.7U_0805_25V6-K
C14 R13 R15
1

C C

0.1U_0402_25V6
1 1 100K_0402_1% 100K_0402_1%
R16 C15
100K_0402_5% AO3401A_SOT23-3 EMC@ @ @

1
2 2

D
Q33 3 1 @
2

EMI Request JEDP1
+LEDVDD 1
CD@ 2 1

G
2
3 2
+3VS R179 1 @ 2 LEDVDD_EN# 4 3
B+ 4
100K_0402_5% CPU_EDP_TX0+ C19 1 2 .1U_0402_10V6-K EDP_TX0+ 5
{4} CPU_EDP_TX0+ CPU_EDP_TX0- EDP_TX0- 5
C16 1 2 .1U_0402_10V6-K 6
{4} CPU_EDP_TX0- 6
2

1
7
R18 R180 CPU_EDP_TX1+ C17 1 2 .1U_0402_10V6-K EDP_TX1+ 8 7
{4} CPU_EDP_TX1+ CPU_EDP_TX1- EDP_TX1- 8
1K_0402_5% 100K_0402_5% C18 1 2 .1U_0402_10V6-K 9
{4} CPU_EDP_TX1- 9
@ @ 10
CPU_EDP_AUX C20 1 2 .1U_0402_10V6-K EDP_AUX 11 10
{4} CPU_EDP_AUX
1

1 2
CPU_EDP_AUX# C21 1 2 .1U_0402_10V6-K EDP_AUX# 12 11
INVT_PWM D {4} CPU_EDP_AUX# 12
R19 1 @ 2 0_0402_5% Q34 13
{4} PCH_EDP_PWM PCH_ENVDD 13
R181 1 @ 2 2 DISPOFF# 14
0_0402_5% G 15 14
15
1

1 INVT_PWM 16
R20 C132 @ S 17 16
3

100K_0402_5% .1U_0402_10V6-K 2N7002KW_SOT323-3 +3VS 18 17

@ 19 18
2 {4} CPU_EDP_HPD 19
R21 1 @ 2 20
2

0_0402_5% 21 20
1 +LCDVDD_CON 21
W=60mils 22
EMC_NS@ C22 23 22
Reserve for power consumption test +3VS 23
680P_0402_50V7K {43} DMIC_DATA 24
2 25 24
{43} DMIC_CLK 25
26 31
27 26 G1 32
R182 1 2 0_0402_5% USB20_P4_R 28 27 G2 33
{9} USB20_P4 28 G3
B R183 1 2 0_0402_5% USB20_N4_R 29 34 B
{9} USB20_N4 29 G4
+3VS_CMOS 30 35
30 G5
2
Touch Screen C24
W=40mils ACES_50406-03071-001
ME@
0.047U_0402_16V7K
EMC_NS@1

+3VS +3VS_TS

R26 1 TS@ 2 0_0402_5% EMI request

JTS1
1
C25 1
.1U_0402_10V6-K R28 2 TS@ 1 0_0402_5% TS_RS 2 1 7
{44} EC_TS_ON# 2 GND1
TS@ 3
2 R23 1 TS@ 2 0_0402_5% USB20_N6_CONN 4 3 8
{9} USB20_N6 USB20_P6_CONN 4 GND2
R24 1 TS@ 2 0_0402_5% 5
{9} USB20_P6 5
6
6 For EMI
CVILU_CI1806M2HR0-NH L12
USB20_P6_CONN USB20_P4 1 2 USB20_P4_R
ME@ 1 2
+3VS_TS USB20_N6_CONN
Touch Screen USB20_N4 4 3 USB20_N4_R
4 3
3

EXC24CH900U_4P
EMC_NS@
1

EMC_NS@
D2
1

For EMI
L15 D1
2

USB20_P6 1 2 USB20_P6_CONN AZC199-02S.R7G_SOT23-3

A 1 2 EMC_NS@ A
2

AZ5215-01F_DFN1006P2E2
USB20_N6 4 3 USB20_N6_CONN
1

4 3
EXC24CH900U_4P For EMI
EMC_NS@

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 eDP/ CMOS/Touch screen
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 33 of 60
5 4 3 2 1
 5 4 3 2 1

L2 EMC@ EMC_NS@
HDMI_CLK-_C 1 2 HDMI_CLK-_CON 1 2
1 2 C26 3.3P_0402_50V8-C
EMC_NS@
HDMI_CLK+_C 4 3 HDMI_CLK+_CON 1 2
4 3 C27 3.3P_0402_50V8-C
EXC24CH900U_4P
+3VS
D L3 EMC@ EMC_NS@ D
HDMI_TX0-_C 1 2 HDMI_TX0-_CON 1 2
1 2 C28 3.3P_0402_50V8-C
EMC_NS@
HDMI_TX0+_C 4 3 HDMI_TX0+_CON 1 2
4 3 C29 3.3P_0402_50V8-C

5
EXC24CH900U_4P

G
Q1B D3
L4 EMC@ EMC_NS@ HDMI_DET 1 1 10 9 HDMI_DET
HDMI_TX1-_C 1 2 HDMI_TX1-_CON 1 2
1 2 HDMICLK_R HDMIDAT_R 2 2
C30 3.3P_0402_50V8-C 4 3 9 8 HDMIDAT_R

S
{4} DDPB_CLK

D
EMC_NS@
HDMI_TX1+_C 4 3 HDMI_TX1+_CON 1 2 2N7002KDWH_SOT363-6 HDMICLK_R 4 4 7 7 HDMICLK_R
4 3

2
C31 3.3P_0402_50V8-C

G
EXC24CH900U_4P Q1A +5VS_HDMI 5 5 6 6 +5VS_HDMI

L5 EMC@ EMC_NS@ 3 3
HDMI_TX2-_C 1 2 HDMI_TX2-_CON 1 2 1 6 HDMIDAT_R

S
1 2 {4} DDPB_DATA

D
C32 3.3P_0402_50V8-C 8
EMC_NS@ 2N7002KDWH_SOT363-6
HDMI_TX2+_C 4 3 HDMI_TX2+_CON 1 2
4 3 C33 3.3P_0402_50V8-C AZ1045-04F_DFN2510P10E-10-9
EXC24CH900U_4P EMC_NS@

For EMC
For EMC

C C
HDMI_CLK-_C R29 1 2 470_0402_5% +5VS +5VS_HDMI_F +5VS_HDMI
D5
HDMI_CLK+_C R30 1 2 470_0402_5% +5VS 2 F1
+3VS 1 1 2
HDMI_TX0-_C R31 1 2 470_0402_5% 3

2
D4 RB491D_SOT23-3 0.5A_8V_KMC3S050RY
HDMI_TX0+_C R32 1 2 470_0402_5% @

HDMI_TX1-_C R33 1 2 470_0402_5% @ LP2301ALT1G_SOT23-3

2
HDMI_TX1+_C R34 1 2 470_0402_5% BAT54S-7-F_SOT23-3 1 3 Q22

S
R35

1
2
Q12 D4

G
1M_0402_5%
HDMI_TX2-_C R37 1 2 470_0402_5% 1
C34

G
1

2
HDMI_TX2+_C R38 1 2 470_0402_5% .1U_0402_10V6-K

2
3 1
{4} HDMI_HPD {46} SUSP 2

D
R39 R40
1

D Q13 2N7002KW_SOT323-3 2.2K_0402_5% 2.2K_0402_5%

2
+3VS 2
G 2N7002KW_SOT323-3 R41

1
20K_0402_5%
S JHDMI1
3

HDMI_DET 19

1
R42 1 @ 2 18 HP_DET
17 +5V
100K_0402_5% HDMIDAT_R 16 DDC/CEC_GND
HDMICLK_R 15 SDA
14 SCL
13 Reserved
HDMI_CLK- C35 2 1 .1U_0402_10V6-K HDMI_CLK-_C R43 2 @ 1 0_0402_5% HDMI_CLK-_CON 12 CEC 20
{4} HDMI_CLK- CK- GND1
11 21
B HDMI_CLK+ C36 2 1 .1U_0402_10V6-K HDMI_CLK+_C R44 2 @ 1 0_0402_5% HDMI_CLK+_CON 10 CK_shield GND2 B
{4} HDMI_CLK+ CK+
HDMI_TX0- C37 2 1 .1U_0402_10V6-K HDMI_TX0-_C R45 2 @ 1 0_0402_5% HDMI_TX0-_CON 9 22
{4} HDMI_TX0- D0- GND3
8 23
HDMI_TX0+ C38 2 1 .1U_0402_10V6-K HDMI_TX0+_C R46 2 @ 1 0_0402_5% HDMI_TX0+_CON 7 D0_shield GND4
{4} HDMI_TX0+ D0+
HDMI_TX1- C39 2 1 .1U_0402_10V6-K HDMI_TX1-_C R47 2 @ 1 0_0402_5% HDMI_TX1-_CON 6
{4} HDMI_TX1- D1-
5
HDMI_TX1+ C40 2 1 .1U_0402_10V6-K HDMI_TX1+_C R48 2 @ 1 0_0402_5% HDMI_TX1+_CON 4 D1_shield
{4} HDMI_TX1+ D1+
HDMI_TX2- C41 2 1 .1U_0402_10V6-K HDMI_TX2-_C R49 2 @ 1 0_0402_5% HDMI_TX2-_CON 3
{4} HDMI_TX2- D2-
2
HDMI_TX2+ C42 2 1 .1U_0402_10V6-K HDMI_TX2+_C R50 2 @ 1 0_0402_5% HDMI_TX2+_CON 1 D2_shield
{4} HDMI_TX2+ D2+
FOX_QJ111A1-RC0AH1-8H
ME@

Close to JHDMI1
D6 D7
HDMI_CLK+_CON 1 1 10 9 HDMI_CLK+_CON HDMI_TX1-_CON 1 1 10 9 HDMI_TX1-_CON

HDMI_CLK-_CON 2 2 9 8 HDMI_CLK-_CON HDMI_TX1+_CON 2 2 9 8 HDMI_TX1+_CON

HDMI_TX0+_CON 4 4 7 7 HDMI_TX0+_CON HDMI_TX2-_CON 4 4 7 7 HDMI_TX2-_CON

HDMI_TX0-_CON 5 5 6 6 HDMI_TX0-_CON HDMI_TX2+_CON 5 5 6 6 HDMI_TX2+_CON

A A
3 3 3 3

8 8

AZ1045-04F_DFN2510P10E-10-9 For EMC AZ1045-04F_DFN2510P10E-10-9

EMC_NS@ EMC_NS@ Security Classification LC Future Center Secret Data Title
Issued Date 2014/12/11 Deciphered Date 2015/12/11 HDMI_CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

WWW.AliSaler.Com
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 34 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS +DP_3V3

+IVDDO +RX_AVCC
RVG16 1 @ 2 0_0603_5%
Change to SA000072B10 IT6515FN/BX-0051
1 LVG2 1 2

.1U_0402_10V6-K
BLM15PD600SN1D_2P
CVG8 +DP_3V3 +DP_3V3 +IVDDO +RX_IVDD
1 1

CVG15
10U_0805_10V6K
D 2 CVG10 D
10U_0603_6.3V6M
2 2

10
40

29
30

32

11
20
37
39
UVG1 +DDCP

OVDD_1
OVDD_2

IVDD33_1
IVDD33_2

IVDDO

IVDD_1
IVDD_2
IVDD_3
IVDD_4
DP_VGA_HPD 33
{4} DP_VGA_HPD HPD
38 +IVDDO +RX_IVDD
CVG3 1 2 .1U_0402_10V6-K DRX0P 22 MCUVDDH
{4} VGA_TX0+ RX0P
CVG2 1 2 .1U_0402_10V6-K DRX0N 23
{4} VGA_TX0- RX0N RVG19 1 @ 2 0_0603_5%

.1U_0402_10V6-K
CVG4 1 2 .1U_0402_10V6-K DRX1P 25
{4} VGA_TX1+ RX1P
CVG5 1 2 .1U_0402_10V6-K DRX1N 26 1
{4} VGA_TX1- RX1N

CVG16
24 @1 TVG1
URDBG
12 2
ISPSCL 13
CVG6 1 2 .1U_0402_10V6-K AUXP 19 ISPSDA
{4} VGA_AUX RXAUXP
CVG7 1 2 .1U_0402_10V6-K AUXN 18 17
{4} VGA_AUX# RXAUXN VGADDCCLK CRT_DDC_CLK {36}
16
+DP_3V3 VGADDCSDA CRT_DDC_DAT {36}
15 1 VGA_VS
DCAUXP VSYNC VGA_HS VGA_VS {36}
14 2
DCAUXN HSYNC VGA_HS {36}
+IVDDO +DAC_VDDC
+DAC_VDDC
+RX_AVCC
LVG4 1 2

4.7U_0805_25V6-K
.1U_0402_10V6-K
C 21 6 BLM15PD600SN1D_2P CVG11 C
27 AVCC_1 VDDC
AVCC_2 1 1

CVG17
IT6515FN 2 2
9 CRT_R
IORP CRT_R {36}

8 CRT_G
IOGP CRT_G {36}

7 CRT_B
IOBP CRT_B {36}
34
NC_2
3 RVG3 1 2 200_0402_1%
28 RSET +DAC_VDDC
ASPVCC RVG3 closed to pin3
5
VDDA
+DDCP
RPVG1
4
3 2 36 NC_1
4 1 35 PCSDA
+DP_3V3 +CRT_VCC_CON PCSCL

2.2K_0404_4P2R_5%

PWD

GND
RVG1 1 2 0_0402_5% +DDCP
@ IT6515FN-BX-0051_QFN40_5X5 CRT_R

31

41
B B
RVG2 1 2 0_0402_5% 1
@ CRT_G

TVG2 CRT_B
@

1
RVG25 RVG26 RVG27
+DP_3V3 75_0402_1% 75_0402_1% 75_0402_1%

2
2
1

RPVG2 CLOSE TO UVG1

2.2K_0404_4P2R_5%
CD@
3
4

CRT_DDC_CLK

CRT_DDC_DAT

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 DP to CRT Convert(IT6515FN)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 35 of 60
5 4 3 2 1
 5 4 3 2 1

+DP_3V3 +CRT_VCC_CON

CRT Connector

5
G

2
1
QVG1B +CRT_VCC_CON +5VS_HDMI
RPVG3
+5VS @
2.2K_0404_4P2R_5% +CRT_VCC
CRT_DDC_CLK 4 3 CRT_DDC_CLK_R RVG39 1 2 0_0603_5%

S
{35} CRT_DDC_CLK

D
CD@ DVG1

3
4
2N7002KDWH_SOT363-6 CRT_DDC_CLK_R @ 2 FVG1

2
1 1 2 @ +CRT_VCC_CON

G
QVG1A 3 1
D CRT_DDC_DAT_R PMEG2010ET_SOT23-3 0.5A_8V_KMC3S050RY D

1
CVG34
CRT_DDC_DAT 1 6 CRT_DDC_DAT_R .1U_0402_10V6-K DVG2
W=40mils

S
1 1

1
{35} CRT_DDC_DAT 2

D
CD@ AZ5425-01F_DFN1006P2E2
2N7002KDWH_SOT363-6 CVG43 CVG44 CD@
100P_0402_50V8J 68P_0402_50V8J EMC_NS@
CRT_DDC_CLK RVG5 1 2 0_0402_5% CRT_DDC_CLK_R @ 2 2 @

2
@

2
CRT_DDC_DAT RVG4 1 2 0_0402_5% CRT_DDC_DAT_R JCRT1
@ 6
11
LVG6 1 2 EMC@ CRT_R_CON 1
{35} CRT_R
BLM15BA220SN1D 7 For EMC
CRT_DDC_DAT_R 12
LVG7 1 2 EMC@ CRT_G_CON 2
{35} CRT_G
BLM15BA220SN1D 8
HSYNC_CON 13
LVG8 1 2 EMC@ CRT_B_CON 3
{35} CRT_B
BLM15BA220SN1D 9

15P_0402_50V8J
CVG35

15P_0402_50V8J
CVG36

15P_0402_50V8J
CVG37

15P_0402_50V8J
CVG38

15P_0402_50V8J
CVG39

15P_0402_50V8J
CVG40
VSYNC_CON 14
1 1 1 1 1 1 4
10 G 16
CRT_DDC_CLK_R 15 G 17
5
2 2 2 2 2 2
1
CVG41 SUYIN_070546HR015M25KZR
100P_0402_50V8J ME@
EMC@ EMC@ EMC@ EMC@ EMC@ EMC@ @
2

C C

VGA_HS RVG32 1 2 33_0402_5% HSYNC_CON

{35} VGA_HS

1
CVG42
10P_0402_50V8-J
2

B B

VGA_VS RVG33 1 2 33_0402_5% VSYNC_CON

{35} VGA_VS

1
CVG45
10P_0402_50V8-J
2

DVG3 DVG4
CRT_B_CON 1 1 10 9 CRT_B_CON VSYNC_CON 1 1 10 9 VSYNC_CON

CRT_G_CON 2 2 9 8 CRT_G_CON HSYNC_CON 2 2 9 8 HSYNC_CON

CRT_R_CON 4 4 7 7 CRT_R_CON CRT_DDC_CLK_R 4 4 7 7 CRT_DDC_CLK_R

5 5 6 6 CRT_DDC_DAT_R 5 5 6 6 CRT_DDC_DAT_R

3 3 3 3
A A
8 8

AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
EMC_NS@ EMC_NS@
For EMC
Security Classification LC Future Center Secret Data Title
Issued Date 2014/12/11 Deciphered Date 2015/12/11 CRT_CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

WWW.AliSaler.Com
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 36 of 60
5 4 3 2 1
 5 4 3 2 1

+3VALW  TO  +3VALW_LAN

+3VALW_LAN  rising  t i me ( 10 %~90 %): 
+3VALW +3VALW_LAN
0.5ms＜s pec＜ 10 0m s +3VALW_LAN +LAN_VDDREG
Need  short
RL1 @
JL1 1 2 @ width : 40 mils 1 2
1 2
JUMP_43X79 0_0603_5%
D D
1 1
+3VALW LP2301ALT1G_SOT23-3 CL1 CL2

.1U_0402_10V6-K

.1U_0402_10V6-K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1 1 1 1 4.7U_0603_6.3V6K .1U_0402_10V6-K

D
Q14 3 1 @ CL4 CL5 CL6 CL7

.1U_0402_10V6-K

.01U_0402_16V7-K
1
2 2
@
RL2 1 1
100K_0402_5% CL8 CL9 @ 2 @ 2 2 2 CD@

G
2
@
2

2 2
RL3 1 @ 2 @ @
{44} LAN_PWR_ON#
47K_0402_5%
Close to Pin11 Close to Pin32 Close to Pin11 Close to Pin32
+3VALW_LAN +3VS

+3VALW_LAN

2
@

2
RL4

G
2
RL5 manual change the Codec PN to RTL8111H-CG QFN 10K_0402_5% QL1

10K_0402_5% UL1

1
@ LAN_CLKREQ#_R 1 3 @
LAN_CLKREQ# {10}

S
1
2N7002KW_SOT323-3
RL7 1 @ 2 0_0402_5% PCIE_WAKE#_R
{11,40,44} PCIE_WAKE#
{40,44} LAN_WAKE# RL6 1 2 0_0402_5%
@ 33 RL18 1 @ 2 0_0402_5%
+3VALW_LAN 32 GND 16 CLK_PCIE_LAN#
C C
AVDD33_2 REFCLK_N CLK_PCIE_LAN CLK_PCIE_LAN# {10}
RL8 1 2 RSET 31 15
+LAN_VDD10 RSET REFCLK_P PCIE_PTX_C_DRX_N5 CLK_PCIE_LAN {10}
2.49K_0402_1% 30 14
LAN_XTALO AVDD10 HSIN PCIE_PTX_C_DRX_P5 PCIE_PTX_C_DRX_N5 {9}
29 13
LAN_XTALI CKXTAL2 HSIP LAN_CLKREQ#_R PCIE_PTX_C_DRX_P5 {9}
28 12
+3VS TL3 @ 1 27 CKXTAL1 CLKREQB 11 +3VALW_LAN
LAN_PWR_ON# @ LAN_DISABLE# LED0 AVDD33_1 LAN_MDI3-
RL121 2 26 10
LED1/GPIO MDIN3 LAN_MDI3+ LAN_MDI3- {38}
0_0402_5% TL4 @ 1 25 9
LED2 MDIP3 LAN_MDI3+ {38}
1

+LAN_REGOUT 24 8 +LAN_VDD10
RL9 +LAN_VDDREG 23 REGOUT AVDD10_2 7 LAN_MDI2-
+LAN_VDD10 VDDREG MDIN2 LAN_MDI2+ LAN_MDI2- {38}
1K_0402_1% 22 6
PCIE_WAKE#_R DVDD10 MDIP2 LAN_MDI1- LAN_MDI2+ {38}
21 5
LANWAKEB MDIN1 LAN_MDI1+ LAN_MDI1- {38}
ISOLATE# 20 4
LAN_MDI1+ {38}
2

PLT_RST# 19 ISOLATEB MDIP1 3 +LAN_VDD10

{11,32,40,44} PLT_RST# PCIE_PRX_C_DTX_N5 18 PERSTB AVDD10_1 LAN_MDI0-
{9} PCIE_PRX_DTX_N5 CL10 1 2 .1U_0402_10V6-K 2
LAN_PWR_ON# PCIE_PRX_C_DTX_P5 17 HSON MDIN0 LAN_MDI0+ LAN_MDI0- {38}
ISOLATE# RL10 1 @ 2 {9} PCIE_PRX_DTX_P5 CL11 1 2 .1U_0402_10V6-K 1
HSOP MDIP0 LAN_MDI0+ {38}
0_0402_5% CL10 close to Pin18
1

RL11 CL11 close to Pin17
15K_0402_5%
@
2

RTL8111H-CG QFN 32P

B B

LAN_XTALI For RTL8111H (LDO mode) +LAN_VDD10

YL1 LAN_XTALO_R 1 2 LAN_XTALO LL1 1 2 @
2.2UH_NLC252018T-2R2J-N_5%
1 4 RL21 1K_0402_5%
OSC1 GND2 +LAN_REGOUT RL20 1 2 0_0805_5%
2 3
GND1 OSC2
1 1 1 1 1 1 1 1
1 1
CL12 CL13 CL15 CL16 CL17 CL18 CL19 CL20 CL21 CL22
15P_0402_50V8J 25MHZ_10PF_X1E000021013300 15P_0402_50V8J 4.7U_0603_6.3V6K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K 1U_0402_6.3V6K .1U_0402_10V6-K
2 2 2 2 2 2 2 2
2 2 CD@

Close to Pin3, 8, 22, 30 Close  to  Pin22(Reserved)

Layout Note: LL1 must be
GCLK@ within  200mil  to  Pin24,
{31} 25M_CLK RL19 1 2 0_0402_5% LAN_XTALO_R CL15,CL16 must be within
200mil  to  LL1
+LAN_REGOUT: Width =60mil
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 LAN_RTL8111H_CG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 37 of 60
5 4 3 2 1
 5 4 3 2 1

DL1/DL2
1'S PN:SC400007R00
TL1
24 1 MCT
D MCT1 TCT1 D
LAN_MDI0+ 23 2 LAN_MDO0+
{37} LAN_MDI0+ MX1+ TD1+
DL1 @
LAN_MDI2+ 1 10 LAN_MDI2+ LAN_MDI0- 22 3 LAN_MDO0-
Tx1+In Tx1+Out {37} LAN_MDI0- MX1- TD1-

1
LAN_MDI2- 2 9 LAN_MDI2- EMC@
Tx1-In Tx1-Out 21 4 MCT RL17
3 8 MCT2 TCT2 20_0603_5%
GND1 GND2

1
LAN_MDI1+ 20 5 LAN_MDO1+
LAN_MDI3+ LAN_MDI3+ {37} LAN_MDI1+ MX2+ TD2+
4 7 DL3

1
2
LAN_MDI3- 5 Tx2+In Tx2+Out 6 LAN_MDI3- LAN_MDI1- 19 6 LAN_MDO1- PDT5061_DO-214AA
Tx2-In Tx2-Out {37} LAN_MDI1- MX2- TD2- EMC@

2
11 18 7 MCT EMC
GND3 12 MCT3 TCT3

2
GND4 13 LAN_MDI2+ 17 8 LAN_MDO2+
GND5 {37} LAN_MDI2+ MX3+ TD3+
LAN_MDI2- 16 9 LAN_MDO2-
{37} LAN_MDI2- MX3- TD3-
RCLAMP3374N.TCT_SLP3020N10-10
15 10 MCT
MCT4 TCT4
1 1
Place Close to TL1 LAN_MDI3+ 14 11 LAN_MDO3+ CL32 CL25
{37} LAN_MDI3+ MX4+ TD4+
DL2 @ 0.022U_0603_50V7K 1000P_1206_2KV7-K
LAN_MDI1- 1 10 LAN_MDI1- 1 LAN_MDI3- 13 12 LAN_MDO3- EMC@ EMC@
LAN_MDI1+ Tx1+In Tx1+Out LAN_MDI1+ {37} LAN_MDI3- MX4- TD4- 2 2
2 9 EMC
Tx1-In Tx1-Out CL24
C C
3 8 0.01UF_0402_25V7-K BOTH_GST5009 LF
GND1 GND2 2
LAN_MDI0- LAN_MDI0- EMC@
4 7 EMC
LAN_MDI0+ 5 Tx2+In Tx2+Out 6 LAN_MDI0+
Tx2-In Tx2-Out
11
GND3 12 CHASSIS1_GND
GND4 13
GND5

RCLAMP3374N.TCT_SLP3020N10-10

Place Close to TL2

JRJ1 ME@
12
GND_4
11
GND_3
10
LAN_MDO0+ 1 GND_2
PR1+ 9
B B
LAN_MDO0- 2 GND_1
PR1-
LAN_MDO1+ 3
PR2+ CHASSIS1_GND
RL14 1 EMC_NS@
2 0_0603_5% LAN_MDO2+ 4
PR3+
RL15 1 EMC_NS@
2 0_0603_5% LAN_MDO2- 5
PR3-
RL16 1 EMC_NS@
2 0_0603_5% LAN_MDO1- 6
PR2-
EMC LAN_MDO3+ 7
PR4+
LAN_MDO3- 8
CHASSIS1_GND PR4-

SANTA_130460-3

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 LAN_Transformer
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 38 of 60
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

Close to U1 REMOTE2+
REMOTE+_R R176 1 @ 2 0_0402_5% REMOTE2+ 1
Near CPU core

1
REMOTE+_R C46 C
1 100P_0402_50V8J 2 Q16
C44 REMOTE-_R R177 1 @ 2 0_0402_5% REMOTE2- @ B MMBT3904WH_SOT323-3
2200P_0402_50V7K 2 E @

3
@ REMOTE2-
2 REMOTE-_R

D REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-: +3VALW D

Trace width/space:10/10 mil Near CPU

Trace length:<8"

1
R25
SMSC thermal sensor 13.7K_0402_1%

placed near DIMM

2
NTC_V2
+3VS

1
U1
1 8 EC_SMB_CK2 PH3
VDD SCL EC_SMB_CK2 {7,44}
100K_0402_1%_NCP15WF104F03RC
1 REMOTE+_R 2 7 EC_SMB_DA2
D+ SDA EC_SMB_DA2 {7,44}
C47

2
.1U_0402_10V6-K REMOTE-_R 3 6
@ D- ALERT#
2 R51 2 @ 1 4 5
+3VS T_CRIT# GND
10K_0402_5%
NCT7718W_MSOP8 @
Address 1001_101xb

+5VLP +5VLP for layout optimized, change the EC_AGND to GND

C +5VLP C

HW thermal sensor

2
C7 R252 R253
1

0.1U_0402_25V6 21.5K_0402_1% 21.5K_0402_1%

@ @
@
2

1
@
U4
1 8 TMSNS1
VCC TMSNS1
2 7 PHYST1 R6 1 @ 2 10K_0402_5%
GND RHYST1
3 6 TMSNS2 R197 1 @ 2 0_0402_5% NTC_V2
OT1 TMSNS2 NTC_V2 {44}
4 5 PHYST2 R7 1 @ 2 10K_0402_5%
{54} EC_ON_R OT2 RHYST2
G718TM1U_SOT23-8

over temperature threshold:

RSET=3*RTMH
92+/-30C
Hysteresis temperature threshold.
RHYST=(RSET*RTML)/(3*RTML-RSET)
56+/-30C
B B

FAN Conn
+5VS

JFAN1
R52 1 @ 2 0_0603_5% +5VS_FAN 1
2 1
{44} EC_FAN_SPEED 2
3
.1U_0402_10V6-K

4 3
1 1 {44} EC_FAN_ANTI 4
C49 @ {44} EC_FAN_PWM 5
5
C50

10U_0805_10V6K 6
7 GND1
2 2 GND2
ACES_50273-0050N-001
ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 Thermal sensor/FAN CONN/TPM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 39 of 60
5 4 3 2 1
 A B C D E

Mini-Express Card(WLAN/WiMAX)
+3VS
+3VS_WLAN

JWLAN1
1 1

1
1 2
3 GND1 3.3VAUX1 4 R258 R259
{9} USB20_P7 USB_D+ 3.3VAUX2
5 6 1 @49.9K_0402_1%
T2 49.9K_0402_1%
{9} USB20_N7 USB_D- LED#1
7 8
9 GND2 PCM_CLK 10

2
11 SDIO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_IN 14
15 SDIO_DAT0 PCM_OUT 16 1 @ T3
17 SDIO_DAT1 LED#2 18
19 SDIO_DAT2 GND11 20
21 SDIO_DAT3 UART_WAKE 22 UART_RX_DEBUG_R R256 1 2 0_0402_5%
SDIO_WAKE UART_RX UART_RX_DEBUG {8}
23
SDIO_RESET

R263 1 2 0_0402_5%
KEY E UART2_RXD {8}
@
25 PIN24~PIN31 NC PIN 24
27 26 R264 1 2 0_0402_5%
29 28 UART2_TXD {8}
@
31 30

33 32 UART_TX_DEBUG_R R257 1 2 0_0402_5%

GND3 UART_TX UART_TX_DEBUG {8}
35 34
{9} PCIE_PTX_C_DRX_P6 PETP0 UART_CTS
37 36
{9} PCIE_PTX_C_DRX_N6 PETN0 UART_RTS EC_TX_RSVD
39 38 R62 1 @ 2 0_0402_5%
41 GND4 RSRVD10 40 EC_RX_RSVD R63 1 @ 2 0_0402_5%
{9} PCIE_PRX_DTX_P6 PERP0 RSRVD11
43 42
{9} PCIE_PRX_DTX_N6 PERN0 RSRVD9
45 44 R88 1 @ 2 0_0402_5%
GND5 COEX3 EC_RX {44}
47 46
{10} CLK_PCIE_WLAN REFCLKP0 COEX2
49 48
{10} CLK_PCIE_WLAN# REFCLKN0 COEX1 SUSCLK_R
2 51 50 R55 1 2 0_0402_5% 2
WLAN_CLKREQ_Q# GND6 SUSCLK PLT_RST# SUSCLK {10}
53 52
CLKEQ0# PERSTO# BT_OFF# PLT_RST# {11,32,37,44}
R262 1 @ 2 0_0402_5% 55 54 R53 1 2 1K_0402_5%
{11,37,44} PCIE_WAKE# PEWAKE0# RSRVD/W_DISABLE#2 WLAN_OFF# PCH_BT_OFF# {8}
57 56 R56 1 @ 2 0_0402_5%
GND7 W_DISABLE#1 PCH_WLAN_OFF# {8}
R57 1 @ 2 0_0402_5%
{37,44} LAN_WAKE#
59 58 WLAN_SMB_DATA R58 1 @ 2 0_0402_5%
RSRVD/PETP1 I2C_DATA WLAN_SMB_CLK SMB_DATA_S3 {7,17,18}
61 60 R59 1 @ 2 0_0402_5%
RSRVD/PETN1 I2C_CLK SMB_CLK_S3 {7,17,18}
63 62
65 GND8 ALERT 64 EC_TX_R R89 1 @ 2 0_0402_5%
RSRVD/PERP1 RSRVD6 EC_TX {44}
67 66
69 RERVD/PERN1 RSRVD7 68 +3VS_WLAN
GND9 RSRVD8

1
71 70
73 RSRVD1 RSRVD12 72 R186
75 RSRVD2 3.3VAUX3 74 100K_0402_5%
GND10 3.3VAUX4
77 76

2
GND15 GND14

LCN_DAN05-67406-0102
ME@

3 3

+3VS +3VS Need  short +3VS_WLAN

+3VS_WLAN J2 @
1 2
1 2
2

JUMP_43X79
2

R60
G

Q18 10K_0402_5%
AOAC@ +3VALW LP2301ALT1G_SOT23-3
1

WLAN_CLKREQ_Q#

D
{10} WLAN_CLKREQ# AOAC@ 3 1 Q17 3 1 AOAC@
S

.01U_0402_16V7-K
2N7002KW_SOT323-3 1 1 1
C51 C52 C53

G
2
.1U_0402_10V6-K @ .1U_0402_10V6-K
@ AOAC@
R61 1 @ 2 0_0402_5% 2 2 2
R54 1 AOAC@ 2
{44} AOAC_ON#
1
If support AOAC, NC R61; 100K_0402_5% C54
.1U_0402_10V6-K
if not support AOAC, stuff R61. AOAC@
2

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 NGFF WLAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

WWW.AliSaler.Com
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 40 of 60
A B C D E
 A B C D E

+USB_VCCA

C55 1 2

+
220U_6.3V_M
C125 1 2
@ 1U_0603_25V6M

C127 1 2
@ 1U_0603_25V6M

1 LEFT SIDE USB3.0 PORT x1 JUSB1 ME@

1

USB30_TX_P1 C126 1 2 .1U_0402_10V6-K USB30_TX_C_P1 R95 1 @ 2 0_0402_5% USB30_TX_R_P1 9

{9} USB30_TX_P1 StdA_SSTX+
1
USB30_TX_N1 C124 1 2 .1U_0402_10V6-K USB30_TX_C_N1 R96 1 @ 2 0_0402_5% USB30_TX_R_N1 8 VBUS
{9} USB30_TX_N1 USB20_P1 USB20_P1_R StdA_SSTX-
R97 1 @ 2 0_0402_5% 3
{9} USB20_P1 D+
7
+5VALW +USB_VCCA USB20_N1 R93 1 @ 2 0_0402_5% USB20_N1_R 2 GND_DRAIN 10
U2 {9} USB20_N1 USB30_RX_P1 USB30_RX_R_P1 D- GND_1
R94 1 @ 2 0_0402_5% 6 11
{9} USB30_RX_P1 StdA_SSRX+ GND_2
5 1 4 12
IN OUT USB30_RX_N1 R98 1 @ 2 0_0402_5% USB30_RX_R_N1 5 GND_5 GND_3 13
1 {9} USB30_RX_N1 StdA_SSRX- GND_4
C128 2
1U_0402_6.3V6K GND SUYIN_020053GR009M2736L
4 3 USB_OC1#
2 {44,45} USB_ON# EN FLG USB_OC1# {9}
1
SY6288D20AAC C140
1000P_0402_50V7K
Low Active 2A EMC_NS@
2

2 2

L13 EMC@
USB30_RX_P1 1 2 USB30_RX_R_P1
1 2

USB30_RX_N1 4 3 USB30_RX_R_N1
4 3
EXC24CH900U_4P
+USB_VCCA D12 EMC_NS@ USB20_P1_R
L16 EMC@ USB30_RX_R_N1 9 10 1 1USB30_RX_R_N1
USB30_TX_C_P1 1 2 USB30_TX_R_P1 USB20_N1_R

AZ5425-01F_DFN1006P2E2
1 2 USB30_RX_R_P1 8 9 2 2 USB30_RX_R_P1

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2
1
D11

1
USB30_TX_C_N1 4 3 USB30_TX_R_N1 USB30_TX_R_N1 7 7 4 4USB30_TX_R_N1 D13 D14

1
4 3

EMC_NS@

1
USB30_TX_R_P1 6 6 5 5 USB30_TX_R_P1

EMC_NS@

EMC_NS@
EXC24CH900U_4P

L8 EMC@ 3 3

2
USB20_P1 1 2 USB20_P1_R
1 2

2
8

2
USB20_N1 4 3 USB20_N1_R AZ1045-04F_DFN2510P10E-10-9
3 4 3 3
EXC24CH900U_4P

EMC EMC

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 P32-USB3.0 PORT (LEFT)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 41 of 60
A B C D E
 A B C D E F G H

SATA HDD Conn.

FOR 14"
JHDD1 ME@

1
SATA ODD Conn.
SATA_PTX_DRX_P0 C66 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P0 2 GND_1
{9} SATA_PTX_DRX_P0 A+
SATA_PTX_DRX_N0 C67 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N0 3
{9} SATA_PTX_DRX_N0 A-
4
1 SATA_PRX_DTX_N0 C68 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N0 5 GND_2 1
{9} SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C69 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P0 6 B- JODD1
{9} SATA_PRX_DTX_P0 7 B+ 1
GND_3 SATA_PTX_DRX_P1 14@ C70 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P1_14 2 GND_1
{9} SATA_PTX_DRX_P1 RX+
SATA_PTX_DRX_N1 14@ C71 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N1_14 3
{9} SATA_PTX_DRX_N1 RX-
8 4
9 V33_1 SATA_PRX_DTX_N1 14@ C72 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N1_14 5 GND_2
10 V33_2 {9} SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 14@ C73 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P1_14 6 TX-
+5VS +5VS_HDD 11 V33_3 {9} SATA_PRX_DTX_P1 7 TX+
Need  short 12 GND_4 GND_3
J3 @ 13 GND_5 ODD_DETECT#_R 8
1 2 14 GND_6 9 DP
1 2 15 V5_1 +5V_ODD 10 +5V_1
JUMP_43X79 16 V5_2 ODD_DA#_R 11 +5V_2 14
17 V5_3 12 MD GND1 15
18 GND_7 13 GND_4 GND2
19 DAS/DSS GND_5
+5VS_HDD 20 GND_8 SUYIN_127382FB013S255ZL
21 V12_1 24 ME@
22 V12_2 GND_10 23
V12_3 GND_9
1 1 1 1 1
@ @ C75 C77 C78 HIGHS_SA2S0226-1511H
C74 C76 .1U_0402_10V6-K 10U_0805_10V6K 10U_0805_10V6K
33P_0402_50V8J 33P_0402_50V8J @
2 2 2 2 2

FOR 15"
2 2

For EMC SATA ODD FFC Conn

JODD2
1
SATA_PTX_DRX_P1 15@ C79 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P1_15 2 1
SATA_PTX_DRX_N1 15@ C80 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N1_15 3 2
4 3
SATA_PRX_DTX_N1 15@ C81 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N1_15 5 4
SATA_PRX_DTX_P1 15@ C82 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P1_15 6 5
7 6
+5V_ODD 8 7
9 8
10 GND_1
Need  Short GND_2
ACES_51524-00801-001
ME@

+5VS +5V_ODD
3 3
J4
1 2
1 2
JUMP_43X79
10U_0805_10V6K

@ 1 1 .1U_0402_10V6-K

2 2
C86
C85

CD@

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 HDD/ODD CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 42 of 60
A B C D E F G H

WWW.AliSaler.Com
 5 4 3 2 1

+3VS

+3VS +3VALW_PCH RA3 1 @ 2 0_0603_5%

+3VALW +5VA AVDD_HP

.1U_0402_10V6-K

.1U_0402_10V6-K
RA2 1 @ 2 0_0603_5% +3.3VD RA44 1 2 0_0402_5%
+3VS AVDD_HP

CA11

CA12
RA5 1 @ 2 0_0603_5% 2 2
+3VL
RA11 1 2 0_0402_5% DVDD_IO
RA43 1 @ 2 0_0603_5%
+5VS 1 1

.1U_0402_10V6-K
@
2
RA7 1 @ 2 0_0603_5% +5VA CA1

RA10 1 @ 2 0_0603_5% +5VD 1 Close to Pin28 Close to Pin24

D Close to Pin3 D

Close to Pin7
DA1
{44} BEEP# 2

.1U_0402_10V6-K

4.7U_0603_10V6-K
.1U_0402_10V6-K CA16 close to Pin18
1 PC_BEEP1 CA2 1 2 PC_BEEP CA17 close to Pin2
2 1
Close to Pin27

1
{8} PCH_BEEP 3
RA14
1 2

CA3

.1U_0402_10V6-K

1U_0402_6.3V6K
BAT54CW_SOT323-3 10K_0402_5%
change the Codec PN to CX11802-33Z,, symbol check ok

CA4

CA7

CA8
2 1

.1U_0402_10V6-K
UA1

2.2U_0603_6.3V6K
2

2 1
HDA_RST_AUDIO# FILT_1.8V

CA5

CA6
9 3
{8} HDA_RST_AUDIO# RESET# FILT_1.8V 7 DVDD_IO CD@ 1 2
VDD_IO 2
HDA_BITCLK_AUDIO 5 VDDO_3.3 18 +3.3VD 1 2
{8} HDA_BITCLK_AUDIO BIT_CLK DVDD_3.3
HDA_SYNC_AUDIO 8 27 AVDD_3.3
{8} HDA_SYNC_AUDIO RA16 SYNC AVDD_3.3 29 VREF_1.65V
33_0402_5% 1 2 SDATA_IN 6 VREF_1.65V 28 +5VA
{8} HDA_SDIN0 HDA_SDOUT_AUDIO SDATA_IN AVDD_5V

.1U_0402_10V6-K

1U_0402_6.3V6K
4
{8} HDA_SDOUT_AUDIO SDATA_OUT

CA9

CA10
MICBIASB
+3.3VD

PC_BEEP 10 CX20751-11Z 12 SPK_L+

2 1
SPKR_MUTE# 39 PC_BEEP LEFT+ 14 SPK_L-
SPKR_MUTE# LEFT- DA2

4LINE_B_R
3LINE_B_L
JSENSE 38 17 SPK_R+ BAT54AWT1G_SOT323-3 1 2
JSENSE RIGHT+
2

1
37 15 SPK_R- @
GPIO1/PORTC_R_MIC RIGHT-

2
RA15 RA42
5.11K_0402_1% 36 35 0_0402_5% RA41
33_0402_5% 1 RA18 2 DMIC_CLK_R 40 MUSIC_REQ/GPIO0/PORTC_L_MIC MICBIASC 34 MICBIASB
{33} DMIC_CLK DMIC_CLK/MUSIC_REQ/GPIO0 MICBIASB 0_0402_5% Close to Pin29
0_0402_5% 1 @ 2 DMIC_DATA_R 1 RPA2
{33} DMIC_DATA
1

RA19 DMIC_DAT/GPIO1 33 LINE_B_R 100_0404_4P2R_1%

1
RA17 1 2 JSENSE .1U_0402_10V6-K PORTB_R_LINE 32 LINE_B_L
{45} PLUG_IN PORTB_L_LINE @ @
39.2K_0402_1% +5VD 1 2 11

1
2
CA13 CLASS-D_REF 30 PORTD_A_MIC
C PORTD_A_MIC C
RA36 1 2 13 31 PORTD_B_MIC
20K_0402_1% 16 LPWR_5.0 PORTD_B_MIC
RPWR_5.0

1
3K_0402_1%

3K_0402_1%
25 RING2_CONN
HGNDA 1 1

RA37

RA38
CA14 1 2 1U_0402_6.3V6K 19 26 RING3_CONN
20 FLY_P HGNDB CA35 CA36
FLY_N 24 AVDD_HP 4.7U_0603_10V6-K 4.7U_0603_10V6-K
CA17 1 2 2.2U_0603_6.3V6K 21 AVDD_HP 2 2 RPA3

2
AVEE 23 HPOUT_R 1 4
PORTA_R HPOUT_L HP_OUTR {45}
41 22 2 3
GND PORTA_L HP_OUTL {45}
82.5_0404_4P2R_1%

CD@ CD@ +5VD CX11802-33Z QFN LOW POWER CODEC

RPA1
PORTD_A_MIC 2 3 CA39 1 2 2.2U_0603_6.3V6K
PORTD_B_MIC RING3_CONN {45}
CA15

CA16

CA18

CA19
4.7U_0603_10V6-K

4.7U_0603_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

1 4 CA40 1 2 2.2U_0603_6.3V6K
RING2_CONN {45}
1 1 2 2 RA1 1 @ 2 0_0402_5%
100_0404_4P2R_1%
RA4 1 @ 2 0_0402_5%
2 2 1 1 RA6 1 @ 2 0_0402_5%

RA9 1 @ 2 0_0402_5%
JSPK1
RA12 1 @ 2 0_0402_5% 15_0402_5% 1 CD@ 2 RA25 SPK_R+ RA26 1 2 PBY160808T-221Y-N SPK_R+_CONN 1
15_0402_5% 1 CD@ 2 RA29 SPK_R- RA31 1 2 PBY160808T-221Y-N SPK_R-_CONN 2 1
RA13 1 @ 2 0_0402_5% 15_0402_5% 1 CD@ 2 RA32 SPK_L+ RA30 1 EMC@ 2 PBY160808T-221Y-N SPK_L+_CONN 3 2
15_0402_5% 1 CD@ 2 RA33 SPK_L- RA34 1 EMC@ 2 PBY160808T-221Y-N SPK_L-_CONN 4 3
Close to Pin11,13,16 4
EMC@
EMC@ 5
6 GND1
GND GNDA GND2

220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K
CA27

CA28

CA29

CA30
+3.3VD

Use 250mils wide trace bridging 2 2 2 2 1 1 1 1 ACES_88231-04001

CA31

CA32

CA33

CA34
AGND and DGND at codec ME@

RA24 1 @ 2 1 1 1 1 2 2 2 2
B B
1

0_0402_5%
RA28
47K_0402_5% HDA_RST_AUDIO# EMC@ EMC@ EMC@ EMC@
RB751V-40_SOD323-2 @
HDA_RST_AUDIO# DA3 1 2 @ HDA_SYNC_AUDIO
2

CD@ CD@ CD@ CD@

SPKR_MUTE# HDA_SDOUT_AUDIO
RB751V-40_SOD323-2
EC_MUTE# DA4 1 2 @ RA27 1 EMC@2 HDA_BITCLK_AUDIO
{44} EC_MUTE#
27_0402_5%
HDA_SDIN0
CA23

CA24

CA25

CA26

EMC@
68P_0402_50V8J

22P_0402_50V8-J

22P_0402_50V8-J

33P_0402_50V8J

33P_0402_50V8J

RA35 1 @ 2
0_0402_5% 1 1 1 1 1
CA22

2 2 2 2 2
EMC_NS@

EMC_NS@

EMC_NS@

EMC@

For EMI

DMIC_CLK

DMIC_DATA
CA37

CA38
100P_0402_50V8J

100P_0402_50V8J

1 1
A A

2 2
EMC_NS@ EMC_NS@

For EMI
Security Classification LC Future Center Secret Data Title
Issued Date 2014/12/11 Deciphered Date 2015/12/11 Codec_CX11802 & Audio jack
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 43 of 60
5 4 3 2 1
 5 4 3 2 1

For EMI RE1 1 2 0_0603_5%

For ESD EMC_NS@
+3VL B+
PLT_RST# CLK_PCI_EC RE2 1 2 10_0402_5%

1
RE3 1 @ 2 0_0603_5%
1 1 Close  EC +3VALW
RE261
CE1 CE2 +3VL_EC_R @ 470K_0402_5%
220P_0402_50V7K 10P_0402_50V8J CE3 +3VL_EC +3VL_EC
2 EMC@ EMC_NS@ 2 1 2 VCOREVCC

2
LE1 1 @ 2 B+_Track
.1U_0402_10V6-K +3VL_EC All capacitors close to EC 0_0603_5%

1
1 1
CE4 +3VL_EC R260

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K
1 1 1 1 1 1 .1U_0402_10V6-K CE5 @ 47K_0402_5%
+3VS +3VL_EC_R CE6 CE7 CE8 CE9 CE10 CE11 1000P_0402_50V7K
LE2 1 @ 2 2 EC_AGND 2

2
1
D D
@ @ 0_0603_5%
2 2 2 2 2 2 RE5
RE6 1 @ 2 0_0402_5% EC_AGND 10K_0402_5%

CD@

2
LAN_WAKE#
minimum trace width 12 mil LAN_WAKE# {37,40}

114
121
127
Change RE6 to 0ohm jump

12

11

26
50
92

74
3
UE1 +3VS

VCORE
VBAT

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VCC

VSTBY(PLL)

AVCC
EC_FAN_SPEED RE10 1 2 10K_0402_5%

EC_FAN_PWM RE11 1 @ 2 10K_0402_5%

RE56 1 @ 2 0_0402_5% 4 24 PWR_LED# LPC_FRAME# RE7 1 @ 2 10K_0402_5%

{7} KBRST# KBRST#/GPB6 PWM0/GPA0 PWR_LED# {45}
RE59 1 @ 2 0_0402_5% 5 25
+3VL_EC {7,32} SERIRQ SERIRQ/GPM6 PWM1/GPA1 BATT_CHG_LED# {45}
RE60 2 @ 1 0_0402_5% LPC_FRAME#_EC 6 28 ENBKL RE9 1 @ 2 100K_0402_5%
{7,32} LPC_FRAME# LFRAME#/GPM5 PWM2/GPA2 BATT_LOW_LED# {45}
RE61 2 @ 1 0_0402_5% LPC_AD3_EC 7 29 EC_VCCST_PWRGD
{7,32} LPC_AD3 LAD3/GPM3 PWM3/GPA3 EC_VCCST_PWRGD {11}
DE1 1 2 @ RE62 2 @ 1 0_0402_5% LPC_AD2_EC 8 PWM 30 CPU_VR_READY RE270 1 2 10K_0402_5%
{7,32} LPC_AD2 LAD2/GPM2 PWM4/GPA4 SYS_PWROK {11}
RE63 2 @ 1 0_0402_5% LPC_AD1_EC 9 31 EC_FAN_PWM
{7,32} LPC_AD1 LAD1/GPM1 PWM5/GPA5 EC_FAN_PWM {39}
RB751V-40_SOD323-2 RE64 2 @ 1 0_0402_5% LPC_AD0_EC 10 32
{7,32} LPC_AD0 CLK_PCI_EC LAD0/GPM0 PWM6/SSCK/GPA6 EC_VCCST_EN_R BEEP# {43} EC_VCCST_EN
13 LPC 34 RE54 2 @ 1 0_0402_5%
{7} CLK_PCI_EC LPCCLK/GPM4 PWM7/RIG1#/GPA7 LAN_WAKE# EC_VCCST_EN {13}
1 2 WRST# 14 120
RE8 15 WRST# TMRI0/GPC4 124 SUSP# +5VS +3VS
1 {9} EC_SMI# ECSMI#/GPD4 TMRI1/GPC6 SUSP# {46,55}
100K_0402_5% EC_RX 16
CE12 {40} EC_RX EC_TX PWUREQ#/BBO/SMCLK2ALT/GPC7 EC_Board_ID
17 66
{40} EC_TX LPCPD#/GPE6 ADC0/GPI0

2
1U_0402_6.3V6K PLT_RST# 22 67
2 {11,32,37,40} PLT_RST# LPCRST#/GPD2 ADC1/GPI1 NTC_V2 {39}
23 68 BATT_TEMP RE52 RE51
{4,8} EC_SCI# EC_RTCRST#_ON ECSCI#/GPD3 ADC2/GPI2 BATT_TEMP {52,53}
126 ADC 69 RE264 2 1 0_0402_5% SD_PWR_EN# 0_0402_5% 0_0402_5%
GA20/GPB5 ADC3/GPI3 CPU_VR_READY SD_PWR_EN# {8}
70 @ @
IT8586E/AX ADC4/GPI4 71
CPU_VR_READY
ADP_I {53}
{59}

1
ADC5/DCD1#/GPI5 72 B+_Track
ADC6/DSR1#/GPI6

{45} KSI[0..7]
KSI[0..7] KSI0 58
LQFP-128L ADC7/CTS1#/GPI7
73
ADAPTER_ID {51,53}
+3VL_EC
TP_CLK RE12 2 1 4.7K_0402_5%
KSI0/STB#

1
KSI1 59 78 SUSWARN# {11}
KSO[0..17] KSI2 60 KSI1/AFD# DAC2/TACH0B/GPJ2 79 RE65 TP_DATA RE13 2 1 4.7K_0402_5%
{45} KSO[0..17] KSI2/INIT# DAC3/TACH1B/GPJ3 H_PROCHOT#_EC MAINPWON {54}
C KSI3 61 DAC 80 100K_0402_5% C
KSI4 62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81
KSI4 DAC5/RIG0#/GPJ5 ENBKL {33}
KSI5 63

2
+3VL_EC KSI6 64 KSI5 85 EC_ON_GPIO RE57 2 @ 1 0_0402_5% +5VALW
KSI6 PS2CLK0/TMB0/CEC/GPF0 EC_ON {54}
KSI7 65 86
KSI7 PS2DAT0/TMB1/GPF1 PBTN_OUT# {11}
KSO0 36 87
EC_SMB_CK1 KSO0/PD0 GPF2 PM_SLP_SUS# {11} USB_ON#
RPE2 PAD 1 @ KSO1 37 Int. K/B PS2 88 RE15 1 2 100K_0402_5%
EC_SMB_CK1 EC_SMB_DA1 IT1 KSO1/PD1 GPF3 TP_CLK SUSACK# {11}
2 3 PAD 1 @ KSO2 38 Matrix 89
EC_SMB_DA1 IT2 KSO2/PD2 PS2CLK2/GPF4 TP_DATA TP_CLK {45}
1 4 PAD 1 @ KSO3 39 90
IT3 KSO3/PD3 PS2DAT2/GPF5 TP_DATA {45}
PAD 1 @ KSO4 40
IT4 KSO4/PD4
2.2K_0404_4P2R_5% PAD 1 @ KSO5 41 EXTERNAL SERIAL FLASH 96 Just for UMA +3VL_EC
IT5 KSO5/PD5 GPH3/ID3 CAPS_LED# {45}
KSO6 42 97
KSO6/PD6 GPH4/ID4 PCH_PWR_EN {46,56} EC_Board_ID
KSO7 43 98 RE171 1 2 100K_0402_5%
KSO7/PD7 GPH5/ID5 ACOFF {53}
KSO8 44 99
+3VS KSO8/ACK# GPH6/ID6 PCH_PWROK {11}
KSI7 PAD 1 @ KSO9 45 SUSP# RE18 1 @ 2 100K_0402_5%
IT6 KSO9/BUSY EC_SPI_CS0#
KSI6 PAD 1 @ KSO10 46 101
IT7 KSO10/PE NC1 EC_SPI_SI
RPE3 WRST# PAD 1 @ KSO11 51 102 SUSP# RE19 1 2 100K_0402_5%
EC_SMB_CK2 IT8 KSO11/ERR# NC2 EC_SPI_SO
1 4 KSO12 52 SPI Flash ROM 103 RE266
2 3 EC_SMB_DA2 KSO13 53 KSO12/SLCT NC3 105 EC_SPI_CLK SD_PWR_EN# 2 1 EC_SD_PWR_EN# SYSON_R RE21 1 2 100K_0402_5%
KSO14 54 KSO13 NC4 PCH_SDIO@
For factory EC flash KSO14 EC_VCCST_EN
2.2K_0404_4P2R_5% KSO15 55 0_0402_5% RE269 1 2 100K_0402_5%
KSO16 56 KSO15 108 ACIN#
KSO17 57 KSO16/SMOSI/GPC3 AC_IN# 109 LID_SW# EC_VCCIO_EN RE268 1 @ 2 100K_0402_5%
KSO17/SMISO/GPC5 UART LID_SW# LID_SW# {45}
@
@ ON/OFF 110 82 EC_FAN_ANTI_R RE53 2 @ 1 0_0402_5%
{45} ON/OFF PWRSW# EGAD/GPE1 EC_FAN_ANTI {39}
EC_ON RE58 2 1 0_0402_5% 111 83
EC_SMB_CK1 XLP_OUT SM Bus EGCS#/GPE2 VDDQ_PGOOD {55}
EC_SD_PWR_EN#
115 84 ADAPTER_ID_ON# {53} RE265 2 1 0_0402_5%
{52,53} EC_SMB_CK1 EC_SMB_DA1 SMCLK1/GPC1 EGCLK/GPE3 EC_SD_PWR_EN# {30}
116 @
{52,53} EC_SMB_DA1 PECI_EC SMDAT1/GPC2 PM_SLP_S4#
{4} H_PECI RE24 1 2 43_0402_5% 117 GPIO 77 RE25 2 @ 1 0_0402_5% CE50 1 2 EMC_NS@ 1000P_0402_50V7K
SMCLK2/PECI/GPF6 GPJ1 PM_SLP_S5# {11}
118 100 GPG2
{37} LAN_PWR_ON# EC_SMB_CK2 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2
94 106
{7,39} EC_SMB_CK2 EC_SMB_DA2 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 EC_MUTE# {43} PM_SLP_S5#
95 104 CE49 1 2 EMC_NS@
1000P_0402_50V7K
+3VL {7,39} EC_SMB_DA2 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 SYSON_R ME_FLASH {8}
107 RE271 2 @ 1 0_0402_5%
DTR1#/SBUSY/GPG1/ID7 SYSON {55}
119 BKOFF#
CRX0/GPC0 BKOFF# {33} PM_SLP_S3#
123 RE263 2 @ 1 0_0402_5% CE21 1 2 EMC_NS@ 1000P_0402_50V7K
CTX0/TMA0/GPB2 AOAC_ON# {40}
RE27 1 @ 2 0_0402_5% 112 18
VSTBY0 RI1#/GPD0 PM_SLP_S3# {11,13,44} EC_VCCIO_EN
RE272 2 @ 125
10_0402_5% 21 PM_SLP_S4# {11,44} RE55 1 @ 2 0_0402_5%
B {57,59} EC_VR_ON GPE4 RI2#/GPD1 EC_VCCIO_EN {13} B
WAKE UP 76 NOVO# {45} SYSON CE13 1 2 EMC_NS@
1000P_0402_50V7K
DE2 1 2 @ TACH2/GPJ0 48
{11,13,44} PM_SLP_S3# TACH1A/TMA1/GPD7 EC_FAN_SPEED EC_TS_ON# {33}
RB751V-40_SOD323-2 47 EC_FAN_SPEED {39}
USB_ON# 33 TACH0A/GPD6 19
{41,45} USB_ON# GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0

2
35 GPIO 20
{11} DPWROK_EC
93 RTS1#/GPE5 L80LLAT/GPE7 NUM_LED# {45} EMC Request
{11} EC_RSMRST# CLKRUN#/GPH0/ID0

PCIE_WAKE# 2 DE3
{11,37,40} PCIE_WAKE#

1
128 CK32KE/GPJ7 RB751V-40_SOD323-2
+3VL {11} AC_PRESENT CK32K/GPJ6 Clock
@
{11,44} PM_SLP_S4#

RE34 2 1 0_0402_5% H_PROCHOT# {4}

{53,59} VR_HOT#
AVSS

RE35 1 @ 2 10K_0402_5% ON/OFF

VSS1

VSS2
VSS3
VSS4
VSS5
VSS6

EC_RTC_RST# {10}
@

1
RE36 1 @ 2 10K_0402_5% BKOFF# 1
IT8586E-AX_LQFP128_14X14 RE267 CE14
1

27
49
91
113
122

75

RE38 1 2 LID_SW# 100_0402_5% 47P_0402_50V8J

100K_0402_5% EMC_NS@

1
2 QE3 D

1 2
EC_RTCRST#_ON 2
RE40 1 2 10K_0402_5% BKOFF# QE1 D G
EC_AGND H_PROCHOT#_EC 2 +3VL
G @ S 2N7002KW_SOT323-3

3
1
2N7002KW_SOT323-3 S RE50
for EC version update to EX,  manual modify PN to FX

2
100K_0402_5%
RE42 @
100K_0402_5%

2
PECI_EC EMC_NS@
CE15 1 2 47P_0402_50V8J

1
+3VL BATT_TEMP EMC_NS@
CE16 1 2 100P_0402_50V8J +3VS ACIN# RE262 2 @ 1 0_0402_5%
{11} ACIN#
+3VL_EC ACIN# EMC_NS@
CE17 1 2 100P_0402_50V8J

1
D QE2
1
A GPG2 RE43 2 @ 1 10K_0402_5% ON/OFF @ CE18 1 2 1U_0402_6.3V6K CE19 2 A
.1U_0402_10V6-K G ACIN {53}
GPG2 RE44 2 1 10K_0402_5% EC_SPI_CS0# RE45 1 @ 2 0_0402_5% SPI_CS0#
SPI_CS0# {7} NOVO# 2 2N7002KW_SOT323-3 S

3
GPG2 RE46 2 @ 1 10K_0402_5% EMC_NS@
EC_SPI_SI SPI_SI @
RE47 1 @ 2 0_0402_5% Check if can save the mos
SPI_SI {7}
.01U_0402_16V7-K

when mirror, GPG2  pull high
CE48

when no mirror, GPG2 pull  low EC_SPI_SO RE48 1 @ 2 0_0402_5% SPI_SO

SPI_SO {7} 1

EC_SPI_CLK SPI_CLK Security Classification LC Future Center Secret Data Title

RE49 1 @ 2 0_0402_5%
SPI_CLK {7} 2
Issued Date 2014/12/11 Deciphered Date 2015/12/11 EC ITE8586LQFP

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 44 of 60
5 4 3 2 1
 5 4 3 2 1

ON/OFF switch +3VL +3VALW

K/B Connector

2
+3VS
R82 R83
100K_0402_5% @ 100K_0402_5%
@ KSI[0..7]
R261 1 2
KSI[0..7] {44}
EMC_NS@ 14" 15"

1
0_0402_5% KSO[0..17]
KSO[0..17] {44} PWR_CAPS_LED
C133 1 2 100P_0402_50V8J JKB2 R84 R90
300_0402_5% 300_0402_5%
D15 PWR_NUM_LED C134 1 2 100P_0402_50V8J 27 15@ JKB1
NOVO# 2 GND1 28 NUM_LED# 30 31
{44} NOVO# {44} NUM_LED#

2
EMC_NS@ CAPS_LED# 26 GND2 PWR_NUM_LED 29 30 GND1 32
NOVO_BTN# {44} CAPS_LED# PWR_CAPS_LED 26 CAPS_LED# 29 GND2
1 25 28
KSO15 24 25 PWR_CAPS_LED 27 28
ON/OFF R85 1 @ 2 0_0402_5% 3 KSO10 23 24 KSO17 26 27
KSO11 22 23 KSO16 25 26
D D
BAT54CW_SOT323-3 KSO14 21 22 KSO15 24 25
KSO13 20 21 KSO10 23 24
EMC@ KSO12 19 20 KSO11 22 23
CAPS_LED# C117 1 2 100P_0402_50V8J KSO3 18 19 CAPS_LED# NUM_LED# KSO14 21 22
+3VALW +3VL KSO6 17 18 KSO13 20 21
NUM_LED# C118 1 2 100P_0402_50V8J KSO8 16 17 KSO12 19 20
KSO7 15 16 KSO3 18 19

AZ5215-01F_DFN1006P2E2

AZ5215-01F_DFN1006P2E2
15 18

2
EMC_15@ KSO4 14 KSO6 17
14 17

1
R111 R114 KSO2 13 KSO8 16
100K_0402_5% 100K_0402_5% KSI0 12 13 D22 D23 KSO7 15 16

1
@ KSO1 11 12 KSO4 14 15
KSO5 10 11 KSO2 13 14

1
KSI3 9 10 KSI0 12 13
9 12

2
ON/OFFBTN# R119 1 @ 2 0_0402_5% ON/OFF KSI2 8 KSO1 11
ON/OFF {44} 8 11
KSO0 7 EMC@ EMC_15@ KSO5 10

2
KSI5 6 7 KSI3 9 10
J5 1 2 KSI4 5 6 KSI2 8 9
KSO9 4 5 KSO0 7 8
SHORT PADS KSI6 3 4 KSI5 6 7
3 For EMC 6
@ KSI7 2 KSI4 5
J6 1 2 KSI1 1 2 KSO9 4 5
1 KSI6 3 4
SHORT PADS ACES_88514-02601-071 KSI7 2 3
KSI1 1 2
@ ME@ 1
ACES_50504-3041-001
ME@

+5VS TP_PWR TP_CLK

C R160 1 @ 2
TP/B Connector TP_DATA PWR/B Connector USB I/O Connector C

2
+3VS 0_0402_5%
JTP1 DT1
R141 1 2 1
0_0402_5% TP_CLK 2 1 EMC_NS@
{44} TP_CLK TP_DATA 3 2
.1U_0402_10V6-K

{44} TP_DATA 3
1 4
TP_P5 5 4
Right Side USB2.0 Port X 2 (USB/B)
100P_0402_50V8J

100P_0402_50V8J

1 1 5
TP_P6 6 7
EMC_NS@

EMC_NS@

6 GND1 8
2 GND2
C114

2 2
C115

C116

ACES_50503-0060N-001
ME@ AZC199-02S.R7G_SOT23-3 +3VL

1
For EMC
JPWRB1
1 +5VALW +USB_VCCB +USB_VCCB
NOVO_BTN# 2 1 U3
ON/OFFBTN# 3 2 5 1 JUSB3
LID_SW# 4 3 IN OUT 18 20
TP_LEFT Button TP_P5
TP_LEFT Button TP_P5 5 4 1
2 17 18 G2 19
C141

AZ5215-01F_DFN1006P2E2
6 5 7 1U_0402_6.3V6K GND 16 17 G1
6 GND1 16

1
8 4 3 USB_OC2# R67 1 @ 2 0_0402_5% USB20_P2_CONN 15
D17 GND2 2 {41,44} USB_ON# EN FLG USB_OC2# {9} {9} USB20_P2
R66 1 @ 2 0_0402_5% USB20_N2_CONN 14 15

1
{9} USB20_N2 14
1

5
AZ5215-01F_DFN1006P2E2

AZ5215-01F_DFN1006P2E2
ACES_50503-0060N-001 1 13
SW1 SW2 ME@ SY6288D20AAC R254 1 @ 2 0_0402_5% USB20_P3_CONN 12 13
EVQPLHA15_4P

EVQPLHA15_4P C142
A

A1

GND2 GND1

A1

GND2 GND1

{9} USB20_P3 12
1

1
DT2 DT3 1000P_0402_50V7K R255 1 @ 2 0_0402_5% USB20_N3_CONN 11
{9} USB20_N3 11

2
Low Active 2A EMC_NS@ 10
For 14" For 15"
1

1
EMC_NS@ 2 9 10

2
PLUG_IN 8 9
LID_SW# {44} {43} PLUG_IN 8
7
1 VDD 1 VDD
B1

B1

7
B

RING3_CONN
2

2
14@ 15@ 6
EMC_NS@ EMC_NS@ {43} RING3_CONN 5 6
3

2
4 5
RING2_CONN 3 4
2 CLK 2 CLK For EMC {43} RING2_CONN HP_OUTR 3
2
{43} HP_OUTR HP_OUTL 2
1
{43} HP_OUTL 1
TP_RIGHT Button TP_P6
TP_RIGHT Button TP_P6 L14 EMC_NS@ ACES_50505-0184N-P01
3 DAT 3 DAT NOVO_BTN# ON/OFFBTN# USB20_P2 1
1 2
2 USB20_P2_CONN ME@
1

USB20_N2 USB20_N2_CONN
AZ5215-01F_DFN1006P2E2

AZ5215-01F_DFN1006P2E2

B 4 3 B
4 GND 4 GND SW3 SW4 4 3
EVQPLHA15_4P

EVQPLHA15_4P
A

A1

GND2 GND1

A1

GND2 GND1

AZ5215-01F_DFN1006P2E2

AZ5215-01F_DFN1006P2E2
1

DT4 DT5 EXC24CH900U_4P

1
1

D20 D21
5 TP-L 5 TP-L

1
L17 EMC_NS@
USB20_P3 1 2 USB20_P3_CONN
B1

B1

1 2
B

B
2

14@ 15@

2
EMC_NS@ EMC_NS@
6 TP-R 6 TP-R
3

EMC@ EMC@ USB20_N3 4 3 USB20_N3_CONN

2
4 3
For EMC EXC24CH900U_4P

For 14" For 15"

PWR_LED# LED1 1 2 R142 1 2 1.5K_0402_5%

{44} PWR_LED# +5VALW
1

D16 LTW-C193TS5
AZ5425-01F_DFN1006P2E2
1
2

@
2

BATT_LOW_LED# LED2 1 2 R143 1 2 470_0402_5%

{44} BATT_LOW_LED# +3VALW
LTST-C193KFKT-LC
1

D18
AZ5425-01F_DFN1006P2E2
1
2

A A
@
2

BATT_CHG_LED# LED3 1 2 R144 1 2 1.5K_0402_5%

{44} BATT_CHG_LED# +5VALW
LTW-C193TS5
1

D19
AZ5425-01F_DFN1006P2E2
1

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 KBD/PWR/IO/LED/TP Conn.
2

@
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
check LED location and BOM structure when placement and Load BOM, PWR LED and BATT LED have the same location on 14"/15" 02/26 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 45 of 60
5 4 3 2 1
 A B C D E

Load Switch
+5VALW To  +5VS +3VS, C173 ‐‐> 2.74ms
+3VALW To  +3VS +5VS, C176 ‐‐> 2.03ms
R64 1 @ 2 0_0402_5% 3VSON
VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=16mohm Need Short
+5VALW U13 +5VS
1 14 J12 @
2 VIN1_1 VOUT1_2 13 +5VS_LS 1 2
1 VIN1_2 VOUT1_1 1 2 1

1 5VSON 3 12 C176 1 2 1000P_0402_50V7K JUMP_43X118 1

SUSP# R27 1 @ 2 0_0402_5% 5VSON EN1 SS1
C177 +5VALW 4 11 C174 @
1U_0402_6.3V6K BIAS GND 0.1U_0402_10V7-K
+3VALW 2 3VSON 5 10 C173 1 2 2200P_0402_25V7-K 2 +3VS
1 1 EN2 SS2 J11 @
C180 C179 6 9 +3VS_LS 1 2
1U_0402_6.3V6K 1U_0402_6.3V6K 7 VIN2_1 VOUT2_2 8 1 2
2 2 VIN2_2 VOUT2_1 JUMP_43X118
1 1
15
C178 GPAD C175 @
1U_0402_6.3V6K
Need Short
G5016KD1U-TRG_TDFN14_2X3 0.1U_0402_10V7-K
2 @ 2

2 2
+3VALW Need  short +3VALW_PCH
+5VALW
J7 @
1 2
1 2
1

JUMP_43X79

22U_0603_6.3V6-M
R155 1

C1103
100K_0402_5% @
@ LP2301ALT1G_SOT23-3 Id=3.2A
2

PCH_PWR_EN#_R 2 100K_0402_5% PCH_PWR_EN# 2

D
R158 1 @ Q29 3 1 @

1
1

Q30 D C130

G
2
PCH_PWR_EN 2 0.01U_0402_25V7K
{44,56} PCH_PWR_EN G @
2
@ S 2N7002KW_SOT323-3
3
1

PCH_PWR_EN#_R

R162 1
100K_0402_5% C131
@ .1U_0402_10V6-K
2

@
1

2
R87
100K_0402_5%
@
2

3 3

+5VLP
+5VALW
For DisCharge
1

R156 +0.675VS
100K_0402_5% R157
100K_0402_5%
1

@
2

R159
2

SUSP @ 47_0603_5%
{34} SUSP
2
1

Q10 D D Q11
2 @ 2 SUSP
{44,55} SUSP# G G

S 2N7002KW_SOT323-3 2N7002KW_SOT323-3 S
3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 DC V TO VS INTERFACE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
BMWQ1&2_UMA
WWW.AliSaler.Com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Monday, July 27, 2015 Sheet 46 of 60

A B C D E
 5 4 3 2 1

B2 A2
D
+3VLP PCH_PWR_EN# 2 D

Q25,+3V_PCH

V
V
AC A1
MODE VIN

V V
A2 A4 B5
3 +3V_PCH

V
PU301 PU904

V
B+
+3VALW
BATT BATT V 1
DPWROK_EC
V
MODE

V V V
B1
4
PCH_RSMRST#
EC 14
PM_DRAM_PWRGD
5 PBTN_OUT#

V
EC_ON PM_SLP_S3# PCH 15
PM_SLP_S4# H_CPUPWRGD CPU

V V
A3 B4
PM_SLP_S5#
PM_SLP_SUS# 6

V
CPU_PLTRST# 16
12
PCH_PWROK

V V
C C

B3 13
SYS_PWROK

V
ON/OFF V
NOVO

NVDD_PWR_EN
(DIS)
Vb
+VGA_CORE

V
11 VR_REDY SYSON 7 +1.35V
PU801

V
PU501
DGPU_PWROK
DGPU_PWR_EN
10
Va (DIS)

V
PU901 VR_ON +1.5VS_VGA

V
Q31
V

PU601

V
+CPU_CORE
+5VS

B B

V
Q32 +1.05VSP_VGA

V
SUSP#,SUSP 9 +3VS PU702

V
VGA

V
PU602
+1.5VS +3VS_VGA

V
Q27

V
PU502
+0.675V
8
SUS_VCCP PU701
V
+1.05VS

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 Power sequence Block
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 47 of 60
5 4 3 2 1
 5 4 3 2 1

PCB

ZZZ5
ZZZ4

PCB PN
PCB PN DAZ0YM00200
DAZ0YJ00200 15@
D
14@ PCB_MB PCB_MB D

CPU

UC1 6100@ UC1 6200@ UC1 6500@

CPU CPU CPU

SA00007GV20 SA00007GP20 SA00007GM20
CPU CPU

HDMI

ZZZ6
C C

HDMI
RO00000040J
HDMI@

Board ID
B B

BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3 Description Stuff Resistor

0 0 0 1 14" + Jet-LE + Single-Rank sku RC107,RC108,RC109,RC121

*
0 0 1 1 14" + Jet-LE + Dual-Rank sku RC107,RC108,RC102,RC121

0 1 0 1 15" + Jet-LE + Single-Rank sku RC107,RC101,RC109,RC121

0 1 1 1 15" + Jet-LE + Dual-Rank sku RC107,RC101,RC102,RC121

1 0 0 1 14" + Topaz-XT + Single-Rank sku RC100,RC108,RC109,RC121

1 0 1 1 14" + Topaz-XT + Dual-Rank sku RC100,RC108,RC102,RC121

1 1 0 1 15" + Topaz-XT + Single-Rank sku RC100,RC101,RC109,RC121

1 1 1 1 15" + Topaz-XT + Dual-Rank sku RC100,RC101,RC102,RC121

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 Virtual symbol
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
BMWQ1&2_UMA
WWW.AliSaler.Com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Monday, July 27, 2015 Sheet 48 of 60
5 4 3 2 1
 5 4 3 2 1

H33 H34 H35

HOLEA HOLEA HOLEA
PCB Fedical Mark PAD
NH1 NH3 NH4
HOLEA HOLEA HOLEA FD1 FD2 FD3 FD4 FD5 FD6

1
1

1
D D

PAD_C2P5D2P5N PAD_O2P5X2P8D2P5X2P8N PAD_O2P5X2P8D2P5X2P8N PAD_SHAPE18P0X9P44 PAD_R46P0X2P49 PAD_R12P0X2P49

H5 H6 H25 H26 H27 H32

H1 H3 H4 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
HOLEA HOLEA HOLEA

1
1

1
PAD_RT8P0X11P0D2P8
pad_ct8p0d2p8 Pad_ct8p0b9p0d2p8 Pad_ct8p0b9p0d2p8 PAD_SHAPET9p0X8P0B9P0D2P8 PAD_Shapet9p0x8p0b7p0d2p8 pad_cb5p0d3p3 PAD_C8P0 PAD_C8P0

C C

H14 H17 H31 H20 H24 H7 H8 H9 H11 H21

HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

1
CHASSIS1_GND
PAD_CT6P0B8P0D2P3 pad_cb8p0d2p5 PAD_OT6P0X5P5D3P3X2P8 pad_c5p5d3p3 PAD_CT5P0B6P0D2P3 pad_c5p0d4p0 pad_c5p0d4p0 pad_c5p0d4p0 PAD_CB9P0D2P5
PAD_CT8P0B7P0D2P5

B B
GP1 GP2 GP3 GP4 GP5 GP6 GP7 GP8 GP13 GP14
PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 PAD_RT2P65X2P2 pad_R2P6X0P4 pad_R2P6X0P4
@ @ @ @ @ @ @ @ @ @
1

1
1

1
LED side for ESD
GP15 GP16
PAD_R4P72X1P9 PAD_R4P72X1P9
GP9 GP10 @ @
PAD_RT2P21X2P99 PAD_RT2P21X2P99

1
@ @ GP11 GP12

1
PAD_RT2P65X2P2 PAD_RT2P65X2P2
1

@ @ FFC CONN GROUND PAD

1

1
1

For EMC
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/12/11 Deciphered Date 2015/12/11 Hole
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&2_UMA
Date: Monday, July 27, 2015 Sheet 49 of 60
5 4 3 2 1
 5 4 3 2 1

Silergy

D
SY8288RAC +1.0VALW/7.5A D

QFN20_3X3
Converter
SUSP# EN PGOOD
FOR PCH

B+
+5VLP/ 100mA
Silergy
SYX198CQNC +5VALW/6A
Adaptor Converter
EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD
PAGE 39

+3VLP/ 100mA
Silergy
SY8286BRAC
QFN20_3X3 +3VALW/ 5A ANPEC
Converter APL5930CKAI-TRG
C EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD
+1.8VALW/1A C
PAGE 39 SO8
EN PGOOD

Richtek +1.35V/14A
NB685GQ-Z
SYSON S5 QFN16_3X3
SUSP# S3 +0.675VS/2A
TI Switch Mode
FOR DDR PGOOD
BQ24780SRUYR
Battery Charger
Switch Mode
Onsemi CPU Core/23A
PAGE 46
NCP81206MNR2G VCCGT/25A
QFN60_7X7
Switch Mode VCCSA/7A
VR_ON
SMBus EN FOR CPU Core PGOOD VGATE
B
PGOOD_NB B

Battery MPS
Li-ion NB681GD-Z_
4S1P QFN13_2X3 +VCCOPC_1.0V/4.5A
VIDs
Switch Mode
VR_ON EN
PGOOD

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Power Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&Q2
Date: Monday, July 27, 2015 Sheet 50 of 60
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

VIN
7A_24VDC_429007.WRML

JDCIN1 PF101 PJ101

1 APDIN 1 2 APDIN1 2 1
1 2 2 1
2 3 @ JUMP_43X118
3 ADAPTER_ID 44,53

470P_0402_50V7K
4
4

1000P_0402_50V7K

470P_0402_50V7K

1000P_0402_50V7K
5
5

EMC@
1

1
EMC@
PC101

PC102

PC103

PC104
D ACES_50299-00501-003 D

EMC@

EMC@
ME@

2
+3VL

1
PR1015
1.5K_0402_5%

2
VCCRTC

1
PR1016
45.3K_0402_1%
PD101
RTC_VCC

2
2

1 RTC_VCC 20MIL
JRTC1 +3VL 20MIL
C 3 2 PR101 1 1 C
2 1 VCCRTC 20MIL
1K_0603_5% 3 2
G1
2

@ BAT54CW_SOT323-3 4
PC105 G2
1U_0402_6.3V6K ACES_50273-0020N-001
1

ME@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 DCIN / RTC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&Q2
Date: Monday, July 27, 2015 Sheet 51 of 60
5 4 3 2 1
 5 4 3 2 1

ME@
SUYIN_125022HB008M202ZL VMB2
8A_24V_F1206HI8000V024T VMB EMC@
D JBATT1 D
PF201 HCB2012KF-121T50_0805
1 PL201
1 2 1 2 1 2
2 EC_SMCA BATT+
9 3 PR202 1 2100_0402_1% EC_SMB_CK1 44,53
10 GND1 3 4 EC_SMDA 1 2 1 2
GND2 4 EC_SMB_DA1 44,53
5 PR201 100_0402_1%
5 6 PL202
6 7 HCB2012KF-121T50_0805
7

2
8 EMC@
8

1
PC201 PC202
1000P_0402_50V7K 0.01U_0402_25V7K

2
EMC@ EMC@

PD201

EMC_NS@

AZC199-02S.R7G_SOT23-3

1
Reverse PD201 PD202 For EMI request

PR209
1 2 +3VALW
100K_0402_1%

PR213
C BATT_TEMP_IN 1 2 C
10K_0402_5%
BATT_TEMP 44,53 A/D
1

PD202
1

EMC_NS@
AZ5215-01F_DFN1006P2E2
2
2

B+ PR227 1 @ 2 0_0603_5%
+20VSB

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 BATTERY CONN/OTP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

WWW.AliSaler.Com
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&Q2
Date: Monday, July 27, 2015 Sheet 52 of 60
5 4 3 2 1
 5 4 3 2 1

AON6414AL_DFN8-5
VIN PQ311 P3
PQ312
P2 AON7408L_DFN8-5 @ PR301
1 PJ301 0.01_1206_1%
2 1 JUMP_43X118
5 3 2 S1 5 1 2 1 4
3 S2 D 1 2 B+
S3

1000P_0402_50V7K

1000P_0402_50V7K
2 3

0.1U_0402_25V6
G
D D

EMC@
10U_0603_25V6-M

10U_0603_25V6-M

0.1U_0402_25V6
0.022U_0402_25V7K
4

2
EMC@
PC311

PC317

PC331
EMC_NS@

EMC_NS@
4
1

2
PC303

PC304

PC312
EMC_NS@

EMC_NS@
1

PC302

1
PC301 PR302

1
4.7_0603_5%

2
470P_0402_50V7K AON7408L_DFN8-5

5
0.1U_0402_25V6

2
PQ314

D
PC305
1 2

BQ24780_BATDRV 4
G

1
3 1

D
PC306

S3
S2
S1
@ PQ313 PC307 0.1U_0402_25V6

1
2N7002KW_SOT323-3 1U_0603_25V6K

3
2
1
2
PR303

G
499K_0402_1% PC308

2
2 1 2 1 0.01U_0402_25V7K

1
VIN BATT+

2
1M_0402_5% 1M_0402_5%
PR304 PR305
@ @

BAT54CW_SOT323-3
PD302
2

3
B+

2200P_0402_50V7K
PQ315
2N7002KW_SOT323-3

10U_0805_25V6K

10U_0805_25V6K
VIN

1
1

2
EMC@
PC310

PC313
4.02K_0603_1%

4.02K_0603_1%
D

ACN
ACP
PR310

PR311

PC314
1 2 2
44 ACOFF
PR309 G

1
2
0_0402_5% AON7408L_DFN8-5
2

5
@ S PR314 BQ24780_VDD
@
3

1
C PR313 10_1206_5% PQ316 C

D
PR312 64.9K_0603_1% 1U_0603_25V6K

ACP

ACN
10K_0402_1% 1 2 432K_0603_1% PC315

1
@ PR315 2 1 780_VCC 28 24 1 2
1

2
VCC REGN 2.2U_0603_10V6-K PC316 4
1 2 ACDET 6 G
PC309 ACDET PR316 PC318

S3
S2
S1
0.1U_0402_25V6 25 BST_CHG
1 2 2 1
BTST 2.2_0603_5% PR317

3
2
1
BQ24780SRUYR_QFN24_4X4 0.047U_0603_16V7K 4.7UH_PCMB063T-4R7MS_5.5A_20% 0.01_1206_1%
3 26 DH_CHG PL302
CMSRC HIDRV 1 2 CHG 1 4 BATT+
@ 2 PR339 1 20K_0402_1% 4
ACDRV 2 3
AON7408L_DFN8-5

1
100K_0402_1% 2 PR324 1 @ 27 LX_CHG
BQ24780_VDD PHASE

10U_0805_25V6K

10U_0805_25V6K
@ 0_0402_5% PQ317 PR321

2
ACIN_R 2.2_0805_5%

PC319
PR325 1 2 5
44 ACIN ACOK

PC320
@ 0_0402_5% EMC_NS@
PR320 1 2 EC_SMB_DA1_R 11

1
44,52 EC_SMB_DA1 SDA PU301 23 DL_CHG 4
@ 0_0402_5% LODRV G

1
PR322 1 2 EC_SMB_CK1_R 12 22

S3
S2
S1
44,52 EC_SMB_CK1 SCL GND PC321
@ 0_0402_5% 1200P_0402_50V7-K

3
2
1

2
PR323 1 2 ADP_I_R 7 29 EMC_NS@

0.1U_0402_25V6

0.1U_0402_25V6
44 ADP_I IADP PAD

1
BQ24780_BATDRV

PC322

PC323
IDCHG 8 18
IDCHG BATDRV
9 PR338 10_0603_5%
Psys

2
PMON 17 2 1
BATSRC
100P_0402_50V8J

100P_0402_50V8J
2

20 SRP_R 2 1 SRP
10 SRP 10_0603_5%
100P_0402_50V8J

44,59 VR_HOT# PR328

PROCHOT#

1
PC324

PC325
1

2
PC326

13 PC327
CMPIN
0.1U_0402_25V6

2
BATPRES#
TB_STAT#
14
1

CMPOUT 19 SRN_R 2 1 SRN

B
ILIM 21 SRN PR329 10_0603_5% B
ILIM
2

PR330

16

15
0_0402_5%
+3VALW VIN @
1

1 2 ILIM_R 1 2 TB_STAT#
+3VALW BATT_TEMP 44,52
PR331 14.7K_0402_1%
316K_0402_1% PR332
1

1
1

PR334 PR333
750_0603_1% @ PC328 100K_0402_1%
PR335 0.1U_0402_25V6
2

1M_0402_5%
2

2
2

@
2

D PQ310A
PR336 2 ADAPTER_ID_ON#_G
0_0402_5% G
@
S 2N7002KDWH_SOT363-6
1

@
ADAPTER_ID 44,51
1

3
680P_0402_50V7K

D
5 ADAPTER_ID_ON# 44
1

PR337 @ G
1M_0402_5%
0.1U_0402_25V6

1
PC329

S PQ310B
2

4
1

1
PC330

PD304 2N7002KDWH_SOT363-6
A AZ5123-01F.R7G_DFN1006P2X2 A
2

@
2

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 CHARGER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&Q2
Date: Monday, July 27, 2015 Sheet 53 of 60
5 4 3 2 1
 5 4 3 2 1

+3VALW

2
PR407
D
100K_0402_5% D
@
B+ @

1
PJ401 1.5A PU401
2 1 +3V_VIN 5 9 +3V_PWRGD
2 1 4 IN1 PG 1 +3VBS 1 2

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
3 IN2 BS

1
PC403

SY8286BRAC_QFN20_3X3
2 IN3 +3VALW

PC401

PC402

PC452
JUMP_43X79 0.1U_0603_25V7-M
IN4 6 @
4A

2
EMC@ 7 LX1 19 PL401 PJ402
8 GND1 LX2 20 +3VLX 1 2 +3VALW_P 2 1
18 GND2 LX3 2.2UH_PCMB063T-2R2MS_8A_20% 2 1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
21 GND3
GND4

1
@ 0_0402_5% JUMP_43X79
EC_ON_R +3VALW_EN +3VALW_P

PC434

PC432

PC431

PC435
PR414 1 2 2 1 12 14 PR403
44 EC_ON 0_0402_5% +3V_VIN 11 EN1 OUT 2.2_0805_5%

2
PR415 EN2 13 +3VALW_FB EMC_NS@
10 FF

2
15 NC1
NC2 100mA +3VLP

1
39 EC_ON_R

1M_0402_5%
16 17

0.1U_0402_25V6
NC3 LDO

1
PR401
1

PC408
PR417 PC410

4.7U_0603_6.3V6K
1
2 1 @ 1200P_0402_50V7-K

2
44 MAINPWON

PC409
0_0402_5% EMC_NS@

2
2

2
PR429
330_0603_5%
@
1 1

D PC411
PQ405 PR405
1

2 1 2 1 2
PR427 G PC425
100K_0402_5% 2.2U_0603_10V7K 1000P_0402_50V7K 1K_0402_1%
+3VL
2

@ S @
+3VLP
3

2N7002KW_SOT323-3 @
2

PJ404
@ 2 1
2 1
C C

JUMP_43X39

+3VALW

2
PR406
100K_0402_5%
@
B+

1
@ PU402
PJ405
2 1
2.5A +5V_VIN 8 2 +5V_PWRGD
2 1 IN PG
10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

SYX198CQNC_QFN10_3X3
1

1
PC413

PC414

PC415
+5VALW
PC412

JUMP_43X79 9 6 +5VBS 1 2
GND BS 3.3UH_PCMB063T-3R3MS_6.5A_20%
5A
2

EMC@ PC416 0.1U_0603_25V7-M PL402 PJ406

1 2+5VVCC 5 10 +5VLX 1 2 +5VALW_P 2 1
VCC LX 2 1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1U_0603_25V6M PR410 @ 0_0402_5%

1
EC_ON_R 2 1 +5VALW_EN 1 4 +5VALW_OUT1 2+5VALW_P JUMP_43X79
B EN OUT B

PC417

PC418

PC419

PC420
0_0402_5% PR411
PR409 2.2_0805_5% @
100mA

2
+5VFB 3 7 EMC_NS@
FB LDO +5VLP
2
1M_0402_5%

4.7U_0603_6.3V6K
1

1
1

1
PR412

PC422

@ PC421 PC423
2

0.1U_0402_25V6 1200P_0402_50V7-K
2

EMC_NS@
2

PC424 PR413
1 2 1 2

6800P_0402_25V7-K 1K_0402_1%

6800pf soft start 2ms

47nf soft start 7ms

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 PWR_3VALW/5VALW

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&Q2
Date: Monday, July 27, 2015 Sheet 54 of 60
5 4 3 2 1
 A B C D

1 1

B+ @ 2A
PJ501
2 1 1.35V_B+
2 1

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
1

1
EMC@
PC503

PC504

PC505
JUMP_43X79 @
2

2
0.1U_0603_25V7-M
PU501 0_0603_5% PC506
1 10 BST_1.35V 1 PR506 2 2 1 PL501 @
VIN BST 0.68UH_PCMB063T-R68MS_16A_+-20% PJ502
PR501 0_0402_5% 9 LX_1.35V 1 2 1.35V_L 2 1
S3_1.35V SW 2 1
+1.35V

NB686GQ-Z_QFN16_3X3
1 2 16
5 CPU_DRAMPG_CNTL EN1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
PR503 JUMP_43X118
@ 44 SYSON 1 2 S5_1.35V 15 13 1.35V_FB @ 220P_0402_50V7K
EN2 FB

1
EMC_NS@

PC515

PC516

PC517

PC518

PC519
2.2_0805_5%
0_0402_5% 0_0402_5% 2 1 2 1
44 VDDQ_PGOOD 1A UMA ------8A

PR508
2 PR511 1 1M_0402_5% @ PC510
44,46,58SUSP# 1.35V_L

0.1U_0402_10V7K

0.1U_0402_10V7K
2 1 12 6 PR513
+0.675VSP

2
PR502 100K_0402_1% PG VDDQ
2

2
PC501 @

DDR_3V3

PC502
3

2
3V3

1
499_0402_1%

41.2K_0402_1%
1U_0402_6.3V6K
@ 5

1.35V_SN
VTT

PR512

PR509
@
1

2
@
1200P_0402_50V7-K
PC509
4.7_0402_5%
4
AGND

PR507 2
8
VTTS

EMC_NS@
2

2
PGND

PC512
22U_0603_6.3V6-M
7 VTTREF
VTTREF @

1
1
PC508
Mode 14 11 PJ504

1
MODE OTW#

1U_0402_6.3V6K
2
+0.675VSP 2 1 +0.675VS
2

1.35V_FB 2 1

2
2

PC511
1.35V_GND
PR504 JUMP_43X79
+3VALW

1
0_0402_5%

2
PR510
32.4K_0402_1%

1
1.35V_GND

2
1.35V_GND

1.35V_GND

PJ505
1 2

JUMPER
@

1.35V_GND

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 1.35VS/+0.675VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&Q2
Date: Monday, July 27, 2015 Sheet 55 of 60
A B C D
 A B C D

+5VALW

500mA

1
PC601
1U_0402_6.3V6K TP Pin connect to GND +1.8VALW_L +1.8VALW

2
500mA
1 PU601 1

PJ601 6 PJ602
2 1 +1.8VALW_VIN 5 VCNTL 3 2 1
+3VALW 2 1 9 VIN VOUT1 4 2 1
TP VOUT2

22U_0805_6.3V6M
JUMP_43X39 JUMP_43X39

1
2 1 EN_+1.8VALW 8 @
44,46,52,56 PCH_PWR_EN EN

1
+1.8VALW_FB

PC604
@ 0_0402_5% 7 2 PC603 @

GND
POK FB

.1U_0402_10V6-K
PC602 PR604 PR602 220P_0402_50V7K

2
4.7U_0603_6.3V6K 30K_0402_1%

PC607
@ APL5930CKAI-TRG_SO8

2
100K_0402_5%
1
2

PR617
@

1
PR605

2
23.7K_0402_1%

+3VALW

2
+3VALW
2 2

1
PR607
10K_0402_5%
@
B+

2
PJ603 PU602
2 1 VIN_+1.0VALW 2 9 0.1U_0603_25V7-M
2 1 IN1 PG +1.0VALW
10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

3 PC619 @
IN2
1

JUMP_43X79 4 1 +1.0VALW_BS 1 2 PL602

IN3 BS PJ604
1
PC608

PC609

PC610

@ EMC@ @ 5 0.68UH_PCMB063T-R68MS_16A_+-20%
IN4 6 +1.0VALW_LX 1 2 +1.0VALW_L 2 1

SY8288RAC_QFN20_3X3
2

7 LX1 19 2 1
2

8 GND1 LX2 20
GDN2 LX3 JUMP_43X118

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
100K_0402_5% 18
GND3

1
330P_0402_50V8J
@ PR608
2.2_0805_5%

PC611

PC612

PC613

PC614
PR614 14
+1.0VALW_ILNT FB

PC618
1 2 13 EMC_NS@
+3VALW

2
ILMT

1
1 2
1

10K_0402_5%
PR616 1 2 +1.0VALW_EN 11 17 +1.0VALW_LDO +1.0VALW
PCH_PWR_EN

2 2
EN VCC

1
1M_0402_5% PC615

1
@ PR610 10 1200P_0402_50V7-K PR613
TDC :7.68A

2
15 NC1 12 EMC_NS@ PR618 20K_0402_1%
+3VALW
2

BYP NC2
1

16 PC632 1K_0402_1%
OCP :14A

2
PC616 NC3 21 4.7U_0603_6.3V6K

2
TP
1

.1U_0402_10V6-K
2

1
3 PC627 +1.0VALW_FB 3

4.7U_0603_6.3V6K
2

1
PR612
29.4K_0402_1%

2
4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 +1.8VAWL/+1.0VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

WWW.AliSaler.Com A B
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C
Custom

Date: Monday, July 27, 2015

D
BMWQ1&Q2
Sheet 56 of 60
0.1
 5 4 3 2 1

D D

ZVM#
{44,46,52,56}

1
100K_0402_1%
U23E@ U23E@
PR710

PR732

U23E@
PR734 PC737
0_0402_5% 2.2_0603_1% 0.1U_0603_25V7-M
U23E@ 1 2 2 1

2
1A

9
B+
4.5A

MODE

BST
LP#
PJ705
2 1 +VCCOPC_VIN 1 U23E@ +VCCOPC_L +VCCOPC_1.0V
2 1 VIN 0.56UH_PH041H-R56MS_5.4A_20%

10U_0805_25V6K

10U_0805_25V6K
JUMP_43X79 PL701 PJ706

0.1U_0402_25V6
1

1
8+VCCOPC_LX

U23E@
PC722

PC720

U23E@

PC750

U23E@
@ 1 2 2 1
PU701 SW 2 1
NB681GD-Z_QFN13_2X3 JUMP_43X79

2
12 1 2 @
+VCCOPC_EN 5 VOUT 2.2_0603_1%
EN

1
PR736

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1

1
U23E@
PR721 U23E@

@
PC716

PC721

PC717

U23E@
1 2 3 PR717
44 EC_VR_ON C1 2.2_0805_5%

2
0_0402_5% EMC_NS@

2
2

47K_0402_5%

U23E@ 4 2
C0 PGND
1
PR719

1200P_0402_50V7-K
1
3V3
11

EMC_NS@
PC719

PG
AGND

PC718
C .1U_0402_10V6-K C
2
1

13

10

2
@ @ U23E@ PR722

U23E@
PR701 1 2
VCCOPC_SENSE 44
U23E@ 5.1_0402_1% 0_0402_5%
+3VS 2 PR718 1 2 1 U23E@
+3VALW
0_0402_5%
PR708 100K_0402_5% 1 2

1U_0402_6.3V6K
VSSOPC_SENSE 44

1
1 2

PC732

U23E@
PR723
0_0402_5%
U23E@

2
VCCOPC_GND U23E@

1 2

0_0402_5% VCCOPC_GND
PR709
U23E@

PJ701
1 2

JUMPER
@

VCCOPC_GND

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 +0.95VS_VGA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&Q2
Date: Monday, July 27, 2015 Sheet 57 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 PWR-VGA_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&Q2
Date: Monday, July 27, 2015 Sheet 58 of 60
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

+VCCST_CPU
+5VS +5VS
B+

2
2.2_0603_5% 2.2_0603_5%

1
PR922 PR926
+VCCST_CPU

1
75_0402_1%
1K_0402_1%

100_0402_1%
45.3_0402_1%
PC918

PR923

PR933

PR943

PR932
1U_0402_6.3V6K

2
@

2.2U_0603_10V7K

2.2U_0603_10V7K
D D

2
Psys

PC912

PC916

VR_VCC

VR_VRMP
VR_PVCC
1

1
PC920

1
0.01U_0402_25V7K

1K_0402_1%

1K_0402_1%
@

2
PR945

PR946
PR944 PR936
54.9_0402_1% @ @ 10_0402_1%
VR_SVID_DAT_1 2 1

18

13

12
VR_SVID_DAT 12
20K_0402_1% PU901 NCP81206MNTXG_QFN52_6X6 PR937

2
1 PR940 2 50 36 VR_SVID_DAT_1 0_0402_5%

VRMP
PVCC

VCC
PSYS SDIO 38 VR_SVID_CLK_1 VR_SVID_ALRT#_1 2 1
SCLK 37 VR_SVID_ALRT#_1 VR_SVID_ALRT# 12
@ 0_0402_5% PR938
PR916 1 2 VR_EN 41 ALERT# 49.9_0402_1%
44 EC_VR_ON EN VR_SVID_CLK_1 2 1
VR_SVID_CLK 12
39
DRON DRON 60
42
44 CPU_VR_READY VR_RDY
35
44,53 VR_HOT# VRHOT# PR919 PC910
26 Vcore_BST 1 2 1 2
BST3 23.2K_0402_1%
2.7K_0402_1% 1500P_0402_50V6-K
VCORE PORTION 2.2_0603_5% 0.22U_0603_16V7K 1 PR947 2
Vcore_COMP Vcore_PH 59,60
1 PR903 2 2 1 PC902 30 25
COMP_1a HG3 Vcore_HG 60
20K_0402_1%
1 2 2 PR901 1Vcore_ILIM 31 22K_0402_1% PH905
PC901 15P_0402_50V8J 1 2 ILIM_1a 24 1 PR948 2 1 2
SW3 Vcore_PH 59,60 +CPU_CORE 12,60
1.58K_0402_1% 1000P_0402_50V7K PC909
1 PR913 2 Vcore_VSP 28 100K_0402_1%_NCP15WF104F03RC
12 VCORE_VCC_SEN VSP_1a
1 2 1 2 23
LG3/ICCMAX_1b Vcore_LG 60
2

PC913 PR910 PC904 1000P_0402_50V7K 1K_0402_1% 11K_0402_1% 1 2

1000P_0402_50V7K 1.58K_0402_1% 1 PR911 2 Vcore_VSN 29 1 PR941 2 PC942 3300P_0402_50V7-K
470P_0402_50V7K VSN_1a
1

1 2 2 1 Vcore_IOUT 34 33 Vcore_CSP 1 2
12 VCORE_VSS_SEN IOUT_1a CSP_1a
330P_0402_50V7K PC906 PC911 PC922 2200P_0402_50V7K
2 1 27 32
PR917 TSENSE_1ph CSN_1a
C C
45.3K_0402_1%
Vcore_TSENSE
VCCGT PORTION 180K_0402_1%
1

7 GT_CSSUM 1 PR949 2
CSSUM_2ph GT_PH1 59,60
PR942 U23E@
MOSFET

0_0402_5% 6 GT_CSCOMP PR950 1 2 180K_0402_1% 1 2 PR904 1 2

CSCOMP_2ph GT_PH2 59,60
470P_0402_50V7K 110K_0402_1% PR1018
100K_0402_1%_NCP15WF104F03RC

2 1 PC930 1 2 180K_0402_1%
2

PH901 1 2 PC925 U23E@

2 1 GT_IOUT 1 U23E@ 220K_0402_5%_ERTJ0EV224J 220P_0402_50V7K
IOUT_2ph
1

5 GT_ILIM 2 1 2 1
8.25K_0402_1%

25.5K_0402_1%
.1U_0402_10V6-K

ILIM_2ph
1
Place close to

PH902

PR931

PC924

PR959 150K_0402_1% PR951 16.9K_0402_1% PC914 330P_0402_50V7K 10_0402_1%

1 PR902 2 8 GT_CSREF 1 PR924 2
CSREF_2ph +VCC_GT 12,60
U23E@

0.22U_0603_16V7K
2

GT_DIFFOUT 2 14 GT_BST1 1 2 PR988

0.01U_0402_25V7K
2

DIFFOUT_2ph/ICCMAX_2ph BST1

PC915
470P_0402_50V7K PR934 2200P_0402_50V7K PR925 2.2_0603_5% 10_0402_1%
2 GT_COMP 4

PC917
1 PR914 2 1 2 1 2 1 1 2
COMP_2ph

1
49.9_0402_1% PC907 7.5K_0402_1% PC908 15
HG1 GT_HG1 60
1 2 1 2 U23E@

1
PR918 PC932 10P_0402_50V8J 0.047U_0402_16V7K

2
1K_0402_1% GT_FB 3 16 PC926
FB_2ph SW1 GT_PH1 59,60

1
2
PC988
17 0.047U_0402_16V7K
GT_LG1 60

2
LG1/ROSC U23E@
PR954
2 1
51 14K_0402_1%
12 VCCGT_VCC_SEN VSP_2ph GT_CSP1
10 1 2
CSP1_2ph GT_PH1 59,60
2

1.5K_0402_1% PR953
PC931 1 PR964 2 GT_VSN 52 1.8K_0402_1%
1000P_0402_50V7K VSN_2ph 9 GT_CSP2 1 2
GT_PH2 59,60
1

1 2 CSP2_2ph PR952
12 VCCGT_VSS_SEN
PC933 3300P_0402_50V7-K 1 2 1.8K_0402_1%

2
22.1K_0402_1% U23E@
PR927 PR1019
GT_TSENSE 11 40 2K_0402_1%
B TSENSE_2ph PWM/ADDR_VBOOT GT_PWM 60 B
U22@

1
1.5K_0402_1% 0.015U_0402_25V7-K

0.22U_0603_16V7K
1 PR965 2 2 1 PC936 SA_COMP 47 22 SA_BST 1 2 +5VS
COMP_1b BST2
1

PC989
PR989 2.2_0603_5% 180K_0402_1%
PR960 1 2 PR912 1 PR956 2
VCCSA PORTION SA_PH 60

2
0_0402_5% PC935 15P_0402_50V8J 2 1 SA_ILIM 46 21
ILIM_1b HG2 SA_HG 60
54.9K_0402_1%
100K_0402_1%_NCP15WF104F03RC

1 2 84.5K_0402_1% PH904
2

1
1000P_0402_50V7K PC940 20 1 PR957 2 1 2
SW2 SA_PH 59,60 +VCCSA 13,60
5.76K_0402_1% 22.6K_0402_1%
1

1 PR966 2 SA_VSP 49 19 1 PR955 2

8.25K_0402_1%

100K_0402_1%_NCP15WF104F03RC
.1U_0402_10V6-K

13 VCCSA_VCC_SEN VSP_1b LG2/ICCMAX_1a

1
PH903

PR963

PC934

5.76K_0402_1%
2

1 PR907 2 1 2 1K_0402_1% 1 2
SA_VSN 48 SA_LG 60
PC937 PC938 1000P_0402_50V7K 1 PR970 2 PC941 1500P_0402_50V6-K
2

VSN_1b
IOUT_1b

1000P_0402_50V7K 44 SA_CSP 1 2
2

CSP_1b
EPAD

1 2 PC927 820P_0402_50V7-K
13 VCCSA_VSS_SEN
220P_0402_50V7K PC939 45
CSN_1b
43

53

SA_Iout
1

1
470P_0402_50V7K PR958
PC929 226K_0402_1%
2
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/09/03 Deciphered Date 2012/09/03 PWR_CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. BMWQ1&Q2
Date: Monday, July 27, 2015 Sheet 59 of 60
5 4 3 2 1
 A
B
C
D
59,60
59

59

59,60

59
59
Vcore_LG
Vcore_PH
Vcore_HG

SA_LG
SA_PH
SA_HG

5
5

4
4

3 5 3 5
2 2

4
4
1 1

59,60

59
59

G
G
3 3
2 S3 5 2 S3 5
1 S2 D 1 S2 D
S1 S1

GT_LG1
GT_PH1
GT_HG1
PQ1002
PQ1001

PQ1004
PQ1003
AON6764_DFN8-5
AON6372_DFN8-5

AON7506_DFN
AON7408L_DFN8-5
2 1 2 1

+5VS

4
4
EMC@

EMC@
PR1002

EMC@

2 1 2 1 3 5 3 5 PC1001
PC1026

2 2 0.1U_0402_25V7-K
2.2_0805_5%

1
1 1 2 1
1000P_0402_50V7K

PC1002

PC1079
PR1017
U23E@

PR1014

U23E@ 10U_0805_25V6K
2
2.2_0603_5%

EMC_NS@
EMC_NS@
PC1034 2 1

2.2_0805_5%
1

1U_0402_10V6K

PQ1006
PQ1005
EMC@ 2 1 PC1003

1200P_0402_50V7-K
PC1082 10U_0805_25V6K
0.1U_0402_25V7-K 2 1

WWW.AliSaler.Com
59

2 1
PL1001

AON6764_DFN8-5
AON6372_DFN8-5
59
2

4
4

1
PC1078
10U_0805_25V6K
GT_PWM

2 1
CPU_VIN

DRON

2 1 2 1
0.15UH_PCMB063T-R15MS_30A_20%

PL1002
PC1081

2
2

10U_0805_25V6K
2 1
2

PC1047
PR1008
1
PJ1001

Vcore_PH

0.47UH_PCMB063T-R47MS_18A_20%
1

EMC_NS@
EMC_NS@
U23E@
PR1005

2.2_0805_5%
+CPU_CORE

10_0402_5%
1

JUMP_43X79

EMC@
U23E@
59,60

1200P_0402_50V7-K
0_0402_5%

PC1032
2
1 PR1004 2
12,59

0.1U_0402_25V7-K
2
1
+

SA_PH
2 1

CPU_VIN

+VCCSA
1
+

GT_EN

1
2 3

GT_VCC

PC1033

59,60
10U_0805_25V6K PC1015
PC1004

GT_PWM_D

12,59
2 1 220U_D2_2VM_R6M
68U_25V_M

9
3
2
4

PL1003
PC1031 EMC_NS@

2
EN
@

10U_0805_25V6K PC1083
VCC
PU902

PWM
2
1
+

FLAG

2 1 0.1U_0402_25V7-K
U23E@

2 1
0.15UH_PCMB063T-R15MS_30A_20%
SW
BST

GND
DRVH

DRVL

EMC_NS@
PC1087

PC1084
6
5
7
8
1
68U_25V_M

CPU_VIN

2200P_0402_50V7K
2 1

2 1
+VCC_GT GT_BST2
NCP81151MNTBG_DFN8_2X2
B+

PC1036
GT_PH1 59,60
1

22U_0805_6.3V6M
12,59
+CPU_CORE

3
3

2 1
GT_LG2
GT_PH2
GT_HG2
U23E@
PR1013

1
+

PC1037
2

2.2_0603_5%

2 3

22U_0805_6.3V6M
PC1045
2 1 220U_D2_2VM_R6M
1

2
1
+

@
PC1038
22U_0805_6.3V6M
2 1 PC1066
U23E@
PC1030
2

330U_2.5V_M R12M

Issued Date
PC1039
0.22U_0603_16V7K

22U_0805_6.3V6M EMC_NS@
2 1 PC1085

Security Classification
0.1U_0402_25V7-K
PC1040 2 1
4
4

22U_0805_6.3V6M
2 1
EMC_NS@ 3 5 3 5
PC1041 PC1086 2 2
22U_0805_6.3V6M 2200P_0402_50V7K 1 1
2 1
2 1

PC1042
+VCC_GT

22U_0805_6.3V6M +VCCSA
U23E@
PQ1008

2013/11/08
U23E@
PQ1007

2 1 2 1
2 1 2 1
AON6372_DFN8-5
@
@

PC1022 PC1005
2 1 2 1 22U_0603_6.3V6-M 22U_0603_6.3V6-M
U23E@ 2 1 2 1
PC1046
PR1006

PC1067 PC1052 PC1027

EMC_NS@
AON6764_DFN8-5 EMC_NS@
@

22U_0603_6.3V6-M 22U_0603_6.3V6-M 0.1U_0402_25V7-K PC1016 PC1006

2.2_0805_5%

2 1 2 1 2 1 22U_0603_6.3V6-M 22U_0603_6.3V6-M
2 1 2 1
1200P_0402_50V7-K

PC1068 PC1053
22U_0603_6.3V6-M 22U_0603_6.3V6-M U23E@ PC1023 PC1007
1

2
2

2 1 2 1 PC1028 22U_0603_6.3V6-M 22U_0603_6.3V6-M

10U_0805_25V6K 2 1 2 1
2 1
Deciphered Date
PC1069 PC1054
22U_0603_6.3V6-M 22U_0603_6.3V6-M PC1017 PC1008
PC1029 22U_0603_6.3V6-M 22U_0603_6.3V6-M
PL1004
U23E@

2 1 2 1 10U_0805_25V6K
2

2 1 2 1 2 1
LC Future Center Secret Data

PC1070 PC1055
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 22U_0603_6.3V6-M 22U_0603_6.3V6-M U23E@ PC1025 PC1009
2 1 2 1 22U_0603_6.3V6-M 22U_0603_6.3V6-M
2 1
0.15UH_PCMB063T-R15MS_30A_20%

PC1071 PC1056 2 1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
GT_VIN

22U_0603_6.3V6-M 22U_0603_6.3V6-M PC1018

2 1 2 1 22U_0603_6.3V6-M PC1013
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

2 1 22U_0603_6.3V6-M
2013/11/08
@

PC1072 PC1057 2 1
2

GT_PH2

22U_0603_6.3V6-M 22U_0603_6.3V6-M PC1024

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

2 1 2 1
2

22U_0603_6.3V6-M PC1010
@

2 1 22U_0603_6.3V6-M
59
+VCC_GT 13,59
PJ1002

PC1073 PC1058 2 1
1

22U_0603_6.3V6-M 22U_0603_6.3V6-M PC1019

22U_0603_6.3V6-M PC1011
1

JUMP_43X79

2 1 2 1 2 1 22U_0603_6.3V6-M
2 1
C
@
@
@

PC1074 PC1059 PC1020

Size

22U_0603_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M PC1014

Date:
Title

2 1 22U_0603_6.3V6-M
2 1 2 1
PC1075 2 1
B+

22U_0603_6.3V6-M PC1060 PC1021

2 1 22U_0603_6.3V6-M 22U_0603_6.3V6-M PC1012
1
+

2 1 22U_0603_6.3V6-M
2 3

PC1076
22U_0603_6.3V6-M PC1061 PC1080
Document Number

2 1 22U_0603_6.3V6-M 220U_D2_2VM_R6M
+VCC_GT

2 1 U23E@
@

PC1077
22U_0603_6.3V6-M PC1062
PWR_CPU_Core

22U_0603_6.3V6-M
Monday, July 27, 2015
+CPU_CORE

2 1
1
1

PC1063
22U_0603_6.3V6-M

2 1
Sheet
BMWQ1&Q2

PC1064
22U_0603_6.3V6-M
60
of
+VCC_GT

60
Rev
0.2
A
B
C
D