8575 PDF

SERVICE MANUAL FOR
8575
BY: Sissel Diao

TESTING
TESTING TECHNOLOGY
TECHNOLOGY DEPARTMENT
DEPARTMENT // TSSC
TSSC
Jun. 2002
Downloaded from www.Manualslib.com manuals search engine

8575 N/B Maintenance
Contents
1. Hardware Engineering Specification ………………………………………………………………… 4
1.1 Introduction …………………………………………………………………………………………………………. 4

1.2 System Hardware Parts ……………………………………………………………………………………………. 7
1.3 Other Functions …………………………………………………………………………………………………….. 53
1.4 Peripheral Components …………………………………………………………………………………………….. 58
1.5 Power Management ………………………………………………………………………………………………… 61
1.6 Appendix 1: SiS961 GPIO Definitions …………………………………………………………………………….. 63
1.7 Appendix 2: H8 Pins Definitions …………………………………………………………………………………… 64
1.8 Appendix 3: 8575 Product Specifications …………………………………………………………………………. 70
2. System View and Disassembly ………………………………………………………………………... 73

2.1 System View …………………………………………………………………………………………………………. 73
2.2 System Disassembly ………………………………………………………………………………………………… 76
3. Definition & Location of Connectors / Switches …………………………………………………….. 94

3.1 Mother Board ……………………………………………………………………………………………………….. 94
3.2 DC Power Board ……………………………………………………………………………………………………. 97
3.3 ESB Board …………………………………………………………………………………………………………... 98
3.4 Touch-pad …………………………………………………………………………………………………………… 99
3.5 Daughter Board …………………………………………………………………………………………………….. 99

Contents
4. Definition & Location of Major Component ………………………………………………………… 100

4.1 Mother Board ……………………………………………………………………………………………………….. 100
5. Pin Description of Major Component ………………………………………………………………... 102
5.1 Intel Pentium 4 Processor mPGA478 Socket ……………………………………………………………………... 102

5.2 SiS650 IGUI Host / Memory Controller …………………………………………………………………………... 108
5.3 SiS691 MuTIOL Media I/O Controller …………………………………………………………………………… 113
5.4 SiS301LV / Chrontel CH7019 TV/LVDS Encoder ……………………………………………………………….. 119
5.5 PCI1410GGU PCMCIA Controller ……………………………………………………………………………….. 122
5.6 uPD72872 IEEE1394 Controller …………………………………………………………………………………… 127
6. System Block Diagram ………………………………………………………………………………… 129
7. Maintenance Diagnostics ……………………………………………………………………………… 130
7.1 Introduction …………………………………………………………………………………………………………. 130

7.2 Error Codes …………………………………………………………………………………………………………. 131
7.3 Maintenance Diagnostics …………………………………………………………………………………………… 133
8. Trouble Shooting ………………………………………………………………………………………. 134
8.1 No Power …………………………………………………………………………………………………………….. 135

Contents
8.2 No Display …………………………………………………………………………………………………………… 141

8.3 VGA Controller Failure LCD No Display ………………………………………………………………………… 145
8.4 External Monitor No Display ……………………………………………………………………………………… 147
8.5 Memory Test Error ………………………………………………………………………………………………… 149
8.6 Keyboard (K/B) Touch-Pad (T/P) Test Error ……………………………………………………………………. 151
8.7 Hard Disk Drive Test Error ……………………………………………………………………………………….. 153
8.8 CD-ROM Driver Test Error ……………………………………………………………………………………….. 155
8.9 USB Test Error ……………………………………………………………………………………………………… 157
8.10 PIO Port Test Error ………………………………………………………………………………………………. 160
8.11 Audio Failure ……………………………………………………………………………………………………… 162
8.12 LAN Test Error …………………………………………………………………………………………………… 165
8.13 PC Card Socket Failure …………………………………………………………………………………………… 167
8.14 IEEE 1394 Failure ………………………………………………………………………………………………… 169
9. Spare Parts List ……………………………………………………………………………………….. 171
10. System Exploded Views ……………………………………………………………………………… 193
11. Circuit Diagram ……………………………………………………………………………………… 198
12. Reference Material …………………………………………………………………………………… 230

1. Hardware Engineering Specification
1.1 Introduction
The 8575 motherboard would support the Intel® Pentium® 4 processor with FCPGA packaged, mPGA478
Socket, which will supports the different levels up to Willamette P4 1.7GHz (Throttling)/Northwood above
2.0GHz (Throttling).
This system is based on PCI architecture, which have standard hardware peripheral interface. The power
management complies with Advanced Configuration and Power Interface (ACPI) 1.0. It also provides easy
configuration through CMOS setup, which is built in system BIOS software and can be pop-up by pressing
F2 at system start up or warm reset. System also provides icon LEDs to display system status, such as power
indicator, HDD/CDROM, NUM LOCK, CAP LOCK, SCROLL LOCK, SUSPEND MODE and Battery
charging status. It also equipped 2 USB ports.
The memory subsystem supports 0MB on board memory, two JEDEC-standard 200-pin, small-outline, dual
in-line memory module (SODIMM), support PC2100 & PC2700.
SiS650 IGUI Host Memory Controller integrates a high performance host interface for Intel Pentium 4
processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4X
interface, and SiS MuTIOL® Technology connecting w/ SiS961 MuTIOL® Media I/O.

The SiS961 MuTIOL® Media I/O integrates the Audio Controller with AC 97 Interface, the Ethernet MAC,
the Dual Universal Serial Bus Host Controllers, the IDE Master/Slave controllers, and the MuTIOL® Connect
to PCI bridge. The PCI to LPC bridge, I/O Advanced Programmable Interrupt Controller, legacy system I/O,
I/O Advanced Programmable Interrupt Controller and legacy power management functionalities are also
integrated. The SiS961 also incorporates an universal interface supporting the asynchronous inputs/outputs of
the X86 compatible microprocessors like PIII, K7 and P4.
The CH7019 is a Display Controller device which accepts two digital graphics input data streams. One data
stream outputs through an LVDS transmitter to an LCD panel, while the other data stream is encoded for NTSC
or PALTV and outputs through a 10-bit high speed DAC. The TV encoder device encodes a graphics signal up
to 1024 x 768 resolution and outputs the video signals according to NTSC or PAL standards. The LVDS
transmitter operates at pixel speeds up to 165MHz per link, supporting 1600 x 1200 panels at 60Hz refresh rate.
The TI PCI4410 is a dual-function PCI device compliant with PCI Local Bus Specification 2.2. Function 0
provides the independent PC Card socket controller compliant with the 1997 PC Card Standard. The PCI4410
provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports
either 16-bit or CardBus PC Cards in the socket, powered at 5 V or 3.3 V, as required.
Function 1 of the PCI4410 is compatible with IEEE1394A and the latest 1394 open host controller interface
(OHCI) specifications. The chip provides the IEEE1394 link function and is compatible with data rates of 100,
200, and 400Mbits per second. Deep FIFOs are provided to buffer 1394 data and accommodate large host bus
latencies.

The PCI4410 provides physical write posting and a highly tuned physical data path for SBP-2 performance.
Multiple cache line burst transfers, advanced internal arbitration, and bus holding buffers on the PHY/Link
interface are other features that make the PCI4410 the best-in-class 1394 Open HCI solution.
To provide for the increasing number of multimedia applications, the AC97 CODEC ALC201 is integrated
onto the motherboard.
A full set of software drivers and utilities are available to allow advanced operating systems such as Windows
Me and Windows 2000 to take full advantage of the hardware capabilities such as bus mastering IDE, Windows
95-ready Plug & Play, Advanced Power Management (APM) and Advance configuration and power interface
(ACPI).
Following chapters will have more detail description for each individual sub-systems and functions.

1.2 System Hardware Parts
CPU Intel® Pentium® 4 processor; Willamette/Northwood with mFCPGA2 Package, mPGA 478
Socket
Support up to Willamette P4 1.7GHz (Throttling) / Northwood above 2.0 GHz(Throttling)
FSB 400MHz /PC 2100/1600
Core logic SiS 650+SiS961: Host & Memory & AGP Controller integrates a high performance host
interface for Intel Pentium 4 processor, a high performance memory controller, a AGP
interface, and SiS MuTIOL® Technology connecting w/ SiS961 MuTIOL® Media IO.
VGA Control Chrontel CH7019
System BIOS 256KB Flash EPROM
Inside -Includes System BIOS, VGA BIOS, and plug & Play capability, ACPI
Memory 0MB on board memory
-Two JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM)
-Support PC2100 & PC2700
Video Memory 8/16/32/64 UMA
Clock Generator ICS 952001
DDR Clock Buffer ICS 93722
Embedded controller Hitachi H8 3437S
PCMCIA Card Bus Controller: TI PCI 4410,One type II slot Card Bus
TSB41AB1 of 1394 PHY
Audio System AC97 CODEC: Advance Logic, Inc, ALC201
Power Amplifier: TI TPA0202
Super I/O PC87393
IR Module for HP3600
Modem 56Kbps(V.90, worldwide) MDC Modem
PHY of LAN ICS1893Y-10 10/100 base T PHY

1.2.1 CPU_Intel Pentium 4 Processor
The Intel® Pentium® 4 processor, Intel’s most advanced, most powerful processor, is based on the new Intel®
NetBurst™ micro-architecture. The Pentium 4 processor is designed to deliver performance across applications
and usages where end users can truly appreciate and experience the performance. These applications include
Internet audio and streaming video, image processing, video content creation, speech, 3D, CAD, games, multi-
media, and multi-tasking user environments. The Intel Pentium 4 processor delivers this world-class
performance for consumer enthusiast and business professional desktop users as well as for entry-level
workstation users.
Highlights of the Pentium 4 Processor :
Available at speeds ranging from 1.50 to 2 GHz

Featuring the new Intel NetBurst micro-architecture
Supported by the SiS650 chipset
Fully compatible with existing Intel Architecture-based software
Internet Streaming SIMD Extensions 2
Intel® MMX™ media enhancement technology
Memory cache ability up to 4 GB of addressable memory space and
system memory scalability up to 64GB of physical memory
Support for uni-processor designs

Based upon Intel’s 0.18 micron manufacturing process
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Intel Pentium 4 Processor Product Feature Highlights
The Intel NetBurst micro-architecture delivers a number of new and innovative features including Hyper
Pipelined Technology, 400 MHz System Bus, Execution Trace Cache, and Rapid Execution Engine as well as
a number of enhanced features Advanced Transfer Cache, Advanced Dynamic Execution, Enhanced Floating-
point and Multi-media Unit, and Streaming SIMD Extensions 2. Many of these new innovations and advances
were made possible with improvements in processor technology, process technology, and circuit design that
could not previously be implemented in high-volume, manufacturable solutions. The features and resulting
benefits of the new micro-architecture are defined below.
Hyper Pipelined Technology:

The hyper-pipelined technology of the NetBurst micro-architecture doubles the pipeline depth compared to
the P6 micro-architecture used on today’s Pentium III processors. One of the key pipelines, the branch
prediction/ recovery pipeline, is implemented in 20 stages in the NetBurst micro-architecture, compared to
10 stages in the P6 micro-architecture. This technology significantly increases the performance, frequency,
and scalability of the processor.
400 MHZ System Bus:

The Pentium4 processor supports Intel’s highest performance desktop system bus by delivering 3.2 GB
of data per second into and out of the processor. This is accomplished through a physical signaling scheme
of quad pumping the data transfers over a 100-MHz clocked system bus and a buffering scheme allowing
for sustained 400-MHz data transfers. This compares to 1.06 GB/s delivered on the Pentium III processor’s
133-MHz system bus.

Level 1 Execution Trace Cache:
In addition to the 8KB data cache, the Pentium 4 processor includes an Execution Trace Cache that stores
up to 12K decoded micro-ops in the order of program execution. This increases performance by removing
the decoder from the main execution loop and makes more efficient usage of the cache storage space since
instructions that are branched around are not stored. The result is a means to deliver a high volume of
instructions to the processor’s execution units and a reduction in the overall time required to recover from
branches that have been mis-predicted.
Rapid Execution Engine:

Two Arithmetic Logic Units (ALUs) on the Pentium 4 processor are clocked at twice the core processor
frequency. This allows basic integer instructions such as Add, Subtract, Logical AND, Logical OR, etc. to
execute in half a clock cycle. For example, the Rapid Execution Engine on a 1.50 GHz Pentium 4 processor
runs at 3 GHz.
256KB, Level 2 Advanced Transfer Cache:

The Level 2 Advanced Transfer Cache (ATC) is 256KB in size and delivers a much higher data throughput
channel between the Level 2 cache and the processor core. The Advanced Transfer Cache consists of a 256-
bit (32-byte) interface that transfers data on each core clock. As a result, the Pentium 4 processor 1.50 GHz
can deliver a data transfer rate of 48 GB/s. This compares to a transfer rate of 16 GB/s on the Pentium III
processor at 1 GHz. Features of the ATC include:
Non-Blocking, full speed, on-die Level 2 cache
8-way set associativity
256-bit data bus to the level 2 cache
Data clocked into and out of the cache every clock cycle
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Advanced Dynamic Execution:
The Advanced Dynamic Execution engine is a very deep, out-of-order speculative execution engine that
keeps the execution units executing instructions. The Pentium 4 processor can also view 126 instructions
in flight and handle up to 48 loads and 24 stores in the pipeline. It also includes an enhanced branch
prediction algorithm that has the net effect of reducing the number of branch mis-predictions by about
33% over the P6 generation processor’s branch prediction capability. It does this by implementing a 4KB
branch target buffer that stores more detail on the history of past branches, as well as by implementing a
more advanced branch prediction algorithm.
Enhanced Floating-Point and Multimedia Unit:

The Pentium 4 processor expands the floating-point registers to a full 128-bit and adds an additional register
for data movement which improves performance on both floating-point and multimedia applications.
Internet Streaming SIMD Extensions 2 (SSE2):

With the introduction of SSE2, the NetBurst micro-architecture now extends the SIMD capabilities that
MMX technology and SSE technology delivered by adding 144 new instructions. These instructions include
128-bit SIMD integer arithmetic and 128-bit SIMD double-precision floating-point operations. These new
instructions reduce the overall number of instructions required to execute a particular program task and as a
result can contribute to an overall performance increase. They accelerate a broad range of applications,
including video, speech, and image, photo processing, encryption, financial, engineering and scientific
applications.
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Features Used for Test and Performance / Thermal Monitoring:
Built-in Self Test (BIST) provides single stuck-at fault coverage of the micro-code and large logic
arrays, as well as testing of the instruction cache, data cache, Translation Lookaside Buffers (TLBs),
and ROMs.
IEEE 1149.1 Standard Test Access Port and Boundary Scan mechanism enables testing
of the Pentium 4 processor and system connections through a standard interface.
Internal performance counters can be used for performance monitoring and event counting.
Includes a new Thermal Monitor feature that allows motherboards to be cost effectively designed to
expected application power usages rather than theoretical maximums.
1.2.2 System Frequency
1.2.2.1 System frequency synthesizer_ICS952001
Programmable Timing Control Hub™ for P4™ processor

General Description :
The ICS952001 is a two chip clock solution for desktop designs using SIS 645/650 style chipsets. When
used with a zero delay buffer such as the ICS9179-06 for PC133 or the ICS93705 for DDR applications it
provides all the necessary clocks signals for such a system.
12

The ICS952001 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing
Control Hub). ICS is the first to introduce a whole product line which offers full programmability and
flexibility on a single clock device. Employing the use of a serially programmable I2C interface, this device
can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal
spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock.
TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting under
unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz
increment.
Recommended Application:
SiS645/650 style chipsets
Output features:
2 - Pairs of differential CPUCLKs @ 3.3V

1 - SDRAM @ 3.3V
8 - PCI @3.3V
2 - AGP @ 3.3V
2 - ZCLKs @ 3.3V
1 - 48MHz, @3.3V fixed
1 - 24/48MHz, @3.3V selectable by I2 C
3 - REF @3.3V, 14.318MHz
13

Features/Benefits:
Programmable output frequency, divider ratios, output rise/fall time, output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system if system malfunctions
Programmable watch dog safe frequency.
Support I2 C Index read/write and block read/write operations
For PC133 SDRAM system use the ICS9179-06 as the memory buffer.
For DDR SDRAM system use the ICS93705 as the memory buffer.
Uses external 14.318MHz crystal.
Key Specifications:
PCI - PCI output skew: < 500ps

CPU - SDRAM output skew: < 1ns
AGP - AGP output skew: <150ps
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1.2.2.2 DDR buffer frequency synthesizer_ICS93722
Low Cost DDR Phase Lock Loop Zero Delay Buffer
Recommended Application:
SiS645/650 style chipsets
Product description/features:
Low skew, low jitter PLL clock driver
I2 C for functional and output control
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
3.3V tolerant CLK_INT input
Switching Characteristics
PEAK - PEAK jitter (66MHz): <120ps

PEAK - PEAK jitter (>100MHz): <75ps
CYCLE - CYCLE jitter (66MHz): <120ps
CYCLE - CYCLE jitter (>100MHz): <65ps
OUTPUT - OUTPUT skew: <100ps
Output Rise and Fall Time: 650ps - 950ps
DUTY CYCLE: 49.5% - 50.5%
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1.2.3 Core Logic_SiS650 + SiS961
1.2.3.1 SiS650 IGUI Host/Memory Controller
SiS650 IGUI Host Memory Controller integrates a high performance host interface for Intel Pentium 4
processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4X
interface, and SiS MuTIOL® Technology connecting w/ SiS961 MuTIOL® Media IO.
SiS650 Host Interface features the AGTL & AGTL+ compliant bus driver technology with integrated on-
die termination to support Intel Pentium 4 processors. SiS650 provides a 12-level In-Order-Queue to support
maximum outstanding transactions up to 12. It integrated a high performance 2D/3D Graphic Engine, Video
Accelerator and Advanced Hardware Acceleration MPEGI/MPEGII Video Decoder for the Intel Pentium 4
series based PC systems. It also integrates a high performance 2.1GB/s DDR266 Memory controller to sustain
the bandwidth demand from the integrated GUI or external AGP master, host processor, as well as the multi
I/O masters. In addition to integrated GUI, SiS650 also can support external AGP slot with AGP 1X/2X/4X
capability and Fast Write Transactions. A high bandwidth and mature SiS MuTIOL® technology is
incorporated to connect SiS650 and SiS961 MuTIOL® Media I/O together. SiS MuTIOL® technology is
developed into three layers, the Multi-threaded I/O Link Layer delivering 1.2GB bandwidth to connect
embedded DMA Master devices and external PCI masters to interface to Multi-threaded I/O Link layer, the
Multi-threaded I/O Link Encoder/Decoder in SiS961 to transfer data w/ 533 MB/s bandwidth from/to Multi-
threaded I/O Link layer to/from SiS650, and the Multi-threaded I/O Link Encoder/Decoder in SiS650 to
transfer data w/ 533 MB/s from/to Multi-threaded I/O Link layer to/from SiS961.
16

An Unified Memory Controller supporting PC133 or DDR266 DRAM is incorporated, delivering a high
performance data transfer to/from memory subsystem from/to the Host processor, the integrated graphic engine
or external AGP master, or the I/O bus masters. The memory controller also supports the Suspend to RAM
function by retaining the CKE# pins asserted in ACPI S3 state in which only AUX source deliver power. The
SiS650 adopts the Shared Memory Architecture, eliminating the need and thus the cost of the frame buffer
memory by organizing the frame buffer in the system memory. The frame buffer size can be allocated from
8MB to 64MB.
The Integrated GUI features a high performance 3D accelerator with 2 Pixel / 4 Texture, and a 128 bit 2D
accelerator with 1T pipeline BITBLT engine. It also features a Video Accelerator and advanced hardware
acceleration logic to deliver high quality DVD playback. A Dual 12 bit DDR digital video link interfaced to
SiS 301B Video Bridge packaged in 100-pin PQFP is incorporated to expand the SiS650 functionality to
support the secondary display, in addition to the default primary CRT display. The SiS301B Video Bridge
integrates an NTSL/PAL video encoder with Macro Vision Ver. 7.1.L1 option for TV display, a TMDS
transmitter with Bi-linear scaling capability for TFT LCD panel support, and an analog RGB port to support a
secondary CRT. The primary CRT display and the extended secondary display (TV, TFT LCD Panel, 2'nd
CRT) features the Dual View Capability in the sense that both can generate the display in independent
resolutions, color depths, and frame rates.
17

Two separate buses, Host-t-GUI in the width of 64 bit, and GUI-t-Memory Controller in the width of 128
bit are devised to ensure concurrency of Host-t-GUI streaming, and GUI-t-MC streaming. In PC133, or
DDR266 memory subsystem, the 128 bit GUI-t-MC bus will attain the AGP4X or AGP 8X equivalent texture
transfer rate, respectively. The Memory Controller mainly comprises the Memory Arbiter, the M-data/M-
Command Queues, and the Memory Interface. The Memory Arbiter arbitrates a plenty of memory access
requests from the GUI or AGP controller, Host Controller, and I/O bus masters based on a default optimized
priority list with the capability of dynamically prioritizing the I/O bus master requests in a bid to offering
privileged service to 1) the isochronous downstream transfer to guarantee the min. latency & timely delivery,
or 2) the PCI master upstream transfer to curb the latency within the maximum tolerant period of 10us. Prior to
the memory access requests pushed into the M-data queue, any command compliant to the paging mechanism
is generated and pushed into the M-CMD queue. The M-data/M-CMD Queues further orders and forwards
these queuing requests to the Memory Interface in an effort to utilizing the memory bandwidth to its utmost by
scheduling the command requests in the background when the data requests streamlines in the foreground.
18

1.2.3.2 SiS961 MuTIOL® Media I/O overview
The SiS961 MuTIOL® Media I/O integrates the Audio Controller with AC 97 Interface, the Ethernet
MAC, the Dual Universal Serial Bus Host Controllers, the IDE Master/Slave controllers, and the MuTIOL®
Connect to PCI bridge. The PCI to LPC bridge, I/O Advanced Programmable Interrupt Controller, legacy
system I/O, I/O Advanced Programmable Interrupt Controller and legacy power management functionalities
are also integrated. The SiS961 also incorporates an universal interface supporting the asynchronous
inputs/outputs of the X86 compatible microprocessors like PIII, K7 and P4.
The Integrated Audio Controller features a 6 channels of AC 97 v2.2 compliance audio to present 5.1-
channel Dolby digital material or to generate stereo audio with simultaneous V.90 HSP modem operation.
Besides, 4 separate SDATAIN pins are provided to support multiple audio Codecs + one modem Codec
maximally, effectuating the realization of 5.1 channel Dolby digital material in theater quality sound. Both
traditional consumer digital audio channel as well as the AC 97 v2.2 compliant consumer digital audio slot are
supported. VRA mode is also associated with both the AC 97 audio link and the traditional consumer digital
audio channel.
The integrated Fast Ethernet MAC features an IEEE 802.3 and IEEE 802.3x compliant MAC supporting
full duplex 10 Base-T, 100 Base-T Ethernet, or 1Mb/s & 10Mb/s Home networking. 5 wake-up Frames,
Magic Packet and link status change wake-up functions in G1/G2 states are supported. Besides, the integrated
MAC provides a scheme to store the MAC address without the need of an external EEPROM. The 25 MHz
oscillating circuit is integrated so as only an external low cost 25 MHz crystal is needed for the clocking
system.
19

The integrated Universal Serial Bus Host Controllers features Dual Independent OHCI Compliant Host
controllers with six USB ports delivering 2 x 12 Mb/s bandwidth and rich connectivity. Besides, each port can
be optionally configured as the wake-up source. Legacy USB devices as well as over current detection are also
implemented. The integrated IDE Master/Slave controllers features Dual Independent IDE channels supporting
PIO mode 0,1,2,3,4, and Ultra DMA 33/66/100. It provides two separate data paths for the dual IDE channels
that sustain the high data transfer rate in the multitasking environment. The MuTIOL® Connect to PCI bridge
supporting 6 PCI master is compliant to PCI 2.2 specification. The SiS961 also incorporates the legacy system
I/O like: two 8237A compatible DMA controllers, three 8254 compatible programmable 16-bit counters,
hardwired keyboard controller and PS2 mouse interface, Real Time clock with 256B CMOS SRAM and two
8259A compatible Interrupt controllers. Besides, the I/O APIC managing up to 24 interrupts with both Serial
and FSB interrupt delivery modes is supported.
The integrated power management module incorporates the ACPI 1.0b compliance functions, the APM 1.2
compliance functions, and the PCI bus power management interface spec. v1.1. Numerous power-up events
and power down events are also supported. 21 general purposed I/O pins are provided to give an easy to use
logic for specific application. In addition, the SiS961 supports Intel Speed Step technology and Deeper Sleep
power state for Intel Mobile processor. For AMD processor, the SiS961 use the CPUSTP# signal to reduce
processor voltage during C3 and S1 state.
20

1.2.4 CH7019 TV Encoder / LVDS Transmitter
General Description
The CH7019 is a Display Controller device which accepts two digital graphics input data streams. One data
stream outputs through an LVDS transmitter to an LCD panel, while the other data stream is encoded for NTSC
or PALTV and outputs through a 10-bit high speed DAC. The TV encoder device encodes a graphics signal up
to 1024x768 resolution and outputs the video signals according to NTSC or PAL standards. The LVDS
transmitter operates at pixel speeds up to 165MHz per link, supporting 1600x1200 panels at 60Hz refresh rate.
The device can also accept one graphics data stream over two 12-bit wide variable voltage ports which support
nine different data formats including RGB and YCrCb (RGB must be used for LVDS output). A maximum of
330M pixels per second can be output through dual LVDS links.
The TV-Out processor will perform non-interlaced to interlaced conversion with scaling, flicker filtering, and
encoding into any of the NTSC or PAL video standards. The scaler and flicker filter are adaptive and
programmable for superior text display. Eight graphics resolutions are supported up to 1024 by 768 with full
vertical and horizontal under-scan capability in all modes. A high accuracy low jitter phase locked loop is
integrated to create outstanding video quality. Support is provided for MacrovisionTM. In addition to TV
encoder modes, bypass modes are included which allow the TV DAC’s to be used as a second CRT DAC .
21

The LVDS transmitter includes a panel fitting up-scaler and a programmable dither function for support of 18-
bit panels. Data is encoded into commonly used formats, including those detailed in the OpenLDI and the
SPWG specifications. Serialized data outputs on three to eight differential channels.
22

1.2.4.1 TV-Out :
VGA to TV conversion supporting up to 1024 x 768
MacrovisionTM 7.X copy protection support
Two variable-voltage digital input ports
Simultaneous LVDS and TV output
TrueScaleTM rendering engine supports under-scan in all TV output resolutions
Enhanced text sharpness and adaptive flicker removal with up to 7 lines of filtering
Support for all NTSC and PAL TV formats
Outputs CVBS, S-Video and RGB
Support for SCART connector
TV/Monitor connection detect
Output video switch for easy wiring to connectors
23

1.2.4.2 LVDS -Out:
Single / Dual LVDS transmitter
Dual LVDS supports pixel rate up to 330Mpixels/sec. when both 12-bit input ports are ganged together
Panel fitting scaler – up scale to 1600 x 1200
VDS low jitter PLL accepts spread spectrum input
LVDS 18-bit and 24-bit output
2D dither engine for 18-bit panels
Panel protection and power down sequencing
Programmable power management
Hot Plug detection
Support for second CRT DAC bypass mode
Four 10-bit video DAC outputs
Fully programmable through serial port
Complete Windows and DOS driver support
Variable voltage interface to graphics device
Offered in a 128-pin LQFP package
24

1.2.5 PC Card and OHCI Interface Controller: TI PCI4410
The PCI4410 is a dual-function PCI device compliant with PCI Local Bus Specification 2.2. Function 0
provides the independent PC Card socket controller compliant with the 1997 PC Card Standard. The
PCI4410 provides features that make it the best choice for bridging between the PCI bus and PC Cards, and
supports either 16-bit or CardBus PC Cards in the socket, powered at 5 V or 3.3 V, as required.
All card signals are internally buffered to allow hot insertion and removal without external buffering. The
PCI4410 is register compatible with the IntelTM 82365SLF and 82365SL ExCA controllers. The PCI4410
internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for
maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed
performance level with sustained bursting. The PCI4410 can be programmed to accept posted writes to
improve bus utilization.
Function 1 of the PCI4410 is compatible with IEEE1394A and the latest 1394 open host controller interface
(OHCI) specifications. The chip provides the IEEE1394 link function and is compatible with data rates of 100,
200, and 400Mbits per second. Deep FIFOs are provided to buffer 1394 data and accommodate large host bus
latencies. The PCI4410 provides physical write posting and a highly tuned physical data path for SBP-2
performance. Multiple cache line burst transfers, advanced internal arbitration, and bus holding buffers on the
PHY/Link interface are other features that make the PCI4410 the best-in-class 1394 Open HCI solution.
25

The PCI4410 provides an internally buffered zoomed video (ZV) path. This reduces the design effort of PC
board manufacturers to add a ZV-compatible solution and ensures compliance with the CardBus loading
specifications.
Various implementation-specific functions and general-purpose inputs and outputs are provided through eight
multifunction terminals. These terminals present a system with options in PC/PCI DMA, PCI LOCK and
parallel interrupts, PC Card activity indicator LEDs, and other platform-specific signals. ACPI-compliant
general-purpose events may be programmed and controlled through the multifunction terminals, and an ACPI-
compliant programming interface is included for the general-purpose inputs and outputs.
The PCI4410 is compliant with the latest PCI Bus Power Management Specification, and provides several low-
power modes which enable the host power system to further reduce power consumption. The PC Card
(CardBus) Controller and IEEE 1394 Host Controller Device Class Specifications required for Microsoft
OnNowTM power management are supported. Furthermore, an advanced complementary metal-oxide
semiconductor (CMOS) process achieves low system power consumption.
Unused PCI4410 inputs must be pulled to a valid logic level using a 43-kΩ resistor.
26

Features
Ability to wake from D3hot and D3cold

Fully compatible with the Intel 430TX (Mobile Triton II) chipset
A 208-pin low-profile QFP (PDV) or 209-ball MICROSTAR BGATM ball grid array (GHK) package
3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
Mix-and-match 5-V/3.3-V 16-bit PC Cards and 3.3-V CardBus Cards
Single PC Card or CardBus slot with hot insertion and removal
Burst transfers to maximize data throughput on the PCI bus and the CardBus bus
Parallel PCI interrupts, parallel ISA IRQ and parallel PCI interrupts, serial ISA IRQ with parallel PCI
interrupts, and serial ISA IRQ and PCI interrupts
Serial EEPROM interface for loading subsystem ID and subsystem vendor ID

Pipelined architecture allows greater than 130M bps sustained throughput from CardBus-to-PCI and from
PCI-to-CardBus
Interface to parallel single-slot PC Card power interface switches like the TITM TPS2211
Up to five general-purpose I/Os
Programmable output select for CLKRUN\
Five PCI memory windows and two I/O windows available to the 16-bit PC Card socket
Two I/O windows and two memory windows available to the CardBus socket
27

Exchangeable Card Architecture (ExCA) compatible registers are mapped in memory and I/O space
Intel 82365SL-DF and 82365SL register compatible
Distributed DMA (DDMA) and PC/PCI DMA
16-Bit DMA on the PC Card socket
Ring indicate, SUSPEND\, PCI CLKRUN\, and CardBus CLKRUN\
Socket activity LED pins
PCI bus lock (LOCK\)
Advanced submicron, low-power CMOS technology
Internal ring oscillator
OHCI link function designed to IEEE 1394 Open Host Controller Interface (OHCI) Specification
Implements PCI burst transfers and deep FIFOs to tolerate large host latency
Supports physical write posting of up to 3 outstanding transactions
OHCI link function is IEEE 1394-1995 compliant and compatible with Proposal 1394a
Supports serial bus data rates of 100, 200, and 400Mbits/second
Provides bus-hold buffers on the PHY-Link I/F for low-cost single-capacitor isolation
28

1.2.5.1 Single-Slot PC Card Power Interface Switch: TPS2211A
The TPS2211A PC Card power-interface switch provides an integrated power-management solution for a
single PC Card. All of the discrete power MOSFETs, a logic section, current limiting, and thermal protection
for PC Card control are combined on a single integrated circuit, using the Texas Instruments LinBiCMOSTM
process. The circuit allows the distribution of 3.3-V, 5-V, and/or 12-V card power, and is compatible with
many PCMCIA controllers. The current-limiting feature eliminates the need for fuses, which reduces
component count and improves reliability. Current-limit reporting can help the user isolate a system fault to
the PC Card.
The TPS2211A features a 3.3-V low-voltage mode that allows for 3.3-V switching without the need for 5 V.
Bias power can be derived from either the 3.3-V or 5-V inputs. This facilitates low-power system designs
such as sleep mode and pager mode where only 3.3 V is available.
End equipment for the TPS2211A includes notebook computers, desktop computers, personal digital assistants
(PDAs), digital cameras, and bar-code scanners.
29

Features
Fully Integrated VCC and Vpp Switching for Single-Slot PC CardTM Interface
Low rDS(on) (70-m 5-V VCC Switch and 3.3-V VCC Switch)
Compatible With Industry-Standard Controllers
3.3-V Low-Voltage Mode
Meets PC Card Standards
12-V Supply Can Be Disabled Except During 12-V Flash Programming
Short-Circuit and Thermal Protection
Space-Saving 16-Pin SSOP (DB)
Compatible With 3.3-V, 5-V, and 12-V PC Cards
Break-Before-Make Switching
PC Card is a trademark of PCMCIA (Personal Computer Memory Card International Association).

LinBiCMO is a trademark of Texas Instruments. .
30

1.2.6 TSB41AB1, IEEE 1394a One-Port Cable Transceiver/Arbiter
The TSB41AB1 provides the digital and analog transceiver functions needed to implement a one-port node in
a cable-based IEEE 1394 network. The cable port incorporates one differential line transceiver. The
transceiver includes circuitry to monitor the line conditions as needed for determining connection status, for
initialization and arbitration, and for packet reception and transmission. The TSB41AB1 is designed to
interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23,
TSB12LV26, TSB12LV31, TSB12LV41, TSB12LV42 or TSB12LV01A.
The TSB41AB1 requires only an external 24.576-MHz crystal as a reference. An external clock may be
provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which
generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide
the clock signals used to control transmission of the outbound encoded strobe and data information. A 49.152-
MHz clock signal is supplied to the associated LLC for synchronization of the two chips and is used for
resynchronization of the received data. The power-down (PD) function, when enabled by asserting the PD
terminal high, stops operation of the PLL.
The TSB41AB1 supports an optional isolation barrier between itself and its LLC. When the ISO\ input
terminal is tied high, the LLC interface outputs behave normally. When the ISO\ terminal is tied low, internal
differentiating logic is enabled, and the outputs are driven such that they can be coupled through a capacitive
or transformer galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in IEEE 1394a-
2000 (section 5.9.4) (hereinafter referred to as Annex J type isolation). To operate with TI bus holder isolation
the ISO/terminal on the PHY must be high.
31

Data bits to be transmitted through the cable port are received from the LLC on two, four or eight parallel paths
(depending on the requested transmission speed) and are latched internally in the TSB41AB1 in
synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted
at 98.304, 196.608, or 393.216Mbits/s (referred to as S100, S200, and S400 speeds, respectively) as the
outbound data-strobe information stream. During transmission, the encoded data information is transmitted
differentially on the TPB cable pair, and the encoded strobe information is transmitted differentially on the
TPA cable pair.
During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the
receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the
encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded
to recover the receive clock signal and the serial data bits. The serial data bits are split into two-, four-, or eight-
bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152-MHz
system clock and sent to the associated LLC.
Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during
initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the
arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this
common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition,
the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the
remotely supplied twisted-pair bias voltage.
32

The TSB41AB1 provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. This bias
voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This
bias voltage source must be stabilized by an external filter capacitor of 1µF. TPBIAS is typically VDD 0.2 V
when the port is not connected to another node.
The line drivers in the TSB41AB1 operate in a high-impedance current mode, and are designed to work with
external 112Ω. line-termination resistor networks in order to match the 110Ω. cable impedance. One network
is provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56Ω.
resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair-A terminals is
connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly
connected to the twisted-pair-B terminals is coupled to ground through a parallel R-C network with
recommended values of 5kΩ and 220pF. The values of the external line termination resistors are designed to
meet IEEE Std 1394-1995 when connected in parallel with the internal receiver circuits. An external resistor
connected between the R0 and R1 terminals sets the driver output current, along with other internal operating
currents. This current-setting resistor has a value of 6.34kΩ± 1.0%.
When the power supply of the TSB41AB1 is off while the twisted-pair cables are connected, the TSB41AB1
transmitter and receiver circuitry presents a high impedance to the cable and does not load the TPBIAS voltage
at the other end of the cable. Fail-safe circuitry blocks any leakage path from the port back to the device power
plane.
33

The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal
operation, the TESTM terminal should be connected to VDD through a 1kΩ resistor, SE should be tied to
ground through a 1kΩ resistor, and SM should be connected directly to ground.
Four package terminals are used as inputs to set the default value for four configuration status bits in the self-
ID packet, and are tied high through a 1kΩ resistor or hardwired low as a function of the equipment design.
The PC0 C2 terminals are used to indicate the default power-class status for the node (the need for power from
the cable or the ability to supply power to the cable). See Table 9 for power-class encoding. The C/LKON
terminal is used as an input to indicate that the node is a contender for either isochronous resource manager
(IRM) or for bus manager (BM).
The TSB41AB1 supports suspend/resume as defined in the IEEE 1394a-2000 specification. The suspend
mechanism allows pairs of directly connected ports to be placed into a low-power state (suspended state) while
maintaining a port-to-port connection between bus segments. While in the suspended state, a port is unable to
transmit or receive data transaction packets. However, a port in the suspended state is capable of detecting
connection status changes and detecting incoming TPBIAS. When the port of the TSB41AB1 is suspended, all
circuits except the band gap reference generator and bias detection circuit is powered down, resulting in
significant power savings. For additional details of suspend/resume operation see IEEE 1394a-2000. The use of
suspend/resume is recommended for new designs.
34

The port transmitter and receiver circuitry is disabled during power down (when the PD input terminal is
asserted high), during reset (when the RESET\ input terminal is asserted low), when no active cable is
connected to the port, or when controlled by the internal arbitration logic. The TPBIAS output is disabled
during power down, during reset, or when the port is disabled as commanded by the LLC.
The cable-not-active (CNA) output terminal (64-terminal PAP package only) is asserted high when there are no
twisted-pair cable ports receiving incoming bias (that is, they are either disconnected or suspended), and can be
used along with LPS to determine when to power down the TSB41AB1. The CNA output is not debounced.
When the PD terminal is asserted high, the CNA detection circuitry is enabled (regardless of the previous state
of the ports) and a pulldown is activated on the RESET\ terminal so as to force a reset of the TSB41AB1
internal logic.
The LPS (link power status) terminal works with the C/LKON terminal to manage the power usage in the node.
The LPS signal from the LLC is used in conjunction with the LCtrl bit to indicate the active/power status of the
LLC. The LPS signal is also used to reset, disable, and initialize the PHY-LLC interface (the state of the PHY-
LLC interface is controlled solely by the LPS input, regardless of the state of the LCtrl bit).
35

The LPS input is considered inactive if it remains low for more than 2.6 us and is considered active otherwise.
When the TSB41AB1 detects that LPS is inactive, it places the PHY-LLC interface into a low-power reset state
in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the
SYSCLK output remains active. If the LPS input remains low for more than 26 us, the PHY-LLC interface is
put into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface
is also held in the disabled state during hardware reset. The TSB41AB1 continues the necessary repeater
functions required for normal network operation regardless of the state of the PHY-LLC interface. When the
interface is in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and
returns it to normal operation.
When the PHY-LLC interface is in the low-power disabled state, the TSB41AB1 automatically enters a low-
power mode if the port is inactive (disconnected, disabled, or suspended). In this low-power mode, the
TSB41AB1 disables its internal clock generators and also disables various voltage and current reference
circuits depending on the state of the port (some reference circuitry must remain active in order to detect new
cable connections, disconnections, or incoming TPBIAS, for example). The lowest power consumption (the
ultralow-power sleep mode) is attained when the port is either disconnected, or disabled with the port interrupt
enable bit cleared. The TSB41AB1 exits the low-power mode when the LPS input is asserted high or when a
port event occurs which requires that the TSB41AB1 become active in order to respond to the event or to
notify the LLC of the event (for example, incoming bias is detected on a suspended port, a disconnection is
detected on a suspended port, a new connection is detected on a nondisabled port, etc.). The SYSCLK output
becomes active (and the PHY-LLC interface is initialized and becomes operative) within 7.3 ms after LPS is
asserted high when the TSB41AB1 is in the low-power mode.
36

The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the
C/LKON signal is a square wave of approximately 163-ns period. The PHY activates the C/LKON output
when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS
input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on
PHY packet addressed to this node is received, or when a PHY interrupt occurs. The PHY deasserts the
C/LKON output when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also
deasserts the C/LKON output when a bus reset occurs unless a PHY interrupt condition exists which would
otherwise cause C/LKON to be active.
37

Functional block diagram
CPS
LPS Received Data
ISO Decoder/Retimer
Link
CNA Interface
I/O
SYSCLK
LREQ TPA+
CTL0 TPA-
CTL1
D0
D1
D2
D3
D4 Arbitration TPB+
D5 and Control TPB-
D6 State Machine
D7 Logic
PC0
PC1
PC2
CLKON
R0 Bias Voltage
R1 and
Current
TPBIAS Generator
Crystal
XI
Transmit Data Oscillator
XO
Encoder PLL System,
PD FILTER0
and Clock FILTER1
RESET Generator
38

Features
Fully supports provisions of IEEE 1394-1995 standard for high performance serial bus and IEEE 1394a-2000
Fully interoperable with firewire™ and i.LINK™ implementation of IEEE Std 1394
Fully compliant with openHCI requirements
Provides one IEEE 1394a-2000 fully compliant cable port at 100/200/400 megabits per second (Mbits/s)
Full IEEE 1394a-2000 support includes: connection debounce, arbitrated short reset, multispeed concatenation,
arbitration acceleration, fly-by concatenation, port disable/suspend/resume
Register bits give software control of contender bit, power class bits, link active control bit, and IEEE
1394a- 2000 Features
IEEE 1394a-2000 compliant common mode noise filter on incoming TPBIAS
Extended resume signaling for compatibility with legacy DV devices, and terminal- and register- compatibility
with TSB41LV01, allow direct isochronous transmit to legacy DV devices with any link layer even when root
Power-Down features to conserve energy in battery powered applications include: automatic device power
down during suspend, device power-down terminal, link interface disable via LPS, and inactive ports
powered down
Failsafe circuitry senses sudden loss of power to the device and disables the port to ensure that the device
does not load TPBIAS of the connected device and blocks any leakage path from the port back to
the device power plane
Software device Reset (SWR)
Industry leading low power consumption
Ultralow-power sleep mode
39

Cable power presence monitoring
Cable ports monitor line conditions for active connection to remote node
Data interface to link-layer controller through 2/4/8 parallel lines at 49.152MHz
Interface to link layer controller supports low cost TI bus-holder isolation and optional annex J electrical
isolation
Interoperable with link-layer controllers using 3.3 V
Single 3.3-V supply operation
Low-cost 24.576MHz crystal provides transmit, receive data at 100/200/400Mbits/s, and link-layer controller
clock at 49.152MHz
Low-cost high-performance 48/64-pin TQFP (PHP/PAP) thermally enhanced packages increase thermal
performance by up to 210%
Meets Intel™ mobile power guideline 2000
1.2.7 AC’97 Audio System: Advance Logic, Inc, ALC201

SiS961 is an AC’97 2.1 compliant controller that communicates with companion Codecs SiS a digital serial
link called the AC-link.
The ALC201 is an AC97 2.2 compatible stereo audio codec designed for PC multimedia systems.The
ALC201 provides the way for PC98 and PC99-compliant desktop, portable and entertainment PCs, where
high-quality audio is required. The ALC201 AC’97 CODEC provides a complete high quality audio solution.
40

Features
Single chip audio CODEC with high S/N ratio (>90 dB)
18-bit ADC and DAC resolution
Compliant with AC’97 2.2 specification
Meet performance requirements for audio on PC2001 systems
18-bit stereo full-duplex CODEC with independent and variable sampling rate
4 analog line-level stereo input with 5-bit volume control: LINE_IN, CD, VIDEO, AUX
2 analog line-level mono input: PC_BEEP, PHONE_IN
Mono output with 5-bit volume control
Stereo output with 5-bit volume control
2 MIC inputs: Software selectable
Power management
3D Stereo Enhancement
Headphone output with 50mW/20ohm driving capability (ALC201)
Line output with 50mW/20ohm driving capability (ALC201A)
Headphone jack-detect function to mute LINE output
Multiple CODEC extension
MC’97 chained in allowed for multi-channel application
External Amplifier power down capability
Support S/PDIF out is fully compliant with AC’97 specification rev2.2
41

DC offset cancellation
Power support: Digital: 3.3V Analog: 5V
Standard 48-Pin LQFP Package
1.2.8 MDC: PCTel Modem Daughter Card PCT2303W

The PCT2303W chipset is designed to meet the demand of this emerging worldwide AMR/MDC market. The
combination of PC-TEL’s well proven PCT2303W chipset and the HSP56TM MR software modem driver
allows systems manufactures to implement modem functions in PCs at a lower bill of materials (BOM) while
maintaining higher system performance.
PC-TEL has streamlined the traditional modem into the Host Signal Processing (HSP) solution. Operating
with the Pentium class processors, HSP becomes part of the host computer’s system software. It requires less
power to operate and less physical space than standard modem solutions. PC-TEL’s HSP modem is an easily
integrated, cost-effective communications solution that is flexible enough to carry you into the future.
The PCT2303W chip set is an integrated direct access arrangement (DAA) and Codec that provides a
programmable line interface to meet international telephone line requirements. The PCT2303W chip set is
available in two 16-pin small outline packages (AC’97 interface on PCT303A and phone-line interface on
PCT303W). The chip set eliminates the need for an AFE, an isolation transformer, relays, opto-isolators, and
2-to 4-wire hybrid. The PCT2303W chip set dramatically reduces the number of discrete components and cost
required to achieve compliance with international regulatory requirements. The PCT2303W complies with
AC’97 Interface specification Rev. 2.1.
42

The chip set is fully programmable to meet worldwide telephone line interface requirements including those
described by CTR21, NET4, JATE, FCC, and various country-specific PTT specifications. The programmable
parameters of the PCT2303W chip set include AC termination, DC termination, ringer impedance, and ringer
threshold. The PCT2303W chip set has been designed to meet stringent worldwide requirements for out-of-
band energy, billing-tone immunity, lightning surges, and safety requirements.
Operating System Compatibility

Windows 98 /NT4.0 /Win 2K /Win XP
Compatibility
ITU-T V.90 56000, 54667, 53333,52000, 50667, 49333, 48000,
46667, 45333, 42667, 41333, 40000, 38667, 37333,
36000, 34667, 33333, 32000, 30667, 29333, 28000bps
K56Flex 56000, 54000, 52000, 50000, 48000, 46000, 44000,
42000, 40000, 38000, 36000, 32000bps
ITU-T V.34Annex 33600,31200 bps
ITU-T V.34 28800 bps
ITU-T V.32bis 14400 bps
ITU-T V.32 9600,4800 bps
ITU-T V.22bis 2400 bps
ITU-T V.22 1200 bps
ITU-T V.21 300 bps
ITU-T V.23 1200/75 bps
43

ITU-T V.17 14400,12000,9600,7200 bps
ITU-T V.29 9600,7200 bps
ITU-T V.27ter 4800,2400 bps
Bell 212A 1200 bps
Bell 103 300 bps
Modulation
56000bps(V90&K56Flex) PCM
33600 bps (V.34Annex) TCM
28800 bps (V.34) TCM
14400 bps (V.32bis) TCM
7200 bps (V.32bis) QAM
9600 bps (V.32) TCM, QAM
4800 bps (V.32) QAM
14400 bps (V.17) TCM
12000 bps (V.17) TCM
9600 bps (V.29) QAM
7200 bps (V.29) QAM
4800 bps (V.27ter) DPSK
44

2400 bps (V.27ter) DPS
2400 bps (V.22bis) QAM
1200/75bps (V.23) FSK
1200bps(V.22/Bell 212A) DPSK
300bps(V.21/Bell 103) FSK
Data Compression
V.42bis, MNP5
Error Correction
V.42 LAPM, MNP 2-4
DTE interface
DTMF Tone Frequency

Low Group Frequency (Hz)
697 770 852 941
High Group 1209 1 4 7 *
Frequency 1336 2 5 8 0
(Hz) 1477 3 6 9 #
1633 A B C D
DTMF signal level
45

1.2.8.1 High Group -10+/-2dBm
1.2.8.2 Low Group -12+/-2dBm

Dialing Type Tone or pulse dialing
Telephone Line interface RJ-11
Return Loss 300HZ - 3400HZ >= 10db
Flow Control XOFF/XON or RTS/CTS
Receive Level -35 +/- 2dBm
Transmit Level >-15 dBm
Specification and features subject to change without notice!
46

1.2.9 Keyboard System: H8 (3437S) Universal Keyboard Controller
CPU Two-way general register configuration
Eight 16-bit registers or sixteen 8-bit registers
High-speed operation
Maximum clock rate: 16Mhz at 5V
Available in temperature range: 0°C~70°C
Memory Include 60KB ROM and 2KB RAM
16-bit free-running timer
One 16-bit free-running counter
Two output-compare lines
Four input capture lines
8-bit timer (2 channels) Each channel has one 8-bit up counter, two time constant registers
PWM timer (2 channels) Resolution: 1/250
Duty cycle can be set from 0 to 100%
I2C bus interface (one channel) Include single master mode and slave mode
Host interface (HIF) 8-bit host interface port

Three hosts interrupt requests (HIRQ1, 11,12)
Regular and fast A20 gate output
Keyboard controller Controls a matrix-scan keyboard by providing a keyboard
scan function with wake-up Interrupts and sense ports
A/D converter 10-bit resolution

8 channels: single or scan mode (selectable)
47

D/A converter 8-bit resolution
2 channels
Interrupts Nine external interrupt lines: NMI#, IRQ0 to 7#
26 on-chip interrupt sources
Power-down modes Sleep mode
Software standby mode
Hardware standby mode
A single chip microcomputer
On-chip flash memory
Maximum 64kbyte-address space
Support three PS/2 port for external keyboard, mouse and internal track pad.
Support SMI, SCI trigger input:
Cover switch
Battery charging control
Smart Battery monitoring
Control D/D system on/off
Fan control and LED indicator serial interface
100pin TQFP
48

1.2.10 System Flash Memory (BIOS)
2 M bit Flash memory
Flashed by 5V only
User can upgrade the system BIOS in the future just running flash program
1.2.11 Memory System

64MB, 128MB, 256MB, 512MB (x64) 200-Pin DDR SDRAM SODIMMs
JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM)
Utilizes 200 Mb/s and 266 Mb/s DDR SDRAM components
64MB (8 Meg x 64 [H]); 128MB (16 Meg x 64, [H] and [HD]); 256MB (32 Meg x 64 [HD]); 512MB
(64 Meg x 64 [HD])
VDD= VDDQ= +2.5V ±0.2V
VDDSPD = +2.2V to +5.5V
2.5V I/O (SSTL_2 compatible)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs; center-aligned with data for WRITEs
Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle
Bi-directional data strobe (DQS) transmitted/received with data—i.e.,source-synchronous data capture
Differential clock inputs (CK and CK# - can be multiple clocks, CK0/CK0#, CK1/CK1#, etc.)
Four internal device banks for concurrent operation
49

Selectable burst lengths: 2, 4 or 8
Auto precharge option
KBC and PS2 mouse can be individually disabled
Auto Refresh and Self Refresh Modes
15.6µs (MT4VDDT864H, MT8VDDT1664HD), 7.8125µs (MT4VDDT1664H, MT8VDDT3264HD,
MT8VDDT6464HD) maximum average periodic refresh interval
Serial Presence Detect (SPD) with EEPROM
Serial Presence Detect (SPD) with EEPROM
Fast data transfer rates PC2100 or PC1600
Selectable READ CAS latency for maximum compatibility
Gold-plated edge contacts
1.2.12 PHY: 3.3-V 10Base-T/100Base-TX Integrated PHYceiver The ICS1893

is a low-power, physical-layer device (PHY)
General Description
The ICS1893 is a low-power, physical-layer device (PHY) that supports the ISO/IEC 10Base-T and 100Base-
TXCarrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards. The ICS1893
architecture is based on the ICS1892. The ICS1893 supports managed or unmanaged node, repeater, and switch
applications.
50

The ICS1893 incorporates digital signal processing (DSP) in its Physical Medium Dependent (PMD) sublayer.
As a result, it can transmit and receive data on unshielded twisted-pair (UTP) category 5 cables with attenuation
in excess of 24 dB at 100 MHz. With this ICS-patented technology, the ICS1893 can virtually eliminate errors
from killer packets.
The ICS1893 provides a Serial Management Interface for exchanging command and status information with a
Station Management (STA) entity.
The ICS1893 Media Dependent Interface (MDI) can be configured to provide either half- or full-duplex
operation at data rates of 10 MHz or 100 MHz. The MDI configuration can be established manually (with input
pins or control register settings) or automatically (using the Auto-Negotiation features). When the ICS1893
Auto-Negotiation sublayer is enabled, it exchanges technology capability data with its remote link partner and
automatically selects the highest-performance operating mode they have in common.
Features
Supports category 5 cables with attenuation in excess of 24 dB at 100 MHz across a temperature range
from -5 to +85 C
DSP-based baseline wander correction to virtually eliminate killer packets across temperature range
from -5 to +85 C
Low-power, 0.35-micron CMOS (typically 400 mW)
Single 3.3-V power supply
51

Single-chip, fully integrated PHY provides PCS, PMA, PMD and AUTONEG sublayers of IEEE standard
10Base-T and 100Base-TX IEEE 802.3 compliant
Fully integrated, DSP-based PMD includes:
Adaptive equalization and baseline wander correction

Transmit wave shaping and stream cipher scrambler
MLT-3 encoder and NRZ/NRZI encoder
Highly configurable design supports:

Node, repeater, and switch applications
Managed and unmanaged applications
10M or 100M half- and full-duplex modes
Parallel detection
Auto-negotiation, with Next Page capabilities
MAC/Repeater Interface can be configured as:

10M or 100M Media Independent Interface
100M Symbol Interface (bypasses the PCS)
10M 7-wire Serial Interface
Small Footprint 64-pin Thin Quad Flat Pack (TQFP)
52

1.3 Other Functions
1.3.1 Hot Key Functions
Keys Feature Meaning

Combination
Fn + F1 Reserve
Fn + F2 Reserve
Fn + F3 Volume Down
Fn + F4 Volume Up
Fn + F5 LCD/external CRT Rotate display mode in LCD only, CRT only, and simultaneously display.
switching
Fn + F6 Brightness down Decreases the LCD brightness
Fn + F7 Brightness up Increases the LCD brightness
Fn + F8 Brightness MAX Toggle Max Brightness
Fn + F9 Pause
Fn + F10 Break
Fn + F11 Panel Off/On Toggle Panel on/off
Fn + F12 Suspend to DRAM / HDD Force the computer into either Suspend to HDD or Suspend to DRAM mode
depending on BIOS Setup.
1.3.2 Power on/off/suspend/resume button

APM mode
At APM mode, Power button is on/off system power.
53

APM mode
At ACPI mode. Windows power management control panel set power button behavior.
You could set “standby”, “power off” or “hibernate”(must enable hibernate function in power Management) to
power button function.
Continue pushing power button over 4 seconds will force system off at ACPI mode.
1.3.3 Cover Switch

System automatically provides power saving by monitoring Cover Switch. It will save battery power and
prolong the usage time when user closes the notebook cover.
At ACPI mode there are four functions to be chosen at windows power management control panel.
1. None
2. Standby
3. Off
4. Hibernate (must enable hibernate function in power management)
1.3.4 Reset Switch

There is a reset switch at bottom side of notebook. It will reset embedded controller H8 and turn off system
totally. When system hands up and Power button has no function, this switch is the only way to turn off
system without remove power source.
54

1.3.5 LED Indicators
System has eight status LED indicators to display system activity, which include three at front side and five
above keyboard.
1) Three LED indicators at front side:

From left to right that indicates: AC Power, Battery Power and Battery Status
AC Power: This LED lights green when AC is powering the notebook, and flash (on 1 second, off 1
second) when Suspend to DRAM is active using AC power. The LED is off when the notebook is off or
powered by batteries.
Battery Power: This LED lights green when the notebook is being powered by Battery, and flash (on 1
second, off 1 second) when Suspend to DRAM is active using Battery power. The LED is off when the
notebook is off or powered by batteries, or when Suspend to Disk.
Battery Status: During normal operation, this LED stays off as long as the battery is charged. When the
battery charge drops to 10% of capacity, the LED lights red, flashes per 1 second and beeps per 2 second.
When AC is connected, this indicator glows green if the battery pack is fully charged or orange (amber) if
the battery is being charged.
2) Five LED indicators above keyboard:

From left to right that indicates LAN, CD-ROM/HARD DISK DRIVE, NUM LOCK, CAPS LOCK and
SCROLL LOCK.
55

1.3.6 Battery Status
Battery Warning
System also provides Battery capacity monitoring and gives user a warning so that users have chance to save
his data before battery dead. Also, this function protects system from mal-function while battery capacity is
low.
Battery Warning: Capacity below 10%, Battery Capacity LED flashes per second, system beeps per 2 seconds.
System will suspend to HDD after 2 Minutes to protect users data.
Battery Low State

After Battery Warning State, and battery capacity is below 4%, system will generate beep for twice per second.
Battery Dead State

When the battery voltage level reaches 7.4 volts, system will shut down automatically in order to extend the
battery packs' life.
1.3.7 Fan power on/off management

FAN is controlled by H8 embedded controller-using AD2201 to sense CPU temperature and PWM control fan
speed. Fan speed is depended on CPU temperature. Higher CPU temperature faster Fan Speed.
56

1.3.8 CMOS Battery
CR2032 3V 220mAh lithium battery
When AC in or system main battery inside, CMOS battery will consume no power.
AC or main battery not exists, CMOS battery life at less (220mAh/5.8uA) 4 years.
Battery was put in battery holder, can be replaced.
1.3.9 I/O Port

One Power Supply Jack.
One External CRT Connector For CRT Display
Supports two USB port for all USB devices.
One MODEM RJ-11 phone jack for PSTN line
One RJ-45 for LAN.
Headphone Out Jack.
Microphone Input Jack.
Line in Jack
One Card Bus Sockets for one type II PC card extension
1.3.10 Battery current limit and learning

Implanted H/W current limit and battery learning circuit to enhance protection of battery.
57

1.4 Peripheral Components
1.4.1 LCD Panel

LCD 14.1 Hyundai HT14X12-100A
1.4.2 Ext.Floppy Disk Drive

Mitsumi D353GU
External USB 3.5” 1.44MB /1.2 MB/720KB FDD (Option)
1.4.3 HDD
Hitachi 30GB
Height: 9.5 mm, 2.5”
1.4.4 24X CD-ROM Drive

TEAC
58

1.4.5 8W/4R CD-RW
KEM
Height: 12.7 mm IDE I/F
1.4.6 Keyboard
Windows 98 Keyboard, 1 color, multi languages support JP, US and Europe Keyboard with “ Volume UP ”
and “ Volume Down ” word.
1.4.7 Track Pad Synaptics

Accurate positioning
Low fatigue pointing action
Low profile
No moving part, high reliability
Low power consumption
Environmentally sealed
Compact size.
Software configurable
Low weight
Operating temperature: 0 to 60 degree C
59

1.4.7 Track Pad Synaptics
Operating humidity: 5%-95% relative humidity, non condensing
Storage temperature: -40 to +65 degree C
ESD: 15KV applied to front surface SEE ESD Testing specification PN 520-000270-01
Power supply voltage: 5.0Voltage ± 10%
Power supply current: 4.0mA max operating
1.4.8 Fan
HY45J05-001
1.4.9 Memory
DDR-RAM/ATP//128M/256M
DDR-RAM/Apacer//128M/256M
DDR-RAM/Unidorsa//128M/256M
1.4.10 Modem MDC

Askey
60

1.5 Power Management
The 8575 system has built in several power saving modes to prolong the battery usage for mobile purpose.
User can enable and configure different degrees of power management modes via ROM CMOS setup
(booting by pressing F2 key). Following are the descriptions of the power management modes supported.
1.5.1 System Management Mode

Full on mode
In this mode, each device is running with the maximal speed. CPU clock is up to its maximum.
Doze Mode
In this mode, CPU will be toggling between on & stop grant mode either. The technology is clock throttling.
This can save battery power without loosing much computing capability. The CPU power consumption and
temperature is lower in this mode.
Standby mode
For more power saving, it turns of the peripheral components. In this mode, the following is the status of each
device:
CPU: Stop grant
LCD: backlight off
HDD: spin down
61

Suspend to DRAM
The most chipset of the system is entering power down mode for more power saving. In this mode, the
following is the status of each device:
Suspend to DRAM:
CPU: off
Twister K: Partial off
VGA: Suspend
PCMCIA: Suspend
Audio: off
SDRAM: self refresh
Suspend to HDD:
All devices are stopped clock and power-down
System status is saved in HDD
All system status will be restored when powered on again
1.5.2 Other Power Management Functions

HDD & Video access
System has the ability to monitor video and hard disk activity. User can enable monitoring function for video
and/or hard disk individually. When there is no video and/or hard disk activity, system will enter next PMU
state depending on the application. When the VGA activity monitoring is enabled, the performance of the
system will have some impact.
62

1.6 Appendix 1: SiS961 GPIO Definitions
SB_SiS961 GPIO
Signal MUX Buffer Power During After
Name Function Mitac Definition Type Plane Tolerant PCISRT# PCISRT# S1 S3 S4/S5
GPIO0 MB_ID0 I/O Main Driven Defined Driven Defined Driven Defined Off Off
GPIO1 LDRQ1# CD_IN# I/O Main Driven Defined Driven Defined Driven Defined Off Off
GPIO2 THERM# SB_THRM# I/O Main Driven Defined Driven Defined Driven Defined Off Off
GPIO3 EXTSMI# EXTSMI# I/O Main Driven Defined Driven Defined Driven Defined Off Off
GPIO4 CLKRUN# CLKRUN# I/O Main Driven Defined Driven Defined Driven Defined Off Off
GPIO5 PREQ5# LCD_ID0 I/O Main Driven Defined Driven Defined Driven Defined Off Off
GPIO6 PGNT5# LCD_ID1 I/O Main Driven Defined Driven Defined Driven Defined Off Off
GPIO7 LCD_ID2 I/O AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined
GPIO8 RING# WAKEUP# I/O AUX High-Z High-Z High-Z High-Z High-Z
GPIO9 AC_SDIN2 SCI# I/O AUX High-Z High-Z High-Z High-Z High-Z
GPIO10 AC_SDIN3 CRT_IN# I/O AUX High-Z High-Z High-Z High-Z High-Z
GPIO11 SPK_OFF I/O AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined
GPIO12 CPUSTP# CPU_STP# I/O AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined
MPCIACT#
GPIO13 DPRSLPVR /DPRSLPVR I/O AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined
GPIO14 CD_PWRON# I/O AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined
GPIO15 VR_HILO# VR_HILO# I/O AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined
GPIO16 LO_HI# LO_HI# OD AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined
GPIO17 VGATEM# VGATEM# I/O AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined
GPIO18 PMCLK CD_RST O AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined
GPIO19 SMBCLK SMBCLK O AUX High-Z High-Z High-Z High-Z High-Z
GPIO20 SMBDATA SMBDATA O AUX High-Z High-Z High-Z High-Z High-Z

63

1.7 Appendix 2: H8 Pins Definitions
The shadowed block is the selected function
Name Pin H8 Pin During After ON STANDBY Function
Definitions RESET RESET/OFF
MD0 6 H8_MODE0 I↑ I H I H I H H
H mode3 single chip mode
MD1 5 H8_MODE1 I↑ I H I H I H
STBY# 8 STBY# I↑ I H I H I H H8 Hardware Standby input pull high

NMI# 7 POWER BTN# I↑ I H I HL I H Power button
H
RESET# 1 RESET# I I LH I H I H H8 chip reset
XTAL 2 Crystal I I I I Crystal input
EXTAL 3 Crystal I I I I
RESET OUT# 100 RESET OUT O O O O
Port A COMOS input level (input high min=3.5V, input low max=1.0V)
PA0 48 LID# I↑ I H I I H
PA1 47 H8 ADEN# I↑ I H/L I I H/L AC adaptor in detect
PA2 31 RI# I↑ I H I I H Ring detect
PA3 30 BATT DEAD# I↑ I H I I H Battery low detect

PA4 21 H8 SUSC I↑ I H I I L System resume from S4 soft off through RTC
Alarm
PA5 20 H8 SUSC# I↑ I L I I H System to S4 soft off
PA6 11 BAT_CLK I↑ I L I I H
PA7 10 H8_SUSB I↑ I H I L I H Invert from SUSA# to wake up H8 when system
resumed by MDC modem and internal LAN.
Inform system power management status
64

PCI reset gate
Port B TTL input voltage (input high min=2V, input low max=0.8V)
PB0 91 H8 SB PWRBTN# T O L IHL O Keep H Power button trigger VIA8231 on/off Duplicate
Power BTN# 5→3V
PB1 10 H8 WAKE# T O H O O Keep H Wake up SB at ACPI mode 5→3V
PB2 81 Force Discharge T O O Keep H Power button trigger VIA8231 on 5→3V

PB3 80 CHARGING1 T O LLH O O Keep Battery charge control
PB4 69 VDD5 SW T↓ O L O H O Keep H H8 VDD5 power source switch
PB5 68 H8 RCIN# T O O LH O Keep H Reset CPU
PB6 58 CHARGING2 T O O O Keep Battery charge control
PB7 57 SMbus SW T O O O Keep
PB6 58 VADJ1 T O O O Keep Lithium ion battery charging CV mode voltage

level adjust
PB7 57 VADJ2 T O O O Keep
Port 1 TTL input voltage (input high min=2V, input low max=0.8V)
P10/A0 79 KB OUT0 L O L O LH O Keep L Key matrix scan output 0

65

Continue to previous

P23/A11 64 KB OUT11 L O 0 O LH O Keep L Key matrix scan output 11
P30/HDB0/D0 82 ISA SD0 T I/O I/O I/O Keep ISA DATA bit 0
66

P40/TMCI0 49 H8 PWR ON T↓ O L O LH O Keep System power on, need pull down to
define initial state during reset
P41/TMO0 50 H8 THRM# T O L O H O Keep H Thermal throttling control to
Southbridge
P42/TMRI0 51 SCI#/ T O H O Keep SCI output and Fan Speed Tachometer
FAN SPD SW Switch
P43/TMCI1/HIRQ1 52 H8 SCI/ T O O O Keep Need invert to SCI# sending to SB
FAN SPEED 5→3V/ Fan speed tachometer
P44/TMCO1/HIRQ1 53 ISA IRQ1 T O 0 O O Keep Keyboard IRQ1
P45/TMRI1/HIRQ1 54 ISA IRQ12 T O 0 O O Keep PS2 mouse IRQ12
P46/PWM0 55 Beep sound T O O O Keep Hot key and battery dead beep sound
P46/PWM0 55 FAN ON#0 T O 1 O O Keep Fan power PWM control
P47/PWM1 56 FAN ON#1 T O 1 O O Keep Fan power PWM control
P50/TXD0 14 LED DATA T O O O Keep LED indicator shift data

P51/RXD0 13 H8 SMI# T O O O Keep External SMI# 5→3V
P52/SCK0 12 LED CLK T O O O Keep LED indicator shift clock
67

Port 6 Schmitt trigger input voltage (min=1.0V max=3.5V)
P60/KEYIN0/FTCI 26 KEY IN0 T↑ I I I Keep Key matrix input 0 need pull high
P61/KEYIN1/FTOA 27 KEY IN1 T↑ I I I Keep H Key matrix input 1 need pull high
P62/KEYIN2/FTIA 28 KEY IN2 T↑ I I I Keep Key matrix input 2 need pull high
P63/KEYIN3/FTIB 29 KEY IN3 T↑ I I I Keep Key matrix input 3 need pull high
P64/KEYIN4/FTIC 32 KEY IN4 T↑ I I I Keep Key matrix input 4 need pull high
P65/KEYIN5/FTID 33 KEY IN5 T↑ I I I Keep Key matrix input 5 need pull high
P66/KEYIN6/IRQ6 34 KEY IN6 T↑ I I I Keep Key matrix input 6 need pull high
P67/KEYIN7/IRQ7 35 KEY IN7 T↑ I I I Keep Key matrix input 7 need pull high
P70/AN0 38 BAT VOLT1 T I I I T Battery voltage measure

P71/AN1 39 BAT VOLT2 T I I I T Battery voltage measure
P71/AN1 39 I_LIMIT T I I I T
P72/AN2 40 3V/PWR ok T I I I T Monitor system on/off state

P73/AN3 41 2.5V T I I I T
P73/AN3 41 LI/NIMH# T I I I Keep To differential 3S3P lithium ion
battery and 9S NiMH battery
P74/AN4 42 BAT TEMP1 T I I I T Battery thermister temperature
P75/AN5 43 BAT TEMP2 T I I I T Battery thermister temperature
P75/AN5 43 VCC CORE T I I I T
P76/AN6/DA0 44 Charge-I_CTR T O O O T Charging current adjust
P77/AN7/DA1 45 BL ADJ T O O O T Backlight inverter brightness adjust
68

P80/HA0 93 ISA SA2 T I I I Keep
P81/GA20 94 X(H8 A20GATE) T O O O Keep H CPU A20gate
P82/CS1 95 H8 KBCS# T I I I Keep IO port 60/64 chip select

P83/IOR 96 ISA IOR# T I I I Keep ISA I/O read#
P84/IRQ2/TXD1 97 ISA IOW# T I I I Keep ISA I/O write
P85/IRQ4/RXD1 98 H8 MCCS# T I I I Keep IO port 62/66 chip select
P86/IRQ5/SCK1 99 BAT CLK T↑ I/O I/O I/O Keep SM BUS clock need pull high 5→3V
P90/IRQ2/ESC2 25 K/M CLK T↑ I/O I/O I/O Keep need pull high
P91/IRQ1/EIOW 24 M CLK T↑ I/O I/O I/O Keep need pull high
P92/IRQ0 23 H8/T CLK T↑ I/O I/O I/O Keep need pull high
P93/RD 22 K/M DATA T↑ I/O I/O I/O Keep need pull high
P94/WR 19 M DATA T↑ I/O I/O I/O Keep need pull high
P95/AS 18 H8/T DATA T↑ I/O I/O I/O Keep need pull high
P96/0 17 ENABKL T↑ I I I T Read H8 send A20gate status
P97/WAIT/SDA 16 BAT DATA T↑ I/O I/O I/O Keep SM BUS clock need pull high 5→3V
↑ Pull High
↓ Pull Low
5→3V Level shift
69

1.8 Appendix 3: 8575 Product Specifications
CPU Intel Pentium 4 Processors Willamette/Northwood with mFCPGA2 Package, mPGA478 Socket
Support up to Willamette P4 1.7GHz (Throttling) / Northwood above 2.0 GHz(Throttling)
FSB 400MHz / PC 2100
Chipset SiS650 + SiS961
L2 Cache 256KB
System BIOS Flash EPROM (Include System BIOS and VGA BIOS)
ACPI 1.0b; DMI 2.3.1 compliant
Memory 0MB SDRAM on board; Expandable to 1024MB
Expandable with combination of optional 128MB/256MB/512MB memory
Two 200-pin DDR SDRAM Memory Module, PC 2100/1600 specifications
ROM Drive 12.7mm Height
24X CD ROM Drive
8X DVD ROM Drive
8X4x24 CD-RW or above
8X8X4X24 Combo or above
HDD  2.5x9.5 mm height: 10/15/20/30GB; Support Ultra DMA 66/100
Reseller Exchangeable
Ext. FDD Support External FDD w/z USB I/F; 3.5" Format for 720KB/1.2MB/1.44MB
Display 14.1”/ 15” XGA TFT display; Resolution: 1024 x 768
14.1”/15” SXGA+ TFT display; Resolution: 1280 x 1024 (P)
70

Video Controller Integrated in SiS650

Support Multi Monitor
Ultra AGP
REAL 256 2D/3D Graphic
Keyboard 19mm pitch/3.0mm stroke
Windows Logo Key x 1; Application Key x 1
Button 5x Easy Start Buttons (functions defined by user)
Pointing Device Glide pad with 2x buttons and 1x scroll button
PCMCIA Type II or Type I x1
CardBus Support
Audio System Sound Blaster Pro compatible
Built-in mono microphone
Support AC97 2.1
2X Speakers (1Watt each)
I/O Port Bi-directional Parallel Port (EPP/ECP) x 1
Standard USB1.1 port x 2
RJ-11 port x 1
RJ-45 port x 1
IR port x1, complies with IrDA 1.1
DC input x 1
VGA monitor port x1
Audio-out x 1 (SPIDF)
Mic-in x 1
71

I/O Port Hardware Volume Control

IEEE1394a Port x 1
S-Video Out Port x 1 (NTSC/PAL )
Communication Built-in 56Kbps V.90 MDC modem
Built-in 10/100 based-T LAN
Power Supply 9-cell Li-ion (2000mAH/3.7V)

User swappable
Battery Life: 1.5 hrs
Support Power off charge : 3hr, 80% in 1.6Hrs
Support Power on charge : 4hr~5.5hr
AC adapter Universal AC adapter 90W ; Input: 100-240V, 50/60Hz AC
Dimensions 328 x 274 x 46~37
Weight 3.8
Accessories Power Cord, AC Adapter, RJ-11 Phone Cable, Manual, System Driver CD-Title
Architecture Support PC2001 specification, designed for Windows ME, Windows 2000 & Windows XP
Options 128MB/256MB/512MB DDR SDRAM, 9-cell Li-ION Battery Pack, AC Adapter w/o
Power Cord, Notebook Carry Bag
72

2. System View and Disassembly
2.1 System View
2.1.1 Front View t
n Stereo Speaker Set

o Device Indicators
p Mini IEEE1394 Connector
q External Microphone Jack
n o pqrs n
r Line Out Phone Jack
s Volume Control
t Top Cover Latch
2.1.2 Left-side View

n Kensington Lock
o Ventilation Openings
p RJ-45 Connector
q PC Card Slot n o p q r
r Hard Disk Drive
73

2.1.3 Right-side View
n Battery Pack
o CD-ROM/DVD-ROM Drive
n o
2.1.4 Rear View

n Power Connector
o S-Video Output Connector
p USB Ports
q Parallel Port
r D/D Fan
s RJ-11 Connector
no p q rs t u
t VGA Port
u Ventilation Openings
74

2.1.5 Top-open View
v
n LCD Screen
u
o Microphone
t
p Keyboard n s
q Touch Pad
r
r Power Button
s Easy Start Buttons
t Battery Charge Indicator o
u Battery Power Indicator p
v AC Power Indicator
q
75

2.2 System Disassembly
The section discusses at length each major component for disassembly/reassembly and show corresponding
illustrations. Use the chart below to determine the disassembly sequence for removing components from the
notebook.
NOTE: Before you start to install/replace these modules, disconnect all peripheral devices and make sure the
notebook is not turned on or connected to AC power.
2.2.1 Battery Pack

2.2.2 Keyboard
Modular Components 2.2.3 CPU
2.2.4 HDD Module
2.2.5 CD-ROM Drive
2.2.6 SO-DIMM
NOTEBOOK 2.2.7 LCD Assembly

LCD Assembly Components 2.2.8 LCD Panel
2.2.9 Inverter Board
2.2.10 System Board
Base Unit Components 2.2.11 Touch-pad
2.2.12 Modem Card
76

2.2.1 Battery Pack
Disassembly
1. Carefully put the notebook upside down.
2. Slide the release lever to the “unlock” ( ) position (), then sliding and holding the release lever
outwards while pull the battery pack out of the compartment (). (Figure 2-1)

Figure 2-1 Remove the battery pack
Reassembly
1. Push the battery pack into the compartment. The battery pack should be correctly connected when you
hear a clicking sound.
2. Slide the release lever to the “lock” ( ) position.
77

2.2.2 Keyboard
Disassembly
1. Open the top cover.
2. Insert a small rod, such as a straightened paper clip, into the eject hole near the power connector of the
notebook. (Figure 2-2)
3. Push the rod firmly and slide the easy start buttons cover to the left (). Then lift the easy start buttons cover up
from the left side (). (Figure 2-3)
Figure 2-2 Insert a rod easy to remove Figure 2-16 Remove easy start
buttons cover
78

3. Remove three screws fastening keyboard on the base unit cover. (Figure 2-4)
4. Slightly lift up the keyboard and disconnect the cable from the system board to detach the keyboard.
(Figure 2-5)
Figure 2-4 Remove three screws Figure 2-5 Remove keyboard
Reassembly
1. Reconnect the keyboard cable and fit the keyboard back into place with three screws.
2. Replace the easy start buttons cover.
79

2.2.3 CPU
Disassembly
1. Remove the easy start buttons cover and keyboard to access the CPU compartment. (See section 2.2.2 Disassembly)
2. Remove seven screws fastening the heatsink cover and the rail. (Figure 2-6)
3. Remove three screws fastening the heatsink. (Figure 2-7)
Figure 2-6 Remove the cover and rail Figure 2-7 Remove the heatsink
80

4. Disconnect the fan’s power cord from the system board, then lift up the heatsink. (Figure 2-8)
5. Push the lever to the right. Then lift up the lever to the vertical position. Finally, Remove the existing CPU.
(Figure 2-9)
Figure 2-8 Remove the fan’s power cord Figure 2-9 Remove the CPU
Reassembly
1. Carefully, align the arrowhead corner of the CPU with the beveled corner of the socket, then insert CPU
pins into the holes. Place the lever back to the horizontal position and push the lever to the left.
2. Connect the fan’s power cord to the system board, fit the heatsink onto the top of the CPU and secure with
four screws.
3. Replace the keyboard .Then replace easy start buttons cover.
81

2.2.4 HDD Module
Disassembly
2. Remove one screw and slide the HDD module out of the compartment. (Figure 2-10)
3. Remove six screws to separate the hard disk drive from the metal shield. (Figure 2-11)
Figure 2-10 Remove HDD module Figure 2-11 Disassemble the hard disk
Reassembly
1. To install the hard disk drive, place it in the bracket and secure with six screws.
2. Slide the HDD module into the compartment and secure with one screw.
82

2.2.5 CD-ROM Drive
Disassembly
2. Remove one screw fastening the CD/DVD-ROM drive. Then hold the CD/DVD-ROM drive and slide it
outwards carefully. (Figure 2-12)
Figure 2-12 Remove one screw to loose

the CD/DVD-ROM drive
Reassembly
1. Push the CD/DVD-ROM drive into the compartment.
2. Secure the CD/DVD-ROM drive with one screw.
83

2.2.6 SO-DIMM
Disassembly
2. Remove seven screws to access the SO-DIMM socket. (Figure 2-13)
3. Full the retaining clips outwards () and remove the SO-DIMM (). (Figure 2-14)
Figure 2-13 Remove the SO-DIMM cover Figure 2-14 Remove the SO-DIMM
Reassembly
1. To install the SO-DIMM, match the SO-DIMM’s notched part with the socket’s projected part and firmly
insert the OS-DIMM into the socket at 20-degree angle. Then push down until the retaining clips lock the
SO-DIMM into cover.
2. Replace the SO-DIMM cover.
3. Replace seven screws to fasten the SO-DIMM socket cover.
84

2.2.7 LCD
Disassembly
1. Open the top cover. Remove easy start buttons cover, keyboard, and heatsink . (See section 2.2.2 and 2.2.3 Disassembly)
2. Remove the two hinge covers and remove two screws fastening the easy start button board.(Figure 2-15)
3. Disconnect the LCD cables from the system board, and remove four screws of the hinges. Now you can
separate the LCD assembly from the base unit. (Figure 2-16)
Figure 2-15 Remove the LCD hinge cover Figure 2-16 Remove cables and screws
and button board to separate LCD
Reassembly
1. Attach the LCD assembly to the base unit and secure with four screws on the hinges.
2. Reconnect the LCD cable connectors to the system board.
3. Fit the easy start button board and secure with tow screws.
4. Replace two hinge cover, the heatsink, keyboard and easy start buttons cover.
85

2.2.8 LCD Panel
Disassembly
1. Remove the LCD assembly. (See section 2.2.7 Disassembly)
2. Remove the four rubber pads and two screws on the lower part of the panel. (figure 2-17)
3. Insert a flat screwdriver to the lower part of the frame and gently pry the frame out. Repeat the process
until the frame is completely separated from the housing.
4. Remove the two screws on two sides and two screws on the lower part of the LCD panel, and disconnect
the cable from the inverter board. (figure 2-18)
Figure 2-17 Remove LCD frame Figure 2-18 Remove LCD panel
86

Reassembly
1. Fit the LCD panel back into place and secure with four screws, and reconnect the cable to the inverter board.
2. Fit the LCD frame back into the housing and replace the four screws and four rubber pads.
3. Replace the LCD assembly. (See section 2.2.7 Reassembly)
87

2.2.9 Inverter Board
Disassembly
1. Remove the LCD assembly and detach the LCD panel. (see instructions in previous two sections)
2. To remove the inverter board on the bottom side of the LCD assembly, disconnect the cable and remove
one screw. (figure 2-19)
Figure 2-19 Remove the inverter board
Reassembly
1. Fit the inverter board back into place and secure with one screw.
2. Reconnect the cable.
3. Replace the LCD frame. (See section 2.2.8 Reassembly)
4. Replace the LCD assembly. (See section 2.2.7 Reassembly)
88

2.2.10 System Board
Disassembly
1. Remove the battery pack, keyboard, CPU, HDD module, CD/DVD-ROM drive and LCD assembly.
(See section 2.2.1 to 2.2.5 and 2.2.7 Disassembly)
2. Remove fourteen screws on the bottom of the notebook. (Figure 2-20)
3. Remove nine screws fastening the base unit cover. (figure 2-21)
Figure 2-20 Remove the bottom Figure 2-21 Remove the speaker assembly
89

4. Lift up the base unit cover and disconnect the touch pad cord. (Figure 2-22)
5. Remove the four screws fastening the base unit. (Figure 2-23)
Figure 2-22 Remove the base unit cover Figure 2-23 Remove the metal shield
90

7. Remove four screws fastening the system board and disconnect the cables. (Figure 2-24)
8. Lift up the system board and disconnect cable. Now you can remove the system board. (Figure 2-25)
Figure 2-24 Remove the screws and Figure 2-25 Remove the system board
disconnect the cable
Reassembly
1. Reconnect the cable to system board.
2. Replace four screws fasten the system board.
3. Reconnect one cable of system board fan and one cable of little battery to system board.
4. Replace four screws fasten the base unit.
5. Reconnect the touch pad cord.
6. Replace the base unit cover and secure with nine screws
7. Carefully put the notebook upside down. Then replace the bottom frame and secure with fourteen screws.
8. Replace the battery pack, LED panel, keyboard, CPU, HDD module, CD/DVD-ROM drive and LCD assembly.
91

2.2.11 Touch-pad
Disassembly
1. Remove the base unit cover. (See steps 1-6 in section 2.2.10 Disassembly.)
2. Remove the eight screws to lift up the touch pad holder and touch pad panel. (Figure 2-26)
Figure 2-26 Remove the touch-pad
Reassembly
1. Replace the touch-pad holder and touch-pad panel, and secure with eight screws.
2. Assemble the base unit cover. (See section 2.2.10 Reassembly)
92

2.2.12 Modem Card
Disassembly
1. Remove the battery pack, keyboard, CPU, HDD module, CD/DVD-ROM drive, and LCD assembly. (See
section 2.2.1 to 2.2.5 and 2.2.7 Disassembly)
2. Disassemble the notebook to access the system board. (See section 2.2.10 Disassembly)
3. Remove the two screws fastening the modem card,and then disconnect the cable from system board. (Figure 2-27)
Figure 2-27 Remove the Modem card
Reassembly
1. Reconnect the cable to the modem card and secure the modem card with two screws.
2. Assemble the notebook. (See section 2.2.10 Reassembly)
93

3. Definition & Location of Connectors / Switches
3.1 Mother Board – A-1
J12 J1 : Modem Connector (RJ11)

J7 J4 J2 : External VGA Connector
J6 J14 J25 J3 : LCD Connector
VR1
J5 J18 J21 J4 : D/D Connector
J20
J1 J24
J5 : MDC Jump Wire Connector
J13 J28
J2
J6 : Easy Start Buttons Connector
J27
J3
J19 J7 : MISC Connector
J8
J11 J8 : Fan Connector
J23 J9 : LAN Connector (RJ45)
J11 : PC Card Socket
J12 : Secondary IDE Connector
J9 J13 : Internal Keyboard Connector
J509
J14 : Battery Connector
94

3.1 Mother Board – A-2
J12
J7 J4
J18 : MDC Connector
J14 J25
J6
J5 VR1 J19 : Primary IDE Connector
J18 J21
J20
J24 J20 : Touch-pad Connector
J1
J2
J13 J28 J21 : Internal Micro Phone Jack
J27 J23 : L Speaker Connector
J19
J3
J8
J24 : Line Out Phone Jack
J11
J25 : R Speaker Connector
J23
J27 : IEEE1394 Port
J28 : External Microphone Jack
VR1 : Volume Control
J9
J509
95

3.1 Mother Board – B
J503 : Fan Connector
J503 J505 : 200-pin expansion DDR SDRAM Socket

J506 : 200-pin expansion DDR SDRAM Socket
J508
J509
ON
2
1 J508 : CMOS Battery Connector
SW503
? J509 : Mini PCI Socket
SW503 : Country Selection for Keyboard
J506 J505
U6 U5 U3
96

3.2 DC Power Board - A
J1 : TV Out Jack
J2 : Power Jack (AC adapter)
SW1
J3 : Parallel Port Connector
J3
J1 J4 : USB Port Connector
PJ2 J2
J5 J7 J4 J8
J6 J5 : USB Port Connector
PJ1
J6 : Inverter Board Connector
J7 : USB Port Connector
J8 : USB Port Connector
PJ1 : D/D Connector
PJ2 : MISC Connector
SW1 : Cover Switch
97

3.3 ESB Board – A,B
SW1 SW2 SW3 SW4 SW5 SW6 J501 : Easy Start Button Connector
SW1 : Programmable Easy Start Button Switch
J501 SW5 : Programmable Easy Start Button Switch
SW6 : Programmable Easy Start Button Power Switch
98

3.4 Touch-pad – A,B
J501 : Touch-pad Board to Touch-pad Connector

J502 : Touch-pad Board to Main Board Connector
SW1 : Scroll Up Button Switch
SW2 : Left Button Switch
J501
SW2 SW1 SW3 SW3 : Right Button Switch
J502
SW4 : Scroll Down Button Switch
SW4
3.5 Daughter Board -A
JP1 : MDC Jump Wire Connector

JP3 : MDC/LAN Transfer Board to M/B Connector
JP1 JP3
99

4. Definition & Location of Major Components
4.1 Mother Board - A
U1 : Intel Pentium 4 Processor mPGA478 Socket

U3 : LF-H80P LAN Buffer
U4 : SiS650 IGUI Host/Memory Controller
U16
U11 U5 : ISC1893Y LAN Controller
PU10 U15 U6 : PCI1410GGU PCMCIA Controller
U10
U9 : ICS93722 Clock Buffer
U4
U1 U10 : Flash ROM
U11 : SN74CBTD3384 Level Shift
U14
U14 : SiS961 MuTIOL Media I/O Controller
U15 : ALC201 Audio CODEC
U18 U16 : TPA0202 Audio Amplifier
U9 U18 : uPD72872 IEEE 1394 Controller
U3 U5
J509
U6
PU10 : CM8500 1.25V Generator
100

4. Definition & Location of Major Components
4.1 Mother Board - B
PU508
PU510
PU511
U504 : SiS301LV/Chrontel CH7019

U509
U505 : TPS2211 PC Card Slot Power Switch
U511
U508 : ICS952001 Clock Generator
U508
U509 : H8/F3437 Micro Controller
U511 : PC87393 Super I/O
? PU508 : LTC1709EG-7 CPU Power Generator
U505
PU510 : LTC3707 1.8V/2.5V Generator
U504
PU511 : TL594C PWM
U6 U5 U3
101

5. Pin Descriptions of Major Components
5.1 Intel Pentium 4 Processor mPGA478 Socket
Name Type Description Name Type Description
A[35:3]# Input/ A[35:3]# (Address) define a 2 36 -byte physical memory address space. AP[1:0]# Input/ AP[1:0]# (Address Parity) are driven by the request initiator along
Output In sub-phase 1 of the address phase, these pins transmit the address of a Output with ADS#,A[35:3]#, and the transaction type on the REQ[4:0]#. A
transaction. In sub-phase 2, these pins transmit transaction type correct parity signal is high if an even number of covered signals
information. These signals are low and low if an odd number of covered signals are low. This
must connect the appropriate pins of all agents on the Pentium 4 allows parity to be high when all the covered signals are high.
processor in the 478-pin package system bus. A[35:3]# are protected by AP[1:0]# should connect the appropriate pins of all Pentium 4
parity signals AP[1:0]#. A[35:3]# are source synchronous signals and processor in the 478-pin package system bus agents. The following
are latched into the receiving buffers by ADSTB[1:0]#. On the table defines
active-to-inactive transition of RESET#, the processor samples a subset
of the A[35:3]# pins to determine power-on configuration. Request Signals subphase 1 subphase 2
A20M# Input If A20M# (Address-20 Mask) is asserted, the processor masks physical
address bit 20 (A20#) before looking up a line in any internal cache and A[35:24]# AP0# AP1#
before driving a read/write transaction on the bus. Asserting A20M# A[23:3]# AP1# AP0#
emulates the 8086 processor's address wrap-around at the 1-Mbyte REQ[4:0]# AP1# AP0#
boundary. Assertion of A20M# is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of BCLK[1:0] Input The differential pair BCLK (Bus Clock) determines the system bus
this signal following an Input/Output write instruction, it must be valid frequency. All processor system bus agents must receive these
along with the TRDY# assertion of the corresponding Input/Output signals to drive their outputs and latch their inputs.
Write bus transaction. All external timing parameters are specified with respect to the
ADS# Input/ ADS# (Address Strobe) is asserted to indicate the validity of the rising edge of BCLK0 crossing V CROSS .
Output transaction address on the A[35:3]# and REQ[4:0]# pins. All bus agents BINIT# Input/ BINIT# (Bus Initialization) may be observed and driven by all
observe the ADS# activation to begin parity checking, protocol Output processor system bus agents and if used, must connect the
checking, address decode, internal snoop, or deferred reply ID match appropriate pins of all such agents. If the BINIT# driver is enabled
operations associated with the new transaction. during power-on configuration, BINIT# is asserted
ADSTB[1:0]# Input/ Address strobes are used to latch A[35:3]# and REQ[4:0]# on their to signal any bus condition that prevents reliable future operation.
Output rising and falling edges. Strobes are associated with signals as shown If BINIT# observation is enabled during power-on configuration,
below. and BINIT# is sampled asserted, symmetric agents reset their bus
LOCK# activity and bus request arbitration state machines. The bus
agents do not reset their IOQ and transaction tracking state
Signals Associated Strobe
machines upon observation of BINIT# activation. Once the BINIT#
REQ[4:0]#, A[16:3]# ADSTB0# assertion has been observed, the bus agents will re-arbitrate for the
A[35:17]# ADSTB1# system bus and attempt completion of their bus queue and IOQ
entries.
If BINIT# observation is disabled during power-on configuration, a
central agent may handle an assertion of BINIT# as appropriate to
the error handling architecture of the system.
BNR# Input/ BNR# (Block Next Request) is used to assert a bus stall by any bus
Output agent who is unable to accept new bus transactions. During a bus
stall, the current bus owner cannot issue any new transactions.
102

BPM[5:0]# Input/ BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance D[63:0]# Input/ D[63:0]# (Data) are the data signals. These signals provide a 64-bit
Output monitor signals. They are outputs from the processor which indicate the Output data path between the processor system bus agents, and must
status of breakpoints and programmable counters used for monitoring connect the appropriate pins on all such agents. The data driver
processor performance. BPM[5:0]# should connect the appropriate pins asserts DRDY# to indicate a valid data transfer.
of all Pentium 4 processor in the 478-pin package system bus agents. D[63:0]# are quad-pumped signals and will thus be driven four
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. times in a common clock period. D[63:0]# are latched off the falling
PRDY# is a processor output used by debug tools to determine edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16
processor debug readiness. data signals correspond to a pair of one DSTBP# and one DSTBN#.
BPM5# provides PREQ# (Probe Request) functionality for the TAP The following table shows the grouping of data signals to data
port. PREQ# is used by debug tools to request debug operation of the strobes and DBI#.
processor. Please refer to the Intel® Pentium® 4 Processor in the Quad-Pumped Signal Groups
478-pin Package and Intel® 850 Chipset Platform Design Guide for
more detailed information. DSTBN#/
Data Group DBI#
These signals do not have on-die termination. Refer to the Intel® DSTBP#
Pentium® 4 Processor in the 478-pin Package and Intel® 850 D[15:0]# 0 0
Chipset Platform Design Guide for termination requirements. D[31:16]# 1 1
BPRI# Input BPRI# (Bus Priority Request) is used to arbitrate for ownership of the D[47:32]# 2 2
processor system bus. It must connect the appropriate pins of all D[63:48]# 3 3
processor system bus agents. Observing BPRI# active (as asserted by
the priority agent) causes all other agents to stop issuing new requests, Furthermore, the DBI# pins determine the polarity of the data
unless such requests are part of an ongoing locked operation. The signals. Each group of 16 data signals corresponds to one DBI#
priority agent keeps BPRI# asserted until all of its signal. When the DBI# signal is active, the corresponding data
requests are completed, then releases the bus by deasserting BPRI#. group is inverted and therefore sampled active high.
BR0# Input/ BR0# drives the BREQ0# signal in the system and is used by the DBI[3:0]# Input/ DBI[3:0]# are source synchronous and indicate the polarity of the
Output processor to request the bus. During power-on configuration this pin is Output D[63:0]# signals. The DBI[3:0]# signals are activated when the data
sampled to determine the agent ID = 0. on the data bus is inverted. The bus agent will invert the data bus
This signal does not have on-die termination and must be signals if more than half the bits, within the covered group, would
terminated. change level in the next cycle.
Output The BCLK[1:0] frequency select signals BSEL[1:0] are used to select DBI[3:0] Assignment To Data Bus
the processor input clock frequency. The required frequency is
determined by the processor, chipset and clock synthesizer. All agents Bus Signal Data Bus Signals
BSEL[1:0]
must operate at the same frequency. The Pentium 4 processor in the
478-pin package operates currently at a 400 MHz system bus frequency DBI3# D[63:48]#
(100 MHz BCLK[1:0] frequency). DBI2# D[47:32]#
COMP[1:0] Analog COMP[1:0] must be terminated on the system board using precision DBI1# D[31:16]#
resistors. Refer to the Intel® Pentium® 4 Processor in the 478-pin DBI0# D[15:0]#
Package and Intel® 850 Chipset Platform Design Guide for details on
implementation. DBR# Output DBR# is used only in processor systems where no debug port is
implemented on the system board. DBR# is used by a debug port
interposer so that an in-target probe can drive system reset. If a
debug port is implemented in the system, DBR# is a no connect in
the system. DBR# is not a processor signal.
103

DBSY# Input/ DBSY# (Data Bus Busy) is asserted by the agent responsible for HIT# Input/ HIT# (Snoop Hit) and HITM# (Hit Modified) convey
Output driving data on the processor system bus to indicate that the data Output transaction snoop operation results. Any system bus agent may
bus is in use. The data bus isreleased after DBSY# is deasserted. assert both HIT# and HITM# together to indicate that it requires
This signal must connect the appropriate pins on all processor Input/ a snoop stall, which can be continued by reasserting
system bus agents. HITM# Output HIT# and HITM# together.
DEFER# Input DEFER# is asserted by an agent to indicate that a transaction IERR# Output IERR# (Internal Error) is asserted by a processor as the result of
cannot be guaranteed in-order completion. Assertion of an internal error. Assertion of IERR# is usually accompanied by
DEFER# is normally the responsibility of the addressed a SHUTDOWN transaction on the processor system bus. This
memory or Input/Output agent. This signal must connect the transaction may optionally be converted to an external error
appropriate pins of all processor system bus agents. signal (e.g., NMI) by system core logic. The processor will keep
DP[3:0]# Input/ DP[3:0]# (Data parity) provide parity protection for the IERR# asserted until the assertion of RESET#, BINIT#, or
Output D[63:0]# signals. They are driven by the agent responsible for INIT#.
driving D[63:0]#, and must connect the appropriate pins of all This signals does not have on-die termination.
Pentium 4 processor in the 478-pin package system bus gents. IGNNE# Input IGNNE# (Ignore Numeric Error) is asserted to force the
DSTBN[3:0]# Input/ Data strobe used to latch in D[63:0]#. processor to ignore a numeric error and continue to execute
Output noncontrol floating-point instructions. If IGNNE# is deasserted,
Signals Associated Strobe the processor generates an exception on a noncontrol
floating-point instruction if a previous floating-point instruction
D[15:0]#, DBI0# DSTBN0# caused an error.IGNNE# has no effect when the NE bit in
D[31:16]#, DBI1# DSTBN1# control register 0 (CR0) is set. IGNNE# is an asynchronous
D[47:32]#, DBI2# DSTBN2# signal. However, to ensure recognition of this signal following
D[63:48]#, DBI3# DSTBN3# an Input/Output write instruction, it must be valid along with the
TRDY# assertion of the corresponding Input/Output Write bus
DSTBP[3:0]# Input/ Data strobe used to latch in D[63:0]#. transaction.
Output
INIT# Input INIT# (Initialization), when asserted, resets integer registers
Signals Associated Strobe inside the processor without affecting its internal caches or
D[15:0]#, DBI0# DSTBP0# floating-point registers. The processor then begins execution at
D[31:16]#, DBI1# DSTBP1# the power-on Reset vector configured during power-on
configuration. The processor continues to handle snoop requests
D[47:32]#, DBI2# DSTBP2#
during INIT# assertion. INIT# is an asynchronous signal and
D[63:48]#, DBI3# DSTBP3# must connect the appropriate pins of all processor system bus
FERR# Output FERR# (Floating-point Error) is asserted when the processor agents. If INIT# is sampled active on the active to inactive
detects an unmasked floating-point error. FERR# is similar to transition of RESET#, then the processor executes its Built-in
the ERROR# signal on the Intel 387 coprocessor, and is Self-Test (BIST).
included for compatibility with systems using MSDOS*-type ITPCLKOUT[1:0] Output The ITPCLKOUT[1:0] pins do not provide any output for the
floating-point error reporting. Pentium® 4 processor in the 478-pin package.
GTLREF Input GTLREF determines the signal reference level for AGTL+ input ITP_CLK[1:0] Input ITP_CLK[1:0] are copies of BCLK that are used only in
pins. GTLREF should be set at 2/3 VCC. GTLREF is used by the processor systems where no debug port is implemented on the
AGTL+ receivers to determine if a signal is a logical 0 or system board. ITP_CLK[1:0] are used as BCLK[1:0] references
logical 1. Refer to the Intel® Pentium® 4 Processor in the for a debug port implemented on an interposer. If a debug port
478-pin Package and Intel® 850 Chipset Platform Design is implemented in the system, ITP_CLK[1:0] are no connects in
Guide for more information. the system. These are not processor signals.
104

LINT[1:0] Input LINT[1:0] (Local APIC Interrupt) must connect the appropriate PWRGOOD Input PWRGOOD (Power Good) is a processor input. The processor
pins of all APIC Bus agents. When the APIC is disabled, the requires this signal to be a clean indication that the clocks and
LINT0 signal becomes INTR, a maskable interrupt request power supplies are stable and within their specifications.
signal, and LINT1 becomes NMI, a nonmaskable interrupt. ‘Clean’ implies that the signal will remain low (capable of
INTR and NMI are backward compatible with the signals of sinking leakage current), without glitches, from the time that the
those names on the Pentium processor. Both signals are power supplies are turned on until they come within
asynchronous. specification. The signal must then transition monotonically to a
Both of these signals must be software configured via BIOS high state. PWRGOOD can be driven inactive at any time, but
programming of the APIC register space to be used either as clocks and power must again be stable before a subsequent
NMI/INTR or LINT[1:0]. Because the APIC is enabled by rising edge of PWRGOOD. The PWRGOOD signal must be
default after Reset, operation of these pins as LINT[1:0] is the supplied to the processor; it is used to protect internal circuits
default configuration. against voltage sequencing issues. It should be driven high
LOCK# Input/ LOCK# indicates to the system that a transaction must occur throughout boundary scan operation.
Output atomically. This signal must connect the appropriate pins of all RESET# Input Asserting the RESET# signal resets the processor to a known
processor system bus agents. For a locked sequence of state and invalidates its internal caches without writing back any
transactions, LOCK# is asserted from the beginning of the of their contents. For a power-on Reset, RESET# must stay
first transaction to the end of the last transaction. active for at least one millisecond after VCC and BCLK have
When the priority agent asserts BPRI# to arbitrate for ownership reached their proper specifications. On observing active
of the processor system bus, it will wait until it observes RESET#, all system bus agents will deassert their outputs within
LOCK# deasserted. This enables symmetric agents to retain two clocks. RESET# must not be kept asserted for more than 10
ownership of the processor system bus throughout the bus ms while PWRGOOD is asserted.
locked operation and ensure the atomicity of lock. A number of bus signals are sampled at the active-to-inactive
MCERR# Input/ MCERR# (Machine Check Error) is asserted to indicate an transition of RESET# for power-on configuration.
Output unrecoverable error without a bus protocol violation. It may be This signal does not have on-die termination and must be
driven by all processor system bus agents. terminated on the system board.
MCERR# assertion conditions are configurable at a system RS[2:0]# Input RS[2:0]# (Response Status) are driven by the response agent
level. Assertion options are defined by the following options: (the agent responsible for completion of the current transaction),
Enabled or disabled. and must connect the appropriate pins of all processor system
Asserted, if configured, for internal errors along with IERR#. bus agents.
Asserted, if configured, by the request initiator of a bus RSP# Input RSP# (Response Parity) is driven by the response agent (the
transaction after it observes an error. agent responsible for completion of the current transaction)
Asserted by any bus agent when it observes an error in a bus during assertion of RS[2:0]#, the signals for which RSP#
transaction. provides parity protection. It must connect to the appropriate
For more details regarding machine check architecture, please pins of all processor system bus agents.
refer to the IA-32 Software Developer’s Manual, Volume 3: A correct parity signal is high if an even number of covered
System Programming Guide. signals are low and low if an odd number of covered signals are
PROCHOT# Output PROCHOT# will go active when the processor temperature low. While RS[2:0]# = 000, RSP# is also high, since this
monitoring sensor detects that the processor has reached its indicates it is not being driven by any agent guaranteeing
maximum safe operating temperature. correct parity.
This indicates that the processor Thermal Control Circuit has
been activated, if enabled. .
105

REQ[4:0]# Input/ REQ[4:0]# (Request Command) must connect the appropriate TDI Input TDI (Test Data In) transfers serial test data into the processor.
Output pins of all processor system bus agents. They are asserted by the TDI provides the serial input needed for JTAG specification
current bus owner to define the currently active transaction type. support.
These signals are source synchronous to ADSTB0#. Refer to the TDO Output TDO (Test Data Out) transfers serial test data out of the
AP[1:0]# signal description for a details on parity checking of processor. TDO provides the serial output needed for JTAG
these signals. specification support.
SKTOCC# Output SKTOCC# (Socket Occupied) will be pulled to ground by the TESTHI[12:8] Input TESTHI[12:8] and TESTHI[5:0] must be connected to a VCC
processor. System board designers may use this pin to determine TESTHI[5:0] power source through a resistor for proper processor operation.
if the processor is present. THERMDA Other Thermal Diode Anode.
SLP# Input SLP# (Sleep), when asserted in Stop-Grant state, causes the THERMDC Other Thermal Diode Cathode.
processor to enter the Sleep state. During Sleep state, the
processor stops providing internal clock signals to all units, THERMTRIP# Output Assertion of THERMTRIP# (Thermal Trip) indicates the
leaving only the Phase-Locked Loop (PLL) still operating. processor junction temperature has reached a level beyond
Processors in this state will not recognize snoops or interrupts. which permanent silicon damage may occur. Measurement of
The processor will recognize only assertion of the RESET# the temperature is accomplished through an internal thermal
signal, deassertion of SLP#, and removal of the BCLK input sensor which is configured to trip at approximately 135°C.Upon
while in Sleep state. If SLP# is deasserted, the processor exits assertion of THERMTRIP#, the processor will shut off its
Sleep state and returns to Stop-Grant state, restarting its internal internal clocks (thus halting program execution) in an attempt to
clock signals to the bus and processor core units. If the BCLK reduce the processor junction temperature. To protect the
input is stopped while in the Sleep state the processor will exit processor, its core voltage (VCC) must be removed following
the Sleep state and transition to the Deep Sleep state. the assertion of THERMTRIP#. Once activated, THERMTRIP#
SMI# Input SMI# (System Management Interrupt) is asserted remains latched until RESET# is asserted. While the assertion of
asynchronously by system logic. On accepting a System the RESET# signal will de-assert THERMTRIP# , if the
Management Interrupt, the processor saves the current state and processor’s junction
enter System Management Mode (SMM). An SMI temperature remains at or above the trip level, THERMTRIP#
Acknowledge transaction is issued, and the processor begins will again be asserted after RESET# is de-asserted.
program execution from the SMM handler. TMS Input TMS (Test Mode Select) is a JTAG specification support signal
If SMI# is asserted during the deassertion of RESET# the used by debug tools.
processor will tristate its outputs. TRDY# Input TRDY# (Target Ready) is asserted by the target to indicate that
STPCLK# Input STPCLK# (Stop Clock), when asserted, causes the processor to it is ready to receive a write or implicit writeback data transfer.
enter a low power Stop-Grant state. The processor issues a TRDY# must connect the appropriate pins of all system bus
Stop-Grant Acknowledge transaction, and stops providing agents.
internal clock signals to all processor core units except the TRST# Input TRST# (Test Reset) resets the Test Access Port (TAP) logic.
system bus and APIC units. The processor continues to snoop TRST# must be driven low during power on Reset. This can be
bus transactions and service interrupts while in Stop-Grant state. done with a 680 . pull-down resistor.
When STPCLK# is deasserted, the processor restarts its internal VCCA Input VCCA provides isolated power for the internal processor core
clock to all units and resumes execution. The assertion of PLLs. Refer to the Intel® Pentium® 4 Processor in the 478-pin
STPCLK# has no effect on the bus clock; STPCLK# is an Package and Intel® 850 Chipset Platform Design Guide for
asynchronous input. complete implementation details.
TCK Input TCK (Test Clock) provides the clock input for the processor
Test Bus (also knownas the Test Access Port).
106

Name Type Description
VCCIOPLL Input VCCIOPLL provides isolated power for internal processor system
bus PLLs. Follow he guidelines for VCCA, and refer to the Intel®
Pentium® 4 Processor in the 478-pin Package and Intel® 850
Chipset Platform Design Guide for complete implementation
details.
VCCSENSE Output VCCSENSE is an isolated low impedance connection to processor
core power(VCC). It can be used to sense or measure power near
the silicon with little noise.
VCCVID Input There is no imput voltage requirement for VCCVID for designs
intended tosupport only the Pentium 4 processor in the 478-pin
package. Refer to the Intel® Pentium® 4 Processor in the
478-pin Package and Intel® 850 Chipset Platform Design
Guide for more information.
VID[4:0] Output VID[4:0] (Voltage ID) pins can be used to support automatic
selection of power supply voltages (Vcc). These pins are not
signals, but are either an open circuit or a short circuit to VSS
on the processor. The combination of opens and shorts
defines the voltage required by the processor. The VID pins are
needed to cleanly support processor voltage specification
variations. The power supply must supply the voltage that is
requested by these pins, or disable itself.
VSSA Input VSSA is the isolated ground for internal PLLs.
VSSSENSE Output VSSSENSE is an isolated low impedance connection to processor
core VSS. It can be used to sense or measure ground near the
silicon with little noise
TMS Input TMS (Test Mode Select) is a JTAG specification support signal
used by debug tools.
TRDY# Input TRDY# (Target Ready) is asserted by the target to indicate that
it is ready to receive a write or implicit writeback data transfer.
TRDY# must connect the appropriate pins of all system bus
agents.
TRST# Input TRST# (Test Reset) resets the Test Access Port (TAP) logic.
TRST# must be driven low during power on Reset. This can be
done with a 680 . pull-down resistor.
VCCA Input VCCA provides isolated power for the internal processor core
PLLs. Refer to the Intel® Pentium® 4 Processor in the 478-pin
Package and Intel® 850 Chipset Platform Design Guide for
complete implementation details.
107

5.2 SiS650 IGUI Host/Memory Controller
Host BUS Interface Host BUS Interface Continue
Name Pin Attr Signal Description Name Pin Attr Signal Description
CPUCLK I Host differential clock input. RS[2:0]# O Response Status:
CPUCLK# 0.71V – M 1.2~1.85V – M RS[2:0]# are driven by the response agent to indicate the transaction
CPURST# O Host Bus Reset: response type. The following shows the response type.
1.2~1.85V – M CPURST# is used to keep all the bus agents in RS[2:0] Response
the same initial state before valid cycles issued. 000 Idle State
CPUPWRGD# CPUPWRGD# is used to inform CPU that main power is 001 Retry
O stable 010 Defer
ADS# 1.2~1.85V
I/O –M Address Strobe : 011 Reserved
1.2~1.85V – M Address Strobe is driven by CPU or SiS650 to indicate the 100 Reserved
start of a CPU bus cycle. 101 No data
HADSTB[1:0]# Source synchronous address strobe used to latch 110 Implicit Write-back
1.2~1.85V – M HREQ[4:0]# & HA[31:3]# at both falling and rising edge. 111 Normal Data
HREQ[4:0]# & HA[16:3]# are latched by HTRDY# O Target Ready:
HASTB0# 1.2~1.85V – M During write cycles, response agent will drive TRDY# to indicate it
HA[31:17] are latched by HASTB1# is ready to accept data.
HREQ[4:0]# I/O Request Command: DRDY# I/O Data Ready:
1.2~1.85V – M HREQ[4:0]# are used to define each transaction type during 1.2~1.85V – M DRDY# is driven by the bus owner whenever the data is valid on
the clock when ADS# is asserted and the clock after ADS# is the bus.
asserted. DBSY# I/O Data Bus Busy:
HA[31:3]# I/O Host Address Bus 1.2~1.85V – M Whenever the data is not valid on the bus with DRDY# is deserted,
1.2~1.85V – M DBSY# deasserted to hold the bus.
BREQ0# O Symmetric Agent Bus Request: HD[63:0]# I/O Data Bus Busy:
1.2~1.85V – M BREQ0# is driven by the symmetric agent to request for the 1.2~1.85V – M Whenever the data is not valid on the bus with DRDY# is deserted,
bus. DBSY# deasserted to hold the bus.
BPRI# O Priority Agent Bus Request: DBI[3:0]# I/O Dynamic Bus Inversion: An active DBI# will invert
1.2~1.85V – M BPRI# is driven by the priority agent that wants to request the 1.2~1.85V – M it’s corresponding data group signals.
bus. DBI0# is referenced by HD[15:0],
BPRI# has higher priority than BREQ0# to access a bus. DBI1# is referenced by HD[31:16]
BNR# I/O Block Next Request: DBI2# is referenced by HD[47:32]
1.2~1.85V – M This signal can be driven asserted by any bus agent to block DBI3# is referenced by HD[63:48]
further requests being pipelined. HDSTBP[3:0]# I/O Source synchronous data strobe used to latch data at falling edge
HLOCK# I Host Lock : 1.2~1.85V – M HD[15:0], DBI0# are latched by HDSTBP0#
1.2~1.85V – M CPU asserts HLOCK# to indicate the current bus cycle is HD[31:16], DBI1# are latched by HDSTBP1#
locked. HD[47:32], DBI2# are latched by HDSTBP2#
HIT# I/O Keeping a Non-Modified Cache Line HD[63:48], DBI3# are latched by HDSTBP3#
1.2~1.85V – M HDSTBN[3:0]# I/O Source synchronous data strobe used to latch data at falling edge
HITM# I/O Hits a Modified Cache Line: 1.2~1.85V– M HD[15:0], DBI0# are latched by HDSTBN0#
1.2~1.85V – M Hit Modified indicates the snoop cycle hits a modified line in HD[31:16], DBI1# are latched by HDSTBN1#
the L1/L2 cache of CPU. HD[47:32], DBI2# are latched by HDSTBN2#
DEFER# O Defer Transaction Completion: HD[63:48], DBI3# are latched by HDSTBN3#
1.2~1.85V – M r defer response to host bus. HNCOMP I GTL N-MOS Compensation Input
M
108

Host BUS Interface Continue SiS MuTIOL Interface
HPCOMP I GTL P-MOS Compensation Input ZCLK I SiS MuTIOL Connect
M 3.3V - M
HVREF[4:0] I AGTL+ I/O reference voltage ZUREQ/ZD I/O SiS MuTIOL Connect Control pins
HNCOMPVREF M REQ 1.8V - M
ZSTB[1:0] I/O SiS MuTIOL Connect Strobe
1.8V - M
ZSTB[1:0]# I/O Strobe Compliment
1.8V - M
ZAD[15:0] I/O I/O
DRAM Controller 1.8V - M 1.8V - M
Name Pin Attr Signal Description ZVREF I SiS MuTIOL Connect Reference Voltage
SDCLK I SDRAM Clock Input M
3.3V - M ZCMP_N I N-MOS Compensation Input
SDRCLKI I SDRAM Read Clock Input M
2.5V/3.3V - M ZCMP_P I P-MOS Compensation Input
FWDSDCLKO O SDRAM Forward Clock Output M
2.5V/3.3V – M
MA[14:0] O System Memory Address Bus
2.5V/3.3V - M
SRAS# O SDRAM Row Address Strobe
2.5V/3.3V - M SiS MuTIOL Interface Continue
SCAS# O SDRAM Column Address Strobe Name Pin Attr Signal Description
2.5V/3.3V - M AGPCLK I AGP Clock
SWE# O SDRAM Write Enable 3.3V – M
2.5V/3.3V - M I/O
AFRAME# AGP Frame#
CS[5:0]# O SDRAM Chip Select 1.5V/3.3V - M
CSB[5:0]# 2.5V/3.3V - M CSB[5:0] multiplexed with DQS[5:0] I/O
AIRDY# AGP Initiator Ready
DQM[7:0]# O SDRAM Input/Output Data Mask 1.5V/3.3V - M
2.5V/3.3V - M ATRDY# I/O AGP Target Ready
DQS[7:0] I/O DDR Data Strobe 1.5V/3.3V - M
2.5V/3.3V - M I/O
ASTOP# AGP Stop#
MD[63:0] I/O System Memory Data Bus 1.5V/3.3V - M
2.5V/3.3V - M I/O
ADEVSEL# AGP Device Select
CKE[5:0] O (open-drain) SDRAM Clock Enable 1.5V/3.3V - M
2.5V/3.3V – ASERR# I AGP System Error
AUX 1.5V/3.3V - M
S3AUXSW# O (open-drain) Aux power switch for ACPI-S3 state, low active. AREQ# I AGP Bus Request
(CKE6) 2.5V/3.3V - 1.5V/3.3V - M
AUX
AGNT# O AGP Bus Grant
DDRVREF[A:B] I DDR I/O Reference Voltage 1.5V/3.3V - M
M
AAD[31:0] I/O AGP Address/Data Bus
1.5V/3.3V - M
109

SiS MuTIOL Interface VB Interface
AC/BE[3:0] I/O AGP Command/Byte Enable VBCLK I Channel B/A Clock Input
1.5V/3.3V - M 1.8V/3.3V - M VBCLK multiplexed with SBA0
APAR I/O AGP Parity VBHCLK O VB Programming Interface Clock
1.5V/3.3V - M 1.8V/3.3V – M VBHCLK multiplexed with RBF#
ST[2:0] O AGP Status Bus VBCAD I/O VB Programming Interface Data
1.5V/3.3V - M 1.8V/3.3V – M VBCAD multiplexed with AREQ#
PIPE# I AGP Pipeline Request VBCTL[1:0] O VB Data Control
1.5V/3.3V - M 1.8V/3.3V - M VBCTL[1:0] multiplexed with AAD[29:28]
SBA[7:0] I/O Side Band Address VGPIO[3:2] I/O VB GPIO pins
1.5V/3.3V - M 3.3V - M VGPIO[3:2] multiplexed with PIPE#/WBF#
RBF# I Read Buffer Full VBHSYNC I/O Channel B H-Sync
1.5V/3.3V - M 1.8V/3.3V - M VBHSYNC multiplexed with AAD30
WBF# I Write Buffer Full VBVSYNC I/O Channel B V-Sync
1.5V/3.3V - M 1.8V/3.3V - M VBVSYNC multiplexed with AAD31
AD_STB[1:0] I/O AD Bus Strobe VBDE I/O Channel B Data Valid
1.5V/3.3V - M 1.8V/3.3V - M VBDE multiplexed with AAD27
AD_STB[1:0]# I/O AD Bus Strobe Compliment VBGCLK I/O Channel B Clock Output.
1.5V/3.3V - M 1.8V/3.3V - M This clock is used to trigger dual edge data transfer.
SB_STB I Side Band Strobe Perfect duty cycle is required.
1.5V/3.3V - M VBGCLK multiplexed with AD_STB1
SB_STB# I Side Band Strobe Compliment VBD[11:0] I/O Channel B Data
1.5V/3.3V - M 1.8V/3.3V - M VBD[11:0] multiplexed with AAD
VAHSYNC I/O Channel A H-Sync
1.8V/3.3V - M VAHSYNC multiplexed with AAD18
VAVSYNC I/O Channel A V-Sync
1.8V/3.3V - M VAVSYNC multiplexed with AAD17
VADE I/O Channel A Data Valid
1.8V/3.3V - M VADE multiplexed with AAD16
VAGCLK I/O Channel A Clock Output.
1.8V/3.3V - M This clock is used to trigger dual edge data transfer.
Stereo Glasses Interface Perfect duty cycle is required.
Name Pin Attr Signal Description VAGCLK multiplexed with AD_STB0
CSYNC O Stereo Clock VAGCLK# I/O Channel A Differential Clock Output. (To support
3.3V - M 1.8V/3.3V - M Chrontel).
RSYNC O Stereo Right VAGCLK# multiplexed with AD_STB0#
3.3V - M VAD[11:0] I/O Channel A Data
LSYNC O Stereo Left 1.8V/3.3V - M VAD[11:0] multiplexed with AAD
3.3V - M
110

VGA Interface Power and Ground Signals continue
Name Pin Attr Signal Description Name Tolerance Power Plane Type Attribute
VOSCI I 14.318 Reference Clock Input C4XAVDD 3.3V MAIN Analog
3.3V - M
C4XAVSS 0V GROUND Analog
HSYNC O Horizontal Sync
3.3V - M DACAVDD1 1.8V MAIN Analog
VSYNC O Vertical Sync
DACAVDD2 1.8V MAIN Analog
3.3V - M
INTA# O Internal VGA Interrupt Pin DACAVSS1 0V GROUND Analog
3.3V - M
DACAVSS2 0V GROUND Digital
VGPIO[1:0] I/O Internal VGA GPIO pins
3.3V - M DCLKAVDD 3.3V MAIN Digital
VCOMP AI Compensation Pin DCLKAVSS 0V GROUND Analog
Analog - M
VRSET AI Reference Resistor DDRAVDD 3.3V MAIN Analog
Analog - M DDRAVSS 0V GROUND Analog
VVBWN AI Voltage Reference
Analog - M ECLKAVDD 3.3 MAIN Analog
ROUT AO Red Signal Output ECLKAVSS 0V GROUND Analog
Analog - M
GOUT AO Green Signal Output IVDD 1.8V MAIN Digital
Analog - M OVDD 3.3V MAIN Digital
BOUT AO Blue Signal Output
Analog - M PVDD 3.3V MAIN Digital
PVDDM 3.3V AUX Digital
PVDDP 1.8V MAIN Digital
PVDDZ 1.8V MAIN Digital
Power and Ground Signals SDAVDD 3.3V MAIN Analog
Name Tolerance Power Plane Type Attribute
SDAVSS 0V GROUND Analog
A1XAVDD 3.3V MAIN Analog
VDDM 2.5/3.3V MAIN(AUX) Digital
A1XAVSS 0V GROUND Analog
VDDQ 1.5/1.8/3.3V MAIN Digitalv
A4XAVDD 3.3V MAIN Analog
VDDZ 1.8V MAIN Digital
A4XAVSS 0V GROUND Analog
VDDMCMP 1.8V MAIN Analog
AGPVSSREF 0V GROUND Analog
VTT 1.2~1.85V MAIN Digital
AUX1.8 1.8V AUX Digital
Z1XAVDD 3.3V MAIN Analog
AUX3.3 3.3V AUX Digital
Z1XAVSS 0V GROUND Analog
C1XAVDD 3.3V MAIN Analog
C1XAVSS 0V GROUND Analog
111

Test Mode/Hardware Trap/Power Management
Name Pin Attr Signal Description
DLLEN# I/O Hardware Trap pin (refer to section 5)
3.3V/5V - M
DRAM_SEL I Hardware Trap pin (refer to section 5)
3.3V/5V - AUX
TRAP[1:0] I Hardware Trap pins (refer to section 5)
3.3V/5V - M
ENTEST I Test Mode enable pin
3.3V/5V - M
TESTMOD I Test Mode select pin
E[2:0] 3.3V/5V - M Nand Tree Test: 100
AUXOK I Auxiliary Power OK :
3.3V - AUXI This signal is supplied from the power source of resume well. It
is also used to reset the logic in resume power well. If there is
no auxiliary power source on the system, this pin should be tied
together with PWROK.
PCIRST# I PCI Bus Reset :
3.3V - AUXI PCIRST# is supplied from SiS MuTIOL Media IO SiS961.
PWROK I Main Power OK :
3.3V - AUXI A high-level input to this signal indicates the power being
supplied to the system is in stable operating state. During the
period of PWROK being low, CPURST and PCIRST# will all
be asserted until after PWROK goes high for 24 ms.
112

5.3 SiS961 MuTIOL Media I/O Controller
Host Bus Interface MuTIOL Connect Interface
FERR# I Floating Point Error: ZCLK I Megaband I/O Connect Clock
1.1V/2.65V -M CPU will assert this signal upon a floating point error occurring. 3.3V - M
IGNNE# OD Ignore Numeric Error: ZUREQ I/O Megaband I/O Conect Controll pins
1.1V/2.65V -M IGNNE# is asserted to inform CPU to ignore a numeric error. 1.8V - M
NMI OD Non-Maskable Interrupt: ZDREQ I/O Megaband I/O Conect Controll pins
1.1V/2.65V -M A rising edge on NMI will trigger a non-maskable interrupt to 1.8V - M
CPU. ZSTB[1:0] I/O Megaband I/O Connect Strobe
INTR OD Interrupt Request: 1.8V - M
1.1V/2.65V -M High-level voltage of this signal conveys to CPU that there is ZSTB[1:0]# I/O Strobe Compliment
outstanding interrupt(s) needed to be serviced. 1.8V - M
APICD[1:0] I/OD APIC Data: ZAD[15:0] I/O Address/Data pins
1.1V/2.65V -M These two signals are used to send and receive APIC data. 1.8V - M
CPUSLP#/ OD CPU Sleep: ZVRE I -M Megaband I/O Connect I/O reference voltage
CPUSTP# 1.1V/2.65V -M The CPUSLP# can be used to force CPU enter the Sleep state. ZCMP_N I -M N-MOS Compensation Input
CPU Clock STOP:
For Intel Mobile processor, this signal can be used to stop the ZCMP_P I -M P-MOS Compensation input
clock to the processor. If the processor is in Quick Start state
and the processor clock is stopped, the processor will enter the
Deep Sleep state.
For AMD processor, this signal can be to reduce processor
voltage during C3/S1 state.
STPCLK# OD Stop Clock: PCI Interface Continue
1.1V/2.65V -M STPCLK# will be asserted to inhibit or throttle CPU activities Name Pin Attr Signal Description
upon a pre-defined power management event occurs PCICLK I PCI Clock:
INIT# OD Initialization: 3.3V/5V -M The PCICLK input provides the fundamental timing and the
1.1V/2.65V -M INIT is used to re-start the CPU without flushing its internal internal operating frequency for the SiS961. It runs at the same
caches and registers. In Pentium III platform it is active high. frequency and skew of the PCI local bus.
This signal requires an external pull-up resistor tied to 3.3V. C/BE[3:0]# I/O PCI Bus Command and Byte Enables:
APICCK I APIC Clock: 3.3V/5V -M PCI Bus Command and Byte Enables define the PCI command
2.5V - M This signal is used to determine when valid data is being sent during the address phase of a PCI cycle, and the PCI byte
over the APCI bus. enables during the data phases. C/BE[3:0]# are outputs when the
A20M# OD Address 20 Mask: SiS961 is a PCI bus master and inputs when it is a PCI slave.
1.1V/2.65V- M When A20M# is asserted, the CPU A20 signal will be PLOCK# I/O PCI Lock:
forced to “0” 3.3V/5V -M When PLOCK# is sampled asserted at the beginning of a PCI
cycle, SiS961 considers itself being locked and remains in the
locked state until PLOCK# is sampled and negated at the
following PCI cycle.
113

PCI Interface Continue PCI Interface
AD[31:0] I/O PCI Address /Data Bus: DEVSEL# I/O Device Select:
3.3V/5V -M In address phase: 3.3V/5V -M As a PCI target, SiS961 asserts DEVSEL# by doing positive or
1.When the SiS961 is a PCI bus master, AD[31:0] are output subtractive decoding. SiS961 positively asserts DEVSEL# when
signals. the DRAM address is being accessed by a PCI master, PCI
2.When the SiS961 is a PCI target, AD[31:0] are input signals. configuration registers or embedded controllers’ registers are
In data phase: being addressed, or the BIOS memory space is being accessed.
1.When the SiS961 is a target of a memory read/write cycle, The low 16K I/O space and low 16M memory space are
AD[31:0] are floating. responded subtractively. The DEVESEL# is an input pin when
2.When the SiS961 is a target of a configuration or an I/O cycle, SiS961 is acting as a PCI master. It is asserted by the addressed
AD[31:0] are output signals in a read cycle, and input signals in agent to claim the current transaction.
a write cycle. PREQ[4:0]# I PCI Bus Request:
PAR I/O Parity: 3.3V/5V -M PCI Bus Master Request Signals
3.3V/5V -M SiS961 drives out Even Parity covering AD[31:0] and PGNT[4:0]# O PCI Bus Grant:
C/BE[3:0]#. It does not check the input parity signal. 3.3V –M PCI Bus Master Grant Signals
FRAME# I/O Frame#: PREQ5# / I PCI Bus Request:
3.3V/5V -M FRAME# is an output when the SiS961 is a PCI bus master. GPIO5 I/O PCI Bus Master Request Signal
The SiS961 drives FRAME# to indicate the beginning and 3.3V/5V- M
duration of an access. When the SiS961 is a PCI slave device, PGNT5# / O PCI Bus Grant:
FRAME# is an input signal. GPIO6 I/O PCI Bus Master Grant Signal
IRDY# I/O Initiator Ready: 3.3V- M
3.3V/5V -M IRDY# is an output when the SiS961 is a PCI bus master. The INT[A:D]# I PCI interrupt A,B,C,D:
assertion of IRDY# indicates the current PCI bus master's 3.3V/5V –M The PCI interrupts will be connected to the inputs of the internal
ability to complete the current data phase of the transaction. For Interrupt controller through the rerouting logic associated with
a read cycle, IRDY# indicates that the PCI bus master is each PCI interrupt.
prepared to accept the read data on the following rising edge of PCIRST# O PCI Bus Reset:
the PCI clock. For a write cycle, IRDY# indicates that the bus 3.3V –M PCIRST# will be asserted during the period when PWROK is
master has driven valid data on the PCI bus. When the SiS961 is low, and will be kept on asserting until about 24ms after
a PCI slave, IRDY# is an input pin. PWROK goes high.
TRDY# I/O Target Ready: SERR# I System Error:
3.3V/5V -M TRDY# is an output when the SiS961 is a PCI slave. The 3.3V/5V –M When sampled active low, a non-maskable interrupt (NMI) can
assertion of TRDY# indicates the target agent's ability to be generated to CPU if enabled.
complete the current data phase of the transaction. For a read
cycle, TRDY# indicates that the target has driven valid data
onto the PCI bus. For a write cycle, TRDY# indicates that the
target is prepared to accept data from the PCI bus. When the
SiS961 is a PCI master, it is an input pin.
STOP# I/O Stop#:
3.3V/5V -M STOP# indicates that the bus master must start terminating its
current PCI bus cycle at the next clock edge and release control
of the PCI bus. STOP# is used for disconnection, retry, and
target-abortion sequences on the PCI bus.
114

IED Interface Power Management Interface
IDA[15:0] I/O Primary Channel Data Bus ACPILED OD ACPILED :
3.3V/5V -M <=5V -AUX ACPILED can be used to control the blinking of an LED at the
IDB[15:0] I/O Secondary Channel Data Bus frequency of 1Hz to indicate the system is at power saving
3.3V/5V -M mode.
IDECSA[1:0]# O Primary Channel CS[1:0] EXTSMI# / I External SMI#:
3.3V -M GPIO3 I/O EXTSMI# can be used to generate wakeup event, sleep event, or
IDECSB[1:0]# O Secondary Channel CS[1:0] 3.3V/5V -M SCI/SMI# event to the ACPI compatible power management
3.3V -M unit.
IIOR[A:B]# O Primary/Secondary Channel IOR# Signals PME# I PME# :
3.3V -M 3.3V/5V -AUX When the system is in power-down mode, an active low event
IIOW[A:B]# O Primary/Secondary Channel IOW# Signals on PME# will cause the PSON# to go low and hence turn on the
3.3V -M power supply. When the system is in suspend mode, an active
ICHRDY[A:B] I Primary/Secondary Channel ICHRDY# Signals PME# event will cause the system wakeup and generate an
3.3V/5V -M SCI/SMI#.
IDREQ[A:B] I Primary/Secondary Channel DMA Request Signals PSON# OD ATX Power ON/OFF control:
3.3V/5V -M <=5V -AUX PSON# is used to control the on/off state of the ATX power
IDACK[A:B]# O Primary/Secondary Channel DMACK# Signals supply. When the ATX power supply is in the OFF state, an
3.3V -M activated power-on event will force the power supply to ON
IIRQ[A:B] I Primary/Secondary Channel Interrupt Signals state.
3.3V/5V -M AUXOK I Auxiliary Power OK:
IDSAA[2:0] O Primary Channel Address [2:0] 3.3V -AUX This signal is supplied from the AUX power source. It is also
3.3V -M used to reset the logic in AUX power well. If there is no
O Secondary Channel Address [2:0] auxiliary power source on the system, this pin should be tied
IDSAB[2:0]
3.3V -M together with PWROK.
I Primary/Secondary Ultra-66 Cable ID PWRBTN# I Power Button:
CBLID[A:B]
3.3V/5V -M 3.3V/5V -AUX This signal is from the power button switch and will be
monitored by the ACPI-compatible power management unit to
switch the system between working and sleeping states.
RING / I Ring Indication:
GPIO8 I/O An active RING pulse and lasting for more than 4ms will cause
3.3V/5V -AUX a wakeup event for system to wake from S1~S5.
Legacy I/O and Miscellaneous Signals
BCLK_STP# O Stop CPU clock:
Signal Name Pin Attr Signal Description
GPIO12 I/O Output to the external clock generator for it to turn off the CPU
SPK O Speaker output: 3.3V/5V -AUX clock during C3/Sx.
3.3V -M The SPK is connected to the system speaker. DPRSLPVR O Deeper Sleep:
ENTEST I SiS961 Test Mode Enable Pin GPIO13 O DPRSLP# can be used to lower the Intel processor voltage
3.3V/5V -M 3.3V/5V -AUX during C3/S1 state.
OSCI I SiS961 Test Mode Enable Pin
3.3V -M
115

LPC Interface AC’97 Interface
LAD[3:0] I/O LPC Address/Data Bus: AC_BIT_CLK I AC’97 Bit Clock:
3.3V/5V-M LPC controller drives these four pins to transmit LPC command, 3.3V/5V -M This signal is a 12.288MHz serial data clock, which is generated
address, and data to LPC device. by primary Codec.
LDRQ# I LPC DMA Request 0: AC_RESET# O AC’97 Reset:
3.3V/5V-M This pin is used by LPC device to request DMA cycle. 3.3V -AUX Hardware reset signal for external Codecs.
LDRQ1# / I LPC DMA Request 1: AC_SDIN0 I AC’97 Serial Data Input :
GPIO1 I/O This pin is used by LPC device to request DMA cycle. 3.3V/5V -AUX Serial data input from primary Codec.
3.3V/5V-M AC_SDIN1 I AC’97 Serial Data Input:
LFRAME# O LPC Frame: 3.3V/5V -AUX Serial data input from secondary Codec. When Modem Codec is
3.3V -M This pin is used to notify LPC device that a start or a abort LPC used, this pin dedicate to Modem Serial data input.
cycle will occur. AC_SDIN[3:2]/ I AC’97 Serial Data Input:
SIRQ I/O I/O GPIO[10:9] I/O Serial data input from third and forth Audio Codec.
3.3V/5V -M 3.3V/5V -M 3.3V/5V -AUX
AC_SDOUT O AC’97 Serial Data Output:
3.3V -M Serial data output to Codecs.
AC_SYNC O AC’97 Synchronization:
3.3V -M This is a 48KHz signal, which is used to synchronize the Codecs
TRC Interface
Name Pin Attr Signal Description
BATOK I Battery Power OK:
3.3V -RTC When the internal RTC is enabled, this signal is used to indicate
that the power of RTC well is stable. It is also used to reset the USB Interface
logic in RTC well. If the internal RTC is disabled, this pin Name Pin Attr Signal Description
should be tied low.
OSC32KHI I RTC 32.768 KHz Input: USBCLK48M I USB 48 MHz clock input:
3.3V-RTC When internal RTC is enabled, this pin provides the 32.768 3.3V/5V -M This signal provides the fundamental clock for the USB
KHz clock signal from external crystal or oscillator. Controller.
OSC32KHO O RTC 32.768 KHz Output: OC[0:5]# I/O USB Port 0-5 Overcurrent Detection:
<3.3V -RTC When internal RTC is enabled, this pin should be connected 3.3V/5V - AUX OC[0:5]# are used to detect the overcurrent condition of USB
with the other end of the 32.768 KHz crystal or left unconnected Ports 0-5.
if an external oscillator is used. UV[2:0]+, I/O USB Port [2:0] Differential:
PWROK I Main Power OK: UV[2:0]- 3.3V - AUX These differential pairs are used to transmit Data/Address
3.3V-RTC A high-level input to this signal indicates the power being /Command signals for ports 0-2. (USB controller 1)
supplied to the system is in stable operating state. During the UV[5:3]+, I/O USB Port [5:3] Differential:
period of PWROK being low, PCIRST# will all be asserted UV[5:3]- 3.3V - AUX These differential pairs are used to transmit Data/Address/
until after PWROK goes high for 12 ms. Command signals for ports 3-5. (USB controller 2)
116

Keyboard Control Interface MAC Interface
KBDAT / I/OD Keyboard Dada: TXEN O Transmit Enable:
GPIO15 O/OD When the internal keyboard controller is enabled, this pin is 3.3V -AUX When set to a 1, and the transmit state machine is idle, then the
3.3V/5V -AUX used as the keyboard data signal. transmit state machine becomes active. This bit will read back
KBCLK / I/OD Keyboard Clock: as a 1 whenever the transmit state machine is active. After initial
GPIO16 O/OD When the internal keyboard controller is enabled, this pin is power-up, software must insure that the transmitter has
3.3V/5V -AUX used as the keyboard clock signal. completely reset before setting this bit
PMDAT / I/OD PS2 Mouse Data: MDIO I/O Management Data I/O:
GPIO17 O/OD When the internal keyboard and PS2 mouse controllers are 3.3V/5V -AUX Bi-direction signal used to transfer management information for
3.3V/5V -AUX enabled, this pin is used as PS2 mouse data signal. the external physical unit. Requires external pull-up resistor.
PMCLK / I/OD PS2 Mouse Clock: RXDV I Receive Data Valid.
GPIO18 O/OD When the internal keyboard and PS2 mouse controllers are 3.3V/5V -AUX This indicates that the external physical unit is presenting
3.3V/5V -AUX enabled, this pin is used as the PS2 mouse clock signal. recovered and decoded nibbles on the RXD[3:0] and that
RXCLK is synchronous to the recovered data. This signal will
encompass the frame, starting with the Start-Of-Frame delimiter
and excluding the End-Of-Frame delimiter.
COL I Collision Detect:
MAC Interface Continue 3.3V/5V -AUX This signal is asserted high asynchronous by the external
Name Pin Attr Signal Description physical unit upon detection of a collision on the medium. It’ll
RXER I RX Packet Error remain asserted as long as the collision condition persists.
3.3V/5V -AUX This event is signaled after the last received descriptor in a CRS I Carrier Sense:
failed packet reception that has been updated with valid status. 3.3V/5V -AUX This signal is asserted high asynchronously by the physical unit
MIICLK25M I PHY 25MHz Clock Input: upon detection of a non-idle medium.
3.3V/5V -AUX This pin provides the 25MHz clock signal input to the built-in RXCLK I Receive Clock
oscillator. 3.3V/5V -AUX A continuous clock that is recovered from the incoming data.
MDC O Management Data Clock: During 100Mb/s operation RXCLK is 25MHz and during
3.3V -AUX Clock signal with a maximum rate of 2.5MHz used to transfer 10Mb/s this is 2.5MHz.
management data for the external physical unit on the TXCLK I Transmit Clock
MIIMDIO pin. 3.3V/5V -AUX A continuous clock that is sourced by the physical unit. During
TXD[0:3] I Receive Data: 100Mb/s operation RXCLK is 25MHz and during 10Mb/s this
3.3V/5V -AUX This is a group of 4 data signals aligned on nibble boundaries is 2.5MHz.
which are driven synchronous to the RXCLK by the external
physical unit.
TXEN O Transmit Data:
3.3V -AUX This is a group of 4 data signals which are driven synchronous
to the TXCLK for transmission to the external physical unit.
RXD[0:3] I Receive Data:
3.3V/5V -AUX This is a group of 4 data signals aligned on nibble boundaries
which are driven synchronous to the RXCLK by the external
physical unit.
117

Power and Ground Signals General Purpose I/O
Name Tolerance Power Plane Type Attribute Signal Name Pin Attr Signal Description
VSS 0V GROUND Digital GPIO[6:0] I/O GPIO:
3.3V/5V -M Can be a general purpose input or output.
VSSZ 0V GROUND Digital
GPIO14,[12:7] I/O GPIO :
IVDD 1.8V MAIN Digital 3.3V/5V -AUX Can be a general purpose input or output.
GPIO13 O GPO:
PVDDZ 1.8V MAIN Digital
3.3V/5V - AUX Can be a general purpose output.
VDDZ 1.8V MAIN Digital GPIO[18:15] O GPO:
3.3V/5V - AUX Can be a general purpose output.
VDDZCMP 1.8V MAIN Analog
GPIO[20:19] I/O GPIO:
VSSZCMP 0V GROUND Analog 3.3V/5V - AUX Can be a general purpose input or output.
ZVSSREF 0V GROUND Analog
PVDD 3.3V MAIN Digital
OVDD 3.3V MAIN Digital
VTT 1.1V-2.65V MAIN Digital
IVDD_AUX 1.8V AUX Digital
PVDD_AUX 3.3V AUX Digital
OVDD_AUX 3.3V AUX Digital
MIIAVDD 3.3V AUX Analog
MIIAVSS 0V GROUND Analog
USBVDD 3.3V AUX Analog
USBVSS 0V GROUND Analog
RTCVDD 3.3V RTC Analog
RTCVSS 0V GROUND Analog
IDEAVDD 1.8V MAIN Analog
IDEAVSS 0V GROUND Analog
118

5.4 SiS301LV / Chrontel CH7019 TV/LVDS Encoder
Pin # Type Symbol Description Pin # Type Symbol Description
66,101 In/Out H1,H2 Horizontal Sync Input / Output 112 In/Out SDD Low-Voltage DDC Serial Data
When the SYO control bit is low, these pins accept a horizontal Low-voltage serial data for DDC. It uses VREF2 / 2 as the
sync inputs for use with the input data. The amplitude will be 0 to threshold voltage. VREF2 divide by 2 function is generated
VDDV. VREF1 is the threshold level for these inputs. These pins on-chip.
must be used as inputs in RGB Bypass mode. 113 In/Out SDC Low-Voltage DDC Serial Clock
When the SYO control bit is high, the TV encoder will output a Low-voltage serial clock for DDC. It uses VREF2 / 2 as the
horizontal sync pulse 64 pixels wide to one of these pins. The threshold voltage. VREF2 divide by 2 function is generated
output is driven from the DVDD supply. This output is valid only on-chip.
when TV-Out is in operation. 114,116 In/Out DD1, DD2 DDC Serial Data
65,102 In/Out V1,V2 Vertical Sync Input / Output Serial data for DDC. (0V to 5V) .
When the SYO control bit is low, these pins accept a vertical sync 111 In VREF2 Reference Voltage 2
inputs for use with the input data. The amplitude will be 0 to Used to generate the threshold level for SDD, SDC, SPD and
VDDV. VREF1 signal is the threshold level. These pins must be SPC port. This pin should be tied externally to the maximum
used as inputs in RGB Bypass mode. voltage seen by the ports. (1.5V to 3.3V).
When the SYO control bit is high, the TV encoder will output a 115,117 In/Out DC1,DC2 DDC Serial Clock
vertical sync pulse one line wide to one of these pins. The output Clock for DDC. (0V to 5V)
is driven from the DVDD supply. This output is valid only when 123-126 In/Out GPIO[5:0] General Purpose Input / Output [5:0]
TV-Out is in operation. 56,57 These pins provide general purpose I/O and are controlled via
63,104 In DE1,DE2 Data Enable the serial port. (3.3V).
These pins accept a data enable signal which is high when active 127 Out ENAVDD Panel Power Enable
video data is input to the device, and remains low during all other Enable panel VDD. (3.3V)
times. The levels are 0 to VDDV. VREF1 is the threshold level. 128 Out ENABLK Back Light Enable
One of these inputs is used by the LVDS links. The TV-Out Enable Back-Light of LCD Panel. (3.3V)
function uses H and V sync signals and values in the SAV register 121 In HPD Hot Plug Detect (Internal Pull-down)
as reference to active video. This input pin determines whether a CRT monitor is connected
62,105 Out FLD/STL1 TV Field / Flat Panel Stall Signal to the VGA connector. When terminated, the monitor is
FLD/STL2 These outputs can be programmed to be either a TV Field output required to apply a voltage greater than 2.4 volts. Changes on
from the TV encoder or a Stall output from the flat panel the status of this pin will be relayed to the graphics controller
Up-scaler. These outputs are tri-stated upon power up. via the HPINT* pin pulling low.
107 In/Out SPD Serial Port Data Input / Output 122 Out HPINT* Hot Plug Interrupt Output
This pin functions as the bi-directional data pin of the serial port, This pin provides an open drain output, which pulls low when a
and uses VREF2 / 2 as the threshold voltage. VREF2 divide by 2 termination change has been detected on the HPD input.
function is generated on-chip. 36 In VSWING LVDS Voltage Swing Control
108 In SPC Serial Port Clock Input This pin sets the swing level of the LVDS outputs. A 2.4K Ohm
This pin functions as the clock input of the serial port and uses resistor should be connected between this pin and LGND ( pin
VREF2 / 2 as the threshold voltage. VREF2 divide by 2 function is 35) using short and wide traces.
generated on-chip. 58 In RESET* Reset * Input (Internal Pull-up)
106 In AS Address Select (Internal Pull-up) When this pin is low, the device is held in the power on reset
This pin determines the device address of the serial port. condition. When this pin is high, reset is controlled through the
serial port.
119

Pin # Type Symbol Description Pin # Type Symbol Description
2 Analog LPLLCAP LVDS PLL Capacitor 52 In XI/FIN Crystal Input / External Reference Input
This pins allows coupling of any signal to the on-chip loop A parallel resonant 14.31818MHz crystal (+ 20 ppm) should
filter capacitor. be attached between this pin and XO. However, an external
5,24 Out LL2C,LL1C Positive LVDS differential Clock2 & Clock1 CMOS compatible clock can drive the XI/FIN input.
6,25 Out LL2C*,LL1C* Negative LVDS differential Clock2 & Clock1 53 Out XO Crystal Output
A parallel resonance 14.31818MHz crystal (+ 20 ppm)
8,11,14,17 Out LDC[7:4] Positive LVDS differential data[7:4] should be attached between this pin and XI / FIN. However,
9,12,15,18 Out LDC[7:4]* Negative LVDS differential data[7:4] if an external CMOS clock is attached to XI/FIN, XO should
21,27,30,33 Out LDC[3:0] Positive LVDS differential data[3:0] be left open.
22,28,31,34 Out LDC[3:0]* Negative LVDS differential data [3:0] 59 Out P-OUT Pixel Clock Output
38 Analog ISET Current Set Resistor Input This pin provides a pixel clock signal to the VGA controller
This pin sets the DAC current. A 140-ohm resistor should be which can be used as a reference frequency. The output is
connected between this pin and DAC_GND (pin 39) using selectable between 1X and 2X of the pixel clock frequency.
short and wide traces. The output driver is driven from the VDDV supply (pin 60).
40,42,44,46 Out DACB[3:0] DAC Output B This output has a programmable tri-state. The capacitive
Video Digital-to-Analog outputs. loading on this pin should be kept to a minimum.
41,43,45,47 Out DACA[3:0] DAC Output A 61 In VREF1 Reference Voltage Input 1
Video Digital-to-Analog outputs. The VREF1 pin inputs a reference voltage of VDDV / 2.
120 Out VOUT V-Sync Output The signal is derived externally through a resistor divider
This pin is the output of a voltage translating digital buffer and and decoupling capacitor, and will be used as a reference
is driven from V5V. level for data, sync and clock inputs.
110 In VIN V-Sync Input 68-73,77-82 In D1[11:0] Data1[11] through Data1[0] Inputs
This pin is the input of a voltage translating digital buffer. These pins accept the 12 data inputs from a digital video
Input threshold can be programmed by serial port to equal to port of a graphics controller. The levels are 0 to VDDV.
VREF2/2 or to DVDD/2. The amplitude will be 0 to VDDV. VREF1 is the threshold level.
VREF1 is the threshold level for these inputs. 76,74 In XCLK1 External Clock Inputs
119 Out HOUT H-Sync Output XCLK1* These inputs form a differential clock signal input to the
This pin is the output of a voltage translating digital buffer and device for use with the H1, V1 and D1[11:0] data. If
is driven from V5V. differential clocks are not available, the XCLK1* input
109 In should be connected to VREF1. The clock polarity can be
HIN H-Sync Input
selected by the MCP1 control bit.
This pin is the input of a voltage translating digital buffer.
Input threshold can be programmed by serial port to equal to 85-90,94-99 In D2[11:0] Data2[11] through Data2[0] Inputs
VREF2/2 or to DVDD/2. These pins accept the 12 data inputs from a digital video
49 Out port of a graphics controller. The levels are 0 to DVDDV.
C/HSYNC Composite / Horizontal Sync
VREF1 is the threshold level.
Provides composite sync in TV modes and horizontal sync in
bypass RGB mode. This pin is driven by the DVDD supply. 93,91 In XCLK External Clock Inputs
50 Out XCLK2* These inputs form a differential clock signal input to the
BCO/VSYNC Buffered Clock Outputs / Vertical Sync
This output pin provides buffered crystal oscillator clock device for use with the H2, V2 and D2[11:0] data. If
differential clocks are not available, the XCLK2* input
output or VSYNC output in bypass RGB mode. This pin is
should be connected to VREF1. The clock
driven by the DVDD supply.
polarity can be selected by the MCP2 control bit.
120

Pin # Type Symbol Description
118 Power V5V 5V supply for H/VOUT (5V)
64,83,84,103 Power DVDD Digital Supply Voltage (3.3V)
67,75,92,100 Power DGND Digital Ground
60 Power VDDV I/O Supply Voltage (1.1V to 3.3V)
55 Power TVPLL_VDD TV PLL Supply Voltage (3.3V)
54 Power TVPLL_VCC TV PLL Supply Voltage (3.3V)
51 Power TVPLL_GND TV PLL Ground
37 Power DAC_VDD DAC Supply Voltage (3.3V)
39,48 Power DAC_GND DAC Ground
7,13,19,20,26,32 Power LVDD LVDS Supply Voltage (3.3V)
4,10,16,23,29,35 Power LGND LVDS Ground
1 Power LPLL_VDD LVDS PLL Supply Voltage (3.3V)
3 Power LPLL_GND LVDS PLL Ground
121

5.5 PCI1410GGU PCMCIA Controller
Power Supply PCI Interface Control
Name I/O Description Name I/O Description
GND Device ground terminals DEVSEL# I/O PCI device select. The PCI1410 asserts DEVSEL# to claim a PCI cycle as
VCC Power supply terminal for core logic (3.3V) the target device. As a PCI initiator on the bus, the PCI1410 monitors
DEVSEL# until a target responds. If no target responds before timeout
VCCCB Clamp voltage for PC Card interface. Matches card signaling environment, occurs, then the PCI1410 terminates the cycle with an initiator abort.
5 V or 3.3 V. FRAME# I/O PCI cycle frame. FRAME# is driven by the initiator of a bus cycle.
VCCI Clamp voltage for interrupt subsystem interface and miscellaneous I/O, 5 V FRAME# is asserted to indicate that a bus transaction is beginning, and data
or 3.3 V transfers continue while this signal is asserted. When FRAME# is
VCCP Clamp voltage for PCI signaling, 5 V or 3.3 V deasserted, the PCI bus transaction is in the final data phase.
GNT# I PCI bus grant. GNT# is driven by the PCI bus arbiter to grant the PCI1410
access to the PCI bus after the current data transaction has completed.
PC Card Power Switch GNT# may or may not follow a PCI bus request, depending on the PCI bus
Name I/O Description parking algorithm.
IDSEL I Initialization device select. IDSEL selects the PCI1410 during configuration
VCCD0 O Logic controls to the TPS2211 PC Card power interface switch to control
space accesses. IDSEL can be connected to one of the upper 24 PCI address
VCCD1 AVCC.
lines on the PCI bus.
VPPD0 O Logic controls to the TPS2211 PC Card power interface switch to control
IRDY# I/O PCI initiator ready. IRDY# indicates the PCI bus initiator’s ability to
VPPD1 AVPP.
complete the current data phase of the transaction. A data phase is
completed on a rising edge of PCLK where both IRDY# and TRDY# are
asserted. Until IRDY# and TRDY# are both sampled asserted, wait states
PCI System are inserted.
Name I/O Description PERR# I/O PCI parity error indicator. PERR# is driven by a PCI device to indicate that
GRST# I Global reset. When the global reset is asserted, the GRST# signal causes the calculated parity does not match PAR when PERR# is enabled through bit 6
PCI1410 to place all output buffers in a high-impedance state and reset all of the command register.
internal registers. When GRST# is asserted, the device is completely in its REQ# O PCI bus request. REQ# is asserted by the PCI1410 to request access to the
default state. For systems that require wake-up from D3, GRST# will PCI bus as an initiator.
normally be asserted only during initial boot. PRST# should be used SERR# O PCI system error. SERR# is an output that is pulsed from the PCI1410 when
following initial boot so that PME context is retained when transitioning enabled through bit 8 of the command register indicating a system error has
from D3 to D0. For systems that do not require wake-up from D3, GRST# occurred. The PCI1410 need not be the target of the PCI cycle to assert this
should be tied to PRST#. signal. When SERR# is enabled in the command register,
When the SUSPEND# mode is enabled, the device is protected from the this signal also pulses, indicating that an address parity error has occurred
GRST#, and the internal registers are preserved. All outputs are placed in a on a CardBus interface.
high-impedance state, but the contents of the registers are preserved. STOP# I/O PCI cycle stop signal. STOP# is driven by a PCI target to request the
PCLK I PCI bus clock. PCLK provides timing for all transactions on the PCI bus. initiator to stop the current PCI bus transaction. STOP# is used for target
All PCI signals are sampled at the rising edge of PCLK. disconnects and is commonly asserted by target devices that do not support
PRST# I PCI reset. When the PCI bus reset is asserted, PRST# causes the PCI1410 to burst data transfers.
place all output buffers in a high-impedance state and reset internal TRDY# I/O PCI target ready. TRDY# indicates the primary bus target’s ability to
registers. When PRST# is asserted, the device is completely nonfunctional. complete the current data phase of the transaction. A data phase is
After PRST is deasserted, the PCI1410 is in a default state. completed on a rising edge of PCLK when both IRDY# and TRDY# are
When the SUSPEND# mode is enabled, the device is protected from the asserted. Until both IRDY# and TRDY# are asserted, wait states are
PRST#, and the internal registers are preserved. All outputs are placed in a inserted.
high-impedance state, but the contents of the registers are preserved.
122

Multifunction and Miscellaneous Pins PCI Address and Data
MFUNC0 I/O Multifunction terminal 0. MFUNC0 can be configured as parallel PCI AD[31:0] I/O PCI address/data bus. These signals make up the multiplexed PCI address
interrupt INTA#, GPI0, GPO0, socket activity LED output, ZV switching and data bus on the primary interface. During the address phase of a
outputs, CardBus audio PWM, GPE#, or a parallel IRQ. primary bus PCI cycle, AD31–AD0 contain a 32-bit address or other
MFUNC1 I/O Multifunction terminal 1. MFUNC1 can be configured as GPI1, GPO1, destination information. During the data phase, AD31–AD0 contain data.
socket activity LED output, ZV switching outputs, CardBus audio PWM, C/BE#[3:0] I/O PCI bus commands and byte enables. These signals are multiplexed on the
GPE#, or a parallel IRQ. same PCI terminals. During the address phase of a primary bus PCI cycle,
Serial data (SDA). When VPPD0 and VPPD1 are high after a PCI reset, the C/BE#3–C/BE#0 define the bus command. During the data phase, this 4-bit
MFUNC1 terminal provides the SDA signaling for the serial bus interface. bus is used as byte enables. The byte enables determine which byte paths of
The two-pin serial interface loads the subsystem identification and other the full 32-bit data bus carry meaningful data. C/BE#0 applies to byte 0
register defaults from an EEPROM after a PCI reset. (AD7–AD0), C/BE#1 applies to byte 1 (AD15–AD8), C/BE2 applies to
MFUNC2 I/O Multifunction terminal 2. MFUNC2 can be configured as PC/PCI DMA byte 2 (AD23–AD16), and C/BE#3 applies to byte 3 (AD31–AD24).
request, GPI2, GPO2, socket activity LED output, ZV switching outputs, PAR I/O PCI bus parity. In all PCI bus read and write cycles, the PCI1410 calculates
CardBus audio PWM, GPE#, RI_OUT#, or a parallel IRQ. even parity across the AD31–AD0 and C/BE#3–C/BE#0 buses. As an
MFUNC3 I/O Multifunction terminal 3. MFUNC3 can be configured as a parallel IRQ or initiator during PCI cycles, the PCI1410 outputs this parity indicator with a
the serialized interrupt signal IRQSER. one-PCLK delay. As a target during PCI cycles, the calculated parity is
MFUNC4 I/O Multifunction terminal 4. MFUNC4 can be configured as PCI LOCK#, compared to the initiator’s parity indicator. A compare error results in the
GPI3, GPO3, socket activity LED output, ZV switching outputs, CardBus assertion of a parity error (PERR#).
audio PWM, GPE#, RI_OUT#, or a parallel IRQ.
Serial clock (SCL). When VPPD0 and VPPD1 are high after a PCI reset,
the MFUNC4 terminal provides the SCL signaling for the serial bus
interface. The two-pin serial interface loads the subsystem identification and 16-Bit PC Card Address and Data (Slots A and B)
other register defaults from an EEPROM after a PCI reset. Name I/O Description
MFUNC5 I/O Multifunction terminal 5. MFUNC5 can be configured as PC/PCI DMA
ADDR[25:0] O PC Card address. 16-bit PC Card address lines. ADDR25 is the most
grant, GPI4, GPO4, socket activity LED output, ZV switching outputs,
significant bit.
CardBus audio PWM, GPE#, or a parallel IRQ.
DATA[15:0] I/O PC Card data. 16-bit PC Card data lines. DATA15 is the most significant
MFUNC6 I/O Multifunction terminal 6. MFUNC6 can be configured as a PCI CLKRUN#
bit.
or a parallel IRQ.
RI_OUT#/PME# O Ring indicate out and power management event output. Terminal provides
an output for ring-indicate or PME# signals.
SPKROUT O Speaker output. SPKROUT is the output to the host system that can carry
SPKR# or CAUDIO through the PCI1410 from the PC Card interface.
SPKROUT is driven as the exclusive-OR combination of card
SPKR#//CAUDIO inputs.
SUSPEND# I Suspend. SUSPEND# protects the internal registers from clearing when the
GRST# or PRST# signal is asserted.
123

16-Bit PC Card Interface Control (Slots A and B)
BVD1 I Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards OE# O Output enable. OE# is driven low by the PCI1410 to enable 16-bit memory PC
(STSCHG#/RI#) that include batteries. BVD1 is used with BVD2 as an indication of the Card data output during host memory read cycles.
condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are DMA terminal count. OE# is used as terminal count (TC) during DMA
high when the battery is good. When BVD2 is low and BVD1 is high, the operations to a 16-bit PC Card that supports DMA. The PCI1410 asserts OE# to
battery is weak and should be replaced. When BVD1 is low, the battery is indicate TC for a DMA write operation.
no longer serviceable and the data in the memory PC Card is lost. READY I Ready. The ready function is provided by READY when the 16-bit PC Card and
Status change. STSCHG# is used to alert the system to a change in the (IREQ#) the host socket are configured for the memory-only interface. READY is driven
READY, write protect, or battery voltage dead condition of a 16-bit I/O PC low by the 16-bit memory PC Cards to indicate that the memory card circuits are
Card. busy processing a previous write command. READY is driven high when the
Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection. 16-bit memory PC Card is ready to accept a new data transfer command.
BVD2 I Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards Interrupt request. IREQ# is asserted by a 16-bit I/O PC Card to indicate to the
(SPKR#) that include batteries. BVD2 is used with BVD1 as an indication of the host that a device on the 16-bit I /O PC Card requires service by the host
condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are software. IREQ# is high (deasserted) when no interrupt is requested.
high when the battery is good. When BVD2 is low and BVD1 is high, the REG# O Attribute memory select. REG# remains high for all common memory accesses.
battery is weak and should be replaced. When BVD1 is low, the battery is When REG# is asserted, access is limited to attribute memory (OE# or WE#
no longer serviceable and the data in the memory PC Card is lost. active) and to the I/O space (IORD# or IOWR# active). Attribute memory is a
Speaker. SPKR# is an optional binary audio signal available only when the separately accessed section of card memory and is generally used to record card
card and socket have been configured for the 16-bit I/O interface. The audio capacity and other configuration and attribute information.
signals from cards A and B are combined by the PCI1410 and are output on DMA acknowledge. REG# is used as a DMA acknowledge (DACK#) during
SPKROUT. DMA request. BVD2 can be used as the DMA request signal DMA operations to a 16-bit PC Card that supports DMA. The PCI1410 asserts
during DMA operations to a 16-bit PC Card that supports DMA. The PC REG to indicate a DMA operation. REG# is used in conjunction with the DMA
Card asserts BVD2 to indicate a request for a DMA operation. read (IOWR#) or DMA write (IORD#) strobes to transfer data.
CD1# I Card detect 1 and Card detect 2. CD1# and CD2# are internally connected RESET O PC Card reset. RESET forces a hard reset to a 16-bit PC Card.
CD2# to ground on the PC Card. When a PC Card is inserted into a socket, CD1# WAIT# I Bus cycle wait. WAIT# is driven by a 16-bit PC Card to extend the completion of
and CD2# are pulled low. the memory or I/O cycle in progress.
CE1# O Card enable 1 and card enable 2. CE1# and CE2# enable even- and WE# O Write enable. WE# is used to strobe memory write data into 16-bit memory PC
CE2# odd-numbered address bytes. CE1# enables even-numbered address bytes, Cards. WE# is also used for memory PC Cards that employ programmable
and CE2# enables odd-numbered address bytes. memory technologies.
INPACK# I Input acknowledge. INPACK# is asserted by the PC Card when it can DMA terminal count. WE# is used as TC# during DMA operations to a 16-bit PC
respond to an I/O read cycle at the current address. Card that supports DMA. The PCI1410 asserts WE# to indicate TC# for a DMA
DMA request. INPACK# can be used as the DMA request signal during read operation.
DMA operations from a 16-bit PC Card that supports DMA. If it is used as WP I Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of
a strobe, then the PC Card asserts this signal to indicate a request for a (IOIS16#) the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is
DMA operation. used for the 16-bit port (IOIS16#) function.
IORD# O I/O read. IORD# is asserted by the PCI1410 to enable 16-bit I/O PC Card I/O is 16 bits. IOIS16# applies to 16-bit I/O PC Cards. IOIS16# is asserted by the
data output during host I/O read cycles. 16-bit PC Card when the address on the bus corresponds to an address to which
DMA write. IORD# is used as the DMA write strobe during DMA the 16-bit PC Card responds, and the I/O port that is addressed is capable of
operations from a 16-bit PC Card that supports DMA. The PCI1410 asserts 16-bit accesses.
IORD# during DMA transfers from the PC Card to host memory. DMA request. WP can be used as the DMA request signal during DMA
IOWR# O I/O write. IOWR# is driven low by the PCI1410 to strobe write data into operations to a 16-bit PC Card that supports DMA. If used, then the PC Card
16-bit I/O PC Cards during host I/O write cycles. asserts WP to indicate a request for a DMA operation.
DMA read. IOWR# is used as the DMA write strobe during DMA VS1# I/O Voltage sense 1 and voltage sense 2. VS1# and VS2#, when used in conjunction
operations from a 16-bit PC Card that supports DMA. The PCI1410 asserts VS2# with each other, determine the operating voltage of the PC Card.
IOWR# during transfers from host memory to the PC Card.
124

CardBus PC Card Interface System (Slots A and B) CardBua PC Card Interface Control (Slots A and B)
CCLK O CardBus clock. CCLK provides synchronous timing for all transactions on CAUDIO I CardBus audio. CAUDIO is a digital input signal from a PC Card to the
the CardBus interface. All signals except CRST#, CCLKRUN#, CINT#, system speaker. The PCI1410 supports the binary audio mode and outputs a
CSTSCHG, CAUDIO, CCD2#, CCD1#, CVS2, and CVS1 are sampled on binary signal from the card to SPKROUT.
the rising edge of CCLK, and all timing parameters are defined with the CBLOCK# I/O CardBus lock. CBLOCK# is used to gain exclusive access to a target.
rising edge of this signal. CCLK operates at the PCI bus clock frequency, CCD1# I CardBus detect 1 and CardBus detect 2. CCD1# and CCD2# are used in
but it can be stopped in the low state or slowed down for power savings. CCD2# conjunction with CVS1 and CVS2 to identify card insertion and interrogate
CCLKRUN# I/O CardBus clock run. CCLKRUN# is used by a CardBus PC Card to request cards to determine the operating voltage and card type.
an increase in the CCLK frequency, and by the PCI1410 to indicate that the
CE1# O Card enable 1 and card enable 2. CE1# and CE2# enable even- and
CCLK frequency is going to be decreased.
CE2# odd-numbered address bytes. CE1# enables even-numbered address bytes,
CRST# O CardBus reset. CRST# brings CardBus PC Card-specific registers,
and CE2# enables odd-numbered address bytes.
sequencers, and signals to a known state. When CRST# is asserted, all
CDEVSEL# I/O CardBus device select. The PCI1410 asserts CDEVSEL# to claim a
CardBus PC Card signals are placed in a high-impedance state, and the
CardBus cycle as the target device. As a CardBus initiator on the bus, the
PCI1410 drives these signals to a valid logic level. Assertion can be
PCI1410 monitors CDEVSEL# until a target responds. If no target responds
asynchronous to CCLK, but deassertion must be synchronous to CCLK.
before timeout occurs, then the PCI1410 terminates the cycle with an
initiator abort.
CFRAME# I/O CardBus cycle frame. CFRAME# is driven by the initiator of a CardBus bus
CardBus PC Card Address and Data (Slots A and B) cycle. CFRAME# is asserted to indicate that a bus transaction is beginning,
Name I/O Description and data transfers continue while this signal is asserted. When CFRAME# is
CAD[31:0] I/O CardBus address and data. These signals make up the multiplexed CardBus deasserted, the CardBus bus transaction is in the final data phase.
address and data bus on the CardBus interface. During the address phase of CGNT# O CardBus bus grant. CGNT# is driven by the PCI1410 to grant a CardBus
a CardBus cycle, CAD31–CAD0 contain a 32-bit address. During the data PC Card access to the CardBus bus after the current data transaction has
phase of a CardBus cycle, CAD31–CAD0 contain data. CAD31 is the most been completed.
significant bit. CINT# I CardBus interrupt. CINT# is asserted low by a CardBus PC Card to request
CC/BE#[3:0] I/O CardBus bus commands and byte enables. CC/BE#3–CC/BE#0 are interrupt servicing from the host.
multiplexed on the same CardBus terminals. During the address phase of a CIRDY# I/O CardBus initiator ready. CIRDY# indicates the CardBus initiator’s ability to
CardBus cycle, CC/BE#3–CC/BE#0 define the bus command. During the complete the current data phase of the transaction. A data phase is
data phase, this 4-bit bus is used as byte enables. The byte enables completed on a rising edge of CCLK when both CIRDY# and CTRDY# are
determine which byte paths of the full 32-bit data bus carry meaningful asserted. Until CIRDY# and CTRDY# are both sampled asserted, wait
data. CC/BE#0 applies to byte 0 (CAD7–CAD0), CC/BE#1 applies to byte states are inserted.
1 (CAD15–CAD8), CC/BE#2 applies to byte 2 (CAD23–CAD8), and
CC/BE#3 applies to byte 3 (CAD31–CAD24).
CPAR I/O CardBus parity. In all CardBus read and write cycles, the PCI1410
calculates even parity across the CAD and CC/BE# buses. As an initiator
during CardBus cycles, the PCI1410 outputs CPAR with a one-CCLK
delay. As a target during CardBus cycles, the calculated parity is compared
to the initiator’s parity indicator; a compare error results in a parity error
assertion.
125

CardBua PC Card Interface Control (Slots A and B) (Continued)
Name I/O Description
CPERR# I/O CardBus parity error. CPERR# reports parity errors during CardBus
transactions, except during special cycles. It is driven low by a target two
clocks following that data when a parity error is detected.
CREQ# I CardBus request. CREQ# indicates to the arbiter that the CardBus PC Card
desires use of the CardBus bus as an initiator.
CSERR# I CardBus system error. CSERR# reports address parity errors and other
system errors that could lead to catastrophic results. CSERR# is driven by
the card synchronous to CCLK, but deasserted by a weak pullup, and may
take several CCLK periods. The PCI1410 can report CSERR# to the system
by assertion of SERR# on the PCI interface.
CSTOP# I/O CardBus stop. CSTOP# is driven by a CardBus target to request the initiator
to stop the current CardBus transaction. CSTOP# is used for target
disconnects, and is commonly asserted by target devices that do not support
burst data transfers.
CSTSCHG I CardBus status change. CSTSCHG alerts the system to a change in the
card’s status, and is used as a wake-up mechanism.
CTRDY# I/O CardBus target ready. CTRDY# indicates the CardBus target’s ability to
complete the current data phase of the transaction. A data phase is
completed on a rising edge of CCLK, when both CIRDY# and CTRDY#
are asserted; until this time, wait states are inserted.
CVS1 I/O CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are
CVS2 used in conjunction with CCD1# and CCD2# to identify card insertion and
interrogate cards to determine the operating voltage and card type.
126

5.6 uPD72872 IEEE1394 Controller
PCI/Cardbus Interface Signals: (52 pins)
Name I/O PIN NO. IOL Volts(V) Function Block* Name I/O PIN NO. IOL Volts(V) Function Block*
PAR I/O 44 PCI/Cardbus 5/3.3 Parity is even parity across Link REQ O 8 PCI/Cardbus 5/3.3 Bus_master Request Link
AD0-AD31 and indicates to the bus arbiter
CBE0-CBE3. that this device wants to
It is an input when become a bus master.
AD0-AD31 is an input; it is
an output when AD0-AD31 GNT I 7 - 5/3.3 Bus_master Grant Link
is an output. indicates to this device that
access to the bus has been
AD0-AD31 I/O 9, 10, 12, 13, PCI/Cardbus 5/3.3 PCI Multiplexed Address Link granted.
15-18, 23, 24, and Data
26-29, 32, 33, IDSEL I 22 - 5/3.3 Initialization Device Select Link
47-50, 52, 53, is used as chip select for
55, 56, 58,59, configuration read/write
62, 63, 65-68 transaction during the phase
CBE0-CBE3 I 21, 34, 45, 57 - 5/3.3 Command/Byte Enables Link of device initialization. If
are multiplexed Bus Cardbus mode (CARD_ON
= 1), this pin should be
Commands & Byte enables.
pulled up to VDD.
FRAME I/O 35 PCI/Cardbus 5/3.3 Frame is asserted by the Link
DEVSEL I/O 39 PCI/Cardbus 5/3.3 Device Select when actively Link
initiator to indicate the driven, indicates that the
cycle beginning and is kept driving device has decoded
asserted during the burst its address as the target of
cycle. If Cardbus mode the current access.
(CARD_ON = 1), this pin
should be pulled up to VDD. STOP I/O 40 PCI/Cardbus 5/3.3 PCI Stop when actively Link
driven, indicates that the
TRDY I/O 37 PCI/Cardbus 5/3.3 Target Ready indicates that Link target is requesting the
the current data phase of the current bus master to stop
transaction is ready to be the transaction.
completed.
PME O 3 PCI/Cardbus 5/3.3 PME Output for power Link
IRDY I/O 36 PCI/Cardbus 5/3.3 Initiator Ready indicates Link management enable.
that the current bus master is CLKRUN I/O 2 PCI/Cardbus 5/3.3 PCICLK Running as input, Link
ready to complete the to determine the status of
current data phase. During a PCLK; as output, to request
write, its assertion indicates starting or speeding up
that the initiator is driving clock.
valid data onto the data bus.
During a read, its assertion INTA O 4 PCI/Cardbus 5/3.3 Interrupt the PCI interrupt Link
indicates that the initiator is request A.
ready to accept data from the
currently-addressed target.
127

5.6 uPD72872 IEEE1394 Controller
Name I/O PIN NO. IOL Volts(V) Function Block*
PERR I/O 41 PCI/Cardbus 5/3.3 Parity Error is used for Link
reporting data parity errors
during all PCI transactions,
except a Special Cycle.
It is an output when
AD0-AD31 and PAR are
both inputs. It is an input
when AD0-AD31 and PAR
are both outputs.
SERR O 42 PCI/Cardbus 5/3.3 System Error is used for Link

reporting address parity
errors, data parity errors
during the Special Cycle, or
any other system error
where the effect can be
catastrophic. When reporting
address parity errors, it is an
output.
PRST I 5 - 5/3.3 Reset PCI reset Link
PCLK I 6 - 5/3.3 PCI Clock 33 MHz system Link
bus clock.
Remark *: If the Link pin is pulled up, it should be connected to L_VDD.
128

6. System Block Diagram
U1
Pentium 4 CPU U2
Thermal Sensor
Willamette/Northwood ADM1032
Micro-FCPGA 478 pin
U504
LCD PANEL
TV-Encoder
SiS301LV/ U4
J509 TV S-VIDEO CH7019
MINI PCI IGUI Host/Memory
200 pin DDR SO-DIMM Socket * 2
Socket Controller
CRT
SiS650
PCI BUS Hyperzip Data Bus
USB External Microphone
U6 Internal Microphone
HDD
PCMCIA U14 AC Link U15 U16
Controller CDROM Internal Speaker
PCI 1410
MuTIOL Media I/O Audio Codec Amplifier
SPDIF JACK
Cover Switch Controller
J18
U5 SiS961 RJ-11 Jack
U505 M.D.C
RJ-45 Jack
LAN PHY
Power
Switch
LPC FAN
U18
ISA BUS U509
IEEE 1394 IR Module U511 Power Button
Controller Super I/O Micro
PCMCIA/ uPD72872 Print Port Controller
CARDBUS
PC87393
U10 Touch Pad
Socket H8/F3437
Flash ROM
Keyboard
129

7. Maintenance Diagnostics
7.1 Introduction
Each time the computer is turned on, the system bios runs a series of internal checks on the hardware.
This power-on self test (post) allows the computer to detect problems as early as the power-on stage. Error
messages of post can alert you to the problems of your computer.
If an error is detected during these tests, you will see an error message displayed on the screen. If the
error occurs before the display is initialized,then the screen cannot display the error message. Error codes or
system beeps are used to identify a post error that occurs when the screen is not available.
The value for the diagnostic port (378H) is written at the beginning of the test. Therefore, if the test
failed, the user can determine where the problem occurred by reading the last value written to port 378H by
the 378H port debug board plug at PIO PORT.
130

7.2 Error Codes
Following is a list of error codes in sequent display on the PIO debug board.
Code POST Routine Description Code POST Routine Description

10h Some type of lone reset 20h Test keyboard
11h Turn off FAST A20 for POST 21h Test keyboard controller
12h Signal power on reset 22h Check if CMOS RAM valid
13h Initialize the chipset 23h Test battery fail & CMOS X-SUM
14h Search for ISA Bus VGA adapter 24h Test the DMA controller
15h Reset counter / Timer 1 25h Initialize 8237A controller
16h User register config through CMOS 26h Initialize int vectors
17h Sizememory 27h RAM quick sizing
18h Dispatch to RAM test 28h Protected mode entered safely
19h Check sum the ROM 29h RAM test completed
1Ah Reset PIC’s 2Ah Protected mode exit successful
1Bh Initialize video adapter(s) 2Bh Setup shadow
1Ch Initialize video (6845Regs) 2Ch Going to initialize video
1Dh Initialize color adapter 2Dh Search for monochrome adapter
1Eh Initialize monochrome adapter 2Eh Search for color adapter
1Fh Test 8237A page registers 2Fh Signon messages displayed
131

7.2 Error Codes
Following is a list of error codes in sequent display on the PIO debug board.
Code POST Routine Description Code POST Routine Description

30h Special init of keyboard ctlr 40h Configure the COMM and LPT ports
31h Test if keyboard Present 41h Initialize the floppies
32h Test keyboard Interrupt 42h Initialize the hard disk
33h Test keyboard command byte 43h Initialize option ROMs
34h Test, blank and count all RAM 44h OEM’s init of power management
35h Protected mode entered safely(2) 45h Update NUMLOCK status
36h RAM test complete 46h Test for coprocessor installed
37h Protected mode exit successful 47h OEM functions before boot
38h Update output port 48h Dispatch to operate system boot
39h Setup cache controller 49h Jump into bootstrap code
3Ah Test if 18.2Hz periodic working 50h ACPI init
3Bh Test for RTC ticking 51h PM init & Geyserville
3Ch Initialize the hardware vectors 52h USB HC init
3Dh Search and init the mouse
3Eh Update NUMLOCK status
3Fh Special init of COMM and LPT ports
132

7.3 Maintenance Diagnostics
7.3.1 Diagnostic Tools :
LED * 8
OR
PIO CONNECTOR * 1
P/N:411904800001
Description: PWA; PWA-378Port Debug BD
Note: Order it from MIC/TSSC
7.3.2 Circuit:
PIO 25 14
Connector 13 1 PIN1 : STROBE PIN 13 : SLCT
PIN10: ACK# PIN 16 : INT#
PIN11: BUSY PIN 17 : SELIN#

LED
PIN12: PTERR PIN 14 : AUTOFD#
PIN{9:2}: PD{7:0}
133

8. Trouble Shooting
8.1 No Power
8.2 No Display
8.3 VGA Controller Failure LCD No Display
8.4 External Monitor No Display
8.5 Memory Test Error
8.6 Keyboard (K/B) Touch-Pad (T/P) Test Error
8.7 Hard Driver Test Error
8.8 CD-ROM Driver Test Error
8.9 PIO Port Test Error
8.10 USB Port Test Error
8.11 Audio Failure
8.12 LAN Test Error
8.13 PC Card Socket Failure
8.14 IEEE 1394 Failure
134

8.1 No Power
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.
No power
Is the
notebook connected No Connect AC adaptor
to power (either AC adaptor Check following parts and signals:
or battery)? or battery.
Parts: Signals:
Board-level Where from J2 PD506 ADINP
Try another known good power source problem AC PF501 PD504
Troubleshooting ALWAYS
battery or AC adapter.
(first use AC to PL508 +DVMAIN
power it)? PL501 +VDD5S
JS501
No PU502
Power
PD502
OK? Battery PD514
PD505
Yes
Is
the M/B and charger
Replace the BD connected Check following parts and signals:
faulty AC properly? Replace
adaptor or Motherboard
Battery. Parts: Signals:
Try another known J14 PU512 BATT

good charger BD. PF502 PR551 VMAIN
PL504 PQ509 -ADEN
PL505 PQ508 BAT_V
PR564 RP553 BAT_T
Replace the Yes Power No PU513 PR552
faulty Charger OK?
BD.
135

8.1 No Power
P15
L32
P25 BATT MIIAVDD
Main Voltage Map U512
P16
PD3,PL5,PQ1,PL6,PU9 +1.8V NOTE:
Charge
P16
U523
USBVDD P1 P3 : Page 1, 2, 3 on D/D board
PU513
circuit diagram.
Discharge PU10
P23
P27 J7 1.25V P6 P29 : Page 6~29 on M/B board
P29
circuit diagram.
L543
P2 PJ2 +PHYVDD
PF501 : Through by part PF501.
P29
L544
PF501 +PHYAVDD
PL501 PD514 PU2
PL508 JO502 PD505 PL504 PU3 JO506
P1 P1 P2
JS501 PU502 PD506 PL505 PU4 JO507 PU503
POWER IN ADINP +DVMAIN +DVMAIN1 +3V_P +3V +3VS To next page
PU4
P2 P2
J2 P2 PU5
PU6 JO1 JS4
P1 P1 P2 P17
PD503 PL3 JO2 PU501 JS5
+5V_P +5V +5VS +5VS_HDD
PD504
P2 JS6 P17
Discharge U3 JS7
P2 ALWAYS USB0VCC5 +5VS_CD
P3 P18
U1 U505
USB5VCC5 VCCA
P2 PJ2
JS2 P20 P18
JS3 U505
PU4 5V_AMP VCCP
P27
J7 PU5
PU6 JS505
P20
F504 PL3 P1 P1 P2 L554
U506 PU507 JO505 PQ1 AVDDAD
+12V_P +12V +12VS
P27
Q509 P22 P27 JO503 P1 P27 PL7 PU7 JO501
P24 P24
L512 Q8 JO504 PJ1/J4 PU510 PU507 JO502
P27 H8_AVREF1 +5VA +5VAS +D/VMAIN VMAIN +1.8V_P +1.8VS To next page
P15 P15 PU8 JO503

P24 P24
Q511 U17 Q14 PU509 JO504
+5V +3VA VCC_RTC +2.5V_P +2.5V_DDR To next page
PL501 PU505 PU501 PU508 P26

PL502 PU506 PU502 PU1~PU6
+VCC_CORE
136

8.1 No Power
Main Voltage Map
P2 P11 P24 P7
L23 R613
+3VS VDDA48 +2.5V_DDR DDRVREFA
From last page P9 From last page P7
P6 P11
L14 L519 L19 R616
CPUAVDD +DVDD VDDZ DDRVREFB
P6 P9 P11 P11
L15 L10 L18 L22
PHYAVDD +VDDV VDDCPU CBVDDA
P6 P9 P11
L507 L7 L21
P11 L24
AGPAVDD1 +TVPLL_VCC VDDAGP CBVDD
P6 P9 P11 P12
L511 L9 L20 R95
AGPAVDD2 +TVPLL_VDD VDDPCI +DDRVREF
P6 P9 P11
R62 L510 L17
AGPVREF +LVDD0/1 VDDREF
P7 P9 P11 P24 P7
L13 L509 L16 R557
SDAVDD +LVDD2 VDDSD +1.8VS ZVREF
From last page P7
P7 P7 P14
L516 L508 L517 L518
DDRAVDD +LVDD3 SZ1XAVDD VDDZCMP
P7 P9 P14 P7
L505 L512 L26 L514
DCLKAVDD +DAV_VDD SZ4XAVDD DACAVDD1,2
P7 P9 P19 P14
L506 L513 L8 L524
ECLKAVDD +LPLL_VDD +3V_LAN SVDDZCMP
Q503
P7 F503 P10 P14
20
L515 L504 Q529 L38
Z1XAVDD LCDVCC +3VS_SPD IDEAVDD
P7 P11 P14
L12 L520 R109
Z4XAVDD VDDA SZVREF
137

8.1 No Power
PD504
D/D Board ALWAYS

PL508 PD503
JO502
120Z/100M ADINP PD514
PL501
PF501 8
J2 120Z/100M
JS501 3 7 PD505
2 6
POWER IN 1
D
5 +DVMAIN
S
PU502 PD506
G
PC502 PC501 PD501 SI4835DY

0.1µ 0.1µ RLZ24D PR507 PC518 PC523
470K 0.1µ 1000P
PR516
4.7K
PR508
100K
PQ501
2N7002 LEARNING 81
P22
Step1 : Connect Adaptor to ( D/D BD ) J2 & O/P “ALWAYS”. 45
U509
P2 P27
Step2 : “ALWAYS” --> U506 Generate +5VA. PR509
1M
Micro
PJ2 J7
Controller
Step3 : H8 O/P “LEARNING” for Charger Circuitry. PR3 R674
10 2.2K H8/F3437
3 6 I_LIMT 39
Step4 : For MOSFET “PU502” G=0,D<-->S. +VDD5S VCC PU1 OUT 47
1
PC5
PC4 4,5 P2
Step5 : O/P “ADINP”& “+DVMAIN”. 0.1µ RS+/- 1µ
MAX4173FEUT-T
R724
100K
-H8_RESET
ALWAYS U506 H8_AVREF1 Q509 +5VA Q511 +5V +5VA
F504 LP2951-02BM SI2301DS SI2301DS
8 1 D S S D
IN OUT
7
F/B
P27 2
D508 D516 C698 C699 R725 RESET
6 2 R621
5VTAP SENSE
G
UDZ5.6B
G
RLZ5.6B 10µ 4.7µ 10K

3
SHUTDN
100K
-SW_+5VA
SW502 R718 4
VCC P22
4 1K
R618 GND To H8 3
MN
10K U515
SW_+5VA
C799
From H8 Q510 0.01µ
DTC144WK
Mother Board
138

8.1 No Power – Battery Charge
D/D Board PQ1 PU9B PU9A

SI4835DY SI4925DY SI4925DY
PD3 PL5 PL6
120Z/100M 8
EC31QS04 3 7 33UH 5 8
2 6 6 3 1 7
ADINP 1 5 BATT
To next page
D
S
+5VAS 4 2
G
PC13 PC14 PC567 PC15 PR4 PR14 PR562 PR15 PD511

PR560
4
0.01µ 10µ 0.01µ 100µ 4.7K 4.7K PD4 100K PR7 100K RLZ20C
EC31QS04 130K 20K
PR3
8
1.25V 3
100K + LI_OVP
PQ3 1
MMBT2222A 2 _ PR16
33k
PU514A
4
PC581 PR558 LMV393M

PD7
PL501 0.1µ 14K PQ4
BAS32L
2N+ 2N7002 LI_OVP
PR9 PR10 PR8

487K 13.7k 976K
4
6
CHARGING PQ506 VADJ_2_P VADJ_1_P BAT_TYPE NIMH_CELL

D/VADJ2 D/VADJ1
From H8 DTC144WK
12.30V 0 0 0 0 1 3
12.40V 0 1 0 0
2
From H8 PQ2B PQ2A From H8
5
PR5 NDC7002N NDC7002N PR6

PR544 12.50V 1 0 0 0 1M 1M
47K
D 12.60V 1 1 0 0
PQ507
G 2N7002
S
8,11
PC573 PR545 PC569
C1,C2 2IN+
150P 1M 0.1µ 12
VCC
P25 2IN+
16 PR547
CHARGE_I_CTR
249K
13
OUTPUTCTRL
PU511 1IN-
2
+5VAS VMAIN
5 From H8
CT
PWM PR543
6 3 6.19K
RT FEEDBACK
+5VAS
14 TL594C 4 PR561 PC580
REF DTC PR546 PR559
PC575 4.7K 0.1µ PR556
2IN- 2.49K 100K
PR542 0.01µ 681K
PC568 PR540 10K
1000P 10K
8
1.25V 5 BATT_DEAD
+
PC575 7
0.01µ PC566
1µ 6 _
To H8
PR541 JS1 PU514A
4
100K LMV393M
C898 PR557
PC570 0.1µ
PQ510 100K
0.1µ
SCK431LCSK-5
139

8.1 No Power – Battery Discharge
D/D Board
PU513
SI4835DY
8
7 3
BATT1 6 2
BATT 5 1
VMAIN
S
PU512
G
SI4835DY
PC579 PC578
1000P 0.01µ 8
7 3 PR553
6 2 100K
5 1
D
S
G
PR564
301K
+5VA H8_AVREF1
PR552
33K
L521
PL504 -ADEN
120Z/100M
120Z/100M PQ508
J14 2N7002
PR551 C709 C708 C731 C728
PL505 226K 0.1µ 0.1µ 0.1µ 0.1µ
PF502
120Z/100M
P23 1,2 ADINP PQ509
+5VA
DTC144WK
4,9,59 36,37
3
-ADEN 47
PC583 PC584 P22
Battery Connector
0.01µ 1000P +5VAS D511

R672 BAV70LT1
2.2K
2
BAT_V BAT_VOLT 38 U509

PR11
4.99K
3 BAT_T BAT_TEMP 42
Micro
R671 C707
22 68P
PC19 PR12 PR563 PC582 C737 C736 3 Controller
0.1µ 20K 100K 0.1µ 0.1µ 0.1µ
R655 H8/F3437
C710 1M
68P
2
X503
16MHZ
140

8.2 No Display
There is no display on both LCD and VGA monitor after power on although the LCD and monitor is known-good.
No Display
Monitor No Replace monitor

or LCD module Board-level
or LCD.
OK? Troubleshooting
Yes
Make sure that CPU module,
DIMM memory are installed
Properly. Refer to port 378H
System
Yes error code description
BIOS writes
section to find out
Yes error code to port
Display which part is causing
Correct it. Replace 378H?
OK? the problem.
Motherboard
No
No
1.Try another known good CPU
module, DIMM module and BIOS.
2.Remove all of I/O device (FDD,
HDD, CD-ROM…….) from
motherboard except LCD or monitor. Check system clock and reset
circuit.
1. Replace faulty part.
Display Yes 2. Connect the I/O device to the
OK? M/B one at a time to find out To be continued
which part is causing the problem. Clock and reset checking
No
141

8.2 No Display
****** System Clock Check ******
+3VS
40 R644 33 HCLK_CPU P4 U1
+VCC_CORE +3VS HCLK_CPU#
R664 39 R648 33
10K
CPU
R673 33
PD#/VTT_PWRGD R626 R645 R649 Pentium 4
10K 4.7K 49.9 49.9
R678
Q516
10K
MMBT3904L
+3VS
9 R641 22 ZCLK0
Q517
MMBT3904L 31 R661 22 AGP_CLK P6 P7
47 R632 22 SDRAMCLK
U4
2 FS0 R630 33 REFCLK0
P11 IGUI
+3VS 44 R635 33 HCLK_SIS650
L520 Host/Memory
300Z/100M HCLK_SIS650#
43 R639 33
36 Controller
R636 R640 FWDSDCLKO SiS650
C715 C719 C718
49.9 49.9
0.1µ 0.1µ 1000P +3VS
To next page
37 R875 R624
10K 4.7K D520
45 CPU_STP#
P14 P15 P16
U508 3 FS1 R633 33 REFCLK1
L17 120Z/100M VDDREF 1 U14
+3VS R625 33 REFCLK3
L19 120Z/100M VDDZ 11 Clock 10 R646 22 ZCLK1 MuTIOL

L20 120Z/100M VDDPCI 13,19
Generator 26 R667 33 USBCLK_SB Media I/O
L23 120Z/100M CLK_SBPCI
Controller
VDDA48 28 14 FS3 R668 33
ICS952001 SiS961
L21 120Z/100M VDDAGP 29
L18 120Z/100M VDDCPU 42

27 R670 22 CLK_SIO 20 P21 U511
L16 120Z/100M VDDSD 48 15 FS4 R656 33 CLK_LPC33 8 Super I/O
PC87393
C702
10P R83 R565
7 4 FS2
33
14.318MHZ_TV
0
MOD_XOUT To U504
P9
SiS301LV/Chrontel CH7019
R660 33
4
3
2
17 CLK_CARDPCI To U6
X502 PCMCIA Controller P18
C701 14.318MHz
10P
1
6 23 R756 33 CLK_MINIPCI To J509

MINI PCI Socket P28
21 R755 33 CLK_1394PCI To U18
IEEE1394 Controller P29
142

8.2 No Display
****** System Clock Check ******
P12 J505
FWDSDCLKO 8 2 R90 0 CLK_DDR0
CLK_INT
From previous page
1 R91 0 CLK_DDR0#
+2.5_DDR
4 R89 0 CLK_DDR1
L22
300Z/100M
CBVDDA 10
VDDA 5 R88 0 CLK_DDR1#
C111 C101 13 R94 0 CLK_DDR2

0.1µ 1000P
P11 R93 0 CLK_DDR2#
14
+2.5_DDR
L24
600Z/100M
CBVDD 3,12,23 20 BF_OUT
VDD[0:2] FBINT
19
C99 C112 C150 C110 FB_OUTT
10µ 0.1µ 0.1µ 0.1µ
R99
22 C196
10P
U27
P12 J506
17 R98 0 CLK_DDR3
Bit 2 Bit 7 Bit 6 Bit 4 Bit 5 CPU SDRAM ZCLK AGP Clock
FS4 FS3 FS2 FS1 FS0 (MHz) (MHz) (MHz) (MHz)
R97 0
0 0 0 0 0 66.7 66.67 66.67 66.67
Buffer 16 CLK8_DDR3#
0 0 0 0 1 100.00 100.00 66.67 66.67

0 0 0 1 0 100.00 200.00 66.67 66.67 24 R100 0 CLK_DDR4
0 0 0 1 1 100.00 133.33 66.67 66.67
0
0
0
0
1
1
0
0
0
1
100.00
100.00
150.00
125.00
60.00
62.50
60.00
62.50
ICS93722 R101 0
25 CLK_DDR4#
0 0 1 1 0 100.00 160.00 66.67 66.67
0 0 1 1 1 100.00 133.33 80.00 66.67
0 1 0 0 0 100.00 200.00 66.67 66.67 26 R102 0 CLK_DDR5
0 1 0 0 1 100.00 166.67 62.50 62.50
0 1 0 1 0 100.00 166.67 71.43 83.33
0 1 0 1 1 80.00 133.33 66.67 66.67 R102 0 CLK_DDR5#
27
0 1 1 0 0 80.00 133.33 66.67 66.67
0 1 1 0 1 95.00 95.00 63.33 63.33
0 1 1 1 0 95.00 126.67 63.33 63.33
0 1 1 1 1 66.67 66.67 50.00 50.00
143

8.2 No Display
****** Power Good & Reset Circuit Check ******
+5VS +5VS
U502
R518 MIC5248 R517
U2 10 10K
+3VS
1,3 4 CPU_CORE_EN
MAX809 IN PG
PWROK
EN P5 VCCPVID
3 2 5
VCC RESET# C514 OUT
0.1µ
C223 P7 R145 C513 P4
0.1µ 100K 1µ
+3V
D513 +VCC_CORE
RLS4148
PWROK U1
P6 P7
CPU
R12 R512
R705
301 51
P24 P26 CPU_CORE_EN 1K
AUXOK U4 CPURST#
Pentium 4
IGUI CPUPWRGD
R706 C782
D15 100K 22µ
PU510 RLS4148 Host/Memory
H_PWRGD
PU508 D14 Controller -PCIRST

RLS4148 +5VS
H8_PWROK 68 SiS650 R214 J19
10K
IDE_RST# 1
8575 P17
R682 R215
Power 1K P22 10K
PWR_ON H8_PWRON 49
Module AUXOK R1 Q18
DTC144TKA
Primary EIDE
C732 R679 P14 P15 -PCIRST R1 Q19 Connector
10P 20K PWROK 5
DTC144TKA
U509 P17 J12

Secondary EIDE Connector
+5VA +3V U14
Micro
Controller R665 MuTIOL P9 P18 P21 P28 P29
H8/F3437 10K
R725 Media I/O -PCIRST U504 U6 U511 J509 U18
SW502 R718
10K 4 P22 1 -H8_RESET 1 SIS_PWRBTN#
To I/O devices
SiS301LV PCMCIA LPC MINI PCI IEEE 1394
1K
VCC RESET Controller Chrotel/CH7019 Controller Super I/O Socket Controller
3
MN U515 91 SIS_PWRBTN Q515
SiS961
R724 DTC144WK AC97_RST# P19 P20
C799 100K
0.01µ J18 U15
MDC Audio Codec
144

There is no display or picture abnormal on LCD although power-on-self-test is passed.
VGA Controller Failure

LCD No Display
1. Confirm LCD panel or monitor is good

Check if Yes
and check the cable are connected Re-soldering.
U504, J3 are cold
properly.
Board-level solder?
2. Try another known good monitor or
LCD module. Troubleshooting
No
Yes Replace faulty

Display One of the following parts on the mother-board may be
OK? LCD or monitor. defective, use an oscilloscope to check the following signal or
replace the parts one at a time and test after each replacement.
No
Remove all the I/O device & cable from Replace Parts: Signals:
motherboard except LCD panel or extended Motherboard
U4 R828 +3VS TX2OUT[0:2]+
monitor. U504 R829 LCDVCC TX2OUT[0:2]-
U509 R830 ENAVDD BLADJ
J3 L514 PID[0:2] KH8_ENABKL
J7 L512 TXCLK+ -LID
Connect the I/O device & cable PJ2 L513 TXCLK-
Display Yes to the M/B one at a time to find J6 L515 TX2CLK+
OK? out which part is causing the Q503 SW1 TX2CLK-
problem. F503 R511 TXOUT[0:2]+
L504 TXOUT[0:2]-
No Q2
145

There is no display or picture abnormal on LCD although power-on-self-test is passed.
Q503
+3VS NDS9410
F503 L504
8
mircoSMDC110 120Z/100M
J3
7 3
6 2 LCDVCC 1,2
5 1
S
D
C506 +12VS G C510 C509 C3 C2
0.1µ +3VS
R505 0.1µ 1000P 0.1µ 1000P
RP1 P10
470K
1K*4
32,34,36
Q2 C506 24 TXCLK+ 8
DTC144TKA R1 0.1µ P9
25 TXCLK- 10
U504
5 TX2CLK+ 7
LCD Connector
ENAVDD 127 6 TX2CLK- 9
SiS301LV/
33,30,27 TXOUT [0:2]+ 20,26,25
DISPLAY LCD_ID2 LCD_ID1 LCD_ID0 ENABKL 128
Chrontel
34,31,28 TXOUT [0:2]- 22,28,27
P7 UNIQAC
HYUNDAI
0
0
0
1
1
0 17,14,11 TX2OUT [0:2]+ 13,14,19
LCD
HANNSTAR 0 1 1 CH7019
CMO 1 0 0 18,15,12 TX2OUT [0:2]- 15,16,21
U4
R828 0 LCD_ID0
IGUI PID0 31
R829 0 LCD_ID1
Host/Memory PID1 33
R830 0 LCD_ID2
Controller PID2 35
1 X
4
3
2
RP40
SiS650 R74
10K*4
100
DC Power Board
5
6
X 8
7
+5VA J6
L514 2,3
+5V
P27 J7 PJ2 P2
R642 L512 11
P2
10K +5VS
P22
U509 45 BLADJ BLADJ L513 4
Inverter
17 H8_ENABKL ENABKL ENPBLT1 L515 1

Micro 7
R511
SW1
Controller 48 -LID -LID
1K C512 C513
5,6
49 0.1µ 0.1µ
H8/F3437 C714 C522
Inverter Board
Cover Switch
2.2µ Signal HI LOW 2.2µ
-LID Normal Suspend
146

There is no display or picture abnormal on CRT monitor, but it is OK for LCD.
External Monitor No Display
1. Confirm monitor is good and check

the cable are connected properly. Check if
Board-level Yes
2. Try another known good monitor. Troubleshooting U4, J2 Re-soldering.
are cold solder?
No
Display Yes
Replace faulty monitor.
OK?
One of the following parts on the mother-board may be
defective, use an oscilloscope to check the following signal or
No
replace the parts one at a time and test after each replacement.
Remove all the I/O device & cable from Replace Parts: Signals:
motherboard except monitor. Motherboard
U4 Q505 CRT_IN#
U14 Q502 REFCLK0
U508 Q501 CRT_DDDA
J2 Q506 CRT_HSYNC
Connect the I/O device & cable R1 FA501
Yes CRT_VSYNC
Display to the M/B one at a time to find R566 L503
R546 L502 CRT_DDCK
OK? out which part is causing the R547 CRT_RED
L501
problem. R548 CRT_GREEN
No CRT_BLUE
147

There is no display or picture abnormal on CRT monitor, but it is OK for LCD.
+3VS
+3VS
R2 J2
R1
+3VS P15 1K
1K
REFCLK0 CRT_IN#
5
P11 To U14 SiS961
From U508 Clock Gen.
C1
R552
2.2K
R558
2.2K
FA501 1000P P10
G 120OHM/100MHZ
R566
100 CRT_DDDA S D 12
G Q505
P7 R546 2N7002
33 CRT_HSYNC S D 13
G Q502
External VGA Connector

R547 2N7002
33 CRT_VSYNC S D 14
G Q501
R548 2N7002
100 CRT_DDCK S D 15
Q506
U4 2N7002
CRT_RED L503 120Z/100M 1
CRT_GREEN L502 120Z/100M 2

IGUI
L501 120Z/100M
Host/Memory CRT_BLUE 3
Controller
1X
X
6,7,8,10
3
2
2
4
2
4
3
C600
VVBWN 0.1µ
RP502 CP501 CP502
SiS650 C593
+1.8VS
75*4 22P*4 22P*4 JL1
VCOMP 0.1µ
L514
6
7
7
5
7
5
6
120Z/100M JL501
X
DACAVDD1,2
C583 C584 C561

0.1µ 1µ 10µ
DACAVSS1,2 JL509
R545
130
VRSET
148

Extend SDRAM is failure or system hangs up.
Memory Test Error
1.If your system installed with expansion

SO-DIMM module then check them for
proper installation. One of the following components or signals on the motherboard
2.Make sure that your SO-DIMM sockets may be defective ,Use an oscilloscope to check the signals or
are OK. Board-level replace the parts one at A time and test after each replacement.
3.Then try another known good SO-DIMM Troubleshooting Parts: Signals:
modules.
U4 R90 +2.5V_DDR
U508 R91 +DDRVREF
U9 R98 CKE[0:3]
Yes J505 R88
Test Replace the faulty DDR_DQM[0:7]
J506 R94
OK? SDRAM module. DDR_MD[0:63]
RP8~RP12 R93
DDR_BA [0,1]
RP13~RP15
No RP16~RP20 DDR_CS[0:3]#
R632 DDR_MA[0:12]
R614 DDR_DQS[0:7]
If your system host bus clock running at R658 DDR_RAS#
266MHZ then make sure that SO-DIMM Replace R662 DDR_CAS#
module meet require of PC 266. Motherboard R98 DDR_WE#
R100 SDRAMCLK
R102 FWDSDCLK
R97
SMBDATA
R101
SMBCLK
Test Yes Replace the faulty R103
CLK_DDR[0:5]
Ok? SDRAM module. CLK_DDR[0:5]#
No
149

Extend SDRAM is failure or system hangs up.
+3VS
L516 +1.25V
120Z/100M
DDRAVDD
C623 C624 C632

J505
0.01µ 0.1µ 10µ
+2.5V_DDR RP21~RP33 SMBDATA
33*8
DDRAVSS JL507
RP7
SMBCLK P12
470
CKE [0:3] CKE 0,1
+2.5V_DDR
P7 DDR_DQM [0:7] DQM [0:7]
+DDRREF
DDR_MD [0:63] MD [0:63]
DDR SODIMM
DDR_BA [0,1], DDR_CS [0:3]# BA [0,1], CS [0:3]# CS [0,1]#
DDR_MA [0:12], DDR_DQS [0:7] MA [0:12], DQS [0:7]
DDR_RAS#, DDR_CAS#, DDR_WE# RAS#, CAS#, WE#
U4
R90,R89,R94
RP8~RP12 10*8 +3VS R91,R88,R93
+2.5V_DDR RP13~RP15 0*8 0 CLK_DDR [0:2] , CLK_DDR [0:2]#
RP16~RP20 10*8
IGUI P15
C689 R613 R836 R837
Host/Memory 0.01µ 150 From U14 SiS961 4.7K 4.7K J506
DDRVREFA
SMBDATA
Controller
C688 R612 +2.5V_DDR
0.01µ 150 SMBCLK
P12
SiS650
C692 R616 R658
0.01µ 150 33
DDRVREFB 47 P11 U508 35
+2.5V_DDR
C693 R615 CS [2,3]#
0.01µ 150 34 +DDRVREF
DDR SODIMM
Clock Gen.
R599
4.7K ICS952001 R662
R95
DRAM_SEL 33
+3VS 1K
R632 7
22
P11 CKE 2,3
SDRAMCLK U9
22 R98,R100,R102 R556
R97,R101,R103 1K
FWDSDCLKO 8 Clock Buffer 0
2,1,4,5,13,14,17,16,24~27 CLK_DDR [0:5] , CLK_DDR [0:5]# CLK_DDR [3:5] , CLK_DDR [3:5]#
R614
ICS93722
22
150

Error message of keyboard or touch-pad failure is shown or any key does not work.
Keyboard or Touch-Pad
Test Error
Check
Yes
U509, J13, J20 Re-soldering
for cold solder?
Is K/B or
T/P cable connected to No
Correct it. Board-level
notebook Troubleshooting
properly? No
Yes One of the following parts or signals on the motherboard

may be defective, use an oscilloscope to check the signals
or replace the parts one at a time and test after each
replacement.
Try another known good Keyboard
or Touch-pad. Parts Signals
Replace U511 L33 +5VA KBD_US/JP#

Motherboard U11 L31 H8_AVREF1 SA2
U509 SW503 +3VS IRQ1
Yes Replace the faulty J13 RP48 IRQ12
Test +5V
Keyboard or J20 -IOR
Ok? -ROMCS
Touch-Pad L521
-MCCS -IOW
R146
No KI[0:7]
R690
F1 KO[0:15]
L29 T_CLK_H8
T_DATA
151

Error message of keyboard or touch-pad failure is shown or any key does not work.
+5VA H8_AVREF1
L521
120Z/100M
+3VS C709 C731 C708 C728

0.1µ 0.1µ 0.1µ 9,59,4 37,36 0.1µ
VCC1,2,B AVCC
R737 AVREF
100K J13
SW503
19 KBD_US/JP# 1 4
KI [0:7] 17~24
P22
2 3
X
R744
10K P22
P21
KO [0:15] 1~16
+5VA
+3VS
Internal Keyboard Connector
U11
R245 R138 R125 U509
4.7K 10K 10K
R146
U511 0
Level Shift
72 -ROMCS 8 9 -H8_KBCS 95
F1 J20
0.25A
LPC Micro KO 0,1 5,6
R690
Controller +5V
Super I/O 73 -MCCS
0
14 15 -H8_MCCS 98 KI 0,5 7,8
P21
PC87393 H8/F3437 L29 120Z/100M 1

93 SA2 93 RP48
T_CLK_H8 0 T_CLK L33 120Z/100M 2
23
87 IRQ1 53
T_DATA L31 120Z/100M 3
18
86 IRQ12 54
4
83 -IOR 96
C222 C221
47P 0.1µ
82 -IOW -IOW_H8 82
Touch-pad
RP48
0
C228
47P
152

8.7 Hard Drive Test Error
Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing
data to hard disk.
Hard Driver Test

Error
1. Check if BIOS setup is OK?. Board-level

2. Try another working drive and cable. Troubleshooting
One of the following parts or signals on the motherboard may
be defective, use an oscilloscope to check the signals or replace
the parts one at a time and test after each replacement.
Yes
Re-boot
Replace the faulty parts. Parts: Signals:
OK?
U14 +5VS
No R212
J12 R213 +5VS_HDD
R215 R211 -PCIRST
Check the system driver for proper Q19 IDE_PIORDY
Replace R205
Q18 IDE_PDD[0:15]
installation. Motherboard R210
R214 IDE_PDA[0:2]
JS6 IDE_PDCS3#
JS7 IDE_PDCS1#
R202 IDE_PDIOR#
RP42 IDE_PDIOW#
Re - Test Yes IDE_PDDACK#
End RP45
OK? R781 IDE_PDDREQ
IDE_IRQ14
No
153

8.7 Hard Drive Test Error
Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing
data to hard disk.
+5VS
+5VS JS4 +5VS_HDD
R214 J19
10K
JS5
41, 42
R215
C261 C273 C258
10K
0.1µ 4.7µ 0.1µ P17
R1 Q18
DTC144TKA
-PCIRST R1 Q19 IDE_RST# 1

DTC144TKA
+5VS D19
R200
470 PG1102W
39
+5VS
R144
P14 4.7K
Primary EDIE Connector

IDE_PIORDY R202 10 PIORDY 27
RP42, PR45
U14 10*8
IDE_PDD[0:15] PDD[0:15] 2~18
MuTIOL IDE_PDA[0:2], IDE_PDCS3# RP528 33*4 PDA[0:2], PDCS3# 33,35,36,38
Media I/O IDE_PDCS1# R781 33 PDCS1# 37

Controller
IDE_PDIOR# R212 10 PDIOR# 25
SiS961 IDE_PDIOW# R213 22 PDIOW# 23
IDE_PDDACK# R211 22 PDDACK# 29
IDE_PDDREQ R205 82 PDDREQ 21
IDE_IRQ14 R210 82 IRQ14 31
154

8.8 CD-ROM Drive Test Error
An error message is shown when reading data from CD-ROM drive.
CD-ROM Driver
Test Error
1. Try another known good compact disk. Board-level

2. Check install for correctly. Troubleshooting
Test Yes
Replace the faulty parts. Parts: Signals:
OK?
U14 R208 +5VS
No J12 R176 +5VS_CD
R215 R203 -PCIRST
Q19 R170 IDE_SIORDY
Check the CD-ROM driver for proper Replace Q18 R207 IDE_SDD[0:15]
Motherboard R214 IDE_SDA[0:2]
installation. R777
JS6 IDE_SDCS3#
JS7 IDE_SDCS1#
R204 IDE_SDIOR#
RP41 IDE_SDIOW#
RP44 IDE_SDDACK#
Re - Test Yes
End RP43 IDE_SDDREQ
OK? IDE_IRQ15
No
155

8.8 CD-ROM Drive Test Error
An error message is shown when reading data from CD-ROM drive.
+5VS
+5VS JS6 +5VS_CD
R214 J12
10K
JS7
38~42
R215
C648 C74 C643
10K
4.7µ 0.1µ 0.1µ P17
R1 Q18
DTC144TKA
-PCIRST R1 Q19 IDE_RST# 5

DTC144TKA
+5VS D18
R743
470 PG1102W
37
+5VS
R73
P14 4.7K
Secondary EDIE Connector

IDE_SIORDY R204 10 SIORDY 27
RP41, PR44
U14 10*8
IDE_SDD[0:15] SDD[0:15] 7~21
MuTIOL IDE_SDA[0:2], IDE_SDCS3# RP43 33*4 SDA[0:2], SDCS3# 31,33,34.36
Media I/O IDE_SDCS1# R208 33 SDCS1# 35

Controller
IDE_SDIOR# R176 10 SDIOR# 24
SiS961 IDE_SDIOW# R203 22 SDIOW# 25
IDE_SDDACK# R170 22 SDDACK# 28
IDE_SDDREQ R207 82 SDDREQ 22
IDE_IRQ15 R777 82 IRQ15 29
156

8.9 USB Test Error
An error occurs when a USB I/O device is installed.
USB Test Error
Check if the USB device is installed

properly. (Including charge board.)
Board-level Check the following parts for cold solder or one of the following
Troubleshooting parts on the mother-board may be defective, use an oscilloscope
Yes to check the following signal or replace the parts one at a time
Test and test after each replacement.
Correct it
OK?
No Parts: Signals:
M/B D/D +3V -USBOC3_5

Replace another known good charge USBCLK_SB USBP5+
U14 PJ2 U1
board or good USB device. -USBOC0_1 USBP5-
J7 JU3 J8
Replace R147 J5 J4 USBP0+ USB5VCC5
R148 J7 D3
Motherboard R75 D504 L520 USBP0- USBP3+
R518 L524 L522 USB0VCC5 USBP3-
Yes R142 L509 L504
Re-test USBP1+
Correct it R143 L516 L508
OK? R161 L518 USBP1-
R163
No
157

8.9 USB Test Error - 1
USBCLK_SB
From U508 clock generator
DC Power Board
L524
+3V +3V USB0VCC5
120Z/100M
L523
120Z/100M P27 J7 PJ2 P2 D504
BAW56
USBVDD
R516 -USBOC1
10K 2 R506 C506
P16 C744 C745 C743 -USBOC0_1 3 33K 0.1µ
0.1µ 1µ 10µ
1 -USBOC0
USBVSS J5
C534 R518 1
1000P 47K
USB_OC0_1# L509 P2
OC0,1# 50 600Z/100M
USBP0+ 3
USB_OC3_5#
OC3,5# 48 1 2
R147 USBP0- 4 3 2
22
USBP0_P USBP0+
U14 32 R504 R505 4
USBP0_N USBP0- 15K 15K
34
GND
C86 C87 R148
MuTIOL 100P 22P 22
+5V
Media I/O R75 USB0VCC5 GND_USB
22 3 5
Controller USBP1_P USBP1+ VIN0 P2 VOUT1
L516
26
120Z/100M
USBP1_N USBP1-
4 1
28 VIN1 U3 VOUT0
SiS961 C122 C121 R158
22 C8 C10
100P 22P R3 C517
1µ 1µ
33K 0.1µ
-USBOC1
R142
J7
C9 R5 1
22
USBP3_P USBP3+ 1000P 47K
14
L518 P2
USBP3_N USBP3-
16 600Z/100M
USBP1+ 3
C83 C84 R143 1 2
100P 22P 22
R161 USBP1- 4 3 2
22
USBP5_P USBP5+
1 R508 R509 4
15K 15K
USBP5_N USBP5- JO512
3
GND
C126 C125 R163
100P 22P 22
GND_USB
158

8.9 USB Test Error - 2
USBCLK_SB
From U508 clock generator
DC Power Board
L520
+3V +3V USB5VC5 120Z/100M
L523
120Z/100M P27 J7 PJ2 P2 D3
BAW56
USBVDD
R10 -USBOC3
10K 2 R7 C525
-USBOC3_5 3 33K 0.1µ
C744 C745 C743
P16 0.1µ 1µ 10µ
1 -USBOC5
USBVSS J8
C11 R8 1
1000P 47K
USB_OC0_1# L522 P3
OC0,1# 50 600Z/100M
USBP5+ 3
USB_OC3_5#
OC3,5# 48 1 2
R147 USBP5- 4 3 2
22
U14 USBP0_P USBP0+
32 R513 R514 4
15K 15K
USBP0_N USBP0-
34
GND
MuTIOL C86 C87 R148
22
100P 22P +5V
Media I/O
R75 USB5VCC5 GND_USB
3 5
Controller USBP1_P
22
USBP1+ VIN0 P3 VOUT1
L504
26
120Z/100M
USBP1_N USBP1- 4 1
28 VIN1 U1 VOUT0
SiS961 C122 C121 R158
22 C3 C509
100P 22P R2 C504
1µ 1µ
33K 0.1µ
-USBOC3
R142 J4
22 C1 R4
USBP3_P USBP3+ 1
14 1000P 47K
USBP3_N USBP3- L508 P3
16
600Z/100M
C83 C84 R143 USBP3+ 3
100P 22P 22 1 2
R161 USBP3- 4 3 2
22
USBP5_P USBP5+
1
R503 R502 4
USBP5_N USBP5- 15K 15K
3 JO501
C126 C125 R163 GND
100P 22P 22
GND_USB
159

When a print command is issued, printer prints nothing or garbage.
PIO Port Test Error
1. Check if PIO device is installed

properly. (J504) Board-level
2. Check CMOS LPT port setting properly. Troubleshooting
Test Yes Parts: Signals:

Correct it
OK?
M/B D/D
No U511 PJ2 +5VS -P_STB
J7 U501 P_LPD0 -P_AFD
RP501 U502
Try another known good Yes Replace the Replace RP503 J3
P_LPD1 -P_ERR
PIO device. faulty parts. Motherboard RP504 RP1 P_LPD2 -P_INIT
RP505 RP2 P_LPD3 -P_SLIN
R501 R1 P_LPD4 -P_ACK
No
CP503 RP3 P_LPD5 P_BUSY
CP504 RP4
P_LPD6 P_PE
CP505 D1
Re - Test Yes CP506 P_LPD7 P_SLCT
End
OK? C504
No
160

When a print command is issued, printer prints nothing or garbage.
+5VS
P3 U501
D501
PAC128401Q BAS32L
PJ2 P2 RP1 12 13
J3
0*4
Mother Board P27 J7 -P_STB 8 1 -PP_STB 11 14 STB# 1
25
-P_AFD 7 2 -PP_AFD 10 15 AFD# 14
P3
23
P_LPD0 6 3 P_LPD0 9 16 LPD0 2
43
RP501 -P_ERR 5 4 -PP_ERR 8 17 ERR# 15
0*4 21
P_LPD [0:3] DP_LPD [0:3] P_LPD1 RP2 8 1 PP_LPD1 7 18 LPD1 3
41
0*4
-P_INIT -PP_INIT
P21 RP503 19
7 2 6 19 INIT# 16
0*4 P_LPD2 6 3 PP_LPD2 5 20 LPD2 4

P_LPD [4:7] DP_LPD [4:7] 39
-P_SLIN 5 4 -PP_SLIN 4 21 SLIN# 17
17
P_LPD3 PP_LPD3 3 22 LPD3
RP504
Parallel Port Connector

5
37
U511 P_SLCT, -P_STB 0*4 DP_SLCT, -DP_STB
R1
2 23
-P_AFD, -P_ERR -DP_AFD, -DP_ERR 1 24 18-27
0
RP505 P3
LPC -P_INIT, -P_SLIN
0*4
-DP_INIT, -DP_SLIN U502
-P_ACK, P_BUSY -DP_ACK, DP_BUSY PAC128401Q GND_IO2
Super I/O RP3 12 13
0*4
R501 P_LPD4 8 1 PP_LPD4 LPD4 6
35 11 14
PC87393 0
P_PE DP_PE P_LPD5 PP_LPD5
7 2 10 15 LPD5 7
33
P_LPD6 6 3 PP_LPD6 9 16 LPD6 8
31
P_LPD7 5 4 PP_LPD7 8 17 LPD7 9
CP503 C504 29
VDD[0:3] +3VS 22P*4 22P -P_ACK -PP_ACK
8 1 7 18 ACK# 10
36
P_BUSY 7 2 PP_BUSY 6 19 BUSY 11
34
P_PE 6 3 PP_PE 5 20 PE 12
32
CP504 CP505 CP506
22P*4 22P*4 22P*4 P_SLCT 5 4 PP_SLCT 4 21 SLCT 13
27
RP4 3 22
X X
0*4 2 23
1 24
GND_IO2 GND_IO2
161

8.11 Audio Failure
No sound from speaker after audio driver is installed.
Audio Failure
1. Check if speaker cables are connected

properly.
2. Make sure all the drivers are installed Board-level Check the following parts for cold solder or one of the following parts on the
properly. Troubleshooting motherboard may be defective,use an oscilloscope to check the following signal
or replace parts one at a time and test after each replacement.
1.If no sound cause 2. If no sound cause 3. If no sound cause

Test Yes of line out, check of MIC, check of CD-ROM, check
OK? Correct it. the following the following the following
parts & signals: parts & signals: parts & signals:
No
Parts: Signals: Parts: Signals: Parts: Signals:
1.Try another known good speaker, U14 AOUT_R U14 +5VS U14 CDROM_LEFT
CD-ROM. U15 AOUT_L U15 AVDDAD U15 CDROM_RIGHT
2. Exchange another known good Replace U16 +3VS J21 MIC1 J12 CDROM_COMM
charger board. Motherboard VR1 5V_AMP J28 R187
L529 +3VS_SPD C272 R185
L28 SPK_OFF L531 R186
L530 SPDIFOUT L532
Q528
Yes Q529
Re-test J24
Correct it.
OK?
No
162

8.11 Audio Failure
L532
600Z/100M J21
AUDIO IN L553
120Z/100M
AVDDAD 1
Internal
1,9 R728 R727
+3VS DVDD1,2 2.7K MIC_VREF 2.2K 2 MIC
C88 C116 C118
10µ 0.1µ 47P
C801 C788 R739
1µ 2.2µ 2.7K
+5VS AVDDAD J28
L554 3
JS505 120Z/100M
25,38 5
AVDD1,2 C272 L531
600Z/100M MIC_3 4
1µ
C784 C117 C120 21 MIC1 MIC MIC_2 2
10µ 0.1µ 0.1µ
1
C798 L535
P20 C264 220P 600Z/100M External
0.1µ
R154
22
22 MIC2 MIC
AC97_SDIN 8
P15 AC97_SDOUT 5
C271 R187
AC97_SYNC R764 22 10 1µ 6.8K
20 CDROM_RIGHT 2
U14 U15
AC97_RST# 11 C269 R185 P17 J12
1µ 6.8K
18 CDROM_LEFT 1
AC97_BITCLK R699 22 6
MuTIOL C270 R186 CDROM
Audio Codec 19 1µ 6.8K CONN
Media I/O CDROM_COMM 3
SPK_OFF#
Controller To next page C227
ALC201 R193 R191 R192 R141
10P
2 100K 100K 100K 0
SiS961 X3 R150
24.576MHZ 1M C274 R173
0.1µ 0
SB_SPKR LINE/IN/L 23
AVDDAD 3
R703 C771 C246 C260 R165 L34 120Z/100M

10K 0.1µ 10P 0.1µ 0
LINE/IN/R 24
L35 120Z/100M
L40 120Z/100M
L545 120Z/100M
5
48 SPDIFOUT
R697 C777
1 470K 0.1µ L546 120Z/100M
4 12
-CARDSPK PC_BEEP
P18 U6 2 36 AOUT_R
L547 120Z/100M
To next page
U513 R698
3
R700 35 AOUT_L
20K
PCI1410GU 10K AGND
163

8.11 Audio Failure
AUDIO OUT -DEVICE_DECT -DECT_HP/OPT

C803 R731 R719 0 0 HP
2.2µ 10K 20K
0 1 OPT
1 0 No this condition
1 1 No device
C804 R732 R720
2.2µ 10K 10K
VR1_5
5V_AMP +3VS +3VS_SPD
L39
600Z/100M J25 Q529
DTA144WK
21 22 SPKROUT+ 1
RLINE IN R96
20 15 SPKROUT- 2 R 4.7K
RHP IN AMP_MUTE
L43
600Z/100M Internal
AMP_MUTE
11
MUTE IN
Speaker
L44
VR1 600Z/100M CONN Q10 R1
DTC144TKA
10K C201 P20 3 SPKLOUT+ 1
5
AOUT_R
0.1µ
4 7 5V_AMP 10 SPKLOUT- 2 L SPK_OFF
Q528 R1 -DECT_HP/OPT
6 L45
From last page U16 600Z/100M J23 DTC144TKA
1 3 R159 From last page
47K R168
AOUT_L 100K
5V_AMP
14
SE/BTL#
2
-DEVICE_DECT R1 Q523 16 R713

HP/LINE# R762 10K
DTC144TKA
4.7K -DECT_HP/OPT -DEVICE_DECT J24
5V_AMP
Amplifier LINE OUT
+5V 5V_AMP C289 R710
100µ 5
22
L27
120Z/100M TPA0202 3
L529
4
4
JS3
7,18
LVDD/RVDD R714 3
22
2 1 2
C245 C284 C247
100µ 0.1µ 0.1µ C280 1
100µ R194 C791 R174 C789
1K 100P 1K 100P
L534
600Z/100M
5
LHP IN L28
L536 SPDIFOUT 600Z/100M
4 LED
LLINE IN 120Z/100M 7
From last page Drive
C805 R733 R721 CAGND AGND 8
2.2µ 10K 20K 9 IC
+3VS_SPD 2 1
C806 R734 R722 3 4

2.2µ 10K 10K L552 L530
VR1_2 120Z/100M
164

8.12 LAN Test Error
An error occurs when a LAN device is installed.
LAN Test Error
1.Check if the driver is installed properly. Check the following parts for cold solder or one of the following
2.Check if the notebook connect with the parts on the mother-board may be defective, use an oscilloscope
LAN properly. to check the following signal or replace the parts one at a time and
test after each replacement.
Board-level
Troubleshooting Parts: Signals:
Yes U14 RP6 MIIAVDD RXIN+

Test Correct it. U5 RP5 +3V_LAN RXIN-
OK? U3 X4 LAN_DATAIO LAN_CT
J9 L6 LAN_DCLK TXD+
No L5 L8
LAN_MTXD[0:3] TXD-
R171 R32
R177 L4 LAN_MTXE PJRX+
R166 R31 LAN_MTXC PJRX-
Check if BIOS setup is ok. R167 R538 LAN_COL PJTX+
R172 R35 LAN_CRS PJTX-
Replace R178 R537 LAN_MRXDV PJ8
Motherboard R72 X1 LAN_MRXER PJ7
R69 LAN_MRXC PJ5
R67
Re-test Yes LAN_MRXD[0:3] PJ4
Correct it. OSC25MHI
OK? OSC25MHO
No
165

8.12 LAN Test Error
An error occurs when a LAN device is installed.
+3V +3V_LAN
L5
120Z/100M +3V_LAN +3V
MIIAVDD 7,8,15,16,25,54,63
VDD[0:6] L8
37 R609 0 120Z/100M
C232 C230 C754 VDD_IO0
0.01µ 0.1µ 10µ +3V_LAN 51 R66 0
JL522 VDD_IO1
MIIAVSS
R595 10K R61 10K C44 C45 C48 C62 C59 C64
55
P0AC 0.1µ 0.1µ 0.1µ 0.1µ 0.1µ 0.1µ
R64
1.5K 18 R49 22K
RESETN
R171 33 LAN_DATAIO 30 C57
1µ C54
R177 33 LAN_DCLK 31 0.1µ
P15 P16 P19
C41
R166 33 LAN_MTXD0 45 10P
R41 R46
R167 33 LAN_MTXD1 46 56 56
R172 33 LAN_MTXD2 47 L6
J9
14 RXIN+ 1
RD+
R178 33 LAN_MTXD3 48 2 1 16 PJRX+ 6
3 RX+
RDC
15 3
U14 LAN_MTXE U5 13 RXIN- 3 4 2
RD-
RX-
PJRX-
P19
43
P19 10 PJTX+ 8
TX+
LAN_MTXC R72 22 44 C310
0.1µ 9 PJTX- 7
MuTIOL TX-
RJ45 LAN Connector

LAN_COL R69 22 49
Media I/O LAN_CRS R67 22
R32
0
U3
50 3 LAN_CT
Controller RP6
ISC1893Y
LAN_MRXDV 1 8 22*4 36 C37 LF-H80P R31 R538
100P 75 75
LAN_MRXER 2 7 39 11 PJ7 1,2
TXC
SiS961 LAN_MRXC 38 5 TXD+ L4
7
3 6 TD+
2 1 R35 R537
4 5 6 75 75
TDC PJ4
14 4,5
6 TXD- 3 4 8 RXC
RP5 TD-
LAN_MRXD0 1 8 22*4 35
C577
R30 R27 1000P
LAN_MRXD1 2 7 34 61.9 61.9
LAN_MRXD2 3 6 33
GND_45
52 L5
LAN_MRXD3 4 5 32 120Z/100M C311
0.1µ
53 1 3 R260 0
OSC25MHI
2
4 R261 0
OSC25MHO C65 C68 LAN_GND
3 1 X1 JS502
2 27P 27P R262 0
25MHZ
4
C305 X4 C306 R263 0
10P 25MHZ 10P
LAN_GND GND_45
166

An error occurs when a PC card device is installed.
PC Card Socket Failure
1. Check if the PC CARD device is

installed properly. Board-level
Check the following parts for cold solder or one of the following
2. Confirm PC card driver is installed ok. Troubleshooting
parts on the mother-board may be defective, use an oscilloscope
to check the following signal or replace the parts one at a time and
Yes Parts: Signals

Test Correct it
OK?
U14 PCI_AD[0:31] PCI_SERR#
U508 PCI_C/BE# [0:3] CARD_PME#
No
U513 PCI_REQ0# SERIRQ
U505 -CARD_RI
Replace PCI_FRAME#
J11 CLK_CARDPCI
Try another known good PC card device. Motherboard PCI_IRDY#
R249 -VCCEN0
PCI_TRDY# -VCCEN1
R785
PCI_DEVSEL# -VPPEN0
Q20
PCI_STOP# -VPPEN1
R789
Re-test Yes Change the faulty R793 PCI_INTC#
+3VS
VCCA
OK? part then end. R219 -PCIRST#
VPPA
R220 PCI_GNT0#
No R218 PCI_PAR
PCI_PERR#
167

An error occurs when a PC card device is installed.
R249
10K +5VS
+3VS SUSPEND# +3VS +12VS
VCCA VPPA
R785
0
J11
3,4 5,6 9
AUX_VCC
-VCCEN0 1 11~13 17,51
PCI_VCC[0:3] -VCCEN1 2 10 18,52
CORE_VCC[0:5] U505
VPPEN0 15
VCCA SKT_VCC0,1
VPPEN1 14 TPS2211 C684
0.1µ
C662
0.1µ
C650
0.1µ
C661
0.1µ
P18
C203
+3VS 0.1µ
P18
R223
10K C217
U513
-CARD_RI 0.1µ CAD[0:31]
To H8 Q20
DTC144WK PCMCIA CAD9 R219 0
Card Bus Socket

CLK_CARDPCI
From U508 Clock Generator

Controller CAD12 R220 0
-CCBE[0:3]
PCI_AD[0:31]
P14 P15 R789
PCI1410 -CFRAME, -CIRDY, -CTRDY
PCI_AD20 100
IDSEL -CDEVSEL, -CSTOP, CPAR
U14
PCI_C/BE#[0:3]
-CPERR, -CBLOCK, CVS1,2
MuTIOL PCI_DEVSEL, PCI_FRAME#, PCI_IRDY#

-CSERR, -CREQ, -CINT
Media I/O PCI_TRDY#, PCI_STOP#, PCI_PAR, PCI_PERR# CAUDIO, CSTSCHG, -CCD1,2

Controller
PCI_SERR#, PCI_REQ0#, CARD_PME#, SERIRQ R2_D2, R2_D14, R2_A18
-CGNT
SiS961 -PCIRST, PCI_GNT0#
R793
0 CCLK R218 0
PCI_INTB#
168

An error occurs when a IEEE 1394 device is installed.
IEEE1394 Fail
1. Check if the 1394 device is installed

properly.
2. Confirm 1394 driver is installed ok.
Check the following parts for cold solder or one of the following
Board-level parts on the mother-board may be defective, use an oscilloscope
Troubleshooting to check the following signal or replace the parts one at a time and
Test Yes Parts: Signals
Correct it.
OK?
U14 PCI_AD[0:31] PCI_SERR#
No U508
PCI_C/BE# [0:3] 1394_PME#
U18 CLK_1394PCI
U7 PCI_REQ1#
SDATA
J27 PCI_FRAME#
Check if BIOS setup is ok. SCLK
L543 PCI_IRDY#
L544 TPA+
Replace R231 PCI_TRDY# TPA-
Motherboard R224 PCI_DEVSEL# TPB+
R198 PCI_STOP# TPB-
Yes R197 TPBIAS1
Re-test Correct it. R196
PCI_INTC#
+3VS
OK? R195 -PCIRST# +PHYVDD
R225 PCI_GNT1# +PHYAVDD
X6 PCI_PAR
No
PCI_PERR#
169

An error occurs when a IEEE 1394 device is installed.
+3VS
+3VS +PHYVDD
L543 R86 R87 R236

2.7K 2.7K 0
116 SDATA 5
C857 C231 C859 C233
4.7µ 0.1µ 0.1µ 0.1µ 117 SCLK 6
U7
P29
7
+3VS +PHYAVDD NM24C02N
8
87 R242
L544 0 C93
88 R225 1M 0.1µ
U18
C861 C235 C863 C239 C241 C252
4.7µ 0.1µ 0.1µ 0.1µ 0.1µ 0.1µ 1 3
2
4
IEEE 1394 C299
22P
X6
C300
22P
24.576MHZ
CLK_1394PCI
Controller
6
From U508 Clock Gen.

J27
uPD72872 101 TPA+ R198 0 4
P29
PCI_AD[0:31]
P14 P15 R231 100 TPA- R197 0 3
PCI_AD22 100
IDSEL R196 0
99 TPB+ 2
U14
1394 Socket
PCI_C/BE#[0:3]
98 TPB- R195 0 1
MuTIOL PCI_DEVSEL, PCI_FRAME#, PCI_IRDY#

R241 R243 R238 R240
Media I/O PCI_TRDY#, PCI_STOP#, PCI_PAR, PCI_PERR# 56 56 56 56
JS506
GND1,2
Controller 96 TPBIAS1
PCI_SERR#, PCI_REQ1#, 1394_PME#,
C303 C304 C302 R239

SiS961 -PCIRST, PCI_GNT1# 0.01µ 0.01µ 270P 5.1K 1394_GND
R224
PCI_INTC# 0
170

9. Spare Parts List - 1
8575 ID2 14” 8575 ID2 14”
Part Number Description Location(s) Part Number Description Location(s)
541667170031 AK;EN,BOX,8575,UTILITY ONLY 340671600035 HOUSING ASSY;LCD,14",ID-2,8175
343671600014 AL-FOIL;HST-PANEL_15"-XGA,8175 451671710001 HOUSING KIT;ID2,8575
441999900057 BATT ASSY OPTION;LI,9-CELL,8175 346671700021 INSULATOR;REAR,SCREW,8575
442671600001 BATT ASSY;11.1V/6AH,LI,PANASONIC 340671700014 KEYBOARD COVER;ASSY-S,8575
221669940001 BOX;AK,7170 451671700032 LABEL KIT;N-B,8575
342671600007 BRACKET;LCD,14",8175 242671700001 LABEL;AGENCY-GLOBAL,8575
342671600005 BRACKET;LCD,R,14",8175 242600000157 LABEL;BAR CODE,125*65,COMMON
221669950008 CARD BOARD;FRAME,PALLET,7170 242669900009 LABEL;BLANK,60*80MM,7170
221669950006 CARD BOARD;TOP,PALLET,7170 441671710031 LCD ASSY;UNIPAC,XGA,14.1",ID2,85
221671220002 CARTON;NON-BRAND,MSL,8170 451671710052 LCD ME KIT;UNIPAC,XGA,14.1",ID2,
431671710001 CASE KIT;ID2,8575 413000020289 LCD;UB141X01,TFT,14.1",XGA,UNIPA
451671600031 CD ROM ME KIT;8175 416267171901 LT PF OPTION;XGA,14.1",ID2,8575
340671600012 COVER ASSY;DIMM,8175 416267171001 LT PF;UNIPAC,XGA,14.1",ID2,85753
340671600029 COVER ASSY;HDD,8175 526267171002 LTXNX;8575/T4XX/XXX/XXXX/L8D3B
340671600034 COVER ASSY;LCD,14",ID1-2,8175 461671600002 PACKING KIT;N-B,14.1",8175
340671710001 COVER ASSY;SILVER,8575 227671600003 PAD;LCD/KB,ANIT-STATIC,8175
344671600042 COVER;DUMMY,ID1-2,8175 224670830002 PALLET;1250*1080*130,7521N
344671600046 COVER;HINGE,ID1-2,8175 221669950001 PARTITION;AK BOX,7170
344671600043 DUMMY CARD;PCMCIA,8175 221671650008 PARTITION;AK BOX,TOP,8175
227671600001 END CAP;14.1",8175 221671650005 PARTITION;BATT,AK BOX,8175
451671600051 HDD ME KIT;8175 221671650006 PARTITION;FDD,AK BOK,BTM,8175
340671600020 HINGE;L,14",8175 221671650004 PARTITION;FDD,AK BOX,8175
340671600018 HINGE;R,14",8175 221671250003 PARTITION;PALLET,8170
340671700002 HOUSING ASSY;8575 221671650007 PARTITION;SIDE,AK BOX,8175
340671600039 HOUSING ASSY;CDROM,8175 222668820001 PE BAG;ANTI-STATIC,170x270MM,ORC
171

8575 ID2 14” 8575 ID2 15”
370102610401 SPC-SCREW;M2.6L4,K-HD,t0.8,NIB/N 541667170001 AK;01-EN,BOX,8575
370102610801 SPC-SCREW;M2.6L8,NIB,K-HD,t=1.1, 441999900057 BATT ASSY OPTION;LI,9-CELL,8175
421671600006 WIRE ASSY;LCD,UNIPAC,14",XGA,817 442671600001 BATT ASSY;11.1V/6AH,LI,PANASONIC
P/N:526267171002 340671600026 BEZEL ASSY;DVD-ROM,QUANTA,8175
221671640001 BOX;AK,8175
342671600006 BRACKET;LCD,L,15",8175
342671600004 BRACKET;LCD,R,15",8175
221669950008 CARD BOARD;FRAME,PALLET,7170
221669950006 CARD BOARD;TOP,PALLET,7170
221671220002 CARTON;NON-BRAND,MSL,8170
431671710001 CASE KIT;ID2,8575
451671600031 CD ROM ME KIT;8175
340671600012 COVER ASSY;DIMM,8175
340671600029 COVER ASSY;HDD,8175
340671600032 COVER ASSY;LCD,15",ID1-2,8175
340671710001 COVER ASSY;SILVER,8575
344671600042 COVER;DUMMY,ID1-2,8175
344671600046 COVER;HINGE,ID1-2,8175
323760000011 DDR SODIMM MODULE;256MB,77.10621
344671600043 DUMMY CARD;PCMCIA,8175
523430061901 DVD DRIVE;8X,SDR-081,H=12.7,QUAN
523467160014 DVD ROM ASSY;8X,SDR-081,QUANTA,8
227671600002 END CAP;15.1",8175
523411442518 FD DRIVE;1.44M,3.5",D353FUE,MITS
345671700006 GASKET;BRACKET LCD,8575
172

8575 ID2 15” 8575 ID2 15”
523401634007 HD DRIVE;30GB,2.5",IC25N030ATCS0 561567176001 MANUAL KIT;EN,8575,N-B
523467170009 HDD ASSY;30G,2.5",9.5MM,8575 561567170001 MANUAL;USER'S,EN,8575,N-B
523499990099 HDD DRIVE OPTION;30G,2.5",9.5MM, 461671600010 PACKING KIT;N-B,15",8175
451671600051 HDD ME KIT;8175 227671600003 PAD;LCD/KB,ANIT-STATIC,8175
340671600019 HINGE;L,15",8175 224670830002 PALLET;1250*1080*130,7521N
340671600017 HINGE;R,15",8175 221671650001 PARTITION;AK BOX,8175
340671700002 HOUSING ASSY;8575 221671650008 PARTITION;AK BOX,TOP,8175
340671600039 HOUSING ASSY;CDROM,8175 221671650005 PARTITION;BATT,AK BOX,8175
340671700011 HOUSING ASSY;LCD,HANSTAR,SILVER, 221671650006 PARTITION;FDD,AK BOK,BTM,8175
451671710001 HOUSING KIT;ID2,8575 221671650004 PARTITION;FDD,AK BOX,8175
324180786126 IC;CPU,P4-WILLAMETTE,1.7G,U-FCPG 221671250003 PARTITION;PALLET,8170
346671700008 INSULATOR;CABLE LCD,8575 221671650007 PARTITION;SIDE,AK BOX,8175
346671700021 INSULATOR;REAR,SCREW,8575 222668820001 PE BAG;ANTI-STATIC,170x270MM,ORC
531099990128 KBD OPTION;86,US,8175 332810000033 PWR CORD;125V/7A,2P,BLACK,AMERIC
531020237342 KBD;86,US,K000918I1,8175 565180626001 S/W;CD*1,DVD,WIN-DVD,INTERVIDEO
340671700014 KEYBOARD COVER;ASSY-S,8575 561860000022 SINGLE PAGE;GN,NOTE FOR BATTERY&
451671700032 LABEL KIT;N-B,8575 370101714501 SPC-SCREW;M1.7L4.5,NIB,K-HEAD
242671700001 LABEL;AGENCY-GLOBAL,8575 370102610401 SPC-SCREW;M2.6L4,K-HD,t0.8,NIB/N
242600000157 LABEL;BAR CODE,125*65,COMMON 370102610801 SPC-SCREW;M2.6L8,NIB,K-HD,t=1.1,
242669900009 LABEL;BLANK,60*80MM,7170 421671600004 WIRE ASSY;LCD,HANN,15",XGA,8175
441671710035 LCD ASSY;HANNSTAR,XGA,15.1",ID2, P/N: 526267171001
451671710054 LCD ME KIT;HANNSTAR,XGA,15.1",ID
413000020296 LCD;HSD150PX11-A,TFT,15",XGA,HAN
416267171004 LT PF;HANNSTAR,XGA,15.1",ID2,857
526267171001 LTXNT;8575/5RCI/30C/1US1/L9D3B/X
173

8575 ID3 14” 8575 ID3 14”
541667170004 AK;04-EU,BOX,8575 340671720011 HOUSING ASSY;CDROM,ID3,8575
343671600014 AL-FOIL;HST-PANEL_15"-XGA,8175 340671720007 HOUSING ASSY;ID3,8575
441999900065 BATT ASSY OPTION;LI-ION,2000mAH 340671720003 HOUSING ASSY;LCD,14",ID3,8575
442671700003 BATT ASSY;11.1V/6AH,LI,ID3,MSL,8 451671720001 HOUSING KIT;ID3,8575
221671640001 BOX;AK,8175 346671720002 INSULATOR;REAR,SCREW,ID3,8575
342671600003 BRACKET;HDD,8175 451671720032 LABEL KIT;N-B,8575 ID3
342671600007 BRACKET;LCD,14",8175 242671720002 LABEL;AGENCY-GLOBAL,ID3,8575
342671600005 BRACKET;LCD,R,14",8175 242600000088 LABEL;BAR CODE,125*65,COMMON
221671650011 CARTON;5 IN 1,8175 242669900009 LABEL;BLANK,60*80MM,7170
431671720001 CASE KIT;ID3,8575 441671720031 LCD ASSY;UNIPAC,XGA,14.1",ID3,85
451671720091 CD-ROM ME KIT;TEAC,ID3,8575 451671720052 LCD ME KIT;UNIPAC,XGA,14.1",ID3,
340671720008 COVER ASSY;DIMM,ID3,8575 413000020289 LCD;UB141X01,TFT,14.1",XGA,UNIPA
340671720001 COVER ASSY;ID3,8575 416267172901 LT PF OPTION;XGA,14.1",ID3,8575
340671720004 COVER ASSY;KB,ID3,8575 416267172001 LT PF;UNIPAC,XGA,14.1",ID3,8575
340671720010 COVER ASSY;LCD,14",ID3,8575 526267172004 LTXNX;8575/T4XX/XXX/3XX9/L9I33/X
344671720002 COVER;DUMMY,ID3,8575 561567176003 MANUAL KIT;EU,8575,N-B
344671720013 COVER;HDD,ID3,8575 561567170001 MANUAL;USER'S,EN,8575,N-B
344671720023 COVER;HINGE,ID3,8575 561567170003 MANUAL;USER'S,EU,8575,N-B
344670500042 DUMMY CARD;PCMCIA,TETRA 461671600018 PACKING KIT;N-B,5 IN 1,8175
227671600005 END CAP;5 IN 1,LOWER,8175 221671650001 PARTITION;AK BOX,8175
227671600004 END CAP;5 IN 1,UPPER,8175 221671650008 PARTITION;AK BOX,TOP,8175
345671600018 GASKET;HEATSINK,K/B_PLATE,8175 221671650005 PARTITION;BATT,AK BOX,8175
451671720071 HDD ME KIT;ID3,8575 221671650006 PARTITION;FDD,AK BOK,BTM,8175
340671600020 HINGE;L,14",8175 221671650004 PARTITION;FDD,AK BOX,8175
340671600018 HINGE;R,14",8175 221671650007 PARTITION;SIDE,AK BOX,8175
174

8575 ID3 14” 8575 ID3 15”
222668820001 PE BAG;ANTI-STATIC,170x270MM,ORC 541667170004 AK;04-EU,BOX,8575
332810000034 PWR CORD;250V/2.5A,2P,BLK,EU,175 346671600021 AL-FOIL;CONDUCTIVE,LCD-SAM_XGA,8
561860000022 SINGLE PAGE;GN,NOTE FOR BATTERY& 441999900065 BATT ASSY OPTION;LI-ION,2000mAH
370102610401 SPC-SCREW;M2.6L4,K-HD,t0.8,NIB/N 442671700003 BATT ASSY;11.1V/6AH,LI,ID3,MSL,8
370102610405 SPC-SCREW;M2.6L4,NIW,K-HD,t=0.8, 221671640001 BOX;AK,8175
370102610805 SPC-SCREW;M2.6L8,K-HD,NIW/NLK 342671600003 BRACKET;HDD,8175
370102010302 SPC-SCREW;M2L3,NIW,K-HD,736 342671600006 BRACKET;LCD,L,15",8175
421671600006 WIRE ASSY;LCD,UNIPAC,14",XGA,817 342671600004 BRACKET;LCD,R,15",8175
P/N: 526267172004 221671650011 CARTON;5 IN 1,8175
431671720001 CASE KIT;ID3,8575
451671720091 CD-ROM ME KIT;TEAC,ID3,8575
340671720008 COVER ASSY;DIMM,ID3,8575
340671720001 COVER ASSY;ID3,8575
340671720004 COVER ASSY;KB,ID3,8575
340671720009 COVER ASSY;LCD,15",ID3,8575
344671720002 COVER;DUMMY,ID3,8575
344671720013 COVER;HDD,ID3,8575
344671720023 COVER;HINGE,ID3,8575
344670500042 DUMMY CARD;PCMCIA,TETRA
227671600005 END CAP;5 IN 1,LOWER,8175
227671600004 END CAP;5 IN 1,UPPER,8175
345671600018 GASKET;HEATSINK,K/B_PLATE,8175
451671720071 HDD ME KIT;ID3,8575
340671600019 HINGE;L,15",8175
340671600017 HINGE;R,15",8175
175

8575 ID3 15” 8575 ID3 15”
340671720011 HOUSING ASSY;CDROM,ID3,8575 222668820001 PE BAG;ANTI-STATIC,170x270MM,ORC
340671720007 HOUSING ASSY;ID3,8575 332810000034 PWR CORD;250V/2.5A,2P,BLK,EU,175
340671720002 HOUSING ASSY;LCD,15",ID3,8575 561860000022 SINGLE PAGE;GN,NOTE FOR BATTERY&
451671720001 HOUSING KIT;ID3,8575 370102610405 SPC-SCREW;M2.6L4,NIW,K-HD,t=0.8,
346671720002 INSULATOR;REAR,SCREW,ID3,8575 370102610805 SPC-SCREW;M2.6L8,K-HD,NIW/NLK
451671720032 LABEL KIT;N-B,8575 ID3 370102010302 SPC-SCREW;M2L3,NIW,K-HD,736
242671720002 LABEL;AGENCY-GLOBAL,ID3,8575 421671600002 WIRE ASSY;LCD,SAM,15",XGA,8175
242600000088 LABEL;BAR CODE,125*65,COMMON P/N: 526267172003
242669900009 LABEL;BLANK,60*80MM,7170
441671720034 LCD ASSY;SAMSUNG,XGA,15.1",ID3,8
451671720053 LCD ME KIT;SAMSUNG,XGA,15.1",ID3
413000020265 LCD;LT150X3-124,TFT,15",LVDS,XGA
416267172902 LT PF OPTION;XGA,15",ID3,8575
416267172003 LT PF;SAMSUNG,XGA,15.1",ID3,8575
526267172003 LTXNX;8575/T5XX/XXX/3XX9/L9I33/X
561567176003 MANUAL KIT;EU,8575,N-B
561567170001 MANUAL;USER'S,EN,8575,N-B
561567170003 MANUAL;USER'S,EU,8575,N-B
461671600018 PACKING KIT;N-B,5 IN 1,8175
221671650001 PARTITION;AK BOX,8175
221671650008 PARTITION;AK BOX,TOP,8175
221671650005 PARTITION;BATT,AK BOX,8175
221671650006 PARTITION;FDD,AK BOK,BTM,8175
221671650004 PARTITION;FDD,AK BOX,8175
221671650007 PARTITION;SIDE,AK BOX,8175
176

8575 ID4 14” 8575 ID4 14”
541667170001 AK;01-EN,BOX,8575 523401634007 HD DRIVE;30GB,2.5",IC25N030ATCS0
441999900062 BATT ASSY OPTION;LI,9-CELL,8575 523467170009 HDD ASSY;30G,2.5",9.5MM,8575
442671700002 BATT ASSY;11.1V/6AH,LI,MSL,8575 523499990099 HDD DRIVE OPTION;30G,2.5",9.5MM,
340671600026 BEZEL ASSY;DVD-ROM,QUANTA,8175 451671600051 HDD ME KIT;8175
221671640001 BOX;AK,8175 340671600020 HINGE;L,14",8175
342671600007 BRACKET;LCD,14",8175 340671600018 HINGE;R,14",8175
342671600005 BRACKET;LCD,R,14",8175 340671700002 HOUSING ASSY;8575
221669950008 CARD BOARD;FRAME,PALLET,7170 340671600039 HOUSING ASSY;CDROM,8175
221669950006 CARD BOARD;TOP,PALLET,7170 340671730002 HOUSING ASSY;LCD,14",ID4,8575
221671220002 CARTON;NON-BRAND,MSL,8170 451671700001 HOUSING KIT;8575
431671700001 CASE KIT;8575 324180786126 IC;CPU,P4-WILLAMETTE,1.7G,U-FCPG
451671600031 CD ROM ME KIT;8175 346671700021 INSULATOR;REAR,SCREW,8575
340671700001 COVER ASSY;8575 531099990128 KBD OPTION;86,US,8175
340671600012 COVER ASSY;DIMM,8175 531020237342 KBD;86,US,K000918I1,8175
340671600029 COVER ASSY;HDD,8175 340671700015 KEYBOARD COVER;ASSY-B,8575
340671600022 COVER ASSY;LCD,14",8175 451671700032 LABEL KIT;N-B,8575
344671600010 COVER;DUMMY,8175 242671700001 LABEL;AGENCY-GLOBAL,8575
344671600011 COVER;HINGE,8175
242600000157 LABEL;BAR CODE,125*65,COMMON
323760000011 DDR SODIMM MODULE;256MB,77.10621
242669900009 LABEL;BLANK,60*80MM,7170
344671600043 DUMMY CARD;PCMCIA,8175
441671730005 LCD ASSY;QDI,XGA,14.1",ID4,8575
523430061901 DVD DRIVE;8X,SDR-081,H=12.7,QUAN
451671730005 LCD ME KIT;QDI,XGA,14.1",ID4,857
523467160014 DVD ROM ASSY;8X,SDR-081,QUANTA,8
413000020304 LCD;QD141X1LH03,TFT,14.1",LCDS,X
227671600001 END CAP;14.1",8175
416267173006 LT PF;QDI,XGA,14.1",ID4,8575
523411442518 FD DRIVE;1.44M,3.5",D353FUE,MITS
526267173009 LTXNT;8575/4QCI/30C/1US1/L9D3D/X
345671600018 GASKET;HEATSINK,K/B_PLATE,8175
561567176001 MANUAL KIT;EN,8575,N-B
177

8575 ID4 14” 8575 ID4 15”
561567170001 MANUAL;USER'S,EN,8575,N-B 541667170004 AK;04-EU,BOX,8575
461671600002 PACKING KIT;N-B,14.1",8175 346671600021 AL-FOIL;CONDUCTIVE,LCD-SAM_XGA,8
227671600003 PAD;LCD/KB,ANIT-STATIC,8175 441999900062 BATT ASSY OPTION;LI,9-CELL,8575
224670830002 PALLET;1250*1080*130,7521N 442671700002 BATT ASSY;11.1V/6AH,LI,MSL,8575
221671650001 PARTITION;AK BOX,8175 221671640001 BOX;AK,8175
221671650008 PARTITION;AK BOX,TOP,8175 342671600006 BRACKET;LCD,L,15",8175
221671650005 PARTITION;BATT,AK BOX,8175 342671600004 BRACKET;LCD,R,15",8175
221671650006 PARTITION;FDD,AK BOK,BTM,8175 221671650011 CARTON;5 IN 1,8175
221671650004 PARTITION;FDD,AK BOX,8175 431671700001 CASE KIT;8575
221671250003 PARTITION;PALLET,8170 451671600031 CD ROM ME KIT;8175
221671650007 PARTITION;SIDE,AK BOX,8175 340671700001 COVER ASSY;8575
222668820001 PE BAG;ANTI-STATIC,170x270MM,ORC 340671600012 COVER ASSY;DIMM,8175
332810000033 PWR CORD;125V/7A,2P,BLACK,AMERIC 340671600029 COVER ASSY;HDD,8175
565180626001 S/W;CD*1,DVD,WIN-DVD,INTERVIDEO 340671600021 COVER ASSY;LCD,15",8175
561860000022 SINGLE PAGE;GN,NOTE FOR BATTERY& 344671600010 COVER;DUMMY,8175
370101714501 SPC-SCREW;M1.7L4.5,NIB,K-HEAD 344671600011 COVER;HINGE,8175
370102610401 SPC-SCREW;M2.6L4,K-HD,t0.8,NIB/N 344671600043 DUMMY CARD;PCMCIA,8175
370102610801 SPC-SCREW;M2.6L8,NIB,K-HD,t=1.1, 227671600005 END CAP;5 IN 1,LOWER,8175
421671600006 WIRE ASSY;LCD,UNIPAC,14",XGA,817 227671600004 END CAP;5 IN 1,UPPER,8175
P/N: 526267173009 345671600018 GASKET;HEATSINK,K/B_PLATE,8175
451671600051 HDD ME KIT;8175
340671600019 HINGE;L,15",8175
340671600017 HINGE;R,15",8175
340671700002 HOUSING ASSY;8575
340671600039 HOUSING ASSY;CDROM,8175
178

8575 ID4 15” 8575 ID4 15”
340671730001 HOUSING ASSY;LCD,15",ID4,8575 332810000034 PWR CORD;250V/2.5A,2P,BLK,EU,175
451671700001 HOUSING KIT;8575 561860000022 SINGLE PAGE;GN,NOTE FOR BATTERY&
346671700021 INSULATOR;REAR,SCREW,8575 370102610401 SPC-SCREW;M2.6L4,K-HD,t0.8,NIB/N
340671700015 KEYBOARD COVER;ASSY-B,8575 370102610801 SPC-SCREW;M2.6L8,NIB,K-HD,t=1.1,
451671700032 LABEL KIT;N-B,8575 421671600002 WIRE ASSY;LCD,SAM,15",XGA,8175
242671700001 LABEL;AGENCY-GLOBAL,8575 P/N: 526267173005
242669900009 LABEL;BLANK,60*80MM,7170
441671730001 LCD ASSY;SAMSUNG,XGA,15”,ID4,85
451671730001 LCD ME KIT;SAMSUNG,XGA,15”,ID4,
526267173005 LTXNX;8575/T5XX/XXX/3XX9/L9I3D/X
561567176003 MANUAL KIT;EU,8575,N-B
561567170003 MANUAL;USER'S,EU,8575,N-B
416267173902 NB PF OPTION;XGA,15",ID4,8575
461671600018 PACKING KIT;N-B,5 IN 1,8175
221671650001 PARTITION;AK BOX,8175
221671650008 PARTITION;AK BOX,TOP,8175
221671650005 PARTITION;BATT,AK BOX,8175
221671650006 PARTITION;FDD,AK BOK,BTM,8175
221671650004 PARTITION;FDD,AK BOX,8175
221671650007 PARTITION;SIDE,AK BOX,8175
222668820001 PE BAG;ANTI-STATIC,170x270MM,ORC
179

8575 ID5 14” 8575 ID5 14”
541667170001 AK;01-EN,BOX,8575 523401634007 HD DRIVE;30GB,2.5",IC25N030ATCS0
343671600014 AL-FOIL;HST-PANEL_15"-XGA,8175 523467170009 HDD ASSY;30G,2.5",9.5MM,8575
441999900062 BATT ASSY OPTION;LI,9-CELL,8575 523499990099 HDD DRIVE OPTION;30G,2.5",9.5MM,
442671700002 BATT ASSY;11.1V/6AH,LI,MSL,8575 451671600051 HDD ME KIT;8175
340671600026 BEZEL ASSY;DVD-ROM,QUANTA,8175 340671600020 HINGE;L,14",8175
221671640001 BOX;AK,8175 340671600018 HINGE;R,14",8175
342671600007 BRACKET;LCD,14",8175 340671700002 HOUSING ASSY;8575
342671600005 BRACKET;LCD,R,14",8175 340671600039 HOUSING ASSY;CDROM,8175
221669950008 CARD BOARD;FRAME,PALLET,7170 340671740002 HOUSING ASSY;LCD,14",ID5,8575
221669950006 CARD BOARD;TOP,PALLET,7170 451671710001 HOUSING KIT;ID2,8575
221671220002 CARTON;NON-BRAND,MSL,8170 324180786126 IC;CPU,P4-WILLAMETTE,1.7G,U-FCPG
431671710001 CASE KIT;ID2,8575 346671700021 INSULATOR;REAR,SCREW,8575
451671600031 CD ROM ME KIT;8175 531099990128 KBD OPTION;86,US,8175
340671600012 COVER ASSY;DIMM,8175 531020237342 KBD;86,US,K000918I1,8175
340671600029 COVER ASSY;HDD,8175 340671700014 KEYBOARD COVER;ASSY-S,8575
340671600034 COVER ASSY;LCD,14",ID1-2,8175 451671700032 LABEL KIT;N-B,8575
340671710001 COVER ASSY;SILVER,8575 242671700001 LABEL;AGENCY-GLOBAL,8575
344671600042 COVER;DUMMY,ID1-2,8175 242600000157 LABEL;BAR CODE,125*65,COMMON
344671600046 COVER;HINGE,ID1-2,8175 242669900009 LABEL;BLANK,60*80MM,7170
323760000011 DDR SODIMM MODULE;256MB,77.10621 441671740005 LCD ASSY;QDI,XGA,14.1",ID5,8575
344671600043 DUMMY CARD;PCMCIA,8175 451671740005 LCD ME KIT;QDI,XGA,14.1",ID5,857
523430061901 DVD DRIVE;8X,SDR-081,H=12.7,QUAN 413000020304 LCD;QD141X1LH03,TFT,14.1",LCDS,X
523467160014 DVD ROM ASSY;8X,SDR-081,QUANTA,8 416267174006 LT PF;QDI,XGA,14.1",ID5,8575
227671600001 END CAP;14.1",8175 526267174007 LTXNT;8575/4QCI/30C/1US1/L9D3E/X
523411442518 FD DRIVE;1.44M,3.5",D353FUE,MITS 561567170001 MANUAL;USER'S,EN,8575,N-B
180

8575 ID5 14” 8575 ID5 15”
461671600002 PACKING KIT;N-B,14.1",8175 541667170002 AK;02-EN,BAG,8575
227671600003 PAD;LCD/KB,ANIT-STATIC,8175 346671600021 AL-FOIL;CONDUCTIVE,LCD-SAM_XGA,8
224670830002 PALLET;1250*1080*130,7521N 441999900062 BATT ASSY OPTION;LI,9-CELL,8575
221671650001 PARTITION;AK BOX,8175 442671700002 BATT ASSY;11.1V/6AH,LI,MSL,8575
221671650008 PARTITION;AK BOX,TOP,8175 342671600006 BRACKET;LCD,L,15",8175
221671650005 PARTITION;BATT,AK BOX,8175 342671600004 BRACKET;LCD,R,15",8175
221671650006 PARTITION;FDD,AK BOK,BTM,8175 221669950008 CARD BOARD;FRAME,PALLET,7170
221671650004 PARTITION;FDD,AK BOX,8175 221669950006 CARD BOARD;TOP,PALLET,7170
221671250003 PARTITION;PALLET,8170 220671600002 CARRY BAG;N-B,8175
221671650007 PARTITION;SIDE,AK BOX,8175 221671220002 CARTON;NON-BRAND,MSL,8170
222668820001 PE BAG;ANTI-STATIC,170x270MM,ORC 431671710001 CASE KIT;ID2,8575
332810000033 PWR CORD;125V/7A,2P,BLACK,AMERIC 451671600031 CD ROM ME KIT;8175
565180626001 S/W;CD*1,DVD,WIN-DVD,INTERVIDEO 340671600012 COVER ASSY;DIMM,8175
561860000022 SINGLE PAGE;GN,NOTE FOR BATTERY& 340671600029 COVER ASSY;HDD,8175
370101714501 SPC-SCREW;M1.7L4.5,NIB,K-HEAD 340671600032 COVER ASSY;LCD,15",ID1-2,8175
370102610401 SPC-SCREW;M2.6L4,K-HD,t0.8,NIB/N 340671710001 COVER ASSY;SILVER,8575
370102610801 SPC-SCREW;M2.6L8,NIB,K-HD,t=1.1, 344671600042 COVER;DUMMY,ID1-2,8175
421671600006 WIRE ASSY;LCD,UNIPAC,14",XGA,817 344671600046 COVER;HINGE,ID1-2,8175
P/N: 526267174007 344671600043 DUMMY CARD;PCMCIA,8175

523499995047 DVD COMBO ASSY OPTION;8175
523467170003 DVD-COMBO ASSY;UJDA720MT-B,8575
523408619025 DVD-COMBO DRIVE;UJDA720,8175
227671600002 END CAP;15.1",8175
227669900007 END CAP;IN BAG,7170
451671600051 HDD ME KIT;8175
181

8575 ID5 15” 8575 ID5 15”
340671600019 HINGE;L,15",8175 221671250003 PARTITION;PALLET,8170
340671600017 HINGE;R,15",8175 222668820004 PE BUBBLE BAG;190X190MM,ANTI-STA
340671700002 HOUSING ASSY;8575 332810000033 PWR CORD;125V/7A,2P,BLACK,AMERIC
340671600039 HOUSING ASSY;CDROM,8175 565180626001 S/W;CD*1,DVD,WIN-DVD,INTERVIDEO
340671740001 HOUSING ASSY;LCD 15",ID5,8575 565167000013 S/W;CD-ROM,B'S RECORDER GOLD2.0
451671710001 HOUSING KIT;ID2,8575 561860000022 SINGLE PAGE;GN,NOTE FOR BATTERY&
346671700021 INSULATOR;REAR,SCREW,8575 370102610401 SPC-SCREW;M2.6L4,K-HD,t0.8,NIB/N
531099990133 KBD OPTION;87,FR,8175 370102610801 SPC-SCREW;M2.6L8,NIB,K-HD,t=1.1,
531020237350 KBD;87,FR,K000918J1,8175 421671600002 WIRE ASSY;LCD,SAM,15",XGA,8175
340671700014 KEYBOARD COVER;ASSY-S,8575 P/N: 526267174002
451671700032 LABEL KIT;N-B,8575
242671700001 LABEL;AGENCY-GLOBAL,8575
441671740001 LCD ASSY;SAMSUNG,XGA,15.1",ID5,8
451671740001 LCD ME KIT;SAMSUNG,XGA,15.1",ID5
526267174002 LTXNX;8575/T5XX/XXK/3FR9/L9C3E/X
416267174902 NB PF OPTION;XGA,15",ID5,8575
461671600012 PACKING KIT;N-B,BAG,15",8175
227671600003 PAD;LCD/KB,ANIT-STATIC,8175
224670830002 PALLET;1250*1080*130,7521N
221671250002 PARTITION;CARRY BAG,8170
221671250001 PARTITION;IN BAG,8170
182

8575-ID2/ID3/ID4/ID5 Common Spare Parts
441999900205 AC ADPT ASSY OPTION;8575 272075101401 CAP;100P ,50V ,10%,0603,COG,SMT C4,C7
442671200004 AC ADPT ASSY;19V/4.74A,DELTA,817 272075101401 CAP;100P ,50V ,10%,0603,COG,SMT C1,C122,C126,C37,C579,C78
541667170032 AK;EN,8575,UTILITY ONLY 272075100701 CAP;10P ,50V ,+-10%,0603,NPO,SM C196,C227,C246,C41,C43,C7
346671700016 AL-FOIL;HDD,M/B,8575 272075100302 CAP;10P ,CR,50V ,5%,0603,NPO,SM C701,C702
242670800113 BFM-WORLD MARK;WINXP,7521N 272021106501 CAP;10U ,10V ,20%,1210,X7R,SMT PC31
340671600028 BRACKET ASSY;T/P,INSULATOR,8175 272021106501 CAP;10U ,10V ,20%,1210,X7R,SMT C100,C132,C133
421015560001 CABLE ASSY;PHONE LINE,6P2C,W/Z C 272011106701 CAP;10U ,10V,+80-20%,1206,Y5V,S C10,C12,C14,C15,C16,C18,C1
272072153401 CAP;.015U ,CR,16V,10%,0603,X7R,S C152,C154,C172,C192 272012106701 CAP;10U ,16V ,+80-20%,1206,Y5U, C531,PC21
272075103702 CAP;.01U ,50V,+80-20%,0603,SMT C212,C213,C232,C26,C265,C 272012106701 CAP;10U ,16V ,+80-20%,1206,Y5U, C698,PC24,PC27,PC533,PC54
272075103401 CAP;.01U ,CR,50V ,10%,0603,X7R,S PC16,PC20,PC27,PC541 272022106701 CAP;10U ,16V,+80-20%,1210,Y5V,S PC1,PC2
272075103401 CAP;.01U ,CR,50V ,10%,0603,X7R,S PC525,PC551 272023106501 CAP;10U ,25V ,20%,1210,Y5U,SMT PC546,PC577
272005103401 CAP;.01U ,CR,50V,10%,0805,X7R PC519 272073151301 CAP;150P ,CR,25V,5% ,0603,NPO,SM PC9
272005103401 CAP;.01U ,CR,50V,10%,0805,X7R PC501,PC583 272073151301 CAP;150P ,CR,25V,5% ,0603,NPO,SM PC573
272073223401 CAP;.022U,CR,25V ,10%,0603,X7R,S PC10 272431157507 CAP;150U ,TPC,6.3V,20%,H1.9,7343 PC12,PC30
272072104702 CAP;.1U ,16V,+80-20%,0603,SMT C143,C144,C145,C146,C147,C 272431157507 CAP;150U ,TPC,6.3V,20%,H1.9,7343 C17,C9,PC524,PC531,PC547,
272073104701 CAP;.1U ,25V,+80-20%,0603,Y5V,S PC4,PC502 272431157508 CAP;150U ,UE,6.3V ,20%,7343,SP-C PC29
272075104701 CAP;.1U ,50V,+80-20%,0603,SMT C504,C506,C512,C513,C517,C 272075150301 CAP;15P ,CR,50V ,5% ,0603,NPO,S C291
272075104701 CAP;.1U ,50V,+80-20%,0603,SMT C106,C107,C108,C110,C111,C 272071105701 CAP;1U ,CR,10V ,80-20%,0603,Y5 C10,C3,C509,C8
272072104402 CAP;.1U ,CR,16V,10%,0603,X7R,SM PC542,PC572 272071105701 CAP;1U ,CR,10V ,80-20%,0603,Y5 C136,C137,C138,C139,C140,C
272003104701 CAP;.1U ,CR,25V ,+80-20%,0805,Y C803,C805,PC22,PC23,PC25, 272001105402 CAP;1U ,CR,10V,10%,0805,X5R,SM PC5
272075102701 CAP;1000P,50V ,+/-20%,0603,X7R,S C101,C130,C151,C153,C155,C 272003105701 CAP;1U ,CR,25V ,+80%-20%,0805, PC550
272030102405 CAP;1000P,CR,3KV,10%,1808,X7R,TU C501,C502,C577 272002105701 CAP;1U ,CR,16V ,-20+80%,0805,Y5 C521,C546,PC566
272075102403 CAP;1000P,CR,50V,10%,0603,X7R,SM C1,C11,C534,C9,PC13,PC23,P 272002225701 CAP;2.2U ,CR,16V ,+80-20%,0805,Y C283,C788,C804,C806
272075102403 CAP;1000P,CR,50V,10%,0603,X7R,SM PC28,PC29,PC521,PC527,PC 272012225702 CAP;2.2U ,CR,16V ,+80-20%,1206,Y C522
272075101701 CAP;100P ,50V ,+ -10%,0603,NPO,S PC22 272012225702 CAP;2.2U ,CR,16V ,+80-20%,1206,Y C714
183


272075200302 CAP;20P ,CR,50V ,5% ,0603,SMT C290 291000153006 CON;FPC/FFC,15P*2,.8MM,BD/BD,ST, J18
272075222701 CAP;2200P,50V ,+/-20%,0603,X7R,S C23,PC548,PC562 291000144004 CON;FPC/FFC,20P*2,1.0MM,H=4.6,ST J3
272075221302 CAP;220P ,50V ,5% ,0603,NPO,SMT PC18,PC28 291000142404 CON;FPC/FFC,24P,1MM,H8.2,ST,ACES J13
272075221302 CAP;220P ,50V ,5% ,0603,NPO,SMT C519,C520,C549,C550,C798 291000150804 CON;FPC/FFC,8P,1MM,R/A,2CONTAC,E J501
272431227504 CAP;220U ,4V ,20%,7343,POSCAP,SM PC20 331040020004 CON;HDR,FM,10P*2,2.54MM,R/A,H8,4 J4
272075220701 CAP;22P ,50V ,+ -10%,0603,NPO,S C121,C125,C299,C300,C504,C 331030044013 CON;HDR,FM,22*2,2MM,ST,C16805
272075220301 CAP;22P ,50V ,5% ,0603,COG,SMT C610,C651 331040050013 CON;HDR,FM,25P*2,1.27X1.27MM,D/R J7
272021226701 CAP;22U ,10V,+80-20%,1210,Y5V,S C109,C11,C21,C22,C255,C51 291000011024 CON;HDR,FM,5P*2,1.27MM,ST,H4.5,S J501
272075271401 CAP;270P ,50V,+-10%,0603,X7R,SMT C2,C5 331040020005 CON;HDR,MA,10P*2,2.54MM,R/A,H8.4 PJ1
272075271401 CAP;270P ,50V,+-10%,0603,X7R,SMT C302,C38,C81 291000011209 CON;HDR,MA,12P*1,1.25,ST,SMT J6
272075270302 CAP;27P ,50V ,5%,0603,COG,SMT C65,C68 291000024409 CON;HDR,MA,22P*2,2MM,R/A,SMT,ALL J19
272075330401 CAP;33P ,CR,50V ,10%,0603,X7R,S C12,C13 331040050012 CON;HDR,MA,25P*2,1.27X1.27MM,D/R PJ2
272001475701 CAP;4.7U ,CR,10V ,+80-20%,0805,Y C756,C857,C861 291000020202 CON;HDR,MA,2P*1,1.25,R/A,SMT,HIR J508
272012475701 CAP;4.7U ,CR,16V ,+80-20%,1206,Y C273,C648,C699 331040050010 CON;HDR,MA,50P,0.8MM,R/A,H1.1 J12
272075471401 CAP;470P ,50V,10%,0603,X7R,SMT PC19 291000011030 CON;HDR,MA,5P*2,1.27MM,ST,H17,85 J6
272075471401 CAP;470P ,50V,10%,0603,X7R,SMT PC534,PC536,PC541,PC556,P 291000020303 CON;HDR,SHROUD,MA,3P,1.25MM,R/A, J503
272075470701 CAP;47P ,50V ,+ -10%,0603,NPO,S C118,C222,C228 291000256823 CON;IC CARD PART;68P,0.635,H5,SM J11
272431476502 CAP;47U ,6.3V,20%,SP-CON,7343,S PC11 331000004018 CON;IEEE1394,MA,4P,.8MM,R/A,LINK J27
272075680302 CAP;68P ,50V ,5% ,0603,NPO,SMT C707,C710 331870004017 CON;MINI DIN,4P,R/A,W/GROND,C108 J1
313000020360 CHOKE COIL;1.25uH,+30-0%,4.5Ts,D PL1,PL2 331870004010 CON;MINI DIN,4P,R/A,W/GROUND,C10
273000111002 CHOKE COIL;120OHM/100MHZ,20%,321 L508,L509,L518,L522 291000810205 CON;PHONE JACK,2P,H=8.4,R/A,SMT J1
273000111002 CHOKE COIL;120OHM/100MHZ,20%,321 L1,L4,L529,L530,L6 291000810802 CON;PHONE JACK,8P,H=12.59,R/A,RJ J9
331000008038 CON;BAT,8P,2.5MM,SUYIN J14 331840010005 CON;POF MINI JACK,10P,W/SPDIF,2F J24
331720015006 CON;D,FM,15P,2.29,R/A,3ROW J2 331910002006 CON;POWER JACK,2P,20VDC,5A,DIP J2
331720025005 CON;D,FM,25P,2.775,R/A J3 331840005013 CON;STEREO JACK,5P,R/A,28MF60-07 J28
184


331000004029 CON;USB,MA,R/A,4P*1,2551A-04G5T- J4,J5,J7,J8 288100020001 DIODE;RLZ20C,ZENER,19.23V,5%,SMT PD511
291000410201 CON;WFR,MA,2P,1.25,ST,SMT/MB J21,J23,J25,J5 288100024002 DIODE;RLZ24D,ZENER,23.63V,5%,SMT PD501
291000410301 CON;WFR,MA,3P,1.25,ST,SMT/MB J8 288100056001 DIODE;RLZ5.6B,ZENER,5.6V,5%,LL34 D10,D5,D508
291000410401 CON;WFR,MA,4P,1.25MM,ST,SMT J502 288100056005 DIODE;UDZ5.6B,ZENER,5.6V,UMD2,SM D516
291000410801 CON;WFR,MA,8P*1,1.25MM,ST,SMT J20 272601107501 EC;100U ,6.3V,20%,D6.3,-40+85'C, C280,C289
313000150093 CORE;LAN CORE,230OHM/100MHZ,LF-1 272602107501 EC;100U,16V,M,6.3*5.5,-55+85'C,S C245
272625220401 CP;22P*4 ,8P,50V ,10%,1206,NPO,S CP501,CP502,CP503,CP504,C 312271006358 EC;100U,25V,RA,M,D6.3*7,SGX,SANY PC25
331660020003 DIMM SOCKET;DDR SODIMM 200P,AMP1 J506 312271006358 EC;100U,25V,RA,M,D6.3*7,SGX,SANY PC15,PC17,PC18
331660020002 DIMM SOCKET;DDR SODIMM200P,AMP13 J505 312271005357 EC;10U,25V,20%,RA,6.3*6.8,+105℃ PC2,PC3
288110355001 DIODE;1SS355,80V,100mA,SOD-23,SM PD503 312271005357 EC;10U,25V,20%,RA,6.3*6.8,+105℃ PC11,PC12,PC14
288100032013 DIODE;BAS32L,VRRM75V,MELF,SOD-80 D501,PD2,PD3,PD515,PD516 312273361501 EC;330U ,6.3V ,RA,M,6.3*7,+105C PC1,PC6
288100032013 DIODE;BAS32L,VRRM75V,MELF,SOD-80 PD506,PD507,PD510,PD7 312304705351 EC;47U,25V,20%,D10X10.5,105'C,SY PC31,PC32,PC33
288100054001 DIODE;BAT54,30V,200mA,SOT-23 D509,D510 312278206152 EC;820U ,4V,+-20%,10X10.5,FPCAP PC3,PC5,PC7,PC9
288100701002 DIODE;BAV70LT1,70V,225MW,SOT-23 D511 481672400002 F/W ASSY;KBD CTRL,SCORPIO U509
288100099001 DIODE;BAV99,70V,450MA,SOT-23 D1,D3,D4,D6 481672400001 F/W ASSY;SYS/VGA BIOS,SCORPIO U10
288100099001 DIODE;BAV99,70V,450MA,SOT-23 PD5,PD8 340671200020 FAN ASSY;8170
288100056003 DIODE;BAW56,70V,215MA,SOT-23 D3,D504 273000610019 FERRITE ARRAY;130OHM/100MHZ,3216 FA501
288100056003 DIODE;BAW56,70V,215MA,SOT-23 D514 273000610019 FERRITE ARRAY;130OHM/100MHZ,3216 FA501
288101004024 DIODE;EC10QS04,RECT,40V,1A,CHIP, PD1,PD4 273000150013 FERRITE CHIP;120OHM/100MHZ,2012, L504,L512,L514,L516,L520,L
288101004024 DIODE;EC10QS04,RECT,40V,1A,CHIP, PD1,PD2 273000150013 FERRITE CHIP;120OHM/100MHZ,2012, L27,L504,L523,L554,PL5,PL5
288100112001 DIODE;EC11FS2,1A,FAST RECOVERY,S PD503,PD504,PD511 273000130039 FERRITE CHIP;130OHM/100MHZ,1608, L1,L4,L513,L515
288100112003 DIODE;EC11FS2-TE12L,SCHOTTKY,200 PD504,PD505 273000130039 FERRITE CHIP;130OHM/100MHZ,1608, L16,L17,L18,L19,L20,L21,L23
288103104001 DIODE;EC31QS04-TE12L,40V,3A,SMT PD505,PD506,PD514 273000150036 FERRITE CHIP;32OHM/100MHZ,2012,S L34,L35,L40,L545,L546,L547
288103104001 DIODE;EC31QS04-TE12L,40V,3A,SMT PD3,PD4,PD501,PD502,PD51 273000130038 FERRITE CHIP;600OHM/100MHZ,1608, L28,L39,L43,L44,L45,L531,L5
288104148001 DIODE;RLS4148,200MA,500MW,MELF,S D11,D14,D15,D16,D17,D513, 422665400002 FFC ASSY;TOUCH PAD,CASE KIT,VENU
185


341671200010 FINGER;EMI GROUND SMD FINGER,H=4 E501,E502 284500201002 IC;ALC201,AC97 CODEC,TQFP,48P U15
341671200010 FINGER;EMI GROUND SMD FINGER,H=4 E511,E518,E519,TP506 286308800006 IC;AME8800AEEV,VOL REG.,SOT23-5, U17
342671700001 FINGER;EMI GROUNDING SMD FINGER E1,E10,E2,E4,E5,E7,E8,E9 286308801002 IC;AME8801MEEV,VOL REG.,SOT23-5, U512
342672400007 FINGER;EMI GROUNDING SMD FINGER E501,E502,E503,E507,E520,E 284508500002 IC;CM8500,3A BUS TERMINATOR,PTSS PU10
288003600001 FIR;HSDL3600#007,FRONT VIEW,10P, U2 283400000003 IC;EEPROM,NM24C02N,2K,SO,8P U7
295000010105 FUSE;1A,NORMAL,1206,SMT F1,F501,F503,F504 283450083001 IC;FLASH,256K*8-70,PLCC32,ST39SF
295000010116 FUSE;FAST, 10A, 86VDC, 6125,SMT PF501 284583437003 IC;H8/F3437S,KBD CTRL,TQFP,100P,
295000010116 FUSE;FAST, 10A, 86VDC, 6125,SMT PF502 286317812001 IC;HA178L12UA,VOLT REGULATOR,SC- PU507
295000010029 FUSE;FAST,.75A,63V,1206,THIN FIL PF501 284501893001 IC;ICS-1893,LAN-PHY,TQFP,64P,SMT U5
345671700009 GASKET;BRACKET T/P,8575 284593722001 IC;ICS93722,DDR ZERO DELAY CLOCK U9
345671700010 GASKET;KB PLATE,8575 284595200101 IC;ICS952001,TIMING CTL HUB FOR U508
345671700011 GASKET;KB PLATE-1,8575 286300811002 IC;IMP811,RESET CIRCUIT,4.38,SOT U515
345671600016 GASKET;LCD-HINGE,8175 286100393004 IC;LMV393,DUAL COMPARTOR,SSOP,8P PU514
345671700019 GASKET;MIC,8575 286302951015 IC;LP2951ACM,VOLTAGE REGULATOR,S U506
345671700004 GASKET;USB,8575 286317099001 IC;LTC1709-9,PWM,QSOP,36P PU508
340671700006 HEATSINK ASSY;N/B,8575 286303707001 IC;LTC3707,PWM SWITCH REG,SOOP,2 PU4
340671700016 HEATSINK ASSY;P4 CPU, 8575 286303707001 IC;LTC3707,PWM SWITCH REG,SOOP,2 PU510
344600000824 IC CARD CON PART;68P,IC11SA-BD-P 286104173001 IC;MAX4173F,I-SENSE AMP,SOT23,6P PU1
291000610032 IC SOCKET;32P,PLCC,TIN,W/O PEGS, U10 286300809002 IC;MAX809S,RESET CIRCUIT,2.9V,SO U12
331650047803 IC SOCKET;BGA-PGA478B-SKT U1 286305258001 IC;MIC 5258-1.2BM5,LV12,LDO REG, U502
282574373004 IC;74AHC373,OCT D-TRAN,TSSOP,20P U8 284501284001 IC;PAC1284-01Q,TERMIN. NETWK,QSO U501,U502
282574186002 IC;74AHCT1G86,SINGLE,XOR,SOT23,S U513 284587393002 IC;PC87393F,TQFP,100P U511
282074338402 IC;74CBTD3384,10 BIT BUS SW,TSOP U11 284501410008 IC;PCI1410AGGU,BGA144P U6
282574164002 IC;74VHC164,SIPO REGISTER,TSSOP, U517 286309701001 IC;RT9701,POWER DISTRI SW,SOT23- U1,U3
284501032001 IC;ADM1032,TEMPERATURE MTR,SO8 U2 286300431014 IC;SC431LCSK-.5,.5%,ADJ REG,SOT2 PQ510
186


284500301004 IC;SIS301LV,TV ENCODER/LVDS,128P U504 242664800013 LABEL;CAUTION,INVERT BD,PITCHING
284500650002 IC;SIS650,N.B.,BGA702 U4 242600000195 LABEL;SOFTWARE,INSYDE BIOS-M
284500961003 IC;SIS961 HM-I/O,S.B.,BGA371 U14 294011200001 LED;GRN,H1.5,0805,PG1102W,SMT D18,D19,D20,D21,D22,D23
286300594001 IC;TL594C,PWM CONTROL,SO,16P PU511 421671600051 MICROPHONE ASSY;8175
286100202001 IC;TPA0202,AUDIO AMP,2W,TSSOP,24 U16 291006212402 MINIPCI SOCKET;124P,0.8MM,H=6,SM J509
286302211001 IC;TPS2211,POWER DISTRI SW,SSOP1 U505 375102030010 NUT-HEX;M2,2,NIW
284572872001 IC;UPD72872;IEEE1394;PQFP120,2PO U18 375120262008 NUT-HEX;M2.6,NCG
273000990012 INDUCTOR;10UH,CDRH127,SUMIDA,SMT PL2 221671250005 PARTITION;HDD CASE,8170
273000990012 INDUCTOR;10UH,CDRH127,SUMIDA,SMT PL4 412155600047 PCB ASSY;MDM,56K,UNIV,F-PACK,WO/
273000990031 INDUCTOR;10UH,CDRH127B,SUMIDA,SM PL3 316671200005 PCB;PWA-8170/ESB BD R01
273000990054 INDUCTOR;10UH,D124C,+/-20%,TOKO, PL3 316671700002 PCB;PWA-8575/DD BD R0B
273000990115 INDUCTOR;3.3uH,3A,CSS054D,SMT PL8 316671700001 PCB;PWA-8575/M BD R0B
273000990021 INDUCTOR;33uH,CDRH124,SMT PL6 316671700003 PCB;PWA-8575/TOUCHPAD BD R00
273000150106 INDUCTOR;4.7UH,10%,2012,SMT L2,L3 222600020049 PE BAG;50*70MM,W/SEAL,COMMON
346671200036 INSULATOR,MDC,8170 222667220003 PE BAG;L560XW345,CERES
346671700001 INSULATOR;AL-FOIL,M/B BOTTOM,857 222670000001 PE BUBBLE BAG;BATTERY,7521
346671700006 INSULATOR;CD-ROM,M-B,8575 273000150033 PHASEOUT;FERRITE CHIP,120OHM/100 L10,L11,L12,L13,L14,L15,L22
346669900004 INSULATOR;INVERTER,7170 343671600006 PLATE;KB,8175
346671600018 INSULATOR;INVERTER,PCB,8175 411671200007 PWA;PWA-8170,ESB BD
346671700007 INSULATOR;MINIPCI,8575 411671700007 PWA;PWA-8575,D/D BD R0A,SMT
346671600015 INSULATOR;PCMCIA,8175 411671700006 PWA;PWA-8575,D/D BD R0A,T/U
242600000145 LABEL;10*10,BLANK,COMMON 411671700010 PWA;PWA-8575,MOTHER R0A BD
242600000145 LABEL;10*10,BLANK,COMMON 411671700013 PWA;PWA-8575,MOTHER R0B BD,SMT
242662300009 LABEL;25*10MM,3020F 411671700014 PWA;PWA-8575,MOTHER R0B BD,T/U
242662300009 LABEL;25*10MM,3020F 411671700009 PWA;PWA-8575,T/P BD
187


411503400201 PWA;PWA-STINGRAY/INVERTER BD,MSL 271071106301 RES;10M ,1/16W,5% ,0603,SMT R189
271046037103 RES;.003,1.5W,1%,2512,SMT PR501,PR503 271071111101 RES;110 ,1/16W,1% ,0603,SMT R20
271046057102 RES;.005,1.5W,1%,2512,SMT PR502,PR504 271071113101 RES;11K ,1/16W,1% ,0603,SMT PR8
271045087101 RES;.008 ,1W ,1% ,2512,SMT PR16 271071113101 RES;11K ,1/16W,1% ,0603,SMT PR530
271045107101 RES;.01 ,1W ,1% ,2512,SMT PR4,PR506 271071121211 RES;12.1K,1/16W,1% ,0603,SMT R578,R731,R732,R733,R734
271045107101 RES;.01 ,1W ,1% ,2512,SMT PR525 271071127211 RES;12.7K,1/16W,1%,0603,SMT PR508
271045157101 RES;.015 ,1W ,1% ,2512,SMT PR515 271071137271 RES;13.7K,1/16W,.1%,0603,SMT PR10,PR558
271586026101 RES;.02 ,2W,1%,2512,SMT PR13 271071131101 RES;130 ,1/16W,1% ,0603,SMT R545
271002000301 RES;0 ,1/10W,5% ,0805,SMT L2 271071134701 RES;130K ,1/16W,0.1% ,0603,SMT PR560
271002000301 RES;0 ,1/10W,5% ,0805,SMT L513 271071147011 RES;147 ,1/16W,1% ,0603,SMT R549
271071000002 RES;0 ,1/16W,0603,SMT PR17,PR522,PR523,R1,R511, 271071151101 RES;150 ,1/16W,1% ,0603,SMT R109,R116,R21,R508,R553,R
271071000002 RES;0 ,1/16W,0603,SMT C305,C723,L538,PR1,PR524, 271071151302 RES;150 ,1/16W,5% ,0603,SMT R503,R504
271071152101 RES;1.5K ,1/16W,1% ,0603,SMT R506,R579 271071153101 RES;15K ,1/16W,1% ,0603,SMT PR13,PR14
271071152302 RES;1.5K ,1/16W,5% ,0603,SMT R64 271071153101 RES;15K ,1/16W,1% ,0603,SMT PR528,PR532,R720,R722
271071100302 RES;10 ,1/16W,5% ,0603,SMT PR3 271071153301 RES;15K ,1/16W,5% ,0603,SMT R502,R503,R504,R505,R508,R
271071100302 RES;10 ,1/16W,5% ,0603,SMT PR514,PR521,R100,R101,R10 271071153301 RES;15K ,1/16W,5% ,0603,SMT R107,R114,R269,R270
271071101101 RES;100 ,1/16W,1% ,0603,SMT R522,R536 271071102102 RES;1K ,1/16W,1% ,0603,SMT PR19,R556,R95
271071101301 RES;100 ,1/16W,5% ,0603,SMT R231,R548,R566,R74,R789,R 271071102302 RES;1K ,1/16W,5% ,0603,SMT PR517
271071104101 RES;100K ,1/16W,1% ,0603,SMT PR557,PR563 271071102302 RES;1K ,1/16W,5% ,0603,SMT PR509,PR537,R1,R174,R194,
271071104302 RES;100K ,1/16W,5% ,0603,SMT PR508,PR518 271071105301 RES;1M ,1/16W,5% ,0603,SMT PR509,PR521,PR6,PR7,R528
271071104302 RES;100K ,1/16W,5% ,0603,SMT PR15,PR3,PR510,PR538,PR5 271071105301 RES;1M ,1/16W,5% ,0603,SMT PR5,PR505,PR539,PR545,PR
271071103101 RES;10K ,1/16W,1% ,0603,SMT PR12,PR19 271071222302 RES;2.2K ,1/16W,5% ,0603,SMT R552,R558,R672,R674
271071103101 RES;10K ,1/16W,1% ,0603,SMT PR507,PR513,PR527,PR540,P 271071249111 RES;2.49K,1/16W,1% ,0603,SMT PR546
271071103302 RES;10K ,1/16W,5% ,0603,SMT R10,R516 271012278101 RES;2.7 ,1/8W,1% ,1206,SMT R14
271071103302 RES;10K ,1/16W,5% ,0603,SMT PR506,R125,R138,R149,R15, 271071272101 RES;2.7K ,1/16W,1% ,0603,SMT PR9
188


271071272101 RES;2.7K ,1/16W,1% ,0603,SMT PR531 271002472301 RES;4.7K ,1/10W,5% ,0805,SMT PR516
271071272301 RES;2.7K ,1/16W,5% ,0603,SMT R86,R87 271071472302 RES;4.7K ,1/16W,5% ,0603,SMT PR14,PR4,PR561,R120,R144,
271071200101 RES;20 ,1/16W,1% ,0603,SMT R544 271071499111 RES;4.99K,1/16W,1% ,0603,SMT PR11
271072201101 RES;200 ,1/10W,1% ,0603,SMT R57 271071471302 RES;470 ,1/16W,5% ,0603,SMT R137,R156,R157,R200,R201,R
271071204101 RES;200K ,1/16W,1% ,0603,SMT PR18 271071474301 RES;470K ,1/16W,5% ,0603,SMT PR507,PR510
271071203701 RES;20K ,1/16W,.1%,0603,SMT PR7 271071474301 RES;470K ,1/16W,5% ,0603,SMT R505,R683,R7
271071203101 RES;20K ,1/16W,1% ,0603,SMT PR12,PR519 271071475011 RES;475 ,1/16W,1% ,0603,SMT R85
271071203302 RES;20K ,1/16W,5% ,0603,SMT R679,R719,R721 271071473301 RES;47K ,1/16W,5% ,0603,SMT R4,R5,R518,R8
271071215211 RES;21.5K,1/16W,1% ,0603,SMT PR526 271071473301 RES;47K ,1/16W,5% ,0603,SMT PR544,R134,R159
271071221302 RES;22 ,1/16W,5% ,0603,SMT R117,R118,R119,R129,R130,R 271071487311 RES;487K ,1/16W,1% ,0603,SMT PR9
271071226311 RES;226K ,1/16W,1% ,0603,SMT PR551 271071499811 RES;49.9 ,1/16W,1% ,0603,SMT R533,R535,R636,R640,R645,R
271071223302 RES;22K ,1/16W,5% ,0603,SMT R49 271071518301 RES;5.1 ,1/16W,5% ,0603,SMT PR17
271071249311 RES;249K ,1/16W,1% ,0603,SMT PR547 271071512101 RES;5.1K ,1/16W,1% ,0603,SMT R239
271071270301 RES;27 ,1/16W,5% ,0603,SMT R509 271071562301 RES;5.6K ,1/16W,5% ,0603,SMT R131,R140
271071202301 RES;2K ,1/16W,5% ,0603,SMT R577,R727,R728,R835 271071510301 RES;51 ,1/16W,5% ,0603,SMT PR2,R512,R513,R514,R515,R
271071301011 RES;301 ,1/16W,1% ,0603,SMT R12,R62 271071511812 RES;51.1,1/16W,1% 0603,SMT R14,R521
271071301311 RES;301K ,1/16W,1% ,0603,SMT PR564 271071513301 RES;51K ,1/16W,5% ,0603,SMT R184
271071324211 RES;32.4K,1/16W,1% ,0603,SMT PR5 271071536211 RES;53.6K,1/16W,1% ,0603,SMT PR18
271071330302 RES;33 ,1/16W,5% ,0603,SMT R9 271071560101 RES;56 ,1/16W,1% ,0603,SMT R41,R46,R605,R676
271071330302 RES;33 ,1/16W,5% ,0603,SMT R16,R166,R167,R171,R172,R 271071560301 RES;56 ,1/16W,5% ,0603,SMT R238,R240,R241,R243,R587,R
271071333301 RES;33K ,1/16W,5% ,0603,SMT R2,R3,R506,R7 271071576311 RES;576K ,1/16W,1% ,0603,SMT PR556
271071333301 RES;33K ,1/16W,5% ,0603,SMT PR16,PR552,R697 271071604111 RES;6.04K,1/16W,1% ,0603,SMT R550
271071390302 RES;39 ,1/16W,5% ,0603,SMT R532 271071619111 RES;6.19K,1/16W,1% ,0603,SMT PR543
271072302301 RES;3K ,1/10W,5% ,0603,SMT R739 271071681111 RES;6.81K,1/16W,1% ,0603,SMT PR522
271071475112 RES;4.75K,1/16W,1% ,0603,SMT PR511 271071682301 RES;6.8K ,1/16W,5% ,0603,SMT R185,R186,R187
189


271071604811 RES;60.4 ,1/16W,1% ,0603,SMT R50 271621473301 RP;47K*8 ,10P,1/16W,5% ,1206,SMT RP513,RP517
271071619811 RES;61.9 ,1/16W,1% ,0603,SMT R27,R30 271611750301 RP;75*4 ,8P ,1/16W,5% ,0612,SMT RP5
271071620102 RES;62,1/16W,1% 0603,SMT R10,R11,R528 271611750301 RP;75*4 ,8P ,1/16W,5% ,0612,SMT RP502
271071681101 RES;680 ,1/16W,1% ,0603,SMT R534 271621822302 RP;8.2K*8,10P,1/32W,5% ,1206,SMT RP37,RP38,RP39
271071750101 RES;75 ,1/16W,1% ,0603,SMT R25,R562 345671600002 RUBBER PAD;LCD,LOWER,8175
271071750302 RES;75 ,1/16W,5% ,0603,SMT R31,R35,R525,R537,R538,R5 345671600001 RUBBER PAD;LCD,UPPER,8175
271071822301 RES;8.2K ,1/16W,5% ,0603,SMT R190 565167170001 S/W;CD ROM,SYSTEM DRIVER,8575
271071806211 RES;80.6K,1/16W,1% ,0603,SMT PR518 340671200013 SCREW ASSY;CPU,8170
271071820301 RES;82 ,1/16W,5% ,0603,SMT R205,R207,R210,R777 340671200014 SCREW ASSY;IC,82845,8170
271071909101 RES;9.09K,1/16W,1% ,0603,SMT R228 371102011502 SCREW;M2L15,FLT(+),NIW/NLK
271071976311 RES;976K ,1/16W,1% ,0603,SMT PR8 340671700007 SHIELDING ASSY;TOP,8575
271611000301 RP;0*4 ,8P ,1/16W,5% ,0612,SMT RP1,RP2,RP3,RP4 341671700001 SHIELDING;AUDIO,8575
271611000301 RP;0*4 ,8P ,1/16W,5% ,0612,SMT RP48,RP501,RP503,RP504,RP 370102610302 SPC-SCREW;M2.6L3,NIB,K-HD,NYLOK
271571000301 RP;0*8 ,16P ,1/16W,5% ,1606,SM RP13,RP14,RP15 370102610603 SPC-SCREW;M2.6L6,K-HD,NIB/NLK
271611100301 RP;10*4 ,8P ,1/16W,5% ,0612,SMT FA502,FA503,FA504,FA505,F 370102610603 SPC-SCREW;M2.6L6,K-HD,NIB/NLK
271571100301 RP;10*8 ,16P ,1/16W,5% ,1606,SM RP10,RP11,RP12,RP16,RP17 370102030301 SPC-SCREW;M2L3,K-HD,1,NIB/NLK
271611103301 RP;10K*4 ,8P ,1/16W,5% ,0612,SMT RP3,RP4,RP40,RP518,RP529 370102030301 SPC-SCREW;M2L3,K-HD,1,NIB/NLK
271611102301 RP;1K*4 ,8P ,1/16W,5% ,0612,SMT RP1 370102030301 SPC-SCREW;M2L3,K-HD,1,NIB/NLK
271621102302 RP;1K*8 ,10P,1/32W,5% ,1206,SMT RP2,RP507 370102030301 SPC-SCREW;M2L3,K-HD,1,NIB/NLK
271611220301 RP;22*4 ,8P ,1/16W,5% ,0612,SMT RP5,RP512,RP6 370102010309 SPC-SCREW;M2L3.0,NIW/NLK,HD07
271611330301 RP;33*4 ,8P ,1/16W,5% ,0612,SMT RP43,RP528 370102010407 SPC-SCREW;M2L4,K-HD,NIB/NLK
271571330301 RP;33*8 ,16P ,1/16W,5% ,1606,SM RP21,RP22,RP23,RP24,RP25 370102010407 SPC-SCREW;M2L4,K-HD,NIB/NLK
271611472301 RP;4.7K*4,8P ,1/16W,5% ,0612,SMT RP36,RP46,RP47,RP511,RP5 370102010606 SPC-SCREW;M2L6,K-HD(t0.2),NIB/NL
271621472303 RP;4.7K*8,10P,1/16W,5% ,1206,SMT RP514,RP519 370103010405 SPC-SCREW;M3L4,NIW,K-HD,T0.3
271621471301 RP;470*4,8P,1/16W,5%,1206,SMT RP7 370103010604 SPC-SCREW;M3L6,NIB,K-HD,t0.8,NYL
190


340671700003 SPEAKER ASSY,L,8575 288204416001 TRANS;Si4416DY,N-MOSFET,.028OHM, PU2,PU5
340671700008 SPEAKER ASSY;R,8575 288204416001 TRANS;Si4416DY,N-MOSFET,.028OHM, PU507,PU509
377244010002 STANDOFF;#4-40DP3.5H5L5.5,NIW 288204425002 TRANS;SI4425DY,PMOS,8.5A/30V,.02 PU502
341668300008 STANDOFF;MDC MODEM,NLK,HOPE 288204425002 TRANS;SI4425DY,PMOS,8.5A/30V,.02 PU512,PU513
297120101007 SW;DIP,SPST,4P,24VDC,.025A,SMT SW503 288204788001 TRANS;SI4788CY,P-MOS,5A1.8~5.5V, PU504,PU505
297040105012 SW;PUSH BUTTOM,4P,SP,12V/50MA,H2 SW502 288204810001 TRANS;SI4810DY,N-MOS,.0155OHM,SO PU3,PU6
297040105012 SW;PUSH BUTTOM,4P,SP,12V/50MA,H2 SW1,SW2,SW3,SW4,SW5,SW6 288204810001 TRANS;SI4810DY,N-MOS,.0155OHM,SO PU7,PU8
297040105010 SW;PUSH BUTTOM,5P,SPST,12V/50MA, SW1,SW2,SW3,SW4 288204835001 TRANS;SI4835DY,PMOS,6A/30V,.035, PQ1
297030102001 SW;TOGGLE,SPST,5V/0.2mA,H10.7MM, SW1 288204925001 TRANS;SI4925DY,P-MOSFET,SO-8 PU9
225600000004 TAPE;DOUBLE SIDE,12MM*15M 288209410001 TRANS;SI9410DY,N-MOSFET,.04OHM,S Q503
345671700002 THERMAL PAD;MOS,8575 288205003004 TRANS;SUD50N03-11,N-MOS,TO252 PU1,PU2,PU4,PU5,PU501,PU
345671700003 THERMAL PAD;SIS301,8575 273001050039 TRANSFORMER;10/100 BASE,LF-H80P, U3
442164900010 TOUCH PAD MODULE;TM41PD-350 271911103906 VR;10K,20%,0.05W,RN101GAC10KPGJ- VR1
288227002001 TRANS;2N7002LT1,N-CHANNEL FET PQ2,PQ501,PQ502,PQ503 421671700002 WIRE ASSY;ANTENNA,8575
288227002001 TRANS;2N7002LT1,N-CHANNEL FET PQ4,PQ501,PQ502,PQ504,PQ 421668300005 WIRE ASSY;BIOS,BATTERY,HOPE J508
288203401001 TRANS;AO3401,P-MOSFET,SOT-23 PQ1 421668300005 WIRE ASSY;BIOS,BATTERY,HOPE J508
288203401001 TRANS;AO3401,P-MOSFET,SOT-23 Q1,Q509,Q511,Q6,Q8 421671600010 WIRE ASSY;INVERT,8175
288200144002 TRANS;DTA144WK,PNP,SMT PQ506,Q529 421671700004 WIRE ASSY;MDC,EMI,8575
288200144003 TRANS;DTC144TKA,N-MOSFET,SOT-23 Q10,Q11,Q17,Q18,Q19,Q2,Q2 421671700001 WIRE ASSY;TOUCHPAD,8575
288200144001 TRANS;DTC144WK,NPN,SOT-23,SMT PQ509,Q20,Q5,Q510,Q9 274011431408 XTAL;14.318M,50PPM,32PF,7*5,4P,S X502
288202222001 TRANS;MMBT2222AL,NPN,TO236AB PQ3 274011431422 XTAL;14.318MHZ,16PF,20PPM,8*4.25 X501
288203904010 TRANS;MMBT3904L,NPN,Tr35NS,TO236 Q15,Q516,Q517 274011600408 XTAL;16MHZ,16PF,50PPM,8*4.5,2P X503
288203906018 TRANS;MMBT3906L,PNP,Tr35NS,TO236 Q14 274012457405 XTAL;24.576M,30PPM,16PF,7*5,4P,S X6
288207002001 TRANS;NDC7002N,N-MOSFET,SSOT-6 PQ2 274012457406 XTAL;24.576MHZ,16PF,50PPM,8*4.5, X3
288202302001 TRANS;SI2302DS,N-MOSFET,SOT-23 Q534 274012500401 XTAL;25MHZ,30PPM,18PF,4P,SMT X1,X4
191

Part Number Description Location(s)

274013276103 XTAL;32.768KHZ,20PPM,12.5PF,CM20 X5
192

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com





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1
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PLACE THESE INSIDE SOCKET CAVITY DESIGN GUIDE PAGE 236

DESCRIPTION(NO extra pull-up

REQUEST NEW PART NUMBER FOR 51.1 Ohm, 1% resistors required) 1 1 1
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1 1 1 1 1 1 1 1 1 1
D
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Reference Material
Intel Pentium 4 Processor mPGA478 Socket Intel, INC
SiS650 IGUI Host / Memory Controller SiS, INC
SiS691 MuTIOL Media I/O Controller SiS, INC
SiS301LV / Chrontel CH7019 TV/LVDS Encoder SiS, INC
PCI1410GGU PCMCIA Controller TI, INC
uPD72872 IEEE1394 Controller NEC, INC
8575 Hardware Engineering Specification Technology Corp./MiTAC

SERVICE
SERVICE MANUAL
MANUAL FOR
FOR 8575
8575
Sponsoring Editor : Jesse Jan
Author : Sissel Diao
Assistant Editor : Janne Liu
Publisher : MiTAC International Corp.
Address : 1, R&D Road 2, Hsinchu Science-Based Industrial, Hsinchu, Taiwan, R.O.C.
Tel : 886-3-5779250 Fax : 886-3-5781245
First Edition : Jun. 2002
E-mail : Willy.Chen @ mic.com.tw
Web : http: //www.mitac.com http: //www.mitacservice.com

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SERVICE MANUAL FOR

BY: Sissel Diao

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1. Hardware Engineering Specification ………………………………………………………………… 4

1.1 Introduction …………………………………………………………………………………………………………. 4

2. System View and Disassembly ………………………………………………………………………... 73

3. Definition & Location of Connectors / Switches …………………………………………………….. 94

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4. Definition & Location of Major Component ………………………………………………………… 100

5. Pin Description of Major Component ………………………………………………………………... 102

5.1 Intel Pentium 4 Processor mPGA478 Socket ……………………………………………………………………... 102

6. System Block Diagram ………………………………………………………………………………… 129

7. Maintenance Diagnostics ……………………………………………………………………………… 130

7.1 Introduction …………………………………………………………………………………………………………. 130

8. Trouble Shooting ………………………………………………………………………………………. 134

8.1 No Power …………………………………………………………………………………………………………….. 135

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8.2 No Display …………………………………………………………………………………………………………… 141

9. Spare Parts List ……………………………………………………………………………………….. 171

10. System Exploded Views ……………………………………………………………………………… 193

11. Circuit Diagram ……………………………………………………………………………………… 198

12. Reference Material …………………………………………………………………………………… 230

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Highlights of the Pentium 4 Processor :

Available at speeds ranging from 1.50 to 2 GHz

Support for uni-processor designs

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Hyper Pipelined Technology:

400 MHZ System Bus:

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Rapid Execution Engine:

256KB, Level 2 Advanced Transfer Cache:

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Enhanced Floating-Point and Multimedia Unit:

Internet Streaming SIMD Extensions 2 (SSE2):

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1.2.2 System Frequency

1.2.2.1 System frequency synthesizer_ICS952001

Programmable Timing Control Hub™ for P4™ processor

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SiS645/650 style chipsets

2 - Pairs of differential CPUCLKs @ 3.3V

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PCI - PCI output skew: < 500ps

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Low Cost DDR Phase Lock Loop Zero Delay Buffer

SiS645/650 style chipsets

PEAK - PEAK jitter (66MHz): <120ps

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1.2.3.1 SiS650 IGUI Host/Memory Controller

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