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ECTE333 ‐ Lecture 5
Interrupts
2019
1
ECTE333 Lecture Topics
• L1) Computer Organisation
• L2) Data Path and Control Unit
• L3) Assembler Language
• L4) Instruction Set Architecture
• L5) Interrupts
• L6) Memory Interfacing
2
Lecture 5 Overview
• Interrupts Overview
• Polling Vs Interrupts
• Interrupt Service Routines
• Interrupt Vector Table
• Steps for using Interrupts
• Example program
3
Lecture 5 Associated Reading
• [STA18]
– Chapter 7
• [GAD01]
– Section 3.12
• [ATM05]
– Interrupts section (pp 54‐58)
– External Interrupts section (pp 77‐79)
4
External Interrupts
• External interrupts are a way of responding to
requests from external circuitry
– Typically, these are signals we cannot predict but we need
to make sure that the CPU is notified the minute (ns?) a
change is experienced on an input pin
– Simplest form of interrupts: created by someone else
• Internal interrupts result in the completion of a
(previously‐requested) action
– Timer overflowed
– ADC conversion completed
5
Responding to an Interrupt
• There are two methods to respond to an interrupt
– Method 1: Polling
• Polling the (external) interrupt pin directly
• Polling the interrupt flag associated with an intertupt
– Method 2: Register an Interrupt
• The CPU registers that it should be notified when the
interrupt is triggered (requested)
• CPU operation jumps to a pre‐determined point in the code
6
Polling an I/O pin
• In this method, the CPU continually checks an I/O
pin to see if it has changed
• Drawbacks: the CPU cannot be doing anything
else while polling the pin
; check if bit0 is 1
LOOP:
in temp, PINA
sbrs temp, 0 ;SBRS: skip (next instr)
rjmp LOOP ;if bit in register set
; next instr.
7
External interrupt/flag I/O pins
• Not every I/O pin can be used to trigger external
interrupts/flags
– We are limited to the number of external interrupt pins offered by
the specific microcontroller
• This depends on how many I/O pins include external interrupts
in their alternate functions
8
Interrupt Program Flow
• Setup an interrupt to
trigger when the I/O pin
t p
rru
rteupt
changes from 0 to 1
InteInr
• When the change happens,
the CPU is interrupted and
the Interrupt Service
Routing (ISR) is executed
• When done, execution
8
returns to where the CPU
was interrupted from
9
Interrupt Service Routines
• When an interrupt triggers, the CPU needs to know
what to execute
• This part of the code is written to service or handle
the interrupt request
• What if we have multiple interrupts to be responded
to?
– We need a way to specify which ISR should be executed for
each specific interrupt request. This is in the format of a
table.
10
Interrupt Vector Table
• In the AVR, the first 17 program memory locations
also double as the interrupt vector table
• The first interrupt we have been using without
knowing it
– The RESET interrupt
– When the reset button is pressed, the program starts
execution from program memory location 0
– When the external interrupt INT0 is triggered, the response
is to start executing from location 1
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IVT
(cont)
12
Interrupt Priorities
• If more than 1 interrupt is triggered simultaneously,
the interrupt with highest priority (lowest program
address in the IVT) will execute first
• Interrupts that set Flags upon triggering will wait until
the current ISR finishes (and global interrupts are
enabled again) before executing the next ISR
13
Using rjmps in the IVT
• If you are using both INT0 and INT1 interrupts,
then INT0 only has space for one instruction to be
executed before the start of the INT1 ISR.
• One instruction is all we need!
– We can use rjmps to jump to the ISR for the relevant
interrupt
Interrupt Response Time
• The interrupt response time is 4 clock cycles minimum.
• After 4 clock cycles the first actual ISR instruction is executed.
• During this 4 clock cycle period:
– the PC is pushed onto the Stack
– SP decremented by 2
– the I‐bit in SREG is cleared
– the IVT instruction (normally a jump to the ISR) takes 3 clock cycles.
• If an interrupt occurs during execution of a multi‐cycle instruction,
this instruction is completed before the interrupt is served.
• A return from an interrupt handling routine takes four clock cycles.
• During these four clock cycles,
– the PC is popped back from the Stack,
– the SP is incremented by 2
– the I‐bit in SREG is set
15
The Steps for Using Interrupts
1) Ensure the Stack is setup
2) Write the ISR to handle the interrupt
3) Create an entry in the IVT to jump to the ISR we’ve
created
4) Set up the interrupt details using configuration I/O
registers
5) Enable your interrupt
6) Enable Global interrupts
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1) Setup the Stack
• We must ensure the stack is setup
– Identical to the setup for subroutines
– This is needed because when the interrupt is finished, the
CPU returns to the next instruction from where it was
interrupted
• When an interrupt is triggered, the PC is
automatically placed onto the stack
• When reti is called at the end of an ISR, the PC is
removed from the stack and used as the address of
the next instruction to be executed
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2) Write your ISR
• This is where we program exactly what it is we want the
CPU to do in response to the interrupt request every time
it is triggered
• For example, we may want a specific counter incremented
; increment a counter when triggered
EXT_INT0:
inc counter
reti
• Notice the reti instruction. This is similar to a ret but
specific to interrupt routines.
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3) Create IVT Entry
• If we were using all interrupts in the IVT, we would simply
create rjmp instructions for each ISR
; setup IVT at the start of our Program Memory
rjmp RESET ; jump to RESET label
rjmp EXT_INT0 ; jump to EXT_INT0 ISR
rjmp EXT_INT1 ; jump to EXT_INT1 ISR
rjmp TIM1_CAPT ; jump to TIM1_CAPT ISR ...
• If we are only using Timer0 overflow interrupt
; setup IVT at the start of our Program Memory
rjmp RESET ; jump to RESET label
.org $007 ; reset ILC to 7
rjmp TIMER0_OVF ; jump to TIMER0_OVF ISR
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4) Setup Interrupt Details
Configuring External Interrupts
• This is where each interrupt is different
– Today we are only looking at external interrupts
– Slides on the necessary configuration registers later.
– Consider all aspects of the interrupt you wish to configure.
• There are three external interrupts on the
ATMega8515 (INT0, INT1 & INT2)
• These pins will trigger an interrupt even if the pin
itself is configured as an output
– Handy way to generate software interrupts
20
INT0 & INT1 Sense Control
• Interrupts INT0 and INT1 can be triggered by any of the 4
possibilities below
• Edge triggered sense control is synchronous
– Pulses shorter than one clock cycle are not guaranteed to generate an
input
• ISC1 and ISC0 bits in the MCUCR Register
21
INT2 Sense Control
• INT2 is an asynchronous External Interrupt
– The minimum pulse width is 50ns
• Only one Sense Control Bit
– Falling/Rising edge triggered only
– ISC2 bit in the EMCUCR Register
22
Sense Control bits in Registers –
MCUCR & EMCUCR
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5) Enable your Interrupt
• Every interrupt that can be triggered has an
equivalent enable bit.
• General Interrupt Control Register (GICR) contains
these bits for external interrupts
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6) Global Enable Interrupts
• Before any interrupts will trigger a response from the
CPU, the global interrupt bit must be set to 1
– This is the “I” bit in the SREG
– Can be accomplished by using the sei instruction
– Disable interrupts by using cli
25
Nested Interrupts
• By default, when an interrupt triggers on the AVR,
the I‐bit in the SREG is cleared, thus not allowing
another interrupt to ‘interrupt’ the current ISR.
• If nested interrupts are required, the programmer
can set the I‐bit as the first instruction in the ISR
• Interrupts which set an ‘Interrupt Flag’ will wait
until the I‐bit is re‐enabled before triggering the
interrupt
26
General Interrupt Flag Register
• Another I/O register for use with external interrupts,
is the General Interrupt Flag register
• Can be used for polling the interrupt
– Need to write a 1 to the bit in order to clear the flag
• Flags are automatically cleared when an ISR is
executed
27
I/O Registers
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External Interrupt
Program Example
• Write a program that toggles odd and even LEDs
on PORTB every time a rising edge is experienced
on Pin PD3.
– This is INT1
– Rising edge is needed, this means we need ISC11,
ISC10 = 1,1
; 29
; Lecture 5 example program
;
.include "m8515def.inc” ; 8515 definition file
.def temp = r16 ; define a temp register
Next Lecture
• Next Fortnight’s lecture
– Last lecture with new material
– Memory Interfacing