Professional Documents
Culture Documents
School of Science
Supervisor
Advisor
Abstract
Usage of microcontrollers and embedded software is a continually rising trend.
The use of established processor technologies in the power electronics industry
combined with the customer- and vendor-based analysis demands create a need
for running more embedded software on products. At the same time, the code
complexity warrants better testing and verification of software.
Tiivistelmä
Sulautettua ohjelmakoodia ajavien mikrokontrollerien suosio kasvaa jatkuvasti.
Vakiintuneiden prosessoriteknologioiden käyttö vastaamaan asiakkaiden ja
valmistajien vaatimuksiin mm. data-analyysissä merkitsee sulautetun koodin
määrän kasvamista tuotteissa tulevaisuudessa. Tuotteita tulee myös enemmän
ja ne ovat entistä kompleksisempia. Vaatimukset tuotteiden koodin parempaan
laadunvarmistukseen ja testaukseen kasvavat myös.
Preface
I would like to thank my family and friends for their continued support and trust
vested in me throught the thesis work. I would also like to specifically thank Lauri
Kääriäinen for his continued support of my academic research. My thanks go to
Lasse Kärkkäinen for teaching me the fundamentals of efficient software development
and how to unlock the full potential of the human mind. I would like to finally thank
Sampo Syreeni for his brutally honest and accurate criticism of the earlier versions
of the thesis. Sampo’s comments helped me the most in finalizing the thesis.
Janne Paalijärvi
6
Contents
Abstract 3
Preface 5
Contents 6
Units 10
1 Introduction 11
1.1 Objective of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2 Overview of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Our Approach 36
4.1 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2 High Level Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3 Individual Components . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.3.1 Test Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.3.2 Firmware Flasher . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.3.3 Probe Microcontroller . . . . . . . . . . . . . . . . . . . . . . 38
4.3.4 Continuous Integration Service . . . . . . . . . . . . . . . . . 38
5 Implementation 39
5.1 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2 Software Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.2.1 Overview of Design Decisions and High-Level Architecture . . 41
5.2.2 UART-Based Communication Protocol . . . . . . . . . . . . . 43
5.2.3 Device List . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.2.4 Test Commands and Test Sequencer . . . . . . . . . . . . . . 47
5.2.5 PWM Signal Capture and Generation . . . . . . . . . . . . . . 48
5.2.6 DUT Input Power Relay . . . . . . . . . . . . . . . . . . . . . 49
6 Challenges 50
6.1 Error-Prone Pin Configuration . . . . . . . . . . . . . . . . . . . . . . 50
6.2 Limited Number of ADC Devices . . . . . . . . . . . . . . . . . . . . 51
6.3 Missing PWM Capture Pins . . . . . . . . . . . . . . . . . . . . . . . 51
6.4 Misbehaving Signal Generator . . . . . . . . . . . . . . . . . . . . . . 52
6.5 Unstable PWM Sample Counter during UART Communication . . . 55
References 66
Units
s second
ms millisecond; 0.001 x second
us microsecond; 0.000001 x second
Hz hertz
kHz kilohertz; 1000 x hertz
V Volt
mV millivolt; 0.001 x Volt
1 Introduction
This thesis researches solutions for the testing and verification of embedded systems
software. Specifically, the researched solutions apply to power electronics products.
In commercial projects in the aforementioned industries, it is usually desirable to
develop a feasible product while meeting an agreed upon deadline. The combination
of embedded software and power electronics has some unique constraints regarding
application development. Some of these constraints are not visible in normal ap-
plication software development for example in established PC-style computers and
operating systems or smartphones. With power electronics projects the actual final
hardware prototype may not be initially available. Instead, the hardware is often
available only at a reduced maturity level in the early stages of the project. Usually,
the hardware is first completely non-existent and then reaches its final form and
functionality at the very end of the actual product development cycle [6].
It is possible to gain momentum in software development for embedded systems
development even before having access to the complete working hardware. The
development process can usually be bootstrapped by using a subset of the final hard-
ware. Typically the software developer can use the product-specific microcontroller(s)
mounted to a debug board. This prototyping board is then connected with signal
generators, switches, oscilloscopes and other instruments to emulate the environment
of the final and complete electronics product. Figure 1 shows a typical setup for
early-stage software development for embedded systems.
Generally, it is favorable to find bugs and defects early in a software project, as
every new chronological step makes it more costly to fix the issues compared to the
previous step. It should be noted, however, that the estimations of defect costs have
varied depending on the source and the time in software engineering history [2]1 .
Zhivich et al. [36] have argued that it is actually quite hard to evaluate the costs of
discovering and fixing bugs in the operation/end user phase because a single error in
an unfortunate place can have catastrophic fiscal consequences.
Figure 1: Embedded systems development setup for the early stages of a project.
Prototyping board has been populated with the chosen microcontroller, and a
plethora of output and input signals have been wired. These wires are connected to
the oscilloscope, switches, power supplies, etc.
equipment connected to the device output. The characteristics can be, for example,
voltage, current, and phase-angle relationships [19]. For regulation and efficiency
purposes, a dedicated controller chip is usually needed for power conversion products.
For simplicity, we will examine next an elementary voltage controller (even though
the same principles can be applied to other characteristics of power conversion).
The mode of operation for an elementary voltage controller is quite simple. In
the controller, there is a reference voltage measurement, which is from a stable
source. This stability is presumed over time and different operating conditions.
For purely analog designs, the reference can be from a dedicated reference voltage
circuit. For digital-based designs, this reference is a predetermined or adjusted
analog-to-digital (AD) reading originating from microcontroller memory and fed
to the dedicated controller chip. In both of these implementations, the controller
continuously measures the voltage of the power processing circuitry output and
compares it to the reference point. If the measurement is lower than the reference,
the controller increases the voltage at the device output. If the measurement is
higher than the reference, the output voltage is decreased [19]. If the reference and
measurements match, no action is taken. It should be noted that the controller does
not directly increase or decrease the voltage. Instead, it passes the new control signal
to actual power processing circuitry of the device, which in turn changes the voltage.
Conceptual picture of a simple controller can be seen in Figure 3.
Figure 3: Simple controller for a power converter. It should be noted that controller
outputs control value and does not solely alter the actual power conversion. Instead,
power conversion circuitry uses the control value to make adjustments.
15
2.1.2 Efficiency
In power electronics it is usually favorable to have as much of the input power
converted to output power as possible due to energy cost reasons. A property
called “efficiency” and denoted by η is used to define the amount of conversion.
In mathematical context, efficiency ranges from 0.00 to 1.00. An ideal converter
transforms 100% of its input power to output power. In actuality, a 100% conversion
rate is never achieved. The power not successfully converted to output is lost as heat.
If the amount of heat is substantially high, a dedicated system for heat transfer must
be incorporated in order to prevent the overheating of the converter. Putting it all
together, maximizing the conversion efficiency benefits the product in 2 ways: 1. it
reduces the cost of input energy by eliminating the waste energy, and 2. it reduces
product costs due to the unnecessity of dedicated heat transfer infrastructure [19].
• AC-to-DC: Rectifier
• DC-to-AC: Inverter
• DC-to-DC: Converter3
2.2.1 Microcontrollers
Embedded software naturally needs a device to run the program code. One type of
these devices is called microcontrollers, or MCUs. These microcontrollers typically
house an actual processing core, special memory for storing the program code and
RAM memory for application purposes. Some microcontrollers also house non-volatile
memory for application purposes or utilized memory chips connected externally.
Microcontrollers also usually incorporate peripheral devices. A peripheral device
is a device that implements a defined functionality inside the microprocessor. The
device may be accessible through the pins of the microprocessor in question and/or
via processor internal hardware registers. Common peripheral devices found in
microcontrollers are analog-to-digital converters (ADCs), digital-to-analog converters
(DACs), communication transceivers (for example U(S)ART4 or I2C5 ), timers, pulse-
width modulators (PWMs), and general purpose input/output (GPIO) pins [35].
Figure 4 displays the typical microcontroller from Texas Instruments, whereas in
Figure 5 there is a schematic diagram of the same microcontroller pin description
and orientation. This diagram is taken from the manufacturer-supplied datasheet,
which also lists the peripheral devices available for this specific microcontroller.
3
Converter is also a generic name for a power conversion device.
4
Universal (Synchronous/)Asynchronous Receiver/Transmitter.
5
Inter-Integrated Circuit.
17
these operations in only a few clock cycles. DSPs can be considered accurate and
sophisticated, low-latency FIFO6 devices. As new, top-level MCUs including DSP
capabilities are entering the market, the distinction between DSPs and MCUs as
processors is getting vague.
The field-programmable gate array, or FPGA, is another way of running embedded
program code. In this implementation, the custom application code is synthetized
on the logic-gate level. The FPGA approach allows tuning specific algorithms per-
formance nearer the hardware-implementation level [22]7 . Different implementation
techniques are tradeoffs between programming flexibility, performance, cost and
power usage.
while(1)
{
// Sleep the CPU until we hit the next 50ms mark:
__WFI();
// Run the actual 50ms task:
run_50ms_task();
}
return 0;
}
Listing 1: Main function of a simple embedded systems program.
In Listing 1, the main() function of the program is shown. Execution of the
code starts from this function. In the beginning, the MCU runs initialization code
provided by the microcontroller vendor. Then, it configures LED and button pins
for operation. Finally, it sets up the internal timing peripheral device to operate on
50 ms time units, called “ticks” and start the main loop. In the main loop (“while
(1)”), two things happen. First, the MCU goes into sleep mode via the __WFI()
function. In sleep mode, the MCU core is mostly idling. It returns to full power
after the timer interrupt is received. The single 50 ms task function is run after this,
and then a new sleep period is started. In other words, the MCU wakes up every
50 ms tick period to run the task function. If there was an additional need to run
21
tasks, for example, every 500 ms, simple arithmetic could be used to determine when
enough multiples of 50 ms were elapsed to trigger the 500 ms task. However, here
only single task is needed, simplifying the main loop somewhat.
The aforementioned sleep/interrupt behavior was chosen to avoid the so-called
“busy-waiting”, where the MCU runs at full speed, continuously polling a condition.
This mode of operation would waste an extremely high number of clock cycles. There
are cases, however, where such behavior would be well suited for the task at hand.
#include "LPC17xx.h"
void setup_led1(void)
{
// Configure LED pin functionality to GPIO:
LED1_PIN_SELECTOR &= ~LED1_PIN_SELECTOR_MASK;
// Configure LED GPIO direction to write:
LED1_GPIO_DIRECTOR |= LED1_GPIO_MASK;
// Dim the LED:
LED1_GPIO_CLEARER |= LED1_GPIO_MASK;
}
void setup_button1(void)
{
// Configure button pin functionality to GPIO:
BUTTON1_PIN_SELECTOR &= ~BUTTON1_PIN_SELECTOR_MASK;
// Configure button GPIO direction to read:
BUTTON1_GPIO_DIRECTOR &= ~BUTTON1_GPIO_MASK;
// Make button read logical level high by default:
BUTTON1_PIN_MODE &= PIN_RESISTORS_MASK;
}
Listing 3: Setup of 2 GPIO pins for LED and button functionalities, respectively.
Listing 3 shows how the processor pins are configured to operate both as a led
and a button. For LED operation, the pin function is chosen as GPIO for both.
This is important, as each pin can act as many different peripheral functionalities.
The same selection is needed for the button pin. The next step is different between
the pins, as the LED pin is configured to be in write mode, and the button pin is
configured to be in read mode. In bit-level, this is about assigning a 1 or 0 bit to a
dedicated director position, respectively. Assigning a 1 without touching any other
bits can be done via straightforward OR operation. 0 bit is slightly trickier to set. It
is accomplished by taking the inversion of the 1 bit pattern, and then ANDing the
result. As a final step for LED, the GPIO value is set to logical 0 V, dimming the
light. For button functionality, the last step is to make the pin “normal” state 3.3 V
via the internal “pull-up resistor”. Combined with software, the active state of the
pin/button can be more easily made 0.0 V, or shorted to ground.
23
void TIMER0_IRQHandler(void)
{
// Dummy interrupt handler to wake the system from sleep
LPC_TIM0->IR = LPC_TIM0->IR;
}
void setup_50ms_timer(void)
{
// Clear counter and generate interrupt when timer matches:
LPC_TIM0->MCR |= (TIMER0_MR0_INT_MASK | TIMER0_MR0_RESET_MASK);
// With prescaler set the counting step to 1 ms:
LPC_TIM0->PR = (SystemCoreClock /
(CONV_1MS_TO_HERTZ * TIMER0_CLOCK_DIVISOR)) - 1;
// Make counter count to 50 counting steps, equaling 50 ms:
LPC_TIM0->MR0 = TIME_50MS;
// Connect the interrupt handler:
NVIC_EnableIRQ(TIMER0_IRQn);
// Finally, enable the timer:
LPC_TIM0->TCR |= TIMER0_ENA_MASK;
}
Listing 4: Dummy interrupt handler and 50 ms timer configuration.
In Listing 4, the timer functionalities are defined. There is a dummy interrupt
handler, whose only task is to clear the interrupt condition. This elementary handler
is needed to make it possible to wake the MCU from sleep mode periodically.
An actual timer configuration function is the most complicated part of the whole
program. The first instruction manipulates the MCR, or match control register. It
makes the timer execute the interrupt handler and reset the timer value once the
counter value equals the MR0, or match register 0 value. The PR, or prescaler register,
controls how many clock cycles need to pass before the counter is actually incremented
by one unit. Here, the adjusted PR value was made to correspond to 1 milliseconds.
MR0 value was set to cause a match when 50 times the 1 millisecond period has
passed. Finally, in the function, the interrupt handler is connected and the timer set
to run.
24
The timer-based definitions presented in the program code are, of course, well-
defined. The definitions can be found in microcontroller-specific documents called
datasheets. These documents are provided by MCU-vendors in order to make the
development of software in the specific microcontrollers possible. Figure 7 shows an
excerpt of the LPC1768 datasheet. Only a small part of the full functionality of the
MCU is presented here as the full document spans almost 850 pages.
25
void run_50ms_task(void)
{
static volatile uint8_t u8_state = STATE_NORMAL;
static volatile uint8_t u8_button_samples = 0;
static volatile uint8_t u8_led_wait_samples = 0;
if(u8_state == STATE_NORMAL)
{
if((BUTTON1_GPIO_READ_DATA & BUTTON1_GPIO_MASK) == 0) // Button read ok
{
if((u8_button_samples++) >= TIME_200MS_IN_TICKS)
{
LED1_GPIO_SETTER |= LED1_GPIO_MASK; // Enough read samples,
u8_button_samples = 0; // light up the LED
u8_state = STATE_LED_ON; // and change state.
}
}
else
{
u8_button_samples = 0;
}
} // Check pass of 3 seconds in state STATE_LED_ON:
else if((u8_led_wait_samples++) >= TIME_3S_IN_TICKS)
{
LED1_GPIO_CLEARER |= LED1_GPIO_MASK; // Enough wait samples,
u8_led_wait_samples = 0; // dim the LED and
u8_state = STATE_NORMAL; // change the state.
}
}
Listing 5: The 50 ms task function of the LED controlling program.
The most important part of the program code for the system is the 50 ms task
function shown in Listing 5. As shown earlier in the state machine diagram, the
system has 2 states, namely “Normal” and “LED On”. In the normal state, the input
of the control button/pin is read. In Normal state, the read happens once every 50
ms. The button is determined to be pressed down when the corresponding pin is
connected to ground. When 4 reads have occurred at 50 ms intervals, the LED is lit,
button sample counter reset, and the state changed to LED On state11 .
The LED On mode counts how many 50 ms samples have passed. When there
has been enough samples for 3 seconds, the LED is dimmed, the local sample counter
is reset, and the state is declared again as Normal. A complete set of program codes
is available on GitHub [23]. A video demonstration of the working system is available
on YouTube [24].
After having introduced both concepts individually, we can then take a look at
how embedded software can be used in power electronics.
11
It should be noted that in Normal mode if an inactive button state (1) is read after an active
state (0), the sample counter is also reset. The behavior is called filtering. It is undesired to trigger
a functionality based on a single sample, which may even be a mishap or temporary electrical glitch.
Therefore more samples are investigated.
26
In this design, the microcontroller housing printed circuit board (PCB) interfaces
with power processing circuitry via conducting pins. These electrical pathways can be
used to read state information from power processing circuitry (for example voltage
and current). The microcontroller can also alter the state of the power conversion by,
for example, changing the reference voltages for power processing circuitry controller
or enabling or disabling the state of the device output. These alterations can be
performed by using microprocessor PWM and digital output peripherals, for example.
In the picture, there are also two RJ45 connectors visible. The microcontroller uses
these connectors in forming a messaging bus to communicate with other products. A
power electronics design can also include multiple different processors that perform
dedicated tasks.
2.3.1 Benefits
Having embedded controllers in power electronic products has many benefits. As
discussed in the previous section, a microcontroller can read measurements and other
27
information from the power conversion circuitry. The microcontroller can analyze
and store this data as well as determine the error conditions in operation (either
internal or when physical conditions reach alarm levels).
As hinted in the previous section, the controller can also participate in the com-
munication bus with other devices. Multiple devices can act together in cooperation
to fulfill dedicated tasks or report measurement and diagnostics data to upstream
devices. Some devices allow the reconfiguration of their parameters via the commu-
nication bus (for example for setting voltage limits and configuring alarms). It is
also possible for devices to collect statistics about their operation and display this
to the user when requested12 . Some power electronics communication buses can
be used during production testing at the factory for calibrations and verification
measurements.
Many proprietary and standardized communication protocols for power electronics
exist. One of these protocols is PMBus [32]13 . Some of the other protocols used in
power electronics running embedded software are SNMP14 and even plain HTTP15 .
If communication happens only between devices, a lightweight binary protocol is
preferred.
2.3.2 Future
There is active research being conducted using FPGA-based solutions for power
electronics devices [14]. As the unit prices of the technology become lower, FPGA
chips can be more interesting candidates for future designs.
Another trend of power electronics is the need for cloud-connected services. In
these scenarios, a lightweight protocol is used to transfer device data to the cloud.
This data can be accessed via multiple different user interfaces. A rudimentary web
browser-based interface can be implemented, but market demand is getting focused
on mobile phone applications for cloud-connected power electronics products.
The last emerging trend in power electronics running embedded software is
self-diagnosing devices. Devices can determine when they have a fault condition
and report this event to upstream devices or the cloud. If the amount of data
sent to the cloud is sufficiently large, machine learning algorithms can be used to
predict upcoming fault conditions based on variations of measurement values. In this
case, automated systems like enterprise resource planning and customer relationship
management (ERP and CRM, respectively) can proactively propose the ordering of
spare parts. An overview of this kind of system is shown in Figure 9.
12
Rudimentary information about the device can also be displayed for example via LED lights
operated by the microcontroller.
13
Power Management Bus.
14
Simple network management protocol.
15
Hypertext transfer protocol
28
Figure 9: The image shows the measurement data flow from power electronic devices
to the cloud. Using data mining, the predictions of spare part needs can be made
and this data used when interacting with the customer via ERP and/or CRM.
Measurement results and status information can also be displayed in a web browser
user interface or dedicated smartphone applications (Sub-picture copyrights: Samsung
Electronics Co. Ltd., Lenovo Group Ltd., Flickr.com/flow2u).
can be considerable. There are usually many standards and regulations involved in a
project. If the product is sold in many market areas, more regulations may apply.
The customer may also oblige the developing party to adhere to other specifications
at will.
3.3.1 Checklists
Checklists are a way of using predetermined listed knowledge to identify the possible
risks of a project [3]. In addition to identifying the risks, checklists also contain
information about how to deal with the risk. A typical software project checklist is
shown in Figure 11.
identified first, and then the test code is written for that specific functionality [12].
After this, the actual application code is written and tested with the pre-written test
code until the functionality works. The method is iterated for all the functionalities
of the application.
In the embedded systems context, this verification method needs to take into
account the hardware-dependent nature of the devices under test. The test platform
may need to expose the microcontroller peripherals, pins, and other functionalities
to the test framework in an emulated way. These emulated components can be used
as direct input for testing or as defining the environment for testing.
3.3.4 Simulation
Simulation can be utilized in the testing and verification of some embedded software.
In some cases, the program code for MCUs can also be compiled for the PC envi-
ronment. The binary can then be run on a PC and the results evaluated. Another
form of simulation is the use of scientific calculation tool, such as MATLAB, in
the development and verification of control algorithms. One such algorithm is the
proportional–integral–derivative, or PID, and its derivatives. In some cases, simple
spreadsheet programs can be used to at least partially verify the correctness of an
algorithm.
33
3.3.9 Hardware-in-the-Loop
Hardware-in-the-loop (HIL) is a design, implementation, and verification methodology
where the developed embedded system’s control part is run on actual hardware, but
its environment is simulated externally to some extent due to the unavailability of
the actual environment [10]. This unavailability may be due to cost or complexity
issues. Bouscayrol [5] has defined different types of HIL simulations, including the
“signal level HIL simulation”, which is presented in Figure 12. The VectorCAST tool
described in previous section also utilizes HIL principles.
3.3.12 Fuzzing
Fuzzing is an automated test technique that means flooding inputs of the tested
system with invalid, partial, and random data [21]. The methodology is cost-effective
in relation to manual boundary testing. Manually devising the “correct” test points
can be a resource-intensive task especially for a human, whereas automatically and
randomly flooding the input and logging pass and fail data is easy and more easily
automatable. A total random nature of the flooded signals is not an absolute necessity.
Analysis of the program code of the tested system can be conducted, yielding efficient
adjustments to the flood data.
In this section, we established the benefits of software testing with power elec-
tronics. We also investigated special testing considerations in the power electronics
context and showcased some of the test and verification methods available.
36
4 Our Approach
This section describes an approach for testing embedded software in a power electron-
ics context. The solution described here can be used to test embedded software in
general also, but the emphasis is on traditional microcontrollers and power electronics.
Figure 13: Overview of the devised system for testing embedded software in power
electronics context.
4.1 Requirements
Primary requirement for the solution was to build a system that could be used to test
embedded software running on microcontrollers in power electronic applications. The
solution should be fast enough to facilitate observing the necessary signal changes,
and it should also be able to generate such signals itself. It needed also be possible to
use the system in both “manual mode” and as part of automated test infrastructure.
Other necessities were the ability to store test specifications and results permanently
and to have the system as easy to use as possible via good user interface (UI) design.
Low hardware cost of the system was also one design goal.
the planned core system. Figure 13 shows the overview of the plans regarding the
components and their relations.
The Test Controller also has a local storage for test cases and a repository of test
results. An off-device backup mechanism should be used in order not to lose test
specifications or result data. The Test Controller instructs the Probe Microcontroller
to test the DUT and to receive test results afterward. Communication between these
two components is performed via a UART bus.
38
In this section, we devised a plan and architecture for building a system for testing
embedded software in a power electronics context with the concepts introduced
in Section 3.3. Each component of the system was defined separately, and their
interconnected relationships were also defined.
22
Serial Peripheral Interface bus.
39
5 Implementation
The implementation of the solution described in Section 4 is described in this section.
Both the hardware and the software parts are discussed. Notable features and
functionalities are also showcased.
Due to timing constraints and the amount of effort needed in implementing
the complete design as a working system, it was decided that only the Probe
Microcontroller part would be implemented during the project. This section reflects
the decision.
As part of the development process, a housing for the Probe Microcontroller was
constructed on prototyping stripboard. Operating software was also developed. The
MCU type was selected to be ARM23 LPC1768 with the Mbed platform PCB because
of relatively cheap price and previous knowledge of the microcontroller.
23
Advanced RISC Machine.
40
Figure 16: Mbed LPC1768 microcontroller PCB pinout. (Copyright: NXP Semicon-
ductors N.V.)
For testing of the actual microcontroller, the system needs to be powered up,
41
which happens via the LPC1768 PCB micro-USB24 connection with 5 V default
voltage. The PCB circuitry has built-in converters to scale the voltage down to 3.3 V
for both the LPC1768 and DUT to use. Another external connection that is needed
is the system UART communication port on pins p13 and p14. Figure 16 shows the
pin names and peripheral devices mapping of the LPC1768 microcontroller. As seen
in the figure, the system UART communication port was chosen this way to retain
the possibility to use I2C communication peripherals on pins p9/p10 and p27/p28
while sacrificing the usability of the SPI peripheral on pins p11 - p13.
int main() {
uint32_t i = 0;
while(1)
{
pwm_handle_monitors(); // Handle PWM signal analysis...
pwm_handle_monitor_logging(); // ... and logging too
gpio_handle_monitors(); // GPIO signal monitoring
handle_uarts(); // Check if UARTs have new input data to be processed
check_wall_clock(); // Run the test sequencer when in run mode
}
return 0;
}
Listing 6: The main() function of the probe microcontroller software.
As can be seen from the listing, the function organization consists of two main
parts. The first part is the collection of initialization routines and the second part is
the continuously running handler loop. Another way of implementing the continuous
functionalities would have been the usage of timer interrupts. Busy-looping was
mainly chosen because of the ease of implementation. In this approach, test event
accuracies of 4 us were not uncommon.
There was also a tiny concern about resource overhead. Every time the microcon-
troller jumps to the so-called interrupt context, a number of instruction cycles are
used. As some of the functionalities in the probe system are highly time-dependent
with interrupt-coupling, interrupts were ruled out as a driver for the main loop as a
precaution. The main loop operates continuously in full-speed checking sequentially
for tasks and advancing the test sequencer position when needed.
Some interrupts were still used in achieving the full functionality of the system.
They were used in setting flags when, for example, a GPIO pin state is altered.
In PWM monitoring mode, the interrupts help keep constant track of the last
encountered up and down signal hold times. Actual logging and analysis of the events
happening during testing are carried out in non-interrupt context through the main
43
loop, in which various functions analyze the flags set by interrupts. These functions
record changes to the test log.
All notable implemented features of the system are presented in the list below.
In the subsections after the list, we highlight some of these features.
Figure 18: Oscilloscope in analysis mode, after having captured a debug string
“Hello”.
After the underlying UART device support was mature enough, the actual
protocol was implemented. Protocol consists of 3 different commands, namely
identify, list devices, and test.
The identify command is used to identify which microcontroller probe type
45
and version is connected. In the future, the Test Controller can use different probes
for testing different microcontrollers. Identifying the probe first allows the selection
of appropriate test cases. The list devices command and test command are
described in more detail in subsections 5.2.3 and 5.2.4, respectively.
Figure 19: Device listing command response from the Probe Microcontroller.
The device listing command gives an exact listing of the available devices of the
specific Probe Microcontroller. The command output is shown in Figure 19. This
output tells what functional devices are available for testing and via which pins. The
printout shows following types of devices: gpio, pwm, dac, and relay. The view
conveys extensive important information. First of all, it tells the symbolic device
names being used, for example, gpio22. For PWM devices, it should be noted that
the names sharing the same main numeral share the same PWM clock internally.
That means, for example, with device pwm1.3, you must use the same base frequency
if, for example, pwm1.5 is used at the same time. More about PWM functionalities
is available in section 5.2.5.
Separated from the first field by the symbol : is the pin identifier. This identifier
corresponds to the printed names on the prototyping board pins, as can be seen in
Figure 15. Note the pwm2.0 device that lists two pins, namely p29 and p30. This
kind of listing means that, in order to achieve the declared device functionality,
both pins need to be used simultaneously. Reason for this syntax is presented in
Section 6.3.
After the final separator, each line has a list of opcodes the specific device
implements. For example, the gpio16 lists both monitor and set, whereas the
46
gpio15 can only do the set functionality. Other proposed but not implemented
commands are the read command for reading instantaneous data and the send for
sending data via UART, SPI, I2C, and similar devices.
typedef struct _dev_desc_t
{
uint8_t au8_probe_dev_name[DEV_MAP_BUF_SIZE];
dev_type e_dev_type;
uint8_t u8_pin_count;
uint8_t u8_pin_group;
uint8_t u8_pin_id;
uint8_t u8_cap_count;
uint8_t au8_probe_pins[DEV_MAP_DEV_PINS_MAX][DEV_MAP_BUF_SIZE];
uint8_t au8_processor_pins[DEV_MAP_DEV_PINS_MAX];
step_e ae_capabilities[DEV_MAP_CAPS_MAX];
3. The flag is set for the user context to indicate new sample.
4. User context polling finds the flag and runs the monitoring routine.
5. Monitoring routine stores the sample counts from 2 capture registers and adds
the correction to facilitate the context switch delay.
6. Routine adds sample values to the software filter and performs sanity check
analysis.
There is also another function that is run straight after performing the steps
above. This function is for logging purposes. It also performs analysis on the samples
of the PWM filter. If there are enough proper values and capture mode is on, the
characteristics of the signal are logged. If the signal has not changed since the last
analysis time, no new values are recorded. Extra care was taken to have as accurate
timestamps in PWM as possible. Filters store the timestamps of the time that the
first samples are stored. Therefore, even if the filter value analysis happened later
than the actual PWM signal change, the actual change time would still be logged as
a timestamp.
The PWM signal generation functionality is also implemented. As has been
briefly noted earlier, all of the generating devices share a single clock. This means
49
that all participating PWM generators need to have the same base frequency. Duty
cycle can be arbitrary, but within 1-100%. Base frequency can differ from 1 Hz to
400 kHz.
The Listing 11 from Section A shows a test log from a verification run of PWM
capture functionality. In this verification test, the oscilloscope PWM signal generator
was set to 200 kHz speed. Duty cycle was initially set to 20%. During testing the
duty cycle was manually and continuously rotated to 80%. From the test log it can
be seen that the implementation is able to detect duty cycle changes of 2% while
operating at 200 kHz. The maximum deviation of frequency is 0.2%. It should be
noted, that 200 kHz is the maximum design frequency of the capture. Therefore, the
error percentages presented are worst-case errors. With lower frequencies, the errors
become even smaller than listed herein above. Figure A1 shows the oscilloscope state
at the end of the test.
In this section, the implementation of the proposed test system was presented
and analyzed. Hardware implementation was briefly demonstrated, as was software
architecture. Important features and concepts, such as PWM generation and cap-
ture as well as the test sequencer were also introduced. PWM capture was also
benchmarked successfully in a high-frequency environment.
50
6 Challenges
During the implementation of the developed system there were many challenges, as
is sometimes the case with embedded systems projects. Some of the issues are listed
in this chapter with the discovered and proposed solutions.
26
PHP: Hypertext Preprocessor.
51
Figure 20: An excerpt from Mbed LPC1768 PCB schematics diagram. (Copyright:
NXP Semiconductors N.V.)
The solution to this problem was to use two normal capture pins in combination.
One of the capture pins was used to capture the up pulse cycle time of the PWM
signal using falling edge. The second capture pin was used to capture the full cycle
time of the signal using rising edge. A specific pin combiner was developed to be
used with PWM capture. It is shown in Figure 21.
52
Figure 22: Oscilloscope PWM generator dropping signal upon frequency change.
of instability. This instability has the same kind of form and duration regardless of
the frequency, as can be seen by comparing Figure 23 to Figure 24. The solution for
offsetting this settling interference was to tweak the PWM capture filters again. A
delay from the encountered PWM sample change time was added first. In addition,
a methodology for handling bad values was implemented. Bad values are determined
by comparing momentary sample values to averaged sample values. Few bad values
are allowed (and discarded), but when thresholds are reached, the filters are declared
stalled and need to be repopulated from the start. The timestamp of the first
acceptable sample is stored to more accurately communicate the starting time of the
PWM signal.
It turned out that having the UART-based debug printing activated was the cause
of these problems. Without debug printing, the 22 filter stalls observed in Figure 25
dropped to 0 stalls in Figure 26. The actual root cause of the problem remains
unknown. The possible reasons could be poor grounding or extra capacitance in pins.
56
Usage of 2 externally connected pins as single PWM capture device is also probably
more error-prone than using a single dedicated capture pin.
Figure 26: Debug printing off during PWM capture at 100 kHz.
This chapter demonstrated various challenges faced during the development of the
Probe Microcontroller. Most of the listed problems included the PWM functionality.
It turned out quite interestingly that most time-consuming problems were due to a
misbehaving oscilloscope signal generator.
57
Figure 27: Power electronics product prototype being tested on the developed Probe
Microcontroller housing.
The implemented Probe Microcontroller was used to test an actual power electronics
product prototype. The results of this test are presented in this chapter. The test
setup can be seen in Figure 27. The product prototype on the bottom right is
connected via wires to the test board. The prototype is a custom PCB with the
small microcontroller running the actual product firmware. The prototype PCB also
has the reference resistors and capacitors needed to operate the MCU, as well as
external pins to input and read signals.
58
Figure 28 shows the specified functional state machine diagram of the prototype.
This diagram has the same basic form as the diagram shown in Section 2.2.4 but in
more complicated form. The idea of testing is to verify that the inputs and outputs
according to the diagram also reflect the functionality of the actual prototype PCB
MCU. In testing, we provide inputs to the PCB MCU and monitor the outputs. The
test, in essence, verifies that the functional blocks of the power electronics prototype
are activated in precise sequential order. In case the order is wrong, the device would
not work as expected. In the worst possible case, the device could get damaged, and
sometimes even explode violently.
59
test reset #r e s e t th e s e q u e n c e
test define #s t a r t new s e q u e n c e
t e s t add 0 s g p i o 2 2 monitor #i n r u s h r e l a y s t a t e (1= d i s c o n n e c t e d )
t e s t add 0 s g p i o 2 3 monitor #monitor PFC b l o c k s t a t e (0= a c t i v e )
t e s t add 0 s g p i o 2 4 monitor #monitor DCDC b l o c k s t a t e (0= a c t i v e )
t e s t add 0 s g p i o 2 5 monitor #monitor POWER_GOOD s i g n a l (0= a c t i v e )
t e s t add 0 s dac1 s e t 0V #z e r o DUT VCC v o l t a g e on r e s e t
t e s t add 0 s g p i o 1 6 s e t 0 #s e t i n v e r t e d Uinrush v o l t a g e f o r w a i t i n g
t e s t add 0 s g p i o 1 7 s e t 0 #s e t UDC measurement f o r f a i l i n g
t e s t add 1 s r e l a y 1 s e t 1 #c o n n e c t VCC t o DUT
t e s t add 5 s dac1 s e t 0 . 5V #i n p u t v o l t a g e < s t a r t l i m i t
t e s t add 10 s dac1 s e t 0 . 7V #i n p u t v o l t a g e > s t a r t , but < f u l l ok
t e s t add 13 s end #end marker
t e s t commit #s e q u e n c e ending
t e s t run #run t h e s e q u e n c e
Listing 9: Script to test partial functionality of the prototype PCB MCU.
Listing 9 shows the first test script used to test the state machine of the prototype
device. As stated in script comments, the state of inrush relay, PFC block, DCDC
block, and POWER_GOOD signal are monitored with GPIO pins. With this specific test,
the idea is to show that when the prototype device input voltage measurement is
below a limit, the state machine does not advance. The test should also show that
when the input is raised above the limit, the state machine advances, but due to the
UDC voltage has been set to zero, the state machine should loop in states shown the
upper parts of the diagram. It should also be noted that the UInrush measurement
is inverted in the said diagram.
60
Figure 29: Test data from the Probe Microcontroller in non-finishing case, combined
with execution relative to the state machine.
Figure 29 shows the test results with relation to the state machine. It can be seen
that, in region 1 of the chart, the signals are kept initialized to the expected values,
although it should be noted that the gpio22 signal for inrush relay is first high and
then turns to low after 1 ms. This change happens even though the prototype PCB
MCU is powered down. The correct signal configuration is in effect when the system
is powered via relay1 device at around 1000 ms.
No test results are logged until approximately 5000 ms, at which point the input
voltage measurement of the prototype device is set to 500 mV via the dac1 device in
the end of region 1. The state machine does not advance due to the fact that 500 mV
is below the threshold to allow this. The next line, in region 2, sets the voltage above
the threshold to allow for an advance. After this, the code path marked with symbol
3 is executed. This results in looping behavior as was the original hypothesis. From
the microsecond-based timestamps in the results, it can be verified that, after the
correct input voltage is applied, there is a 700 ms second delay before inrush relay
disconnect. After 400 ms, there is a relay connect with another disconnect/connect
cycle. The last cycle is due to a device reset in the reset state.
Even though the execution clearly loops via the path marked with symbol 3,
there is one seemingly strange behavior. It can be observed that the state of PFC
is not changed during the loop, even though there is activation and deactivation in
61
test reset #r e s e t th e s e q u e n c e
test define #s t a r t new s e q u e n c e
t e s t add 0 s g p i o 2 2 monitor #i n r u s h r e l a y s t a t e (1= d i s c o n n e c t e d )
t e s t add 0 s g p i o 2 3 monitor #monitor PFC b l o c k s t a t e (0= a c t i v e )
t e s t add 0 s g p i o 2 4 monitor #monitor DCDC b l o c k s t a t e (0= a c t i v e )
t e s t add 0 s g p i o 2 5 monitor #monitor POWER_GOOD s i g n a l (0= a c t i v e )
t e s t add 0 s dac1 s e t 0V #z e r o DUT VCC v o l t a g e on r e s e t
t e s t add 0 s g p i o 1 6 s e t 1 #s e t i n v e r t e d Uinrush v o l t a g e f o r p a s s i n g
t e s t add 0 s g p i o 1 7 s e t 1 #s e t UDC measurement f o r p a s s i n g
t e s t add 1 s r e l a y 1 s e t 1 #c o n n e c t VCC t o DUT
t e s t add 5 s dac1 s e t 2 . 7V #s e t i n p u t v o l t a g e t o f u l l ok
t e s t add 13 s end #end marker
t e s t commit #s e q u e n c e ending
t e s t run #run t h e s e q u e n c e
Listing 10: Script to test completing functionality of the prototype PCB MCU.
the code path. The observation can be explained by the slow settle time of the PFC
signal. After activating the signal in the PFC Starting state, the state machine is
advanced to the DCDC Starting state. As the UDC measurement fails at this point,
it short-circuits the execution directly to the Primary Fail state. In this state, the
PFC signal is deactivated. This deactivation happens too fast to be noticed regarding
the previous activation or the signal has no actual time to change at all. Therefore,
it seems that PFC signal was not touched and that the PFC Starting state was never
visited, even though this has not been the case.
Another test was also conducted on the state machine of the prototype device.
Listing 10 shows the second test script. The idea of the test is to make execution
reach the Primary OK state as smoothly as possible after input voltage via dac1 has
been set. A notable change to previous script other than the aforementioned device
is setting gpio16 to 1 to enable fast passing in the Inrush state. The second change
is setting gpio17 to 1 to enable passing in the DCDC Starting state.
62
Figure 30: Test data from the Probe Microcontroller in finishing case, combined with
execution relative to the state machine.
Figure 30 shows which test results were recorded, and to what part of the state
machine diagram that they correspond to. The first difference happens after the
dac1 line. Whereas in the previous test there was a 700 ms wait time, now it is
almost entirely absent. This behavior happens because the inverted UInrush voltage
is set to 1 via gpio16, signifying zero physical voltage. No wait time is needed at this
point. After the 700 ms wait, there is a 400 ms wait for the states PFC Starting
and DCDC Starting, respectively. The POWER_GOOD signal activation requires that
6.8 seconds have passed since the input voltage to the prototype device under test
was set. This voltage was set at 5000005 us. The signal activated at 11805900 us.
The difference of these numbers is 6805895 us, or roughly 6.8 s, as required in the
specification.
During the testing of the two cases above, it was discovered that the original
state machine drawing as documentation differed significantly from the actual im-
plementation. The diagram was later corrected to reflect reality. It can be said
that the developed probe for microcontroller testing was successful in catching a
documentation bug from an actual prototype power electronics product.
running embedded software. The test results were analyzed and their relevance
to specifications was also shown. It turned out that the prototype state machine
diagrams had actual documentation bugs, which were exposed with the developed
system.
64
8.1 Conclusions
The goals and requirements for the implemented system were set in Section 4.1. One
requirement was to “build a system that could be used to test embedded software
running on microcontrollers in power electronic applications”. This requirement
was partially met. Due to resource and timing constraints, the full system with
all of the components and their integration was not realized. However, the Probe
Microcontroller component was implemented. It was also successfully demonstrated
to be able to test real power electronics prototypes as shown in Section 7. In this
case study, it was also shown that the developed component was able to measure
and generate the necessary signals with adequate speeds, therefore fulfilling another
requirement.
As the Test Controller component was not implemented due to the aforementioned
constraints, the automatic test mode requirement was not met. However, the
implemented component can be used in manual mode, thereby partially fulfilling
a requirement. As the Test Controller was not implemented, the repository and
user interface goals were not met. The low cost of the system was achieved for the
microcontroller probe, as components for building the housing and acquiring the
Mbed PCB cost less than 100 EUR in the currency of 2017.
The best thing in the realization of the Probe Microcontroller was the fact
that it was successfully used to test an actual power electronics prototype in a time-
dependent environment27 . An even more captivating discovery was that the developed
component was actually able to catch a real bug in the project documentation. To
make testing feasible, up-to-date documentation is a necessity.
Slope functionality should also be implemented for the input power of the device
under test (DUT). It should also be made possible to dip the DUT input voltage below
0 V, as temporary brownouts and under-voltages can cause unexpected behavior in
microcontrollers. Sometimes this behavior is even unknown to the vendors and can
cause extensive delays in debugging and development. The current transistor-based
input voltage relay control needs to be superseded with a linear voltage dip-capable
design. Implementing all of the necessary hardware changes means that there needs to
be an actual custom circuit board designed for housing all of the related components
and pathways.
A few completely software-based functionalities could also be implemented, for
example the monitor functionality of the DAC device to read momentary voltages.
In addition, as interconnected microcontrollers in power electronics sometimes need
mutual communication, the bus functionalities of the implemented system should be
significantly extended. New hardware buses, such as SPI or I2C, should be made
available and operable with send and monitor functionalities. Generic or product
family based protocols could also be implemented on top of the hardware buses.
Regarding PWM capture, the implementation currently captures only duty cycle
and frequency. As a sine-form PWM signal can be used in power electronics as a
regulation control signal, the generation and capture should also support sine-forms in
the Probe Microcontroller. Another capture option is the monitoring of the minimum
and maximum duty cycle and frequency values.
The implemented solution in this thesis operates on 3.3 V logic level. Therefore,
it may be incompatible with other logic levels, such as 5 V or 2.5 V. Level shifters
may be an adequate way to resolve the problem. It should be investigated though,
if this solution is acceptable regarding the rise and fall times of signals, especially
in high-speed bus communication. More research should also be conducted about
usage of entirely interrupts-driven test sequencer.
This thesis demonstrated that it is possible to build a test system for microcontrollers
using relatively cheap off-the-shelf parts. The test system was also verified as being
able to test the validity of both implementation and documentation of a power
electronics prototype.
66
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69
Figure A1: Oscilloscope PWM signal generator at 200 kHz after having cycled the
duty cycle from 20 % to 80 %.
ok
t e s t complete
r e s u l t s get
400013 pwm2. 0 monitor 20% 200000Hz
2131261 pwm2. 0 monitor 21% 200000Hz
2253288 pwm2. 0 monitor 22% 200000Hz
2306845 pwm2. 0 monitor 23% 199584Hz
2357435 pwm2. 0 monitor 25% 200000Hz
2420022 pwm2. 0 monitor 26% 200000Hz
2601937 pwm2. 0 monitor 27% 200000Hz
2662173 pwm2. 0 monitor 28% 200000Hz
2720818 pwm2. 0 monitor 30% 200000Hz
2804492 pwm2. 0 monitor 31% 200000Hz
2859565 pwm2. 0 monitor 33% 199584Hz
2923412 pwm2. 0 monitor 34% 200000Hz
2948104 pwm2. 0 monitor 36% 199584Hz
2966143 pwm2. 0 monitor 37% 200000Hz
3491534 pwm2. 0 monitor 39% 199584Hz
3606333 pwm2. 0 monitor 40% 200000Hz
3647627 pwm2. 0 monitor 41% 200000Hz
70