Phsical Design Automation of FPGAs

Physical Design Automation of FPGAs

In order to reduce time to fabricate interconnects, FPGAs have
been introduced, which allow users to program the devices as well as
~ the interconnect. In its simplest form, an FPGA consists of a regular
array of programmable logic blocks interconnected by a programmable
routing network.

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 Phsical Design Automation of FPGAs

FPGA Architecture
1. Logic blocks
(a) Look-up table based logic blocks
(b) Multiplexer based logic blocks
~
2. Routing network
(a) Segmented
(b) Non-segmented

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 Phsical Design Automation of FPGAs

Look-up Table Based Logic Blocks

A look-up table based logic block is just a segment of RAM. A
function can be implemented by simply loading its look-up table into
the logic block at power up. In this way, on receiving a certain set
~ of inputs, the logic blocks simply `look up' the appropriate output
and set the output line accordingly. Because of the recongurable
nature of the look-up table based logic blocks, they are also called
the Congurable Logic Blocks (CLBs).

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 Phsical Design Automation of FPGAs

Multiplexer Based Logic Blocks

Typically a multiplexer based logic block consist of three 2-to-1
multiplexers and one two-input OR gate as shown in Figure(b). The
number of inputs in eight. The circuit within the logic block can be
~ used to implement a wide range of functions. One such function, shown
in Figure(a) can be mapped to a logic block as shown in Figure(b). Thus,
the programming of multiplexer based logic block is achieved by routing
dierent inputs into the block.
A
B
C
f=ABC+ABC
A
B
C
(a)

C
C
B
A AB

A f=ABC+ABC
B
AB

(b)

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 Phsical Design Automation of FPGAs

Non-segmented Model
A typical non-segmented model is shown in Figure below. The non-segmented model is set up
as a regular grid of ve horizontal and ve vertical metal lines passing between switch
~ blocks (S). The switch blocks are rectangular switch boxes. They are used to connect the
wiring segments in one channel segment to those in another. There are also the connection
blocks (C) that are used to connect the logic block (L) pins to the routing channels.
0 1 2 3 4
Wiring
Segment
L L L
C C

4
Grid Line
S S

C C C

3
Channel
L L L Segment
C C

2
Vertical
C
S

C
S
C
Routing Channel

L L L
Horizontal
C C Routing Channel
0

IO Pads L = Logic Block

S = Switch Block
C = Connection Block

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 Phsical Design Automation of FPGAs

Segmented Model
In segmented model, the tracks in the channels contain predened wiring segments of same
or dierent lengths. Other wiring segments pass through the channels vertically. Each
input and output of a logic block is connected to a dedicated vertical segment. As a
~ result, there are no vertical constraints. There are additional global vertical lines which
provide connections between dierent channels. Connection between two horizontal segments
is provided through an antifuse, whereas the connection between a horizontal segment
and a vertical segment is provided through a cross fuse (see Figure below).

B B B
1 2 3

B B B
4 5 6

B B B
7 8 9

B B B
10 11 12

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 Phsical Design Automation of FPGAs

Physical Design Cycle for FPGAs

System design

Partitioning

Placement
(mapping of
subcircuits)

Routing
(programming of
interconnections)

Physical Design

Customized
FPGA

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 Phsical Design Automation of FPGAs

DAG Representation of a Boolean Circuit

a1
b c1
a 1
2
b3

a
3 b2
a
4
(a)

v1 v2 v3 v4

1 1 1 1

v5 v6

0 1

v7

(b)

In the Directed Acyclic Graph (DAG) of a boolean circuit, each vertex vi represents an input
or an AND or OR gate. An edge eij = (vi; vj ), directed from vi to vj , represents a
connection from the input or gate vi to an input of vj , either through a NOT gate or direct.
~
If connection between vi and vj is through a NOT gate, then a weight 0 is associated with
the edge eij , otherwise the weight of edge eij is 1. A logic network is shown in
Figure(a) and corresponding DAG is shown in Figure(b)
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 Phsical Design Automation of FPGAs

Partitioning a DAG
The partitioning problem can be formally stated as follows:
Given a directed acyclic graph G, maximum number of output terminals
of a logic block denoted as Omax and maximum number of input
terminals of a logic block denoted as Imax, partition G into
minimum number of vertex sets V1; V2; : : : ; Vk such that
~ subgraphs G1; G2; : : : ; Gk satisfy the constraints
I (Gi)  Imax ; 1  i  k
O(Gi)  Omax ; 1  i  k
Where
I (Gi) = jf(vi; vj )j(vi; vj ) 2 E; vi 62 Vi; vj 2 Vigj
O(Gi) = jf(vi; vj )j(vi; vj ) 2 E; vi 2 Vi; vj 62 Vigj

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 Phsical Design Automation of FPGAs

An Example of Partitioning a DAG

vi
(a)

vi
(b)

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 Phsical Design Automation of FPGAs

Node Decomposition

v1
(a)

(b)

In the cases when a node in DAG has a fan-in of greater than Imax,
a node decomposition phase has to be carried out before applying
~
the above algorithm. Figure(b) shows a DAG obtained after
decomposition of node v1 in Figure(a).

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 Phsical Design Automation of FPGAs

Routing Algorithm for the Non-Segmented Model

1. Global routing: The global route denes a course route for each
connection by assigning it a sequence of channel segments.
2. Detailed routing: Given a course route, the objective of the detailed
router is to choose specic wiring segments in each channel segment
assigned during global routing. This is achieved in two steps:
~ (a) Expansion of coarse grid graph: In this step, a coarse grid
graph is expanded to record a subset of possible ways of
implementing the connection.
(b) Connection formation: The expanded graph GD = (VD ; ED) contains
a number alternative paths. In this step, all these paths are
enumerated, their cost is computed and the minimum cost path is
selected to implement the connection.

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 Phsical Design Automation of FPGAs

Coarse Grid Graph and Expanded Graph

Block Grid Coordinates Blocks Grid Coordinates

L 4,1 L Edge label 2,2

1 2

C 3,1 C 2,3
3 4 5

S 2,1 S 3,3

6 7 8 9

C 1,1 C 3,4

10 11 12 13

L 0,1 L 4,4

(a) (b)

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 Phsical Design Automation of FPGAs

GRAPH-EXPANSION Algorithm
Algorithm GRAPH-EXPANSION( ) G

begin
G = G;
D
while (DFS-COMPLETE(GD)==FALSE) do
vi =CURRENT-DFS-VISIT(GD );

li =WIRE-SEGMENT(vi ; GD );

if (NODE-TYPE(vi)=C OR NODE-TYPE(vi)=S) then

vj =SUCCESSOR(GD ; vi );

Tj =SUBTREE(GD ; vj );

if (NODE-TYPE(vi)=C) then
~
for (each wiring segment l in FC (vi; vj ; l) ) do
T =DUPLICATE(Tj );

CONNECT(vi; vj ; T ; l);
DELETE(GD ; Tj );
if (NODE-TYPE(vi)=S) then
for (each wiring segment l in FS (vi; vj ; l; vk) ) do
T =DUPLICATE(Tj );

CONNECT(vi; vj ; T ; l);
DELETE(GD ; Tj );
end.
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 Phsical Design Automation of FPGAs

Routing Algorithms for the Segmented Model

Algorithm SEG-ROUTER (I ; T , A)
input: I ; T ;
output: A;
begin
for i = 1 to n do
~ for j = 1 to m do
s=GET-SEGMENT(j; LEFT (Ii));
if OCCUPIED(s) =FALSE then
A[i]=j;
MARK-OCCUPIED(Ii ,Tj );
end.

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 Phsical Design Automation of FPGAs

Examples of Models
1 4 0 0 2 0 0 3 0 5 0 0 0 0

0 0 0 1 0 0 4 0 2 0 3 0 0 5
(a)

1 4 0 0 2 0 0 3 0 5 0 0 0 0

0 0 0 1 0 0 4 0 2 0 3 0 0 5

(b)

1 4 0 0 2 0 0 3 0 5 0 0 0 0

0 0 0 1 0 0 4 0 2 0 3 0 0 5
(c)

1 4 0 0 2 0 0 3 0 5 0 0 0 0

0 0 0 1 0 0 4 0 2 0 3 0 0 5
(d)

(a)Non-segmentation (b)uniform segmentation (c)uniform staggered

~
segmentation (d)non-uniform staggered segmentation
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 Phsical Design Automation of FPGAs

Routing Algorithm for Staggered Model

Algorithm FSCR(I ; T ; A)
input: I ; T ;
output: A;
begin
for i = 1 to n do
selected-track = 0;
minimum-delay = 1;
for j = 1 to m do
if (OK-TO-ASSIGN(Ii; Tj ) =TRUE) then
current-delay = COMPUTE-DELAY(Ii; Tj );
~

if ( minimum-delay > current-delay ) then

minimum-delay = current-delay;
selected-track = j;
if (selected-track 6= 0) then
A[i]=j;
MARK-OCCUPIED(Ii ,Tj );
else exit; (* Routing not possible *)
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Algorithms for VLSI Physical Design Automation
 Phsical Design Automation of FPGAs

Summary
1. FPGAs are being used as a new approach to ASIC design which oers
dramatic reduction in manufacturing turnaround time and cost.
2. The physical design cycle of an FPGA consists of three steps, partitioning,
placement and routing.
3. The FPGA partitioning depends on the architecture in which the circuit
~
has to be implemented.
4. Placement problem is equivalent to gate array placement problem.
5. Because of the segmented nature of the FPGA channels, the routing
considerations are quite dierent than those in other design styles.
6. In high performance FPGA designs, the number of antifuse elements
along with unused tracks and antifuses must be given due considerations
as part of the routing phase.

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