Dr.B.

Krishna Kumar
Professor, Methodist College of Engineering
and Technology
Abids, Hyderabad
 1.VHDL CODE FOR BASIC LOGIC GATES
Aim:
To write VHDL code for AND,NAND,OR,NOR,NOT,XOR gates and to plot the
simulation results.

Software used:
XILINX project navigator
MODELSIM XE II/starter 5.8 C

VHDL code for AND and NAND gates:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY and1 IS
PORT ( x2,y2 : IN std_logic;
b: OUT std_logic);
END ENTITY;
ARCHITECTURE df OF and1 IS
BEGIN
b<= x2 AND y2;
END df;

library ieee;
use ieee.std_logic_1164.all;
entity nand12 is
port (A,B:in std_logic;
C:out std_logic);
end entity;
architecture df of nand12 is
begin
C<= A nand B;
end df;

VHDL code for OR and NOR gates:

library ieee;
use ieee.std_logic_1164.all;
entity or1 is
port (A,B:in std_logic;
C:out std_logic);
end entity;
architecture df of or1 is
begin
C<=A or B ;
end df;

library ieee;
use ieee.std_logic_1164.all;
entity nor1 is
port (A,B:in std_logic;
C:out std_logic);
end entity;
architecture df of nor1 is
begin
C<=not (A or B) ;
end df;

VHDL code for XOR and NOT gates:

library ieee;
use ieee.std_logic_1164.all;
entity xor1 is
port (a,b:in std_logic;
c:out std_logic);
end entity;
architecture df of xor1 is
begin
c<=a xor b;
end df;

library ieee;
use ieee.std_logic_1164.all;
entity not12 is
port( a: in std_logic;
a1 : out std_logic);
end entity;
architecture df of not12 is
begin
a1<= not a;
end df;
 VHDL CODE FOR HALF ADDER AND HALF SUBTRACTOR
Aim:
To write VHDL code for half adder and half subtractor and to plot the simulation results.

Software used:
XILINX project navigator
MODELSIM XE II/starter 5.8 C
HALF ADDER
library ieee;
use ieee.std_logic_1164.all;
entity halfadd is
port (a,b:in std_logic;
s,c:out std_logic);
end entity;
architecture df of halfadd is
begin
s<= a xor b;
c<= a and b;
end df;
 HALF SUBTRACTOR
library ieee;
use ieee.std_logic_1164.all;
entity halfsub1 is
port( a,b: in std_logic;
d,bo:out std_logic);
end entity;
architecture df of halfsub1 is
begin
d<= a xor b;
bo<= (not a) and b;
end df;
 VHDL CODE FOR FULL ADDER AND FULL SUBTRACTOR

Aim:
To write VHDL code for full adder and full subtractor and to plot the simulation results.

Software used:

XILINX project navigator

MODELSIM XE II/starter 5.8 C

FULL ADDER
library ieee;
use ieee.std_logic_1164.all;
entity fulladder is
port(a,b,cin:in std_logic;
s,cout: out std_logic);
end entity;
architecture df of fulladder is
begin
s<= a xor b xor cin;
cout<= (a and b) or (b and cin) or (a and cin);
end df;

FULL SUBTRACTOR
library ieee;
use ieee.std_logic_1164.all;
entity fullsub1 is
port(a,b,bin:in std_logic;
d,bo: out std_logic);
end entity;
architecture df of fullsub1 is
begin
d<= a xor b xor bin;
bo<= (not a and b) or (b and bin) or (not a and bin);
end df;

VHDL CODE FOR 4X1 MULTIPLEXER

Aim:
To write VHDL code for 4x1 multiplexer and to plot the simulation results.

Software used:

XILINX project navigator

MODELSIM XE II/starter 5.8 C
VHDL CODE

library ieee;
use ieee.std_logic_1164.all;
entity mux4df is
port(a: in std_logic_vector(0 to 3);
so,s1:in std_logic;
y:out std_logic);
end entity;
architecture df of mux4df is
signal sel:integer;
begin
sel<= 0 when so='0' and s1='0'else
1 when so='0' and s1='1' else
 2 when so='1' and s1='0' else
3;
y<=a(0) after 0.5 ns when sel=0 else
a(1) after 0.5 ns when sel=1 else
a(2)after 0.5 ns when sel=2 else
a(3) after 0.5 ns;
end df;

VHDL CODE FOR 8X1 MULTIPLEXER

Aim:
To write VHDL code for 8x1 multiplexer and to plot the simulation results.

Software used:

XILINX project navigator

MODELSIM XE II/starter 5.8 C

library ieee;
use ieee.std_logic_1164.all;
entity mux8 is
port (a:in std_logic_vector (0 to 7);
so,s1,s2:in std_logic;
y:out std_logic);
end entity;
architecture df of mux8 is
signal sel:integer;
begin
sel<= 0 when so='0' and s1='0' and s2='0' else
 1 when so='0' and s1='0' and s2='1' else
2 when so='0' and s1='1' and s2='0' else
3 when so='0' and s1='1' and s2='1' else
4 when so='1' and s1='0' and s2='0' else
5 when so='1' and s1='0' and s2='1' else
6 when so='1' and s1='1' and s2='0' else
7;
y<=a(0) when sel=0 else
a(1) when sel=1 else
a(2) when sel=2 else
a(3) when sel=3 else
a(4) when sel=4 else
a(5)when sel=5 else
a(6) when sel=6 else
a(7);
end df;

VHDL CODE FOR 2 TO 4 DECODER

Aim:
To write VHDL code for 2 to 4 decoder and to plot the simulation results.

Software used:

XILINX project navigator

MODELSIM XE II/starter 5.8 C

library ieee;
use ieee.std_logic_1164.all;
entity decoder4 is
port(g,a,b:in std_logic;
y:out std_logic_vector(0 to 3));
end entity;
architecture df of decoder4 is
signal yin:std_logic_vector(0 to 3);
begin
yin<="0111" when a='0' and b='0' else
"1011" when a='1' and b='0' else
"1101" when a='0' and b='1' else
"1110" when a='1' and b='1' else
"1111";
y<=yin when g='0' else
"1111";
end df;

VHDL CODE FOR 3 TO 8 DECODER

Aim:
To write VHDL code for 3 to 8 decoder and to plot the simulation results.
Software used:

XILINX project navigator

MODELSIM XE II/starter 5.8 C

library ieee;
use ieee.std_logic_1164.all;
entity decoder3to8 is
port(x: in bit_vector(0 to 2);
y:out bit_vector (0 to 7));
end entity ;
architecture df of decoder3to8 is
begin
with x select
y<="01111111" when "000",
"10111111" when "001",
"11011111" when "010",
"11101111" when "011",
"11110111" when "100",
"11111011" when "101",
"11111101" when "110",
"11111110" when "111",
"11111111" when others;
end df;
 VHDL CODE FOR HALF ADDER AND HALF SUBTRACTOR(STRUCTRAL
MODEL)
Aim:
To write VHDL code for half adder and half subtractor and to plot the simulation results.

Software used:
XILINX project navigator
MODELSIM XE II/starter 5.8 C
HALF ADDER

library ieee;
use ieee.std_logic_1164.all;
entity hastr is
port (x,y:in std_logic;
s,c:out std_logic);
end entity;
architecture struct of hastr is
component xorf
port(a1,a2:in std_logic;
a3:out std_logic);
end component;
component andf
port (a,b:in std_logic;
c:out std_logic);
end component;
begin
c1: xorf port map(x,y,s);
c2:andf port map(x,y,c);
end struct;

HALF SUBTRACTOR

library ieee;
use ieee.std_logic_1164.all;
entity hsubstr is
port(x,y:in std_logic;
D,bo:out std_logic);
end entity;
architecture struct of hsubstr is
component xorf
port(a1,a2: in std_logic;
a3:out std_logic);
end component;
component andf
port (a,b:in std_logic;
c:out std_logic);
end component;
signal c2: std_logic;
begin
c1:xorf port map (x,y,D);
c2<= not x;
c3: andf port map (c2,y,bo);
end struct;

VHDL CODE FOR FULL ADDER AND FULL SUBTRACTOR(STRUCTRAL

MODEL)

Aim:
To write VHDL code for full adder and full subtractor and to plot the simulation results.

Software used:
XILINX project navigator
MODELSIM XE II/starter 5.8 C
FULL ADDER

library ieee;
use ieee.std_logic_1164.all;
entity fastr is
port(x,y,c:in std_logic;
s,co:out std_logic);
end entity;
architecture struct of fastr is
component xorf3
port (x1,x2,x3:in std_logic;
x4: out std_logic);
end component;
component andf
port (a,b:in std_logic;
c:out std_logic);
end component;
component orf3
port (a1,a2,a3:in std_logic;
a4:out std_logic);
end component;
signal s1,s2,s3:std_logic;
begin
c1:xorf3 port map(x,y,c,s);
c2:andf port map (x,y,s1);
c3: andf port map(x,c,s2);
c4: andf port map (y,c,s3);
c5:orf3 port map (s1,s2,s3,co);
end struct;

FULL SUBTRACTOR
library ieee;
use ieee.std_logic_1164.all;
entity fullsub is
port(x,y,bin:in std_logic;
D,bo:out std_logic);
end entity fullsub;
architecture struct of fullsub is
component xorf
port(a1,a2 : in std_logic;
a3:out std_logic);
end component;
component orf
port(b1,b2:in std_logic;
b3:out std_logic);
end component;
component andf
port(a,b:in std_logic;
c:out std_logic);
end component;
signal c2,c5,p1,p2,p3:std_logic;
begin
c1:xorf port map (x,y,p1);
c2<= not x;
c3:andf port map (c2,y,p2);
c4:xorf port map(bin,p1,D);
c5<= not p1;
c6:andf port map (c5,bin,p3);
c7:orf port map(p2,p3,bo);
end struct;

VHDL CODE FOR 4X1 MULTIPLEXER(STRUCTRAL MODEL)

Aim:
To write VHDL code for 4x1 multiplexer and to plot the simulation results.

Software used:

XILINX project navigator

MODELSIM XE II/starter 5.8 C

library ieee;
use ieee.std_logic_1164.all;
entity mux4str is
port (m1,m2,m3,m4,s1,s2:in std_logic;
m5:out std_logic);
end entity;
architecture str of mux4str is
component and3
port (a,b,c:in std_logic;
d:out std_logic);
end component;
component notf
port(x:in std_logic;
y:out std_logic);
end component;
component or4
port(b1,b2,b3,b4:in std_logic;
b5:out std_logic);
end component;
signal p1,p2,p3,p4,p5,p6:std_logic;
begin
c1:notf port map (s1,p5);
c2:notf port map (s2,p6);
c3:and3 port map (m1,p5,p6,p1);
c4: and3 port map (m2,p5,s2,p2);
c5: and3 port map (m3,p5,s2,p3);
c6: and3 port map (m4,s1,s2,p4);
c7:or4 port map(p1,p2,p3,p4,m5);
end str;
 VHDL CODE FOR 4 BIT COMPARATOR (STRUCTRAL MODEL)
Aim:
To write VHDL code for 4 bit comparator and to plot the simulation results.

Software used:

XILINX project navigator

MODELSIM XE II/starter 5.8 C

library ieee;
use ieee.std_logic_1164.all;
entity comp4 is
port (x,y:in std_logic_vector(0 to 3);
cin:in std_logic;
cout:out std_logic);
end entity;
architecture struct of comp4 is
component xnor1
port (y1,y2:in std_logic;
y3:out std_logic);
end component;
component andf
port (a,b:in std_logic;
c:out std_logic);
end component;
signal e1,e2,e3,s1,s2,s3,s4:std_logic;
begin
c1:xnor1 port map (x(0),y(0),s1);
c2:andf port map (s1,cin,e1);
c3:xnor1 port map(x(1),y(1),s2);
c4:andf port map(s2,e1,e2);
c5:xnor1 port map(x(2),y(2),s3);
c6:andf port map (s3,e2,e3);
c7:xnor1 port map (x(3),y(3),s4);
c8:andf port map(s4,e3,cout);
end struct;