GAL Databook 1991 PDF

DATA BOOK
Lattice°
Semiconductor
Corporation
GAL PRODUCT INDEX
Commercial Grade Devices

DEVICE PINS tpo
tpD (ns) Icc (rnA)
Icc (mA) DESCRIPTION
DESCRIPTION PAGE
PAGE
GAL16V8NB 20 7.5,10,15,25
7.5, 10, 15,25 55,90,115
55, 90, 115 FCMOS
E2CMOS Generic PLD 2-1
2-1
GAL20V8NB 24 7.5,10,15,25
7.5, 10, 15,25 55,90,115
55, 90, 115 E2CMOS
E2CMOS Generic PLD 2-25
2-25
GAL18V10
CALI 8V10 20 15,20
15,20 115
115 E2CMOS
E2CMOS Universal PLO
PLD 2-47
2-47
GAL22V10/B 24 10,15,25
10, 1 5 , 2 5 130
130 E2CMOS
E2CMOS Universal PLD
PLO 2-61
2-61
GAL26CV12 28 15,
15, 20 130
130 E2CMOS
PLO 2-81
2-81
GAL20RA10
GAL2ORA10 24 12,15,20,30
12, 15, 20, 30 100
100 E2CMOS
E2CMOS Asynchronous PLD
PLO 2-95
2-95
GAL6001 24 30,35
30, 35 150
150 E2CMOS
E2CMOS FPLA 2-109
2-109
ispGAL 16Z8
i5pGAL16Z8 24 20, 25 90
90 E2CMOS
E2CMOS In-System-Programmable PLD
PLO 2-121
2-121
Industrial Grade Devices

DEVICE PINS tpD (ns)
tpD (ns) Icc (rnA)
Icc (mA) DESCRIPTION
DESCRIPTION PAGE
PAGE
GAL16V8NB 20 10,15,20,25
10, 15, 20, 25 65, 130 E2CMOS
E2CMOS Generic PLD
PLO 2-1
2-1
GAL20V8A 24 15,20,25
15, 20, 25 65,
65, 130 FCMOS
E2CMOS Generic PLD
PLO 2-25
2-25
GAL18V10 20 20 125
125 E2CMOS
E2CMOS Universal PLD 2-47
2-47
GAL22V10/B 24 15,20,25
15, 20, 25 150
150 E2CMOS
PLO 2-61
2-61
GAL26CV12 28 20 150
150 E2CMOS
PLD 2-81
2-81
GAL20RA10
GAL2ORA10 24 20 120
120 E2CMOS
E2CMOS Asynchronous PLD
PLO 2-95
2-95
MIL-STD-883C Grade Devices

DEVICE PINS (ns)
tpD (ns)
tpD Icc
Icc (rnA)
(mA) DESCRIPTION
DESCRIPTION PAGE
PAGE
GAL16V8NB 20 10,15,20,25,30
10, 15, 20, 25, 30 65,130
65, 130 E2CMOS
E2CMOS Generic PLD
PLO 3-5
3-5
GAL20V8A 24 15,20,25,30
15, 20, 25, 30 65,130
65, 130 E2CMOS
E2CMOS Generic PLD
PLO 3-13
3-13
GAL22V10/B 24 15,20,25,30
15, 20, 25, 30 150
150 E2CMOS
PLD 3-19
3-19
GAL20RA10
GAL2ORA10 24 20, 25 120
120 E2CMOS
E2CMOS Asynchronous PLD 3-27
3-27
line.
Thank you for your interest in our high performance GAL product line.
As the inventor and world leader of the GALS device, we at Lattice are
GAL· device,
dedicated to providing you with the fastest, highest quality and most
flexible solution to your logic needs.
In our new 1991 Data

Data Book, you will see that we have substantially
expanded our product line and continue to offer the world's highest
performance CMOS programmable logic devices.
We look forward to satisfying all of your programmable logic requirements.
Sinc rely,
.Steven Laub
Vice President and General Manager
iiii
GAL Data Book
1991
f/J
.l..I
Lattice®
Semiconductor
IldISnaficto!dincr®
Corporation
Corporation
ic
iiiiii
itLLattke®
/;Lattire°
.l.J SemiconducUJr
Semiconductor
Corporation
Corporation
Copyright ©
1 91991 Lattice Semiconductor Corporation
9 1 Lattice Corporation
Generic Array Logic, Latch-Lock, and RFT are

are trademarks
trademarks of
of Lattice Semiconductor
Semiconductor Corporation.
Corporation.
ispGAL, GAL, PCMOS and UltraMOS are
GAL, E2CMOS are registered
registered trademarks
trademarks of Lattice
Lattice Semiconductor
Semiconductor Corporation.
Corporation.
PAL is a registered trademark of Advanced Micro Devices, Inc.
Products discussed in this literature are

are covered
covered by U.S. Patents No.4,
U.S. Patents 761,768, 4,766,569,
No. 4,761,768, 4,766,569, 4,833,646,
4,833,646, 4,852,044,
4,852,044,
4,855,954, 4,879,688, 4,887,239 and 4,896,296 issued to to Lattice
Semiconductor Corporation,
Corporation, and
and by
by U.S.
U.S. and
and
foreign patents pending.
foreign patents pending.
LATTICE
LATTICE SEMICONDUCTOR CORP.
5555
5555 Northeast Moore Court
Hillsboro, Oregon 97124
Hillsboro, Oregon 97124 U.S.A.
U.S.A.
Tel.: (503) 681-0118
FAX: (503) 681-3037
TELEX 277338 LSC
TELEX 277338 LSC UR
UR
iv
iv
Section 1:
1: Introduction
Introduction to Generic Array Logic
Introduction to Generic Array Logic 1-1
1-1
II
Section 2: GAL Datasheets 22
Datasheet Levels 2-ii
2-ii
GAL16V8NB
GAL16V8A1B 2-1
2-1
GAL20V8A/B
GAL20V8A1B 2-25
2-25
GAL18V10 2-47
2-47
GAL22V10/B 2-61
2-61
GAL26CV12 2-81
2-81
GAL2ORA10
GAL20RA10 2-95
2-95
GAL6001 2-109
2-109
ispGAL16Z8 2-121
2-121
Section 3: GAL Military Products

Military Program Overview 3-1
3-1
33
MIL-STD-883C Flow 3-2
3-2
Military Ordering Information 3-3
3-3
GAL16V8A/B
GAL 16V8A1B Military Datasheet 3-5
3-5
GAL20V8A Military
Military Datasheet 3-13
3-13
GAL22V10/B Military Datasheet 3-19
3-19
GAL2ORA10
GAL20RA 10 Military Datasheet 3-27
3-27
Section 4: Quality and Reliability

Quality Assurance Program 4-1
4-1 44
Qualification Program 4-3
4-3
E2CMOS Testability Improves Quality 4-5
4-5
Section 5: Technical Notes

GAL Metastability Report 5-1
5-1 55
Latch-up Protection
Protection 5-17
5-17
Section 6: Article
Article Reprints
Avoid the Pitfalls of High-Speed Logic Design 6-1
6-1 66
Extending the 22V1
22V10 0 EPLD 6-7
6-7
In-Circuit Logic Device Can be Reprogrammed on the Fly 6-9
6-9
Multiple Factors Define True Cost of PLDs 6-13
6-13
Section 7: General Information
Development Tools 7-1
7-1 77
Copying PAL, EPLD & PEEL Patterns into GAL Devices 7-3
7-3
GAL Product Line Cross Reference 7-5
7-5
Package Thermal Resistance 7-8
7-8
Package Diagrams 7-9
7-9
Tape-and-Reel Specifications 7-16
7-16
Sales Offices 7-17
7-17
1-i
1-i
1-ii
Introduction to wit .J
Logic a t
Generic Array Logic I
INTRODUCTION THE GAL

THE GAL CONCEPT
CONCEPT I
Lattice Semiconductor,
Lattice Semiconductor, located
located in
in Hillsboro,
Hillsboro, Oregon,
Oregon, was
was E2CMOS -— THE
EZCMOS THE IDEAL
IDEAL TECHNOLOGY
TECHNOLOGY
founded in I
founded in 1983
1983 toto design,
design, develop
develop and
and manufacture
manufacture Of the three
Of three major
major technologies
technologies available
available for
for producing
producing
high-performance semiconductor components. It is a firm
high-performancesemiconductorcomponents.ltisafirm PLDs, the
PLDs, the technology
technology of choice
choice is clearly
clearly E2CMOS.
E2CMOS.
belief at
belief at Lattice
Lattice that
that technological
technological evolution
evolution can
can be
be E2CMOSoffers
E2CMOS offerstestability,
testability, quality,
quality, high
high speed,
speed, low
lowpower,
power,
accelerated through
accelerated through the
the continued
continued development
developmentof ofhigher-
higher- and instant erasure.
and erasure.
speed and architecturally superior products.
TESTABILITY
TESTABILITY
GAL devices are ideal for four important reasons:
reasons: The biggest
The biggest advantage
advantage of of E2CMOS
PCMOS over over competing
competing
technologies is its inherent testability.
technologies testability. Capitalizing on
Capitalizing on
1. GAL
GAL devices
devices have
have inherently
inherently superior
superior quality
quality and very fast(1
and veryfast (100ms) erasetimes,
OOms) erase times, Lattice
Lattice repeatedly
repeatedlypatterns
patterns
reliability. and erases
and erases allall devices
devices during
during manufacture.
manufacture. Lattice tests
Lattice tests
eachGAL
each GALdevice
devicefor
forAC,
AC,DC,
DC,and
andfunctional
functionalcharacteristics.
characteristics.
2. GAL devices can directly
directly replace PAL devices in nearly
nearly The
The result
result i is
s guaranteed
guaranteed 100%100% programming
programming and and
every application. functional yields.
functional yields.
3. GAL
GAL devices
devices have
have the
the low
low power
power consumption
consumption of LOW POWER
LOW POWER
CMOS, one-fourth to one-haH
one-half that of
of bipolar devices. Another advantage of E2CMOS
Another E2CMOS technology
technology is the the low
low
powerconsumption
power consumption of of CMOS.
CMOS. CMOS provides users
CMOS provides usersthethe
4. GAL devices utilize Output Logic Macrocells (OLMCs), immediate benefit
immediate benefit ooff decreased
decreased systemsystem powerpower
which allow the user to configure outputs as needed. requirements allowing
requirements allowing for higher reliability
reliability and cooler
running systems. LLow
running o w power CMOS
CMOS technology
technology alsoalso
permits circuit
permits circuit designs
designs of
of much
much higher
higherfunctional
functional density,
density,
because of
because of lower
lower junction
junction temperatures
temperatures and and power
power
requirements on
requirements on Chip.
chip. The user
user benefits
benefits because
because higher
higher
functional density means
functional means further
further reduction
reduction of of chip
chip count
count
and smaller boards
and boards in
in the
the system.
system.
HIGH
HIGH SPEED
Also advantageous
Also advantageous is is the
the very
veryhigh
high speed
speed attainable
attainablewith
with
Lattice's state-of-the-art E2CMOS
Lattice's process. Lattice
PCMOS process. Lattice GAL
GAL
devices are as
devices as fast
fast or
or faster
faster than
than bipolar
bipolar and LJVCMOS
and UVCMOS
PLDs.
PLDs.
PROTOTYPING
PROTOTYPING AND AND ERRORERROR RECOVERY
RECOVERY
Finally, E2CMOS
Finally, E2CMOSgivesgivesthethe user
userinstant
instanterasabilitywith
erasability with no
no
additional handling
additional handling or or special
special packages
packages necessary.
necessary. This
provides ideal
provides ideal products
products for for prototyping
prototyping because
because designs
designs
can be
can be revised
revisedinstantly,
instantly, with
with nonowaste
wasteand
and no
nowaiting.
waiting. On
On
the manufacturing
the manufacturing floorfloor instant
instant erasability
erasability can
can also
also be
be aa
big advantage
big dealing with
advantage for dealing with pattern
pattern changes
changes or or error
error
recovery. If aa GAL
recovery. GAL device
device is is accidentally
accidentally programmed
programmed to to
the wrong
the wrong pattern,
pattern, simply
simply reprogram
reprogramthethe device.
device. No
No other
other
technology offers
technology offers this
this advantage.
advantage.
1-1
1-1
Introduction to
Generic Array Logic
A LOOK AT OTHER TECHNOLOGIES THE
THE GAL ADVANTAGE
ADVANTAGE
Here, the
the technologies
technologies that competecompete with E2CMOS E2CMOS -— GAL GAL devices
devices are are ideal
ideal programmable
programmable logic logic devices
devices
bipolar and UVCMOS -are — are compared with with the E2CMOS because,
the E2CMOS because, as the name implies, implies, they are architecturally
architecturally
approach. generic. Lattice
generic. Lattice has has employed
employed the the macrocell
macrocell approach,
approach,
which allows
allows users users to definedefine the the architecture
architecture and and
BIPOLAR functionality of
functionality of each
eachoutput.
output. The key keybenefit
benefitto tothetheuser
userisis
Bipolar fuse-link technology was the first available available for the the freedom
freedom from from beingbeing restricted
restricted tto o any
any specific
specific
programmable logic logic devices.
devices. Although
Although itit offers
offers high architecture. T This
high architecture. h i s iis s advantageous
advantageous aatt both both the the
speed, itit is
is saddled
saddled with high high power dissipation. High manufacturing level
High manufacturing level and
and thethe design
design level.
level.
power dissipation increases your system power supply
cooling requirements, and limits
and cooling limitsthethefunctional
functionaldensity DESIGN ADVANTAGES
density DESIGN ADVANTAGES
of bipolar devices. Early programmable
Early programmable logic logic devices gave the user user thethe
ability to
ability to specify
specify a function,
function, but but limited
limited them
them to to specific,
specific,
Another weakness of this technology technology is the one-time- predetermined predetermined output output architectures.
architectures. Comparing
Comparing the theGAL
GAL
programmable fuses. Complete testing testing of ofbipolar
bipolar PLDs
PLDsis devicewith
is device withfixed-architecture
fixed-architectureprogrammable
programmablelogic logicdevices
devices
impossible because
because the the fuse
fuse array
array cannot
cannot be tested is
be tested is much
much like
like comparing
comparing these these same
same fixed
fixed PLDs
PLDs with with SSI/
SSI/
before programming. Bipolar Bipolar PLD manufacturers must MSI MSI devices. The The GAL GAL family
family isis the
the next
next generation
generation in in
rely on complex schemes using test rows rows and
and columns
columns to simplified system
to simplified system design. TThe h e user does not have have to
simulate and correlate their device's performance. The search for the architecture
The search architecture that best best suits a particular
particular
result is programming failures at the customer location. design. design. Instead, the theGALGALfamily's
family'sgeneric
genericarchitecture
architecturelets lets
Any misprogrammed
misprogrammed devices devices due due to mistakes during him
mistakes during him configure
configure as as he goes.goes.
prototyping or or errors
errors onon the
the production
production floor must be
because bipolar
discarded because bipolarPLDscannot
P LDs cannotbe bereprogrammed. MANUFACTURING ADVANTAGES
reprogrammed. MANUFACTURING ADVANTAGES
The one-device-does-all
The one-device-does-all approach approach greatlygreatly simplifies
simplifies
UVCMOS manufacturingflow
manufacturing flow.. Inventorying one onegeneric-architecture
generic-architecture
UVCMOS addresses many
UVCMOSaddresses many weaknesses of the bipolar bipolar GALGAL device type type versus
versus having
having to to monitor
monitor and and maintain
maintain
approach but introduces many shortcomings of of its own. many manydifferent
different device
devicetypes,
types, saves
saves money
moneyand andminimizes
minimizes
This technology
technology requiresrequires l eless s s ppower
o w e r aand s paperwork:
n d i is paperwork. Manufacturing
Manufacturingflow flowisismuch
muchsmoother
smootherbecausebecause
reprogrammable, but but reprogrammability
reprogrammability comes comes at the the handling process
the handling process is greatly simplified.simplified. AA generic generiC
expense of slower speeds. architecture
architecture GAL GAL device
device alsoalso reduces
reduces the the risk
risk of of running
running
out of
out of inventory
inventory and and halting
haltingproduction,
production, whichwhichcan canbe bevery
very
Testability is increased over bipolarbipolar since
since the array expensive.
the "fuse" array expensive. ReducedReduced chance chance of of obsolete
obsolete inventory
inventory and and
can be programmed and tested tested by the manufacturer. The easier
by the easier QA tracking ate
QA tracking are additional
additional benefits
benefits of of the
the generic
generic
problem here ill is the
the long (20 minutes) erase times coupled architecture.
timescoupled architecture.
with the requirement of exposing the the devices
devices to to ultraviolet
ultraviolet
THE IDEAL
THE IDEAL PACKAGE
PACKAGE
light for erasing. This becomes a very
erasing. This very expensive step in in
themanLJfacturing
the manufacturing process.
process. Because ofthe of thetime
time involved,
involved, Programmable
Programmable logic
logicdevices
devicesare areideal
idealfordesigningtoday's
for designing today's
patterning and and erasing
erasing is is performed
performed only only once
once — - a systems. Lattice Semiconductor
systems. Lattice Semiconductor believes believes thatthat thethe ideal
ideal
compromised rather than complete functional functional test. design approach should
design approach should be supported
supported with the the ideal
ideal
products.
products. It It was
was on on this
this premise
premise that that GAL
GAL devices
devices were were
Additionally, the devices must be housed in expensive invented. invented. The The ideal
idealdevice-with
device—withaageneric genericarchitecture-
architecture—
windowed packages to allow users to to erase them. Again, fabricated
them. Again, fabricated withwith thethe ideal
ideal process
process technology,
technology, E2CMOS.
E2CMOS.
programming these these devices
devices is is time-consuming
time-consuming and and
cumbersome due to the 20-minute UV exposure exposure required
required
to erase them. As As a a cost-cutting
cost-cutting measure, UVCMOS UVCMOS PLD PLD
manufacturers offertheirdevices
offe r their devices ininwindowless
windowlesspackages.
packages.
Although windowless packages are less expensive, expensive, they they
cannot be completely tested or reprogrammed. These These
factors significantly
significantly detract from the desirability
desirability of this
technology.
1-2
1-2
Section 1: Introduction to Generic Array Logic 1
Introduction to Generic Array Logic 1 - 1 1-1
Section 2: GAL Datasheets

Datasheet Levels
GAL16V8NB
GAL16VSNB
GAL20V8NB
GAL20VSNB 2
2
2
-
-
-
2
i
1
i
5
2-ii
2-1
2-25
at
GAL18V10
GAL1SV10 2 - 4 7 2-47
GAL22V10/B 2 - 6 1 2-61
GAL26CV12 2 - 8 1 2-S1
GAL2ORA10
GAL20RA10 2 - 9 5 2-95
GAL6001 2 - 1 0 9 2-109
ispGAL16Z8
ispGAL16ZS 2 - 1 2 1 2-121

3
Military Program Overview 3 - 1 3-1
MIL-STD-883C Flow
MIL-STD-S83C 3 - 2 3-2
Military Ordering Information 3 - 3 3-3
GAL16V8NB
GAL 16VSNB Military Datasheet 3 - 5 3-5
GAL20V8A Military Datasheet
GAL20VSA 3 - 1 3 3-13
GAL22V10/B Military Datasheet 3 - 1 9 3-19
GAL2ORA10
GAL20RA 10 Military Datasheet 3 - 2 7 3-27

Quality Assurance Program 4 - 1 4-1
4
Qualification Program 4 - 3 4-3
E2CMOS Testability Improves Quality
FCMOS 4 - 5 4-5

GAL Metastability Report 5 - 1 5-1 5
Latch-up Protection 5 - 1 7 5-17
Section 6: Article Reprints

Avoid the Pitfalls of High-Speed Logic Design 6 - 1 6-1 8
Extending the 22V1
22V10 0 EPLD 6 - 7 6-7
In-Circuit Logic Device Can be Reprogrammed on the Fly 6 - 96-9
Multiple Factors Define True Cost of PLDs 6 - 1 3 6-13

Development Tools 7 - 1 7-1 7
Copying PAL, EPLD & PEEL Patterns into GAL Devices 7 - 37-3
GAL Product Line Cross Reference 7 - 5 7-5.
Package Thermal Resistance 7 - 8 7-S
Package Diagrams 7 - 9 7-9
Tape-and-Reel Specifications 7 - 1 6 7-16
Sales Offices 7 - 1 7 7-17
2-i
2-1
Definition of Datasheet Levels
DEFINITION OF DATASHEET
DATASHEET LEVELS
LEVELS
Datasheet Identification Product Status

Product Status DeflnHlon
Definition
'PA""ii'F't
Preliminary Sampling
Sampling or
Pre-Production
Pre-Production
This
This datasheet contains
data
data will
will be
contains preliminary
be published
published at
preliminary data
at aa later
later date.
data and
and supplementary
date. Lattice
supplementary
Lattice reserves
reserves the
the
right
right to make
make changes
changes at
at any
any time
time without
without notice.
notice.
No Identification Full Production This

This datasheet contains
contains final
final specifications. Lattice reserves
specifications. Lattice reserves the
the
right
right to
to make
make changes
changes at
at any
anytime
time without
without notice.
notice.
2-ii
2-11
[JJtatUce®
Ind /Lattice®
SemioonducWr
Corporation
Corporation
GAL1 6118B
GAL16V8B
GAL1 61113A
GAL16V8A
High Performance E2CMOS
High E2CMOS PLD
PLD
FEATURES FUNCTIONAL BLOCK
FUNCTIONAL BLOCK DIAGRAM
DIAGRAM
• HIGH PERFORMANCE E2CMOS®
ElCMOS· TECHNOLOGY
-— 7.5 ns Maximum Propagation Delay Voc
Vee.
-— Fmax ==100 MHz 20 J
20
-— 5 ns Maximum from Clock Input to
to Data Output
-— TTL Compatible 24 mA Outputs 8 OLIAC 19
19
-— UltraMOS®
UHraMOS· Advanced
Advanced CMOS Technology 19
22 - - D =
• 50%
500/0 to 75')/o
750/0 REDUCTION IN POWER FROM BIPOLAR
-— 75mA Typ I = on Low Power Device
TYP Icc 4 OLMC
18
18
18
-— 45mA Typ TYP lex
Icc on Quarter Power Device 33 — 0 =
• ACTIVE PULL-UPS ON ALL
ALL PINS (GAL16V8B)
OLPAC 17
17
• E2E2 CELL TECHNOLOGY 17
-— Reconfigurable
Reconflgurable Logic
logic 44 - - 0 =
1
-— Reprogrammable Cells OLMC
-1000/0 16
16
— 100% Tested/Guaranteed 100%
1000/0 Yields 16
-— High Speed Electrical Erasure «100ms)
(<100ms) 5 — 0 =
-— 20 Year Data Retention
MAC 15
15
• EIGHT
EIGHT OUTPUT LOGIC MACROCELLS 15
-— Maximum Flexibility
FlexlbllHy for Complex Logic Designs 6
1
-— Programmable Output Polarity OIJAC
-— Also Emulates 2o-pln PAL· Devices with Full Func-
20-pin PAL® 14
14
14
tion/Fuse Map/Parametric CompatlbllHy
tlon/Fuse Compatibility 7
1
• PRELOAD
PRELOAD AND POWER-ON RESET OF ALL
ALL REGISTERS
REGISTERS OLMC 1 3 13
8
-1000/0
— 100% Functional Testability 13
8 =0—
• APPLICATIONS
APPLICATIONS INCLUDE:
-— DMA Control MAC 12
12
-— State Machine Control 12
-— High Speed Graphics Processing 99 — 1 : =
11
-— Standard Logic Speed Upgrade 10
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
DESCRIPTION PIN
PIN CONFIGURATION
CONFIGURATION
The GAL 16V8B, at 7.5 ns maximum propagation
GAL16V8B, propagation delay
delay time,
time,
combines a high performance CMOS process with Electrically DIP
DIP
(E') floating gate technology to provide the highest speed
Erasable (E2)
performance available in the PlD PLD market. High
High speed erase
erase times
times PLCC
PLCC
«100ms)
(<100ms) allow the devices to be reprogrammed quickly and IICLK
I/CLK Vee
Vcc
efficiently. IIOJQ
trOr0
l'CUC
I VO Veos I /roIO
L K Ve 0/0
The generic architecture provides maximum design flexibility
flexibility by E71:1=111
20 11010
1 1/0/0
allowing the Output logic (OLMC) to be configured by
Logic Macrocell (OlMC) 1vOla
110/0
the user. An An important
important subset of the many architecture con· con- VOID
figurations
figurations possible with the GAL 16V8A1B are the PAL archi-
GAL16V8A/B vOla
V0/0
11010
tectures listed in the table of the
the macrocell description section. GAL16V8A/B
GAL16VSAlB
1vOla
1/010
GAL 16V8AIB devices are capable of
GAL16V8A/B of emulating
emulating any of these
these PAL
PAL Top View
Top View 11010
architectures with full function/fuse maplparametric
map/parametric compatibility.
compatibility. 1VOla
IIOJQ
1
Unique test circuitry and reprogrammable cells allow
allow complete
complete 1VO/Q 1 11010
AC, DC, and functional testing during manufacture. As As a result,
result,
LATTICE is able to guarantee 100%1000/0 field programmability and II CIHO rIIOi
ONO VOla tioto
t a tio/o vOla 1 11010
functionality of all GAL·
GAL® products. LATTICE
LATTICE also guarantees 100 aND
GND
erase/rewrite cycles and data retention in in excess of
of 20 years.
Copyright C1991 Lattice Semiconductor Corp. G
01991 Lattice GAL. PCMOS and UlltaMOS
A L E'CMOS regls..rod trademarks
UltraMOS are registered trademarks 01
of lattice Semiconductor Corp.
Lattice Semiconductor GonorIc "ray
Corp. Generic Logic Is
Array Logic is aatrademarl<
trademark of Lattice SeRiconduc·
of Lattlca Semiconduc-
tor
tor Corp. PAL is
Corp. PAL a registered
Is a registered tradomar1< of Advanced
trademark of Micro Dovlcoo.
Advanced Micro Devices, Inc. The specifications
Inc. The and Information
specifications and information heroin
herein are subject to
are subject to change
change without
without noflca.
notice.
Hillsboro, Oregon 97124, U.S.A.

LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, U.S.A. April
April 1991.Rev.A
1991.1:tev.A
Tel. (503) 681-0118: 1-800-FASTGAL;
1-800-FASTGAL: FAX (503)681-3037
(503) 681-3037 2 - 1 2-1
LLattice®
flJ.Semiconductor
Semiconductor
GAL1
Specifications GAL 6118B
16V8B
Corporation
Corporation GAL16118A
GAL 16V8A·
GALII6V8A/B
GAL 16V8A'B ORDERING INFORMATION
Commercial Grade Specifications
Tpd (ns)
Tpd(n8) Tsu (n8)
T8U (ns) Teo (ns) icc (mA)
Icc(mA) Ordering #
Ordering Package
Package
7.5 7 55 115
115 GAL16V8B-7LP
GAL16V8B-7LP 20-Pin Plastic
20-Pin Plastic 01
DIPP
115
115 GAL16V8B-7LJ
GAL16V8B-7LJ 20-Lead PLCC
20-Lead PLCC
10 10 77 115
115 GAL16V8B-10LP
GAL16V8B-l0LP 20-Pin Plastic
20-Pin Plastic DIP
DIP
115
115 GAL16V8B-101—I
GAL16V8B-l0LJ 20-Lead PLCC
20-Lead PLCC
115
115 GAL 16V8A-l OLP
GAL16V8A-10LP 20-Pin Plastic
20-Pin Plastic DIP
DIP
115
115 GAL16V8A-l0LJ
GAL16V8A-10LJ 20-Lead PLCC
20-Lead PLCC
15 12 10
10 55
55 GALI6V8A-I50P
GAL16V8A-15QP 20-Pin Plastic
20-Pin Plastic DIP
DIP
55
55 GAL16V8A-I50J
GAL16V8A-150,1 20-Lead
20-Lead PLCC
PLCC
115
115 GAL 16V8A-15LP
GAL16V8A-15LP 20-Pin
20-Pin Plastic
Plastic DIP
DIP
115
115 GAL16V8A-15LJ
GAL16V8A-15LJ 20-Lead PLCC
20-Lead PLCC
25 15
15 12 55
55 GAL 16V8A-250P
GAL16V8A-25QP 20-Pin
20-Pin Plastic
Plastic DIP
DIP
55
55 GAL 16V8A-25QJ
GAL16V8A-25al 20-Lead
20-Lead PLCC
PLCC
90
90 GAL 16V8A-25LP
20-Pin Plastic
Plastic DIP
DIP
90
90 GAL 16V8A-25LJ
GAL16V8A-25LI 20-Lead
20-Lead PLCC
PLCC
Industrial Grade Specifications

Tpd (n8)
(ns) Tsu(ns)
Tsu (ns) Teo
Tco (ns) Icc
icc (mA) Ordering ##
Ordering Package
Package
10
10 10
10 7 130
130 GALI6V8B-l0LPI
GAL16V8B-10LPI 2O-Pin
20-Pin Plastic
Plastic DIP
DIP
130
130 GAL 16V8B-l0LJI
GAL16V813-10LJI 20-Lead
20-Lead PLCC
PLCC
15 12
12 10 130
130 GAL 16V8B-15LPI
GAL16V8B-15LPI 20-Pin
20-Pin Plastic
Plastic DIP
DIP
130
130 GAL 16V8B-15LJI
GAL16V8B-15LJI 20-Lead
20-Lead PLCC
PLOD
130
130 GAL 16V8A-15LPI
GAL16V8A-15LPI 20-Pin
20-Pin Plastic
Plastic DIP
DIP
130
130 GALI6V8A-15LJI
GAL16V8A-151-11 20-Lead
20-Lead PLCC
PLCC
20 13 11
11 65
65 GAL 16V8A-200PI
GAL16V8A-200PI 20-Pin
20-Pin Plastic
Plastic DIP
DIP
65
65 GAL 16V8A-2OQJI
GAL16V8A-200,11 20-Lead
20-Lead PLCC
PLOD
25 15 12
12 65
65 GAL 16V8A-250PI
GAL16V8A-25QPI 20-Pin
20-Pin Plastic
Plastic DIP
DIP
65
65 GAL 16V8A-25QJ1
GAL16V8A-250J1 20-Lead
20-Lead PLCC
PLCC
130
130 GAL 16V8A-25LPI
20-Pin Plastic
Plastic DIP
DIP
130
130 GAL 16V8A-25LJI
GAL16V8A-25LJI 20-Lead
20-Lead PLCC
PLOD
PART NUMBER DESCRIPTION

DESCRIPTION
XXXXXXXX X X X X X
GAL16V8A D e v i c e Name
GAL16V8B
Speed (ns) _ _ _ _ _ _....J
Speed (ns) lank =
Grade BBlank = Commercial
Commercial
II = Industrial
Industrial
L _ Low Power Power _ _ _ _ _ _ _ _....J ' - - - - - - Package
L = Low Power Power Package PP =Plastic
Plastic DIP
DIP
QQ=-1/4
1/4 Power J.= PLCC
PLCC
2-2
2-2 4/91.Rev.A
4/91.IRev.A
GALI16VBB
1 1 s t Semiconductor
Corporation GAL1
GAL 6118A
16VBA
OUTPUT LOGIC MACROCELL (OLMC)
The following discussion pertains to configuring the output logic

macrocell. ItIt should be noted that actual implementation is
is ac- PAL Architectures
PAL Architectures GAL161/8A/6
GALl6V8AlB
software/hardware and is completely
complished by development softwareJhardware completely Emulated by
Emulated by GAL
GA Ll6V8A/B
16V8A1B Global ollie
Global W I C Mode
Mode
transparent to the user.
16R8
16R8 Registered
Registered
There are three global OlMC
There OLMC configuration modes possible: 16R6
16R6 Registered
Registered
simple, complex, and and registered. Details
Details of each of of these
these 16R4
16R4 Registered
Raglstered
modes is illustrated
illustrated in
in the
the following pages. Two
Two global bits,
bits, SYN 16RP8
16RP8 Registered
Raglstered
16RP6
16RPB Registered
Raglstered
and ACO, control the mode configuration for all macrocells. The 16RP4
16RP4 Registered
Raglstered
XOR bit of each macrocell controls the polarity of the
the output
output in any
of the three modes, while the AC1 bit of of each of
of the
the macrocells 16L8
16La Complex
Complex
configuration. These two global and
controls the input/output configuration. and 16 16H8
18H8 Complex
Complex
individual architecture bits define all possible configurations in a 16P8
16P8 Complex
Complex
GAL 16V8A1B. The
GAL16V8A/B. The information given on these architecture bits 10L8
lOLa Simple
Simple
is only to give a better understanding of the the device. Compiler
Compiler 12L6
1216 Simple
Simple
software will transparently set these architecture bits
bits from
from the
the pin
pin 1414
14L4 Simple
Simple
definitions, so the user should not need to directly manipulate 1612
16L2 Simple
Simple
these architecture bits. 10H8
10H8 Simple
Simple
12H6
12H6 Simple
Simple
14H4
14H4 Simple
Simple
The following is a list of the PAL
PAL architectures that
that the
the GAL 16V8A
GAL16V8A 16H2
16H2 Simple
Simple
and GAL16V8B
GAL 16V8B can emulate. IItt also also shows the OlMCOLMC mode 10P8
10P8 Simple
Simple
under which the GAL16V8A/B
GAL16V8A1B emulates the the PAL
PAL architecture. 12P6
12P6 Simple
Simple
14P4
14P4 Simple
Simple
16P2
16P2 Simple
Simple
COMPILER SUPPORT FOR OLMC

Software compilers support the three different global OlMC OLMC In
In registered
registered mode
mode pin and pin
pin 1 and pin 11
11 are
are permanently
permanentlyconfigured
configured
modes as different device types. These device types are listed as
as clock
clock and
and output
output enable,
enable, respectively. These pins
respectively. These pins cannot
cannotbe
be
in the table below. Most
Most compilers have the the ability
ability to
to automati-
automati- configured
configured asas dedicated
dedicated inputs
inputs in
in the
the registered
registered mode.
mode.
cally select the device type, generally based on on the
the register usage
usage
and output enable (OE) usage. RegisterRegister usage on the device In
Incomplex
complex modemode pinpin 1 and
and pin
pin 11
11 become
become dedicated
dedicated inputs
inputsand
and
forces the software to choose the registered mode. All All combi-
combi- use
usethethe feedback
feedbackpaths
pathsofofpin
pin 19 andpin
19 and pin 12
12respectively. Because
respectively. Because
natorial outputs with OE controlled by the product term term will
will force
force of
of this
this feedback
feedback path
path usage,
usage, pin
pin 19
19 and
and pin
pin 12
12 do
do not
not have
have the
the
the software to choose
choose the complex mode. The The software will feedback
feedback option
option in
in this
this mode.
mode.
choose the simple mode only when all outputs are dedicated
combinatorial without OE control. TheThe different device types
types listed In
In simple
simple mode
mode allall feedback
feedback paths
paths of
ofthe
the output
output pins
pins are
are routed
routed
in the table can be used to override the
the automatic device
device selection
selection via
via the
the adjacent
adjacent pins. In doing
pins. In doing so,
so, the
thetwo
two inner
inner most
mostpins
pins ((pins
pins
by the software. For
For further details, refer to
to the compiler
compiler software
software 15
15 and
and 16)
16) will
will not
not have
have the
the feedback
feedback option
option as
as these
these pins
pins are
are
manuals. always
always configured
configured as dedicated
dedicated combinatorial
combinatorial output.
output.
When using compiler software to configure the device, the user

must pay special attention to the
the following
following restrictions in each
mode.
Registered Complex Simple

Simple Auto
Auto Mode
Mode Select
Select
ABEL P16V8R
P1 6V8R P16V8C
P16V8C P16V8AS
P1 6V8AS P16V8
P1 6V8
CUPL G16V8MS G16V8MA
G1 6V8MA G16V8AS
G1 6V8AS G16V8
G1 6V8
LOG/IC GAl16V8
GAL16V8_13R GAl16V8
GAL1 6V8S7C7 GAl16V8
GAL16V8S8 C8 GAL16V8
CALI 6V8
OrCAD-PLD
OrCAD- PLO "Registered"'
"Registered"' "Complex"'
"Complex"' "Simple"'
"Simple"' GAL16V8A
GAL16V8A
PLDeslgner
PLDesigner P16V8R2
P1 6V8R2 P16V8C2
P1 6V8C2 P16V8C2
P16V8C2 P16V8A
P1 6V8A
TANGO-PLD G16V8R
G1 6V8R G16V8C
G1 6V8C G16V8AS3
G16V8AS3
AS G16V8
G1 6V8
1) Used with Configuration
1) Used Configuration keyword.
keyword.
2) Prior to Version
2) Prior Version 2.0
2.0 support.
support.
3) Supported
Supported on Version 1.20 or later.
2-3 4/91.Rev.A
4/91.Rev.A
GAL161/13B
Specifications GAL 16VBB
1 1 1 "itt e r ;
Corporation GAL116VBA
GAL 61113A
REGISTERED MODE
In the Registered mode, macrocells are configured as dedicated mode. Dedicated input
mode. input or
oroutput
outputfunctions
functions can
can be
be implemented
implemented
registered outputs or as
as I/O functions. as subsets
as subsets of the VO
of the I/Ofunction.
function.
Archkecture
Architecture configurations available in this mode are similar to
to Registered
Registered outputs
outputs have
have eight
eightproduct
product terms
terms per
per output. VO's
output. VO's
the common 16R8 and 16RP4 devices
devices with
with various
various permutations
permutations have
have seven
seven product
product terms
terms per
per output.
output.
VO and register placement.
of polarity, I/O
The
TheJEDEC
JEDECfuse fusenumbers,
numbers, including
includingthe
theUser
UserElectronic
ElectronicSignature
Signature
All registered macrocells share common clockclock and
and output
output enable
enable (UES)
(UES) fuses
fuses andand the
the Product
Product Term
Term Disable
Disable (PTD)
(PTD) fuses,
fuses, are
are
control pins. Any
Any macrocell can be configured as registered or shown
shown onon the
the logic
logic diagram
diagram onon the
the followihg
following page.
page.
VO. Up to eight registers or up to
I/O. Up eight VO's
to eight I/0's are
are possible
possible in
in this
this
ClK
CLK
---____ .-------.. . . . . . . . -------.. . . . . . -- -----! Registered
Registered Configuration
Configuration for
for Registered
Registered Mode
Mode
-SYN=O.
- SYN=0.
-ACO .. 1.
ACO-1.
-- XOR",O
XOR-0 defines
defines Active
Active Low
LowOutput.
Output.
-- XOR
X0R-1..1 defines Active
Active High
High Output.
Output.
-- AC1 ",0 defines
AC1-0 defines this
this output
output configuration.
configuration.
-- Pin
Pin 1 controls
controls common
common CLK CLKfor
forthe
the registered
registered outputs.
outputs.
-- Pin 11 controls
Pin 11 controls common
common OE OE for
forthe
the registered
registered outputs.
outputs.
·· .. -- Pin
Pin 1 &
OE.
OE.
& Pin 11 are permanently
Pin 11 permanently configured
configured asas CLK
CLK &
&
.. --------.---- . -. -----------.
OE
OE
..... -- .. - .. _- ...... -- ........ -- ...... - ..... .

Combinatorial
Combinatorial Configuration
Configuration for
for Registered
Registered Mode
Mode
-SYN",O.
- SYN=0.
-ACO=1.
- AC0=1.
- XOR
XOR=0 ..Odefines
defines Active
Active Low
Low Output.
Output.
-- XOR
XOR-1 ..1 defines Active
Active High
High Output.
Output.
-- AC1
AC1-1=1 defines this
this output
configuration.
-- Pin
Pin 11 & Pin 11 are permanently
Pin 11 permanently configured
configured as
as CLK
CLK &&
OE.
OE.
Note: The development software configures all

all of
of the
the architecture
architecture control
control bits and checks
checks for
for proper
proper pin
pin usage
usage automatically.
automatically.
2-4
2-4 4191.Rev.A
4/91.Rev.A
Lattice® GAL161/13B
Specifications GAL 16V8S
1.,.;
LISemiconductor
Semiconductor
GAL 16V8A
Corporation
REGISTERED MODE LOGIC DIAGRAM
.....
DIP &
DIP & PLCC
PLCC Package Pinouts
Plnouts II
I
J
2126
!
0 44 8 8 2 12 1 6 2 020 24
2 4 2 62tI P pm
M
" I.
0000
00(81
1111111111111111111111111M111011 §: OLMC 19
OLMC 19 1 "...,.,
—t>0— C 1 119
9
022'
0224
:§: X0A-2048
XOR·2048
IInumm•Immommommommo
I II
AC1-2120
AC1·2120
0256
0256
1r>0
-
OLIAC 18
OLMC 18 18
0480
X0R-2049
XOR·2049
AC1•2121
AC1·2121
0512
0512
:g: OLMC 17
OLMC 1 C 1117
7
073<
0736 :§:
411mommi
H U M ' XOR•2050
XOR·1050
4E C . ; 3 AC1·2122
AC1.2122
lu
1
0768
0765
IIMIIMMIIIIIIIM1111111111111111111111 OLMC 16 n
OLMC 16 16
0992
D
0912
mmumuni munnimummlionitin XOR·1051
XOR-2051
AC1·2123
AC1-2123
1024
1024
111111111111111111111111111MIIIMERIE
! : ! M I W I T U I L I I I : = P W • • • • • • • " ' " ' " ' "§:
=••••
OLMC15
OLMC 15 1 ....... 1515
.-....
1248
1240 UIUIIIIIIIUIIIII :::IMMIMEMEM1111
zuranraurzmiziEziFFETF:==ii
1110111111101111•1111111191 111k1 11 9 1 1 1 1 1 1 1 f i r r i l i i i
- XOR·1052
XOR-2052
AC1·2124
AC1-2124
1280
1200
1111111111111111111 M I 6 1·
IIIlIIIIIItlIIIIIlIIIlIUItlIIIIII .......
s: M K 14
OLMC 14 -1)0 K J 14
14
1504
::c
D
1504
iiiimiiiiiummol
IME111•1111•11111111111111111
miumummol: .If
XOR·1053
XOR-2053
AC1·2125
AC1-2125
HIIIIIIIIIIIIIIIIIII111111MI6
,,3<
1536
EimimprommErpanur.::;==3222
,..,. OLMC 13
M C 13 1 ....... 1313
1760 §:
1760
nunimmommunnim XOR·1054
X0R-2054
AC1·2126
AC1-2120
IIIIHIIIIIIIHIIIIIHIII 111111E16
1792
1792
IIIIIIMIIIIIIMIIM11111111111111111111
ESEESEEMEMBEFERF-7:=Ersz OLMC 12
OLIE 12 1 12
2016
limmoommoomummol I!S.:::;
-
2016 XOR·1055
.-.... XOR-2055
1111•11111•111111EMEIIIIMIBIEIMEI AC1·2127
AC1-2127
A OE,....,
11
2191
fI4.USEII ElECTRONIC SIGNA
04-USER ELECTRONIC lURE FUSES
SIGNATURE FUSES
12068, 2057, ..•. .... 211 21181
.. 2118
2118, SYN·2192
SYN-2192
Byte71Byte8
Byte7-1Byte ....B y t e 11Byte 0 ACO·2193
A00-2193
M
M L
S5 5 S
B
B BB
4/91.Rev.A
4/91.Rev.A
2-5
2-5
[JJ
.Ii
.
l.J
Lattice-
/Lattice
Semiconductor
Semiconducwr
GAL1
Specifications GAL 61MB
16V8B
Corporation
Corporation . GALI16V8A
GAL 6118A
COMPLEX MODE
In the Complex mode, macrocells are configured as output only pability. Designs
pability. requiring eight
Designs requiring eight I/O's
I/0's can
can be
be implemented
implemented in
inthe
the
or I/O
110 functions. . Registered mode.
Registered mode.
Architecture configurations available in

in this
this mode are similar to
to All
All macrocells
macrocells have
have seven
sevenproduct
product terms
terms per
peroutput.
output. One
One product
product
the common 16L8 and 16P8 devices withwith programmable polarity
polarity term is
term is used
usedfor
for programmable
programmable output
output enable
enable control.
control. Pins and
Pins 1 and
in each macrocell. 11
11 are always
always available
available as
as data
data inputs
inputs into
into the
theAND
AND array.
array.
Up to six I/O's
I/0's are possible
possible in
in this
this mode. Dedicated
Dedicated inputs
inputs or
or The
TheJEDEC
JEDECfuse
fuse numbers
numbers including
includingthe
the UES
UESfuses
fusesand
andPTD
PM fuses
fuses
outputs can be implemented as subsets of the I/O function.
function. The are shown
are shown on
on the
the iogic
logic diagram
diagram on on the
thefollowing
following page.
page.
two outer most macrocells (pins 12 & 19) do not have input ca-
ca-
·......................................................
·
,
.. Combinatorial I/O Configuration
Combinatorial 1/0 Configuration for
for Complex
Complex Mode
Mode
-- SYN.1.
SYN=1.
-ACO-1.
• AC0=1.
-• XOR.O
XOR=0 defines
defines Active
Active Low
Low Output.
Output.
-- XOR.1 defines Active
XOR=1 defines Active High
HighOutput.
Output.
-AC1-1.
-AC1=1.
-- Pin
Pin 13
13 through
through Pin
Pin 18 are
are configured
configured to
to this
thisfunction.
function.
,
..................................................... .
....................................................,
: : Combinatorial
Combinatorial Output
Output Configuration
Configuration for
for Complex
Complex Mode
Mode
Pr7R ·
- SYN.1.
SYN-1.
-ACO-1.
- AC0=1.
-- XOR.O
XOR=0 defines
defines Active
Active Low
Low Output.
Output.
-- XOR
XOR=1.. 1 defines Active
Active High
High Output.
Output.
-- AC1-1.
AC1=1.
-- Pin
Pin 12 and Pin 19
and Pin 19 are
are configured
configured to
to this
this function.
function.
...............................................................:

all of
of the architecture control bitt;
bits and
and checks
checks for
for proper
proper pin
pin usage
automatically.
2·6
2-6 4/91.Rev.A
4/91.Rev.A
[[J
I Ld
.J.,,; S
/aLatuoo
em
t tc
iiocnd
SemJoonducUJr
Corporation
eu
co
tr e
GAL116VBB
GAL16118A
GAL 16VBA
COMPLEX MODE LOGIC
LQGIC DIAGRAM
DIAGRAM
& PLCC Package Pinouts
DIP & Pinouts
..., ...
v
.... • • 4 a8 12
12 11
16 20 24
24 2B
28
mJ
PTD
2128
0000
.224
0224
:i=t::=
=1::$
:B=
OLIAC 19
OLMC 19
XOR·2048
X0R-2048
n L:119
':::1
AC1-2120
AC1·2120
D-
.251
0256
<= OLMC 18
OLJAC18 n .... 18
D--
D<8O
0480
-. XOR·2049
X0R-2049
AC1·2121
AC1-2121
0512
0612
:a= M C 17
OLMC 17 n 117
.-...
...,
.731
0716 XOR·2050
XOR-2050
AC1-2122
Ad1-2122 U
.788
-
0768
:R:::::=:
OLMC 16
OLJAC16 Il. -0116
.-...
...,
0902 XOR·2051
X011-2051
ACl·2123
AC1-2123 U
P.M I I1024I I M
I I IIMI E
I I' 11111111111111"1
InEmommillommunmunumm-a:l'•
1024
<= OLMC15
IIIEFEEMEISESIEMEIREIREBE-.- OLMC 15 Il.....L>oJ E l 15
1241 HIEIHEE:BilialhEnarmain==E=
1248 -0--;.... XOR·2052
X0R-2052
D - k IHIMM111111111111111111111111M AC1·2124
Ad1-2124
IIIII IIIIIIIIIIII 111111111ln

limiumumpmemmEsimmoneom
Il
l!SO
1280
.-...
'--'
150.
1604
INEINES:SittwastunignmEEEE OLMC
INEWMISEMETME:::E:::::=E=--
=1111111111•111110•11111•1111M
11 M i 1n i m. u m 0 1'
I
1 11 1 1
.1
M
-0--;....
1
14
OLJAC14
XOR·2053
X0R-2053
AC1:2.125
AC1-2125
v
J-G 14
14
1531
1536
1
is1im
11muumummommegunnomommE
1111111111111011111111111
ISESEEMENEEMILINIMITME= n ,....,.
D-
176.
1760
eitemommusemi1 muelb:
§= OLMC 13
MAC 13
-: XOR·2054
X011-2054
AC1·2126
AC1-2126
J- 13
13
IIIIIIIIIIIIIIIIIIIIIIIIIi11111
17112
1792
111111111111111111111111111111111111111111111211•11
SIEREMEESERIBEHEISEIESEE=
ISEIRSHIESISEIMIFIEESI0=E—
B==
OLMC 12
OLPAC12 n -a
— 1....> c * K . : 3 12
12
- 2011 XOR·2055
X0R-2055
rr
' --'
2016
iiiMiiiiiIIIIiiiiIIIIIMBI IN . .
i i imnamonautuommilimuseimam.41 AC1·2127
AC1-2127
l a 11
21"
2191
84-USER ELECTRONIC
II4-USER ELECTRONICSIGNATURE
SIGNATURERJ8fiS
FUSES
12068,2067.....
2058, 2057, .... 2118.2"'1
....2118, 2119 SVN·2192
SYN-2192
Byte7 I'Byte
By\! By\! • ....B y 11
t .... eBy\! 1 IBy\!
Byte00 . ACO-2193
ACO-2193
II
M LL
SS SS
B
B BB
2-7 4191.Rev.A
4/91.1Rev.A
[JJ
'L tattiOO-
.
Lattices
Semiconductor
SemkxJnductor
Corporation
Corporation
GAL1
Specifications GAL 61/8B
16V8B
GAL161/8A
GAL 16V8A
SIMPLE MODE
In the Simple mode, macrocells
macrooells are configured as dedicated inputs Pins 1 and
Pins and 1111 are always available
are always available as
as data
data inputs
inputs into
intothe
theAND
AND
or as dedicated, always active, combinatorial outputs. array. The center
array. centertwo
two macrocells
macrocells (pins
(pins 15
15 &
& 16)
16) cannot
cannotbe beused
used
as input or
as or I/O
I/O pins,
pins, and
and are
areonly
only available
available as
as dedicated
dedicated outputs.
outputs.
in this
to
the common 10L8
10la and 12P6 deviCes
devices with many permutations of of TheJEDEC
The JEDECfuse
fusenumbers
numbers including
includingthe
the UES
UESfuses
fusesand
and PTD
PTDfuses
fuses
generic output polarity or input choices. are shown
are shown on
on the
the logic
logic diagram.
diagram.
All outputs in the simple mode have a maximum

maximum of eight
eight product
product
terms that can control the logic. In addition, each
logic. In each output has
has
programmable polarity.
Combinatorial
Output with
with Feedback
Feedback Configuration
Configuration
Vcc for Simple
for Simple Mode
Mode
•
---+--\ -SYN=1.
- SYN=1.
-ACO.O.
- AC0=0.
-- XOR.O
XOR=0 defines
defines Active
Active Low
Low Output.
Output.
• - XOR
XOR=1.. 1 defines
defines Active
Active High
High Output.
Output.
XO R --AC1
AC1.0 =0 defines
defines this
this configuration.
configuration.
--All
All OlMC
OLMC except
except pins
pins 15 & 16
15 & 16 can
can be
be configured
configured to
to
this
this function.
function.
t. __ ... __ ....... _............................... j
;._- ..........................................
Combinatorial
Configuration for
for Simple
Simple Mode
Mode
Voo
-- SYN=1.
SYN=1.
-ACO.O.
- AC0=0.
-• XOR=O
XOR.0 defines
defines Active
Active Low
Low Output.
Output.
-- XOR
XOR=1.. 1 defines
defines Active
Active High
High Output.
Output.
-- AC1-0
AC1=0 defines
defines this
this configuration.
configuration.
-- Pins
Pins 15
15 && 16 are
are permanently
permanently configured
configured to
tothis
this
... __ ................... _-
'............ _.............. _ function.
function.
Dedicated
Dedicated Input
Input Configuration
Configuration for
for Simple
Simple Mode
Mode
-SYN.1.
- SYN=1.
-ACO.O.
- AC0=0.
-- XOR=O
XOR.0 defines
defines Active
Active Low
Low Output.
Output.
-- XOR
XOR=1 .. 1 defines
defines Active
Active High
High Output.
Output.
--AC1
AC1=1 .. 1 defines this
this configuration.
configuration.
--All
All OlMC
OLMC except
except pins
pins 15 & 16
15 & 16 can
can be
be configured
configured to
to
this
this function.
function.
Note:
Note: The
The development
development software
software configures
configures all
all of
of the
the architecture
control bits
bits and
and checks
checks for
for proper
proper pin
pin usage
automatically.
2-8
2-8 4/91.Rev.A
4/91.Flev.A
Lattice® I 6118B
Specifications GAL 16V8B
1..1 Corporation
Semiconductor
Semronductor
Corporation GAL1
GAL 6118A
16V8A
i
I
SIMPLE MODE LOGIC DIAGRAM
L..I v
...
, •
DIP &
DIP
I
& PLCC Package Pinouts
"
1
Plnouts
1
11 II .. "a iI:a:::::::
218
OLMC 19
OLMC 19
IJ
- I
,.....,
...
0224
XOR-2048
XOR·2Q.48
AC1-2120
AC1·2120
v K1;119
-01
""
l
-
111•11111111111111111111111111111111•111 OLMC 1 8
OLMC18
iiirEINSFEHEETEMENEE H=
XOR-2049
XOR·2Q.49 C:I18
-01
3ED C - , 3 iiiiiiiiiiiiiiiliuiliuiiiiiii
1<=
......---- AC1-2121
AC1·2121
-
't612
512 111 • 11111111111111111111 • 111111 M E M I l l
•:1:=:::=::=LILIM::=1:::71:::=L1==Zammum
••••••••=mmosoommoom••••••••••••••••••mom
••••••••ammfogemoommoomalomoomotoommemEnum••=mo,
:!3= OLMC
OLMC 117
7
X011-2050
XOR·2050
J 17
••••••••••••••olammemsommosoamm.monmemnem••
0738 ••••••••••moistmealooloommeemmemdmoloosammo• :§=:
l l m''''i l l Ai n i imunummommilum-
m o n . o
tm
g
AC1-2122
AC1·2122
111111111 i l l i i i i i i i i i i i i i
''''
0768
111111111111111•1111•1111•111•111111111
:gmisioneskaymmimemonommamm000loomm••=mmo••••••
::=:::=::=1:=1=:::=:::=:::=M•Z=
•••••••••••••miamonowneen••••••••••••••=mooZmom
OLMC 16
XOR·2051
IJ IS
.---. "'" 111 . 111 . 111 . 1 1 . 1 1 1 0 1 1 1 . 1 1 1 . 1 1 1 . .

MINI : 4 1 1 E 1 1 B M
AC1·2123
,.,. I I I I I I I I I I I I I 11111111111111011
1024
i l i E l l i n i n . M . M . M . i i i i n i n i t i . 1 4 1 .
•••••••••••••=1.••••••••••••••••mommonmEnZonum
11•1•••••••1•••••••••••=0•••••••••••••IMI•••111MIEM...ONEEMEI
••••••••=••••••••••••••••••••••••••1011100EIMMEMN.MIME
• • 1 1 1 • • • • • • • • • • • • = • • • = • • • • • • • • . • • • • • = 2 0 6 1 . , • • • • • • •
OLMC
OLMC 115
5
X0R-2052
XOR·2052
11 v - 0 15
'''' AC1·2124
= =
1248 AC1-2124
D 1 1 1 . 1 1 1 . 1 1 1 1 1 1 1 . 1 I I I I I I I I I I I I I .
*Olin . 1 1 1 1 1 1 1 1 • 1 1 1 1 1 1 1 1 • 1 1 1 1 1 1
I*
4
I.l
IIIIIIIIIIIIIIIII 11101110111
'2!D
1280
luniummoinomonenummumo OLMC
OLMC 14
1<=
MIMIIIIMEIMMENER-E1=— XOR·2053
XOR-2053 v - 0 14
,SOl
1504 =c::: AC1·2125
AC1-2125
D liM111111111111111111101
nuesonommosoo A
I M InI I I I IsI I Ea m
lo
e
s
u
m
IJ
's:!6
15,3t I I I I I I I I I I I I I I I I I I I I I 111111111
immunnantommlimilminni -=- OLMC
OLMC 113
3
arzanrancan===t1rmuram::====
:§:::::: XOR·2054
XOR-2054 v - 0 13
13
IJ..
1760 AC1·2126
.r--.. iiMiiMMIEMEME11119 inillill .-:.
nommommoommonmaimm •usommt:411
AC1-2126
I___
'102
1122
mi•==8= ""ammo
.......,ano...,
mon...."mommi
OLMC
OLMC 112
2
XOR·2055
XOR-2055
I.l -........
v 12
12
,." Emlom —mom
unnoCamo AC1·2127
ACI -2127
- 11111•111•111111•1111=11101111111111•1 1111111111A
I'" 1111
84-USER
64-USEREl£CTRONIC
ELECTRONICSIONATURE
SKINAIUREFUIES
FUSES
12056, 2057, •.•• •....2118,2110
•.• 2118, 211P
11
I SYN·2192
SYN-2192
ACO·2193
BYte718y1e
EIy!e 71%11 8e .•. B y t••• eEIy!e 11EIy!e
Byte 00 . AC0-2193
M L
hi
SS SS
B
B BB
2-9
2-9 4 / 9 1 4/91.Rev.A
•Rev.A
[JJ
.l..J
'LatUoo@
LLattice® Semiconductor
Semiconductor
Corporation
Corporation
GALI16V8B
Specifications GAL 61/13E3
Commercial
Commercial
ABSOLUTE MAXIMUM RATINGS0)
RATINGS(1) RECOMMENDED OPERATING
RECOMMENDED OPERATING CONDo
COND.
Supply voltage Vcc — 0 . 5-0.5 to
Vee ....................................... to +7V
+7V Commercial
Commercial Devices:
Input voltage applied ...........................
— 2 . -2.5 5 to to Vcc
Vee +1.0V Ambient Temperature
Ambient Temperature (TAl
(TA)................................
0 to 75°C
0 to 75°C
Off-state
Off -state output voltage applied ..........— 2-2.5 . 5 toto Vee
Vcc +1
+1.0V
.OV Supply voltage
Supply voltage (Veel
(Vcc)
Storage Temperature .................................
— 6 5 -65 to 150°C with Respect
with Respect to
to Ground
Ground ......................
+ 4 . 7+4.75 5 to to +5.2SV
+5.25V
Ambient Temperature with
— 5 5 -55 to 125°C
Power Applied ........................................
1.Stresses
1°Stresses above those listed under the the "Absolute
"Absolute Maximum
Ratings·
Ratings" may cause permanent damage to to the device. These
These
are stress only ratings and functional operation of the
the device
device
at these or at any other conditions above those indicated in
in the
the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
programming.
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating
Operating Conditions (Unless Otherwise
Otherwise Specified)
Specified)
SYMBOL PARAMETER CONDITION

CONDITION MIN.
MIN. TYP.'
TYR' MAX.
MAX. UNITS
UNITS
VII_
VIL Input Low
Low Voltage
Voltage Vss-0.5
Vss –0.5 -— 0.8
0.8 VV
VIH
V1H Input High Voltage 2.0
2.0 -— VCC+1
Vcol-1 VV
ILI
IlL' Input or 1/0
I/O Low
Low Leakage
Leakage Current OV
OV5S_VIN
VIN 5S_VII_
VIL (MAX.)
(MAX.) -- -- -1 oo
-100 RA
Illi
IIH Input or 1/0
I/O High Leakage Current 3.SV
3.5V S VIN S
s. VIN Vcc
5 VCC -
— -— 10
10 IlA
RA
VOL Output Low Voltage IOL
lot_..= MAX. Vin
MAX. Vi n ..= VIL
VII_or
or VIH
Vii-i -— -— 0.5
0.5 VV
VOH Output High Voltage IOH
ION..
= MAX. Yin = VII_
MAX. Vin VIL or VIH
or VIH 2.4
2.4 -— -— VV
10L
IOL Low Level Output Current -— -— 24
24 mA
mA
10H High Level Output Current -— -— -3.2
–3.2 mA
mA
los·
10S2 Output Short Circuit Current Vcc=5V YOUTz= O.SV
Vcc = 5V VOLIT TA= 25°C
0.5V TA= 25*C -30
–30 -— -150
–150 mA
mA
ICC
Icc Operating Power Supply Current VIL=
\in_ = 0.5V ViH =
0.5V VIH = 3.0V ftoggle ..= 2SMHz
3.0V ftoggle 25MHz -— 75
75 115
115 mA
mA
Outputs
Outputs Open
Open (no
(no load)
load)
1) The leakage current is due to the internal pull-up resistor
resistor on
on all
all pins. See Input Buffer
pins. See Buffer section
secfon for
for more
more information.
information.
2) One output at a time for a maximum duration of one second. Vout ..0O.SV
second. Vout . 5 V was
was selected
selected to
to avoid
avoid test
test problems
problems caused bytester
caused by tester
ground degradation. Guaranteed
Guaranteed but not 100%
100*k tested.
3) Typical values are at Vee
Vcc ..
= 5V
5V and TA== 25°C
and TA 25 'C
(TA = 2.5°C,
CAPACITANCE (TA 25°C, f = 1.0 MHz) =
SYMBOL PARAMETER MAXIMUM"
MAXIMUM* UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
C, Input
Input Capacitance 88 pF
pF Vcc -= 5.0V.
Vcc 5.0V, V,
V,..= 2.0V
2,0V
Ciic
C'iO 1/0
I/O Capacitance 88 pF
pF Vcc =5.0V.
Vcc = 5.0V, VIIO -2.0V
Vito = 2.0V
'Guaranteed
*Guaranteed but not 100% tested.
2-10
2-10 4191.Rev.A
4/91.RevA
[JJ
J.J,
Sem iconductor
LatUCC
'Lattice® SemiconduCUJr
Corporation
CorporaUon
Gl
Specifications GAL
GAL161/8B
16V8S
Commercial
AC SWITCHING CHARACTERISTICS
Recommended Operating
Over Recommended Operating Conditions
Conditions
TEST -7
-7 -10
-10
PARAMETER DESCRIPTION UNITS
UNITS
CONDI.
COND'. MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX.
tpd 11 Input or I/O to Combinational Output
Output I 88 outputs
outputs switching
switching 33 7.5
7.5 33 10
10 ns
ns
J 11output switching
switching -
— 77 -
— - — ns
ns
tco 11 Clock to Output Delay 22 55 22 77 ns

ns
tcf2
tcf' -— Clock to Feedback Delay -
— 33 -
— 66 ns
ns
tsu -— Setup Time, Input or Feedback before

before Clock"
Clocki 77 -— 10
10 -— ns
ns
th -— Hold Time, Input or Feedback after Clock"

Clocki 00 -— 00 -— ns
ns
11 Maximum Clock Frequency with 83.3
83.3 -— 58.8
58.8 -— MHz
MHz
External Feedback, 1/(tsu + teo)
tco)
fmax33
fmax 11 Maximum Clock Frequency with 100
100 -— 62.5
62.5 -— MHz
MHz
Internal Feedback, 1/(tsu + tcf)
tcf)
11 Maximum Clock Frequency with 100
100 -— 62.5
62.5 -— MHz
MHz
No Feedback
twh4
twh -— Clock Pulse Duration, High
High 55 -— 88 -— ns
ns
tw14
twt' -— Clock Pulse Duration, Low 55 -— 88 -— ns
ns
ten 2 Input or I/O to Output 33 99 33 10
10 ns
ns
22 OE.!.
0E,I, to Output 22 66 22 10
10 ns
ns
tdis
td is 33 Input or I/O to
to Output 22 99 22 10
10 ns
ns
3 °ET to Output
OE" 1.5
1.5 66 1.5
1.5 10
10 ns
ns
i) SWitching Test Conditions section.
1) Refer to Switching section.
!) Calculated from imax
fmax with internal feedback.
feedback. Refer to fmax Descriptions section.
section.
I) Refer to fmax Descriptions section.
I)
t) Clock pulses of widths less than the specification may be detected as
as valid clock
clock signals.
signals.
SWITCHING TEST CONDITIONS

CONDITIONS
Input Pulse Levels GNDto
GND to 3.0V +5V
+5V
Input Rise and Fall Times
Times 3ns
3ns 10%-90%
10'/0 – 90%
Input Timing Reference Levels 1.SV
1.5V
Output Timing Reference Levels 1.SV
1.5V
Output Load See
See Figure
I-state
-state levels are measured 0.5V
O.SV from steady-state active FROM OUTPUT (0/0)
FROMOUTPUT (0/0) - -.....- -....-TESTPOINT
TESTPOINT
°vol.I.
eve UNDER TEST
UNDERTEST
)utput Load Conditions (see figure)
R2
Test
Test Condition Rl
131 Rz
R2 CL
CL
11 200n
2000 390n
3900 SOoF
50pF
2 Active High
Active High .0 3900
3900 SOpF
50pF
Active Low 200n
200c1 390n
390c2 SOpF
50pF
3
3 Active High
Active High ,,. 3900
39012 SpF
5pF C
CLLIN
INCLUDES
CLUDESJIG AND
JIGANDPPROBE
ROBETTOTAL
OTALCCAPACITANCE
APACITANCE
Active Low 200n
2000 390n
390c2 SpF
5pF
2-11
2-11 4191.Rev.A
4/91.Rev.A
LILattice
'L Semiconductor
C()IJXX'aUOIl
Corporation
Specifications GAL
GAL1 61/8A
16V8A
Commercial
Commercial
ABSOLUTE MAXIMUM RATINGS(l)
RATINGS') RECOMMENDED OPERATING
COND.
Supply voltage Vcc
Vee .......................................
— 0 . 5-o.5to to +7V Com Commercial
m e r c i a l Devices:
Devices:
— 2 . -2.5to
5 to Vee
Vcc +1.0V
+1.0V A m Ambient
b i e n t Temperature
Temperature (T(TA) 0
A ) •••••••••••••••••••••••••••••••• 0 to
to 75°C
75°C
Off-state output voltage applied .......... — 2-2.5 . 5 to Vee
Vcc +1.0V
+1.0V S u Supply
p p l y voltage (Vee)
(Vcc)
— 6 5 -65 to 150°C w i twith
h Respect to to Ground ......................
+ 4 . 7+4.75 5 to to +5.25V
+5.25V
— 5 5 -55 to 125°C
Power Applied ...•....................................
1.Stresses above those listed under the the "Absolute
"Absolute Maximum
Ratings'. may cause permanent damage to
Ratings" to the
the device.
device. These
These
are stress only
only ratings and functional operation
operation of the device
device
or at any other conditions
at these or conditions above those
those indicated
indicated in
in the
the
programming.
Over Recommended Operating Conditions (Unless Otherwise
Over Otherwise Specified)
Specified)

CONDITION MIN.
MIN. TYP}
TYP.2 MAX.
MAX. UNITS
UNITS
VIL
VIL Input Low Voltage
Input Vss – 0,5
Vss-O.5 -- 0.8
0.8 VV
VIH Input High Voltage 2.0

2.0 -— Vcc+l
VcC+1 VV
IlL
IlL Input or 1/0
Input Low Leakage Current
I/O Low Current OV VIN S5 VIL
OVSVIN VII, (MAX.)
(MAX.) -- -- -10
-10 p.A
I1A
IIH Input or
or 110
I/O High Leakage Current VIHS5 VIN
VIH VIN S5 VCC
Vee -— -— 10
10 ixA
I1A
VOL Output Low Voltage
Voltage 10L=MAX. Yin
l a = MAX. Vi n == VIL
Vit. or
or VIH
VIH -— -— 0.5
0.5 VV
VOH Output High Voltage loH = MAX.

IOH MAX. Vi n == VILor
Yin VII. or VIH
VIH 2.4
2.4 -— -— VV
10l
10L Low level
Level Output Current -— -— 24
24 mA
mA
–3.2 mA
mA
los'
lost Output Short Circuit Current Vcc=5V VOUT
Vcc = 5V Va i l ' == 0.5V TA=
0.5V TA =25·C
25°C -30
–30 -— -150
–150 mA
mA
Operating Power
Power VIL=
ViL = 0.5V VIH=3.0V
0.5V VIH = 3.0V ftoggle
floggie =
= 15M
1 5 M Hz
Hz LL -25
-25 -— 75
75 90
90 mA
mA
Icc
iCC Supply Current Outputs
Outputs Open (no load) floggle
(no load) fungi° == 25MHz
25MHz L-10/-15
L -10/-15 -— 75
75 115
115 mA
mA
ftoggle = 15MHz
ftoggle = 15MHz
I Q
Q -15/-25
-15/-25 -— 45
45 55
55 mA
mA
1}
1) One output at a time for a maximum duration of one second. Vout
Vout == 0.5V
0.5V was
was selected
selected to
to avoid
avoid test
test problems
problems caused
caused by
by tester
tester
Guaranteed but not 100'/0
100% tested.
tested.
2) Typical values are at Vcc = 5V
5V and TA
TA = 25
25 ·C
'C
CAPACITANCE (TA
(TA = 25°C, =
25°C, ft = 1_0
1.0 MHz)
MHz) =
SYMBOL PARAMETER
PARAMETER MAXIMUM'
MAXIMUM* UNITS
UNITS TEST
TESTCONDITIONS
CONDITIONS
C, Input
pF Vcc =
Vee = 5.0V.
5.0V, V,
Vi == 2.0V
2.0V
Cm
Coo ilO
I/O Capacitance 10
10 pF
pF Vee
Vcc== 5.0V. VIJO
5.0V, V1 10== 2.0V
2.0V
'Guaranteed
*Guaranteed but not 100"/0
but not 100% tested.
tested.
2-12
2-12 4!91.Rev)
4/91.Rev.i
I
1 6118A
Specifications GAL 16VBA I:
I m d Semiconductor
t ®
Corporation Commercial
Commercial
1 AC SWITCHING CHARACTERISTICS
Over Recommended
OVer Recommended Operating Conditions
Conditions
..•
-10
-10 -15
-15 -25
-25
TEST DESCRIPTION
PARAMETER UNITS
UNITS
CONDt.
COND'. MlfIC
MI )ftAx.
AX. MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX.
tpd 11 to Combinational Output
Input or I/O to Output 33 •' 10
10 33 15
15 33 25
25 ns
ns
tco
teo 11 Clock to Output Delay 22 ,; 77 22 10
10 22 12
12 ns
ns
,
1 t c ftcf2
2 -— to Feedback Delay
Clock to -
—i 7 - 88 -— 10
10 ns
ns
tsu -— Setup Time, Input or Feedback before

Input or before Clocki
Clockt 10
10 -— 12
12 -— 15
15 -— ns
ns
- Hold Time,
Time, Input or
or Feedback
Feedback after
after Clocki
ClockT 0
= -- - ns
58.8 =-
th - Hold - 00 00 - ns
o
11 Maximum Clock Frequency with
External Feedback,1/(tsu
with
tco)
Feedback, 1f(tsu + teo) all . - 45.5
45.5 -- 37
37 -- MHz
MHz
tmax33
fmax 11 Maximum Clock Frequency with
Internal Feedback, 1/(tsu
with
1f(tsu ++ tcf)
tcf)
58.8
58.84
*
i
S- 50
50 -— 40
40 -— MHz
MHz
11 Maximum Clock Frequency with 62.5 ..:: 62.5

62.5 -— 41.6
41.6 -— MHz
MHz
No Feedback )
twh4 -— Clock Pulse Duration, High 88 t ;- 88 -— 12
12 -— ns
ns
tw14
tw" -— Clock Pulse Duration, Low 88 •'I — 88 -— 12
12 -— ns
ns
ten 2 Input or I/O

Input I/O to
to Output Enabled —.t.: 10
-SCI '10 -— 15
15 -— 25
25 ns
ns
22 0E1 to Output Enabled
OE.!. . )10
I.' 10 -— 15
15 -— 20
20 ns
ns
' t d tdis
i s 33 to Output
Input or I/O to Output Disabled 10 -— 15
15 -— 25
25 ns
ns
33 OEi
0E1 to Output Disabled -:
—1 )10
10 -— 15
15 -— 20
20 ns
ns
1) Refer
Aefer to Switching Test Conditions section.
section.
2) Calculated from fmax
'max with internal feedback. Aefer to
feedback. Refer to 'max
fmax Descriptions
Descriptions section.
section.
3) Refer
Aefer to 'max
fmax Descriptions section.
4) Clock pulses of widths less than the
the specification may bebe detected
detected as valid
valid clock signals.
signals.
1SWITCHING TEST CONDITIONS

Input
i1Input GNDt03.0V +5V
+5V
Pulse Levels GND to 3.0V
: Input Rise
Aise and Fall Times 3ns
3ns 10"04
10% -– 90%
, Input Timing Reference
Aeference Levels 1.5V
1.5V
Output Timing Reference
Aeference Levels 1.5V
1.5V
Output Load See
See Figure
3-state levels are
are measured 0.5V
0.5V from
from steady-state active FROM OUTPUT (0/0)
FROMOUTPUT (0/0) - - + - - ' - - T E STEST
T POINT
POINT
level. UNDER TEST
UNDERTEST
OUtput
Output Load Conditions (see
(see figure)
figure) CL
R2
Test Condition R1
RI R2
R2 CL
CL
11 2000
2000 3900
390Q 50pF
50pF
2
2 Active High
Active High co
0. 3900
390n 50pF
50pF
Active Low 2000
2000 3900
3900 50pF
50pF
3
3 Active High co
.0 3900
3902 5pF
5pF C
CL INCLUDES JIG
LINCLUDES AND PROBE
JIGAND TOTAL CAPACITANCE
PROBETOTAL CAPACITANCE
Active
Active Low
Low 2000
2000 3900
3900 5pF
5pF
2-13 4/91.Aev.A
4/91.Rev.A
[JJ
.l...I
'LattiOO*
SemJconductor·
Corporation
Corporation
GAL16118B
Industrial
Industrial
ABSOLUTE MAXIMUM RATINGS(1)
COND.
Supply voltage
Supply voltage Vcc — 0 . 5-0.5 to
Vee ....................................... to +7V
+7V Industrial Devices:
Industrial
— 2 . -2.5 5 to to Vcc +1 .0V
(TA)............................
— 4 0-40 to
to 85°C
85°C
Off-state output
Off-state output voltage
voltage applied
applied ..........
— 2-2.5 . 5 toto Vcc
Vee + +11.0V
.0V Supply voltage
Supply voltage (V
(Vcc)
eel
Storage Temperature .........•.......................
with Respect to
to Ground
Ground ......................
+ 4 . 5+4.50 0 to
to +5.50V
+5.50V
— 5 5 -55to
Power Applied .......................................• to 125°C
1.Stresses above those listed under the "Absolute "Absolute MaximumMaximum
Ratings" may cause permanent damage to the device. These
device. These
are stress only ratings and functional operation of of the
the device
above those
at these or at any other conditions above those indicated
indicated in in the
the
programming, follow
follow the
the programming specifications).
OVer
Over Recommended
Specified)

CONDITION MIN.
MIN. TYP.3
TYP.3 MAX.
MAX. UNITS
UNITS
VII_
VIL Input Low Voltage Vss –0.5
Vss-O.5 -— 0.8
0.8 VV
2.0 -— VCC+1
Vcc+l VV
IlL'
ilLI Input or 110
I/0 Low Leakage Current OV
OVS5 VIN VIL (MAX.)
VIN SVII_ (MAX.) -— -— -100
–100 pA
IIH Input or 1/0
I/0 High Leakage Current 3.5V VIN _S•VCC
3.5V SVIN Vee -— -
— 10
10 I.LA
VOL Output Low Voltage 10L
loL ..= MAX. Vin
MAX. Vi n ..= VIL
Vii_or
orVIH
VIH -— -— 0.5
0.5 VV
VOH Output High Voltage 10H
loH = MAX. Vin
Vin ..
= VIL
VILor VIH
or VIH 2.4
2.4 -— -— VV
10L
24 mA
mA
10H
i0H High Level Output Current -— -— -3.2
–3.2 mA
mA
los'
i0S2 Output Short Circuit Current Vce=5V VOUT== 0.5V TA
Vcc = 5V VOUT TA==25°C
25°C -30
–30 -— -150
–150 mA
mA
Icc
iCC Operating Power Supply Current VIL=
Vit. = 0.5V VIH = 3.0V
0.5V VIH 3.0V ftoggle
f.toggle == 25MHz
25MHz -— 75
75 130
130 mA
mA
Outputs
Outputs Open
Open (no load)
load)
1) The leakage current is due to the internal pull-up on
on all
all pins. See
See Input Buffer
Buffer section
section for
for more
more information.
information.
2) One output at
at a time for
for a maximum duration of one
one second. Vout =00.5V
was selected
selected to
to avoid
avoid test
test problems
problems caused
caused by
bytester
tester
Guaranteed but
tested.
3) Typical values are at Vcc ..55V TA = 25 °C
V and TA
(TA = 25'C,
CAPACITANCE (TA 25°C, ff = 1.0 MHz)
SYMBOL PARAMETER
PARAMETER MAXIMUM·
MAXIMUM* UNITS
UNITS TEST
TESTCONDITIONS
CONDITIONS
C,
CI Input
pF Vee
Vcc=. 5.0V,
5.0V, V,
VI == 2.0V
2.0V
C10
C'iO I/O Capacitance
1/0 88 pF
pF Vcc =5.0V,
Vcc . 5.0V, VIJO=2.0V
Vvo. 2.0V
·Guaranteed
*Guaranteed but not 100°/0
100% tested.
2-14 4191.Rev.A
4/91.RevA
/1.l..J
L LlLattice"
attice
Semiconductor
Semiconductor
Corporation
Corporation
GAL161/8B
Specifications GAL 16V8B
Industrial
Over Recommended
Operating Conditions
Conditions
-10
-10 -15
-15
TEST DESCRIPTION
PARAMETER
PARAMETER UNITS
UNITS
COND1.
COND'. MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX.
tpd 11 Input or I/O to
to Combinational Output 33 10
10 33 15
15 ns
ns
too
tco 11 Clock to Output Delay 22 77 22 10
10 ns
ns
tcf2 -— Clock to Feedback Delay -— 66 -— 88 ns

ns
tsu -— Setup Time, Input before Clocki

Input or Feedback belore 10
10 -— 12
12 -— ns
ns
I
I th -— Hold Time, Input or Feedback alter
after Clocki 00 -— 00 -— ns
ns
58.8 -— 45.5
45.5 -— MHz
MHz
External Feedback, 1/(tsu + tco)
,
I
f max
fmax' 11 Maximum Clock Frequency with 62.5
62.5 -— 50
50 -— MHz
MHz
1/(tsu + tcl)
Internal Feedback, 1/(tsu tot)
62.5 -— 62.5
62.5 -— MHz
MHz
No Feedback
twh4 -— Clock Pulse Duration, High 88 -— 88 -— ns

ns
twt'
tw14 -— Clock Pulse Duration, Low 88 -— 88 -— ns
ns
ten 2 Input or I/O to
to Output 33 10
10 -— 15
15 ns
ns
2 OEL
OE/ to Output 22 10
10 -— 15
15 ns
ns
tdis 3 Input or I/O to
to Output 22 10
10 -— 15
15 ns
ns
3 OEi
OET to Output 1.5
1.5 10
10 -— 15
15 ns
ns
1) Refer
Reier to Switching Test Conditions section.
Refer to
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
section.
3}
3) Refer to fmax Descriptions section.
01 widths less than the specification may be
4) Clock pulses of be detected as valid
valid clock
clock signals.
signals.

Input Pulse Levels GND
GND t03.0V
to 3.0V +5V
+5V
Input Rise and Fall Times 3ns 10%-90%
3n s 10'k – 90%
input
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V
1.5V R1
Output Load See
See Figure
3-state levels are measured 0.5V from
from steady-state active FROM OUTPUT (010)
FROMOUTPUT (0/0) - -.....- -.....-TESTPOINT
TESTPOINT
level. UNDER TEST
1J
UNDERTEST
Output Load
Load Conditions (see figure)
Test Condition Rl
RI R2
R2 CL
CL R2
1 2000 3900 50pF
50pF
2 Active High .0
co 3900 50pF
50pF
Active Low 2000 3900 50pF
50pF -
3 Active High
Active High ..
00 3900 5pF
5pF C
CL INCLUDESJIG
llNClUDES JIGA NDP
AND ROBET
PROBE OTALC
TOTAL APACITANCE
CAPACITANCE
Active
Active Low 2000
2000 3900
3900 5pF
5pF
2-15
2-15 4 / 9 1 . R e v .4191.Rev.A
A
U Lattice'
1..1 j;Lattioo'
Semiconductor
Semicondllctor
C o r p Corporation
oration
GAL16118A
Specifications GAL 16V8A
Industrial
Industrial
MAXIMUM RATINGS(l)
ABSOLUTE MAXIMUM RATINGS') RECOMMENDED OPERATING
COND.
Supply voltage Vcc - 0 . 5 -0.5 to +
Vce ....................................... +7V
7V Industrial
Industrial Devices:
- 2 . 5-2.5 to Vcc
Ambient Temperature (T(TA) - 4
A) ............................ to 85°C
0 -40 to 85°C
Oft-state output voltage applied ..........
Off-state - 2 -2.5
. 5 to VccVee ++1.0V
1.0V Supply voltage (Vee)
Supply (Vcc)
- 6 5 -65 to 150°C with Respect to
with + 4 . 5+4.50
to Ground ...................... to +5.50V
0 to +5.50V
- 5 5 -55 to 125°C
Power Applied ........................................
1.Stresses above those listed under the the "Absolute Maximum
Ratings" may cause permanent damage to to the
the device.
device. These
These
are stress only ratings and functional operation of the device device
at these or at any other conditions above those those indicated inin the
the
operational sections of this specification is not not implied (while
programming, follow thethe programming specifications).
CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
(Unless Otherwise Specified)

CONDITION MIN.
MIN. TYP.2
TYR' MAX.
MAX. UNITS
UNITS
VIL Input Low Voltage Vss -0.5

Vss-O.5 -— 0.8
0.8 VV

2.0 -— Vcc+1
Vcc+1 VV
IIL
IlL Input or I/O Low
Low Leakage Current OV 5 VIN
OV:s VIN:SVit. (MAX.)
Vil (MAX.) -— -— -10
·10 p,A
IIH Input or I/O High Leakage Current VIH:S VIN .•:SVCC
VIH 5 VIN Vec -- -- 10
10 I.LA
VOL Output Low Voltage l a = MAX.
10l= MAX. Vi
Vinn = VIL
Vii_ or
or VIH
VIH -- -- 0.5
0.5 VV
VOH
IOH MAX. Vi n = VIL
Yin or VIH
VIL or ViH 2.4
2.4 -— -— VV
10l
IOL Low
Low Level Output Current -— -— 24
24 mA
mA
-3.2 mA
mA
los'
IOS Output Short Circuit Current Vcc = 5V
Vee VOUT = O.SV
5V VOUT TA== 25°C
0.5V TA 25°C -30
-30 -— -150
-150 mA
mA
ICC
Icc Operating Power
Power VIL VIH = 3.0V
VII_ = 0.5V V11-I 3.0V toggle = 25M
floggl. Hz
25MHz lL ·15/-25
-15/-25 -— 75
75 130
130 mA
mA
Supply Current Outputs Open (no load) f10991o
floggie =- 15MHz
15M Hz a0 -20/·25
-20/-25 -— 45
45 65
65 mA
mA
1) One output at a time for a maximum duration

duration of
of one
one second. Vout == 0.5V
second. Vout 0.5V was
was selected
selected to
to avoid
avoid test
test problems
problems caused
caused by
by tester
tester
Guaranteed but not 100% tested.
ground degradation. Guaranteed tested.
2) Typical
Typical values are at Vcc
Vce = 5V and TA
TA = 25
25°C
*C
=
(TA = 25°C, f = 1.0 MHz)
CAPACITANCE (TA =
SYMBOL PARAMETER
PARAMETER MAXIMUM'
MAXIMUM* UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
C,
C, Input
pF Vcc =- 5.0V,
Vee V, = 2.0V
5.0V, V, 2.0V
CliO I/O Capacitance 10
10 pF
pF Vcc== 5.0V:
Vee 5.0V, V,,c,
VIIO =. 2.0V
2•0V
"Guaranteed
'Guaranteed but not 100% tested.
tested.
2-16 4/91.Rev.A
4/91.Rev.A
/fILatUre"
/L
1.J
Lattice®
Semiconductor
Semiconductnr
Corporation
Specifications GAL-16118A
GAL 16V8A
Industrial
1AC SWITCHING CHARACTERISTICS
-15
-15 -20
-20 -25
-25
)ARAMETER
TEST DESCRIPTION UNITS
UNITS
'ARAMETER
COND'. MIW7.MAX.
Mlt{;.,. )v1AX. MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX.
,„
11 Input or I/O to
to Combinational Output &t 15
33 te,,,,t 33 20
20 33 25
25 ns
ns
t pd
tpd >I' ""15
==::.
tco 11 Clock to Output Delay ?

k4k,,
22 0,-.,"'10 10
;§
22 11
11 22 12
12 ns
ns
tolz
tct> -— Clock to Feedback Delay -— i"V<,..„.JI 88 -— 99 -— 10
10 ns
ns
tsu -— Setup Time, Input or

or Feedback belore
before Clock!
Clocki 12 L-,'• -
12 C 13
13 -— 15
15 -— ns
ns
th -— Hold Time, Input or Feedback alter

after Clocki o 00 -— 00 -— ns
ns
1!!Ij
11 Maximum Clock Frequency with 45.54, — 41.6
41.6 -— 37
37 -— MHz
MHz
.1l
"', '"
f max3 Maximum Clock Frequency with 5 0 P<: 45.4
45.4 -— 40 -— MHz
fmax 11 50 ''
l- - 40 MHz
Internal Feedback, 1/(tsu ++ tet)
tcf) tL?',...
.-
1 Maximum Clock Frequency with 62.5 r:p!,i\!•—

- 50
50 -— 41.6
41.6 -— MHz
MHz
No Feedback
No C
P 5
twh4
twh' -— Clock Pulse Duration, High 88t
¢' ."
C)- 10
10 -— 12
12 -— ns
ns
w.,
twl4
tw14 -— Clock Pulse Duration, Low
Low 88 10
10 -— 12
12 -— ns
ns
ten 2 110 to
Input or I/O to Output :i 151
.*
-— 20
20 -— 25
25 ns
ns
22 OEJ.
0E1 to Output _— to!
' ' •f15
15 -— 18
18 -— 20
20 ns
ns
s,
to Output -— ;>'1;15 -— 20
20 -— 25
25 ns
ns
3
3 OEi
OET to Output — ""
- 4 ,$15
15 -— 18
18 -— 20
20 ns
ns
) Refer to Switching Test Conditions section.
')) Calculated from
lrom fmax with internal feedback. Refer to
to Imax
section.
;)) Refer to fmax Descriptions section.
) Clock pulses of widths less than the
the specification may be detected as valid
valid clock
clock signals.
signals.

Input Pulse Levels GNDt03.0V
GND to 3.0V +5V
+5V
Input Rise and
and Fall Times 3ns
3ns 10% -– 90e/0
90%
1.5V
Reference Levels 1.5V
1.5V
Output Load
Load See
See Figure
,-state
-state levels are measured 0.5V from steady-state active FROM OUTPUT (O/Q)
FROMOUTPUT (0/0)
weI.
?vel. TESTPOINT
POINT
UNDER TEST
UNDERTEST
CL
Test Condition R1 R2 CL R2
ill R2 CI-
1 2000 3900 50pF
2 Active High 0. 3900 50pF
50pF
Active Low i 2000
2000 3900 50pF
50pF
3
3 Active High
Active Hlgn .. 3900
3900 5pF
5pF C
C L INCLUDES
INCLUDES JIG AND PROBE
JIGAND PROBE TOT
TOTAL
ALCAPACITANCE
CAPACITANCE
Active
Active Low 2000
2000 3900
3900 5pF
5pF
2-17 4/91.Rev.A
4/91.Rev.A
IllLattioo
Lattice®
'
.l..I Corporation
Semiconductor
Semiconductor
GAL1
16VBB
GAL16143A
GAL 16VBA
SWITCHING WAVEFORMS
SWITCHING
INPUTor
INPUT or
vaVOFEEDBACK
FEEDBACK
VALIDINPUT
to u th
INPUTor CLK
elK
INPUT or
va
VOFEEDBACK
FEEDBACK VALIDINPUT
4— to
tpd REGISTERED
REGISTERED
OUTPUT
OUTPUT 1
COMBINATORIAL
COMBINATORIAL if imax
OUTPUT
OUTPUT (external idbk)
Combinatorial Output Registered

Registered Output
Output
INPUT
INPUTor
OE
OE
va FEEDBACK
VOFEEDBACK
tdIs 4—ten—0•• 4 — t d s —111.• 4— t en
OUTPUT
OUTPUT OUTPUT
OUTPUT
Input or UO
I/O to Output Enable/Disable O E OE to
to Output
Output Enable/Disable
Enable/Disable
elK
CLK
tw h Iwl
tw
1/ titian (internal UN() *
elK
CLK
REGISTERED
REGISTERED
FEEDBACK
FEEDBACK
mss2,/, 4—tct 0 4 t s u
Clock Width
fmax with
fmax with Feedback
Feedback
2-18
2-18 4191.Rev.l
4/91.Revi
aJLattire'
.l..J ILattice®
Semiconductor
Semiconductor
C o r p CorporaUon
oration
Specifications GAL
GAL16118B
16V8B
GAL16118A
GAL 16V8A
firm
fmax DESCRIPTIONS
DESCRIPTIONS
CLK
elK
.......................................... _--_ ..
elK
CLK
_. _. _ •• - _ • • • • • _. - - - - _. - - - _. - eo • • _ •• _ 00 _ . _ • • • •,
LOGIC
lOGIC REGISTER
REGISTER
AR R AY
RRAV LOGIC
ARRAY
REGISTER
REGISTER
14
/o.II1
. I s o t i ..o
....f - -o-
fmax with External Feedback 1/(tsu+tco) • • • • OM • • • • • _ •• __________ • ____ •• _______ • ____ • ___ !
r.-14------tcl
tcl O k i
Note: fmax
'max with
with external feedback is
is calculated
calculated from
from measured 1<I!041-----tpd
tpd0 1
tsu and too.

tco.
frnax with
fmax with Internal Feedback 1/(tsu+tcf)
Internal Feedback 1/(tsu+tcf)
Note: tet
Note: tcf is aa calculated
calculated value,
value, derived
derived by by subtracting
subtracting tsu tsu from
from
the period
the period ofof fmax
Imax w/internal
w/internal feedback
feedback (tet(tot 1/Imax
1lfmax -- tsu).
tsu). The
The
value of tet
value tot is
is used
used primarily
primarily when
when calculating
calculating the the delay
delay from
from
elK
CLK clocking
clocking a register
register to
to aa combinatorial
combinatorial output
output (through
(through registered
registered
. . . . . 0-- 0 . - - - • • • • • • • • • • • • • • • • - _ . __ • • _-_ • • • • • • • • • feedback), as
feedback), as shown
shown above. For example,
above. For example, the the timing
timing from
from clock
clock
to
to a combinatorial output is
combinatorial output is equal
equal to tcl ++ tpd.
to tcf tod.
V
LOGIC
lOGIC
REGISTER
REGISTER
ARRAY I--+--'
.
• __ . 0 • • • • • • - ••••••• - . · · ••• - . · · . - . · _ - •••• -- •• ·_--
.
fmax With No Feedback
with no feedback may be less than 1ltwh

Note: fmax with litwh + twl. This
This
is to allow for a clock duty cycle ol'other
of other than 50%•
50%.
2-19 4/91.Rev.A
4/91.Flev.A
U
l..tI lLattiooo
L_Lattice® Semiconductor
Semiconductor
Corporation
CorporaUon
GAL16118B
GAL16118A
GAL 16VBA
ELECTRONIC SIGNATURE OUTPUT REGISTER
OUTPUT REGISTER PRELOAD
PRELOAD
every GAL
An electronic signature (ES) is provided in every GAL16V8A
16V8A and
and When testing
When testing state
state machine
machine designs.
designs, all
allpossible
possiblestates
statesand
andstate
state
GAL16V8B
GAL 16V88 device. ItIt contains 64 bits
bits of
of reprogram
reprogrammable memory
mabie memory transitions must
transitions must bebe verified
verified inin the
the design.
design, not
not just
just those
those required
required
that can contain user defined data. Some Some uses include user ID 10 in the
in the normal
normal machine
machine operations.
operations. This is because.
This is because, in in system
system
codes, revision numbers,
codes. inventory control.
numbers. or inventory control. The signature data operation, certain
operation. certain events
events occur
occurthat
that may
may throw
throwthethe logic
logicinto
into an
an
is always available to the user independent of the the state
state of the
the illegal state
illegal state (power-up.
(power-up, line
line voltage
voltage glitches.
glitches, brown-outs,
brown-outs, etc.).
etc.). To
security cell. test a design
test design for
forproper
propertreatment
treatment ofofthese conditions, aaway
theseconditions, waymust
must
be
be provided
provided to to break
break the
the feedback
feedback paths,
paths, and force any
and force anydesired
desired
NOTE: The
The ES is is included
included in checksum calculations. Changing
calculations. Changing (i.e., illegal) state
(i.e., state into
into the
the registers.
registers. Then the machine
Then the machine can can bebe
the ES will alter checksum.
checksurn. sequenced
sequenced and andthe
theoutputs
outputstested
tested for
forcorrect
correct next
nextstate
stateconditions.
conditions.
The GAL
The GAL16V8A and GAL
16V8A and GAL16V8B devices include
16V88 devices include circuitry
circuitry that
that
allows each
allows each registered
registered output
outputto
tobe
besynchronously
synchronously setseteither
eitherhigh
high
SECURITY CELL or
or low.
low. Thus, any present
Thus, any present state
state condition
condition can
can be
be forced
forced for
fortest
test
sequencing.
sequencing. If necessary,
necessary, approved
approved GAL
GALprogrammers
programmers capable
capable
A security
security cell is provided in the GAL16V8A
GAL 16V8A and GAL16V8B
GAL 16V88 of
of executing
executing text
text vectors
vectors perform
perform output
output register
register preload
preload auto-
auto-
devices to prevent unauthorized copying of the the array patterns. matically.
matically.
Once programmed,
programmed. this cell prevents further readread access to the
the
functional bits in the device. This
This cell can
can only be erased
erased by re-
re-
programming the device.
device, so
so the
the original configuration
configuration can
can never
be examined
examined once this cell is programmed.
programmed. TThe h e Electronic INPUT BUFFERS
INPUT BUFFERS
Signature is always available to to the user. regardless
the user, regardless of the
the state
of this control cell. GAL 16V8A and
GAL16V8A and GAL 16V88 devices
GAL16V8B devices are
are designed
designed with
withTIL TTLlevel
level
compatible
compatible input
input buffers.
buffers. These buffers
buffers have
have aacharacteristically
characteristically
high
high impedance,
impedance, andand present
present aa much
much lighter
lighter load
load to
to the
the driving
driving
logic
logic than
than bipolar
bipolar TIL
- r n devices.
devices.
PROTECTION
LATCH-UP PROTECTION
The
The GAL 16V88 input
GAL16V8B input and
and 110
I/O pins
pins have
have built-in
built-in active
active pull-ups.
pull-ups.
GAL 16V8A and GAL
GAL16V8A 16V88 devices
GAL16V8B devices are designed with an onon- As
As a result,
result, unused
unused inputs and I/O's I/0's will
will float
float to
to aa TIL
TTL "high"
"high"
board charge pump to negatively bias the the substrate.
substrate. The
The negative
negative (logical
(logical "1").
"1"). In contrast,
contrast, the
the GAL 16VSA does
GAL16V8A does notnot have
haveactive
activepull-
pull-
bias is of sufficient magnitude to prevent input undershoots from from ups
ups within
within their input
input structures. Lattice recommends
structures. Lattice recommends that that all
all
causing the
the circuitry
circuitry to latch. Additionally,
Additionally. outputs
outputs are
are designed
designed unused
unused inputs and and tri-stated
tri-stated I/O
I/O pins
pins for
for both
both devices
devices bebe con-
con-
with n-channel pull-ups instead of the the traditional p-channel
p-channel pull- nected
nected toto another
another active
active input,
input, VCJ::' or
Vcc, orGround. Doing this
Ground. Doing thiswill
willtend
tend
ups to
to eliminate any possibility of SCASCR induced latching. to
to improve
improve noise
noise immunity
immunity andand reduce
reduce Icc lc, forthe
for thedevice.
device.
DEVICE PROGRAMMING Typical

Typical Input
Input Pull-up
Pull-up Characteristic
Characteristic
GAL devices are programmed using using a Lattice-approved Logic

Logic
Programmer.
;;; 0
Programmer, available from
from a number ofof manufacturers (see
(see the
the /
GAL Development Tools section). Complete programming of of the
the
device takes only aa few seconds.
takes only seconds. Erasing
Erasing of the device
device isis ;" ·20
/'
transparent to the
the user.
user, and
and is done automatically as part of
of the
the " ./
V
(,)
programming cycle. :; ·40

•40
Q.
.!:
·60
-60
o0 1.0
1.0 2.0
2.0 3 . 3.0
0 4.0
4.0 5.0
5.0
Input
Input Voltag'
Voltage (Volts)
(Volts)
2-20 4/91.Rev.A
4/91.Rev.A
1 1.Ilattice®
.l.Jd Semiconductor
SemJronducwr
Specifications GAL
GALI16V8B
61f8B
Corporation
COl'poration GAL1
GAL 61f8A
16V8A
POWER-UP RESET
Vee
V cc
OV
0V
t pr
V
V IH rT"...-tt...--.-rrrr"\lr---------
CL K
CLK
Vil
V IL lk 1 VALIDCLOCK
VALID CLOCKSIGNAL
SIGNAL
INTERNAL
INTERNAL INTERNAL
INTERNAL REGISTER
REGISTER
REGISTER
REGISTER RESET
RESETTO
TO LOGIC
LOGIC00
0-OUTPUT
a·OUTPUT
FE
F E EDBACK/E
EDBACK/EXXTE
TERRNAL
NAL EXTERNAL REGISTER
EXTERNAL REGISTER
OUTPUT REGISTER
OUTPUT R EGISTER OUTPUT
OUTPUT =L OLOGIC
GIC 1
circuitry within the GALA

GAL 16V8A
6V8A and GAL 16V8B provides a reset
GAL16V8B reset The
The timing
timing diagram for for power-up
power-up is is shown
shown above. Because of
above. Because of
,ignalto
signal to all registers during power-up. All
All internal registers
registers will the
the asynchronous
asynchronous nature
nature of of system
system power-up,
power-up, some
some conditions
conditions
lave their Q0 outputs set
set low after a specified time (t R
RESET' 45115
ESET' 45P,S must
must be be met
met to guarantee
guarantee a valid valid power-up
power-up reset
reset of the the
\/lAX).
MAX). As a result, the state on the registered output pins (if they GAL 16V8A and
GAL16V8A and GAL 16V8B. First,
GAL16V8B. First, the
the Vee
Vcc rise
rise must
must bebe mono-
mono-
ue
ore enabled through OE) will always be high on power-up, re- re- tonic. Second, the
tonic. Second, the clock
clock input
input must
must become
become aa proper
proper TTL
TTLlevel
level
Jardless
jardless of the programmed polarity of the the output pins: This
pins. This within
within the
the specified
specified time
time (tPR' 100ns MAX).
(tpn, lOOns MAX). The registers
registers will
will reset
reset
'eature
eature can greatly simplify state machine design by providing a within
within a maximum
maximum of tREsETtime. time. AsAs inin normal
normal system
system operation,
operation,
mown
(nown state on on power-up. avoid
avoid clocking
clocking the
the device
device until
until all
all input
input and
and feedback
feedback path
path setup
setup
times
times have been
been met.
met.
INPUT/OUTPUT EQUIVALENT SCHEMATICS
PIN PIN
Feedback
Active Pull-up
Vcc
Vee
CircuM
Circuit ActivePull-tJp
Active Pull-up
(GALI6V8B
(GALA6V8D only)
only) Cil'aJit
Circuit
(GAL16V88
(GAL16V8Bonly)
-------------- --- _., ....y.... ...y.....
only)
Vco
Wet Trl-State
Tri-State W e it Vret i
Control
Control
: ESD
ESD
: Protection
i ClrcuR
Circuit
:----------------- _eo!
Data
Data
!lIN
PIN PIN
PIN
Output
Output
,.---------------- __ e.
: ESD
ESD :
: Protection
Protection :
l
··
CircuM
Circuit l
.
··.----.-------.-.- ----... Feedback
Feedback
(To
(ToInput
inputBuffer)
Buffer)
Typ. Vref =
= 3.2V Typ.
Typ. Vref == 3.2V
3.2V
Typical Input Typical

Typical Output
Output
2-21
2-21 4191.Rev.A
4/91.Rev.A
GALI16V8B
I I s I Sleiscondue ctor6
Corporation Typical Characteristics
Normalized Tpd vs Vee
Normalized Vcc Normalized Teo
Normallzad Tco vs
vs Vee
Vcc Normalized Tsu
Normallzad I s u vs
vs Vee
Vcc
t1.2
.•
J.....
1.2
,I--FALL
u t.'
i---t---t-i
PTH..L
..... RISE
PT 1.1-8.1.,
!-
t.t
......... 1--
- PT L-9H
J!122
0 Lt.t
I
- FALL
,!!
0 1t.t
.1
- PT 1.-›/.1
1 +1--====1=' ]t --- -" ....... ]t

II--PTL ..H
J
]
0.9 t---t--+.,--t---;
-'-
•48.4.4,8,8
........
J 0.'
. ...... ............
J 0.'
0.' 0.9 0.9
.... .... .... ....

•.• + - - - - 1 - - 4 - - - - 1 - - - - 1
.... •...... .... .... ....
4.50 ".75
4 . 7 5 5 . 0 0 5 . 2 5 5.50
00.8
.•
4.50 4 . 74.711
5 .... ....
5 . 0 0 5 2 5 5 . 5 0 ...0 4 . 0
0.8
0 4 2 4.711
5 5 . 0 0 5 2 5 5.50
Supply (V)
Supply Voltage (V) Supply
Supply Voltage
Voltage (V) Supply Vohage
Supply Voltage (V)
(V)
Normalized Tpd vs Temp

Normalized Normalized Teo
Normalized Tco vs
vs Temp
Temp Normalized Tsu
Normellzad Tsu vs
vs Temp
Temp
t.3
1.3 t.3
1.5
t.'
1.4
LI
1.2 ••••. PTH
PT H..
91_
t.'
1.2 RISE t.3
1.3 ••••. PTH..L I L
.., ./ /'
-- .. ..
o
,.2-1.1 --PTL->HI
PT I.-9H 1.1 - - FALL
,
.' iii t1••2
--PTL.. HI
/
1 /'
0- '
] •• "i
:os 1 ,.,..
1
t.t
.. ' .'
/.-
J . 0.•
'
e 0.9
0.'
t
Z 0.9
0.'
t
....... . /
0.8
0.8 0.'
0.8
0.' /"
0.8
......
0.1
0.7
...
55 0 2 5 ..
Temperature (deg. C)
9 0 to t125
..
0.1
0.7
...
55 0 2 5 .. 9 0 to t125
..
0.1
0.7
... 55 0 2 5 .. 9 0 to t 125
..
Temperature
Temperature (deg. C) Temperature
Temperature (deg.
(deg. C)
C)
Delta Tpd vs #It of

Delta of Outputs
Outputs Delta
Delta Teo vs ## of
Tco vs of Outputs
Outputs
Switching
Switching Switching
Switching
:.:-
.. , .. ' ;;.:.. p .. .' .
'
pr""
] : -0.5
..,
.'
.'
/
i-"'"
_-0.55
..s. .. '
.'
/
.-'
.e- ., ./ J! ·t ./
c!'l .t .•
V ••••• RISE}
RISE /" ..... RISJ
c!'l .t.'
--FALL
- FALL FALL
..
-2 .. I I
2 3 4 5 6 7 6 2 3 4 5 6 7
Number of Outputs SwUching

Number Switching Number of Outputs
Number Outputs SwUching
Switching
Delta
Delta Tpd vs Output
Output Loading Delta
Delta Teo vs Output
Too VI Output loading
Loading
to
j .....
R I S RISE
E I
/
to
••••. I
V
g' --FALLI
- FALL
/,. 134
'
--FALLI
..'
1--;':".,
L /.
.' .'
/- L
-. ..
50
50 1 0 tOO
0 1 5150
0 2 0200
0 2 529
0 3 0300
0 0 5 050 1 0100
0 I S150
O 2 0200
0 2 5250
0 300
300
Output
Output Loading (pF) O u t p u Output
t Loading
Loading (pF)
(pF)
2-22 4191.Rev.A
4/91.Rev.A
Ita Lattice® GAL16V8B
Specifications GAL 16V8S
.l.J oSemiconductor
Semiconductor
C o r p Corporation
ration Typical Characteristics
I'
lol
Vol vs 101 Voh VI
Voh vs Ioh
loh V o h vs loh
Voh VI loh
5 ....
4-50
0.75
0.75
....
0.25
,/
,/
,/'
/
/
s
5 0 2
3
........
""-
--- r- r-- ,
425
42'
4.00
'.75
3.75
"'- r-.
---r---
0 V 0 .... .... ....
3.50
0.00 2 020.00
00 4 40.00
0 00 6 10.00
0 00 8 '0.00
0 00 100.00
0000 0.00
0_00 1 10.00
0 00 2 20.00
0 00 330.00
0 00 4 CO.OO
0 00 550.00
0 00 610.00
0 00 0.00
0_00 1 . 0 0 2 . 0 0 3 . 03.00
0 4.00
4.00
lol (mA)
101 loh(mA)
Ioh(mA) loh(mA)
10h(mA)
Normalized Ice
Icc vs Vee
Vec Normalized lee vs
Normalized Icc vs Temp
Temp Normalized !cc vs
Normalized Icc vs Fraq.
Freq.
12.
120 12.
120 u.
1.30
I'-.. ....
120
1.10
1.10
V
1.10
1.10
I'--- .l;l L V
"il
3 too "il I'-.. "2
13 1.10
.......
----- 1,·00 V L
1.00 _1_1 1.00
1.00
1
= 00.80
.90
1.... 0.00
1""- I'..
... .0.90
f'-, .A.
0.80
0.80
....
4_50 4 . 74.75
5 0 , 05.00
0
Supply Voltage (V)

5 . 25.25
5 ....
5.00
0.80
020
-55 . 2 5 0
Temperature
2 5Z5
1'5
7 5 t o tOO
o 125
125 .0.80
25 5
Frequency
.
0
Frequency (MHz)
(MHz)
7 5 ...
100
Delta Icc vs Vin (1

Delta Ice (1 input)
input) Input
Input Clamp
Clamp (Vik)
(Vik)
.....
•• /
4
••
20
3D
30
/
40
<-,40 1/
2 2
/1\ .§. ..
50
60 /
..
60
J \ 70
70
/
/
1
.....
II
80
1/
I'- 90
•100
00
0.00
0.00 0.50
0.50 1 1.00
. 0 0 1 1.50
. 5 0 22.00
. 0 0 2 2.50
_ 5 0 33.00
. 0 0 33.50
. 5 0 C4.00
OO ·2.00
-2 00 - 1 ·1.$0
50 . 1 . -1.00
0 0 -0.50
. 0 9 0 0.00
0.00
Vin(V)
Vito (V) Vik(V)
VA (V)
2·23
2-23 4191.Rev.A
4/91.Rev.A
[J;J
.l..i
'Lattice@
LLattice® SemiconductDr
Semiconductor
Corporation
CorporaUon
GAL161/8A
Specifications GAL 16V8A
Typical Characteristics
Normalized Tpd vs.
VS. Vcc
Vee Normalized Tsu
Normalized Ts u vs. Vee
Vcc Normalized TTco
Normalized vs. Vee
co vs. Vcc
"- 1.3
1.3
--- -
02
1.'
Oil 08
- r--
1 1.1
1-
-
'0
al to
1'"
1 1.0
OJ
E
o 0 05
0.'
Z
0.6
0.'
0.7
t1'74-!:
..
430 475 5 ...
00 5 2 5 5...
50 O. 0.7
450
.5O 4 75
4.76 5 0 5.00
0 5 2 5.25
5 5.50
450
'.SO 75
4.75 6 0 6.00
0 5 . 25.25
5 50
5,SO
Supply Voltage (V)
(V) S u p p l y
Supply Voltage (V)
Voltage Supply Vonage
Supply Voltage (V)
(V)
Normalized Tpd vs
vs. Temperature
Temperature N o r m a l Normalized
i z e d Tsu vs.
vs Temperature
Temperalure Normalized Too vs.
Normalized Teo vs. Temperature
1.3 1.3 I.,
1.3
-
2
1.2 12
12
1:111.1
'0 1.1
. . .v '"
II
1.1
. . .v I.'1.2
0.. III
g 1.1
1—
1-
V 1-
V 0
0
.. . /V
I-
a1
-? 1.0
1.0 a1-E t1.0
o
.to!
To
EE 00.'
4
V stt
IV
§ 09
E 0.'
V al4,4
g
13
.!:! 1.0
V
0'6
z V Z V 0.9
5 0.'
z
./
V
0.•
8 0.8
0.8
0.7 / 0.7
0.7
/ 0.'
0.8
.•
00.6
·so
.50 2 ·25
5 0 2 525 5 050 7 575 t o100
o 125
'25
00.•
6
·.0
.so ·25 0 25
2S 50 75
7S 100
100 125
125
0.7
07
.,
..50 • 2 ·25
5 0 2 5 5 0 5 1 0 0 1 2'25
5 "0
Ambient Temperalure (OC)
Temperature (CC) Ambient Temperature (0C)
Ambient ('C) Ambient Temperature('C)
Ambient (T)
Normalized Tpd
Tod vs.
.s.• Swhching
# of Outputs Switching Delta pd vs.
Delta TTpd vs. Output
Output Loading
Loading Normalized tcc vs.
Normalized Icc vs. Vcc
Vcc
1Co "1,3
/
1.00
V 12
12
R
090
0.98 L /
V
............
/
'.1
t—
/
1-
'0
/B
090
1-0T, 0.95
'iii
./ <D
1.0
.!:i 1.0
E
/ 77:
'iii
E 0.9 " ...............
....
ost
, /
Z
a'5 0.'
OS
0.'
...........
,/ ., /'
.92
0117
o 11110
2 0 0200 3 0 0300
100
07
0.7
•.4.50
SO 4 7 4.75
5 0 0 5.00
0 5 2 5.25
5 ....
5.50
• of Outputs Output
Output Loading
Loading Capacitance
Capacitance (pQ
(pf) Supply Voltage(V)
SupplyVoltage M
IOL vs. VOL

loL ye. VOL lom VS.
IOH VOH
vs. VOH Normalized icc vs.
Normalized Icc vs. Temperature
Temperature
-
250
2SO 150
·150
'.3
200
200
,.- '2
<" 150
.s
-'
12
056
,13 too
100
/
V :?
.s
::t
.Q
100
·'00
.50
·50
'" " ""'" ........
a1N
1ij
'TO
E
1.1
...
1.0
0.8
--r-- I'--..
......
i'--
r-....
""
a
Z
so
so
V
OS
0.'
•. 7
07 50
2 4 2 3 -50 25
-25 0 2 525 50 7 5
50 75 100
100 125
125
VOL
V O L (V)
(V) VOH(V)
VOH (V) Ambienl
Ambient Temperature
Temperature (0C)
(°C)
2-24 4/91.Rev.A
4 / 9 1 . R ev.A
i Lattke®
J; lLatUoo"
Semiconductor
Semiconductor
C o r pCorporation
oration
GAL20118B
GAL20V8B
GAL20118A
GAL20V8A
High E2CMOS PLD
PLD r o
DIAGRAM
• HIGH
HIGH PERFORMANCE E2CMOS® TECHNOLOGY Voc
— 7.5 ns Maximum Propagation Delay
-7.5
-— Fmax == 100 MHz 24 —I
23
-— 5 ns Maximum from Clock Input to Data Output 11AUX
-— TTL Compatible 24 mA Outputs
-— UltraMOS® Advanced
Advanced CMOS Technology / OLL1C 22
22
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
I
-— 75mA Typ
lYP !cc
Icc on Low Power Device
01-PAC 21
-— 45mA Typ
lYP !cc
Icc on Quarter Power
Power Device 21
• ACTIVE
ACTIVE PULL-UPS ON ALL PINS (GAL20V8B) ,t
20
• E2
E2 CELL TECHNOLOGY
-— Reconfigurable
Logic
-— Reprogrammabie
Reprogrammable Cells 41
— 100% Tested/Guaranteed 100% Yields
-100% ouxig
(<100ms) =r3--
°LAC 18
18
• EIGHT
EIGHT OUTPUT LOGIC MACROCELLS
-— Maximum Flexibility for
for Complex Logic Designs
-— Programmable Output Polarity OLMC 17
17
-— Also Emulates 24-pln
24-pin PAL® Devices with Full
Full Func-
tion/Fuse Map/Parametric Compatibility
8 OLPAC 16
• PRELOAD
PRELOAD AND POWER-ON RESET OF ALL REGISTERS
REGISTERS 16
.3--
-— 100% Functional Testability
• APPLICATIONS
APPLICATIONS INCLUDE: OLOAC 15
15
-— DMA
DMA Control
-— State Machine Control 11 —C. 14
11111®
-— High Speed Graphics Processing 12 13
-— Standard Logic Speed Upgrade
• ELECTRONIC
ELECTRONIC SIGNATURE FOR IDENTIFICATION PIN
PIN CONFIGURATION
CONFIGURATION
DESCRIPTION
The GAL20V8B,
GAL20\18B, at 7.Sns
7.5ns maximum propagation delay time,
time, com-
com- DIP
DIP
bines a high performance CMOS process with Electrically Eras- PLCC
PLCC
able (E2)
(E2) floating gate technology to provide the
the highest speed IICLK
VCLK 1 2 4 1 Vee
Vcc
performance available in the PLD market. High
High speed
speed erase
erase times
times
«1 OOms) allow the devices to be reprogrammed quickly and I!
(<looms) and ef-
_ g !11 >8 -
ficiently. 1/0/0
1/0/0
2.28
flexibility by 1/0/0
VOIQ 1/0/0
i/O/Q
allowing the Output Logic Macrocell (OLMC) to bebe configured
configured by 110/0
3 1/0/0
110/0
I/0/0
the user.
user. An
An important subset of the many architecture con- GAL20VSAlB
GAL20V8A/B 1/0/0
IIO/Q
figurations possible with the

the GAL20V8A1B
GAL20V8A/13 are the PAL architec- NC
NC • NC
NC GAL I 1/0/o
1/0/0
tures listed in
in the table of the macrocell description
description section. 1 Top
Top View
View 110/0
8083
20V8A I 110/0
tioio
GAL20V8A1B
GAL20V8A/B devices are capable of emulating any of of these
these PAL
PAL 1 UOIO
90/0
architectures with full functionlfuse
function/fuse map/parametric compatibility.
compatibility. 1I0/Q
1NOM I 110/0
I/0/G
- - - - - - 1/0/0
1/0/0
Unique test circuitry and reprogrammable
reprogram mabie cells allow complete
complete 0
-
AC, DC,
DC, and functional testing during manufacture. AsAs a result,
result,
z2 2
" '" " 1/0/0
1/0/0
LATTICE is able to guarantee 100% fieldfield programmability and I
functionality of all GAL®
GAL products. LATTICE
LATTICE also guarantees 100
erase/rewrite cycles and data retention in in excess of 20 GND
GND 12 1 3 I IIOE
20 years.
years.
Copyright 01991
e1991 Lattice
Semicondudor Corp. GAL. PCMOS
Corp. GAL, PCMOS andand UltraMOS
UltraMOS are
are registered
registered trademarks of Lattice
trademarksof Lattice Semiconductor
SemiconductorCorp. Generic Array
Corp. Generic ArrayLogic
Logicisic aatrademark ofLattice
trademarkof LatticeSemiconduc·
Semiconduc-
tor Corp.
Corp. PAL is a registered trademark of Advanced
PAl is Advanced Micro
Micro Devices, Inc. The
Devices, Inc. The specifications
specifications and
and information herein are
are subject
subject to
to change
change without
without notice.
notice.
LATTICE SEMICONDUCTOR CORP.,

LATTICE SEMICONDUCTOR CORP., 5555
5555 N.E.
N.E. Moore
Moore Ct., Hillsboro, Oregon
Ct., Hillsboro, Oregon 97124,
97124, U.S.A.
U.S.A. M a y May 1991.Rev.A
1991.13evA
Tel. (503) 681-0118;
Tel. (503) 681-0118; 1-800-FASTGAL;
1-800-FASTGAL; FAX (503) 681-3037
FAX (503) 681-3037
2-25
!lJtattiOOGl
LLattice®
.l.J Corporation
Semiconductor
Semironducwr
GAL201/8B
Specifications GAL20V8B
GAL20118A
GAL20V8A
GAL20V8A/B ORDERING INFORMATION

Tpd (ns)
Tpd Ts(' (n8)
Tsu (ns) Tco (ns)
Tco icc (mA)
Icc (mA) Ordering ##
Ordering Package
Package
7.5 7 55 115
115 GAL20V8B-71-1
GAL20V8B-7W 28-Lead PLCC
28-Lead PLCC
10 10 7 115
115 GAL20V8B-l0W
GAL20V8B-10LJ 28-Lead PLCC
28-Lead PLCC
115
115 GAL20VSA-l0LP
GAL20V8A-1 OLP 24-Pin
24-Pin Plastic DIP
DIP
115
115 GAL20V8A-l0LJ
GAL20V8A-101-1 28-Lead
28-Lead PLCC
PLCC
15 12 10
10 55
55 GAL20VSA-15QP
GAL20V8A-150P 24-Pin
24-Pin Plastic DIP
DIP
55
55 GAL20V8A-I5QJ
GAL20V8A-150J 2B-Lead
28-Lead PLCC
PLCC
115
115 GAL20V8A-15LP
24-Pin Plastic
Plastic DIP
DIP
115
115 GAL20V8A-15LJ
GAL20V8A-15LI 28-Lead
28-Lead PLCC
PLCC
25 15
15 12 55
55 GAL20V8A-25QP
GAL20V8A-250P 24-Pin
24-Pin PlastK:
Plastic DIP
DIP
55
55 GAL20V8A-25QJ
GAL20V8A-25CLI 28-Lead
28-Lead PLCC
PLCC
90
90 GAL20V8A-25LP
24-Pin Plastic
Plastic DIP
DIP
90
90 GAL20V8A-25LJ
GAL20V8A-251-1 28-Lead
28-Lead PLCC
PLCC

Tpd (ns)
(n5) Tsu (n5)
T5U (ns) Tco (n5)
Tco (ns) icc (mA)
Icc Ordering ##
Ordering Package
Package
15 12
12 10 130
130 GAL20V8A-15LPI
24-Pin Plastic DIP
DIP
130
130 GAL20V8A-151-11
GAL20V8A-15WI 28-Lead
28-Lead PLCC
PLCC
20 13
13 11
11 65
65 GAL20V8A-200PI
GAL20V8A-200PI 24-Pin
24-Pin Plastic
Plastic DIP
DIP
65
65 GAL20V8A-200JI
GAL20V8A-200JI 28-Lead PLCC
28-Lead PLCC
25 15 12
12 65
65 GAL20V8A-25QPI
GAL20V8A-25QPI 24-Pin
24-Pin Plastic
Plastic DIP
DIP
65
65 GAL20V8A-25OJ1
GAL20V8A-250,11 28-Lead
28-Lead PLCC
PLCC
130
130 GAL20V8A-25LPI
24-Pin Plastic
Plastic DIP
DIP
130
130 GAL20V8A-25WI
GAL20V8A-25LJI 28-Lead
28-Lead PLCC
PLCC
xxxxxxxx
XXXXXXXX -Xxx
X XX XX X
X
GAL20V8A DDevice
e v i c e N,me
Name
GAL20V8B
Speed (ns)
(n5) ' - - - - - Grade
Grade BBlank
l a n k == Commercial
Commercial
II = Industrial
L ==Low Power Power

Power L -_ _ _ _
Package PP =
Package = Plastic
Plastic DIP
DIP
Q = Quarter Power J== PLCC
2-26
2-26 4191.Rev.A
4/91.Rev.A
Serniconducwr
Corporation GAL20V8A

macrocell. It should be noted that actual implementation is ac- PAL Architectures GAL20V8A1B
complished by development soflwarelhardware and is completely Emulated by GAL20V8A1B Global OlMC Mode
transparent to the user.
20R8 Registered
There are three global DLMC configuration modes possible: 20R6 Registered
simple, complex, and registered. Details of each of these 20R4 Registered
modes is illustrated in the following pages. Two global bits, SYN 20RP8 Registered
20RP6 Registered
and ACO, control the mode configuration for all macrocells. The 20RP4 Registered
XDR bit of each macrocell controls the polarity of the output in any
of the three modes, while the ACI bit of each of the macrocells 2018 Complex
controls the input/output configuration. These two global and 16 20H8 Complex
individual architecture bits define all possible configurations in a 20P8 Complex
GAL20V8A1B. The information given on these architecture bits l4l8 Simple
is only to give a better understanding of the device. Compiler soft- l6l6 Simple
ware will transparently set these architecture bits from the pin l8l4 Simple
definitions, so the user should not need to directly manipulate 2012 Simple
these architecture bits. l4H8 Simple
l6H6 Simple
l8H4 Simple
The following is a list of the PAL architectures that the GAL20V8A 20H2 Simple
and GAL20V8B can emulate. It also shows the DLMC mode un- l4P8 Simple
der which the devices emUlate the PAL architecture. l6P6 Simple
l8P4 Simple
20P2 Simple

Software compilers support the three different global DLMC In registered mode pin 1 and pin 13 are permanently configured
modes as different device types. These device types are listed as clock and output enable, respectively. These pins cannot be
in the table below. Most compilers have the ability to automati- configured as dedicated inputs in the registered mode.
cally select the device type, generally based on the register usage
and output enable (DE) usage. Register usage on the device In complex mode pin 1 and pin 13 become dedicated inputs and
forces the software to choose the registered mode. All combi- use the feedback paths of pin 22 and pin 15 respectively. Because
natorial outputs with DE controlled by the product term will force of this feedback path usage, pin 22 and pin 15 do not have the
the software to choose the complex mode. The software will feedback option in this mode.
choose the simple mode only when all outputs are dedicated
combinatorial without DE control. The different device types listed In simple mode all feedback paths of the output pins are routed
in the table can be used to override the automatic device selection via the adjacent pins. In doing so, the two inner most pins ( pins
by the software. For further details, refer to the compiler software 18 and 19) will not have the feedback option as these pins are
manuals. always configured as dedicated combinatorial output.
When using compiler software to configure the device, the user

must pay special attention to the following restrictions in each
mode.
Registered Complex Simple Auto Mode Select

ABEL P20V8R P20V8C P20V8AS P20V8
CUPL G20V8MS G20V8MA G20V8AS G20V8
LOG/IC GAL20V8 R GAL20V8 C7 GAL20V8 C8 GAL20V8
OrCAD-PLD "Registered"' "Complex"' "Simple"' GAL20V8A
PLDeslgner P20V8R2 P20V8C2 P20V8C2 P20V8A
TANGO-PLD G20V8R G20V8C G20V8AS3 G20V8
1) Used with Configuration keyword.
2) Prior to Version 2.0 support.
3) Supported on Version 1.20 or later.
2-27 4/91.Rev.A
[JJ
1.J
LattiOO@
Semironductor
Corporation
Corporation
GAL20118B
GAL20118A
GAL20V8A
REGISTERED MODE
In the Registered mode, macrocells are
In are configured
configured as dedicated mode. Dedicated
mode. input or
Dedicated input oroutput
output functions
functions can
can be
be implemented
implemented
registered outputs or as I/O
110 functions. as subsets
as subsets of
of the
the VO
I/O function.
function.
Architecture configurations available in this

this mode
mode are similar to
to Registered outputs
Registered outputs have
have eight
eight product
product terms
terms per
per output.
output. I/0's
I/O's
the common 20R8 and 20RP4 devices with with various permutations
permutations have seven
have seven product
product terms
terms per
per output.
output.
of polarity, I/O and register placement.
TheJEDEC
The JEDECfuse
fuse numbers,
numbers, including
includingthe
theUser
UserElectronic
ElectronicSignature
Signature
All registered macrocells share common
common clock
clock and
and output
output enable
enable (UES) fuses
(UES) fuses and
and the
the Product
Product Term
Term Disable (PTD) fuses,
Disable (PTD) fuses, are
are
control pins. Any
Any macrocell can be configured as registered or shown on
shown on the
the logic
logicdiagram
diagram on
on the
the following
following page.
page.
I/O. Up
Up to eight registers or up to
to eight
eight I/O's
I/0's are
are possible
possible in
in this
this
CLK
elK
Registered Configuration for
for Registered
Registered Mode
Mode
- SYN-0.
-SYN=O.
- AC0=1.
-ACO=1.
X0R-0 defines
- XOR=O defines Active
Active Low
Low Output.
Output.
-• XOR=1
XOR.1 defines Active High
defines Active High Output.
Output.
AC1=0
- AC1 defines this
=0 defines this output
configuration.
-- Pin
Pin 1 controls common CLK
controls common CLK for
for the
the registered
registered outputs.
outputs.
-- Pin
Pin 13
13 controls
controls common
common OEOE for
for the
the registered
registered outputs.
outputs.
-- Pin
Pin 1 & Pin 13 are
Pin 13 are permanently
configured asas CLK
CLK &&
OE.
OE.
'.. ... - .. ,_._----------------------------------,
OE
OE
Combinatorial
Configuration for
for Registered
Registered Mode
Mode
- SYN=O.
SYN=0.
-ACO:1.
- AC0=1.
-- XOR=O
XOR=0 defines
defines Active
Active low
Low Output.
Output.
-- XOR=1 defines Active
High Output.
Output.
-- AC1
AC1=1=1 defines
defines this
this output
configuration.
-- Pin
Pin 11 & Pin
Pin 13
13 are
are permanently
configured as
as CLK
CLK &
&
OE.
OE.
'..----------------------.---------------------,

all of
of the architecture control
control bits and
and checks
checks for
for proper
proper pin
pin usage
automatically.
2-28
2-28 4/91.Rev.A
4/91.Rev.A
I id c t o r ®
GAL201f8B
GAL20V8A
DIP (PLCC)
DIP (PLCC) Package Pinouts
....
".
1(2)
1(2) D ....
0 • B ,. 11 20 .. 211
" " Pro
2(3)
2(3) D 23(27)
-CJ23( 27)
rr'
0000 I n • URIC 22
M•m•!".•"•!!!•1"•M•MEMEHIE:111•! OLMC 22
22(26)
2(26)
0210 XOIT2560
XDR·2560
3(4)
3(4) D Otamsommomm molomoolosonumumoomelsosoomounwl ACI2632
AC1·2632
tr"
03,. 1111111111111111111111111111111111110
LIKIMEMEMEMEMEREMEMENEMEIN OLMC21
OLMC 21
(25)
21(25)
111111111 P I N E 1111111111111111 M a r i l l
06DO X011-2561
XOR·2561
4(5)
4(5) D AC12633
AC1·2633
kl..111111111111111111111111111111111111111111
0='
0840"'0 M E M B E I R F L I T H E I R E E R E I M I S I L I
OLMC20
OLMC 20
20(24)
0(24)
0920
== 3=f XOR·2562
X011-2562
5(6)
5(0 AC1-2634
AC1·2634
k 709S0„ 0 11111111111111111111111111111111111111111111
0='
-0- OLMC19
OLMC 19
MIMMIRMIMMONIMMIREMI 9(23)
9(23)
1240 X011-2563
XDR·2563
6(7)
6(7) molusloomosnosieneoloum AC1·2635
AC1-2635
1280 I H I I I I I I I I I I I I I I 1111111111111111111111111
M C 18
OLMC 18 rJ 8(21)
18(21)
[J
1
"'"1'"1'"1'111111111111111111111111!
1560 XOR·2564
XOR-2564
7(9))8
7(9 AC1·2636
AC1-2636
1600
•LELEMEMBLIEREMEMEMEHEREILI
.r, OLMC17
OLMC 17 rJ 7(20)
(7(20)
8(10))8
8(10
"10
kannto•oommoolomsnagoonummin lionmentimosariii
3=f
1880i i i i i i i i i i i i i i i i I i i i i i i i i • i i i i i i i i i i i i i i i ; j j XDR·2565
XOR-2565
AC1·2637
ACI-2637 [J
/820 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 H 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 M e i n
1920
IPEIPLIMELIELTEMBRIMEMERMI OLMC 16
OLMC 16 11 6(19)
116(19)
9(11
9(11)
22DO XOR·2566
XOR-2566
AC1·2638
ACI-2638
[J
2240
2240IHEMEREMEMEHEIPMEH•EEKILI -0 OLMC 15
U K 15 rJ 15(18)
10(12)) 0
10{12
2520
2520
moulz:::::::Emzsuzuoamii=111SEEE1
Iltsioninommeamloomanootommemoneoloom luitonin
XDR·2567
X0R-2567
AC1·2639
ACI-2639 [J
11(13)) 0
11111111111 I I I M i l l
11(13 Oltassoommoonalommoulanutin m u m n o m • E i n :4 -CJ 14(17)
14(17)
DE
"03 13(16)
3(16)
64-USERELECTRONIC SIGNATUIEFUSES
•-••2630, 2eal SYN·2704
SYN-2704
Byte 71Byte 8 B y t e 1 !Byte 0 ACO·2705
AC0-2705
L
S
B B
2-29
2-29 4 / 9 1 . 1 R e v 4/91.Rev.A
. A
ALLattice
.l..J Semiconductor
Semioonductor
GAL20118B
Specifications GAL20VBB
Corporation
GAL20VBA
COMPLEX MODE
In the Complex mode, macrocells are configured as
as output
output only pability. Designs
Designs requiring eight IIO's
I/0's can
can be
be implemented
implemented in
inthe
the
or I/O
1/0 functions. Registered mode.
Registered mode.

in this
to All macrocells
All macrocells have
have seven
seven product
productterms
termsperperoutput.
output. One
One product
product
the common 20L8 and 20P8 devices withwith programmable
programmable polarity
polarity term is
term is used
used for
for programmable
programmable output
output enable
enable control.
control. Pins and
Pins 1 and
in each macrocell. 13 are
13 are always
always available
available as
as data
data inputs
inputs into
intothe
theAND
AND array.
array.
Up to six IIO's
I/0's are possible
possible in this mode. Dedicated
Dedicated inputs
inputs or
or The
TheJEDEC
JEDECfuse
fuse numbers
numbers including
including the
the UES
UESfuses
fusesand
and PTD
PTDfuses
fuses
outputs can be implemented as subsets of of the I/O function.
function. The are
are shown
shown on
on the
the logic
logic diagram
diagram on on the
thefollowing
following page.
page.
two outer most macrocells (pins
(pins 15 &
& 22) do
do not have input
input ca-
ca-
................... _------_ ..... _............ Combinatorial I/O Configuration

Combinatorial 1/0 Configuration for
for Complex
Complex Mode
Mode
J -SYN-1.
- SYN=1.
-ACO
- XOR.O
.. 1.
- AC0=1.
XOR=0 defines
defines Active
Active Low
Low Output.
Output.
-- XOR=1
XOR=1 defines Active
Active High
High Output.
Output.
-AC1=1.
-AC1=1.
-- Pin
Pin 16
16 through
through Pin
Pin 21 are configured
21 are configured to
tothis
this function
function..
...... -............ -- ................................
po . . . - . . . . . . . . . . _ - . . . . - - • • - - . . . . . . . - - . - - - _ . . . - . . .
Combinatorial
Configuration for
for Complex
Complex Mode
Mode
i; P-r,D XOR
X0 R
Cl--o
o f l
-SYN=1.
- SYN=1.
-ACO .. 1.
- AC0=1.
-- XOR
XOR=0
-- XOR=1
..Odefines
defines Active
Active Low
XOR=1 defines Active
-AC1-1.
Low Output.
Active High
Output.
High Output.
Output.
- AC1=1.
-- Pin
Pin 15
15 and Pin 22
and Pin 22 are
are configured to
to this
this function.
function.
-- .... ---.-.. _-_ ...... __ ._------------_ ...

all of the
the architecture control bits.and
bits and checks
checks for
for proper
proper pin
pin usage
automatically.
!
/
2-30
2-30 4191.Rev.A
4/91.Rev.A
!lJ
tBttice
LLattice®
Semiconductor
Semironductor
Corporation
®
GAL20118B
GAL20118A
GAL20V8A
COMPLEX MODE LOGIC DIAGRAM
DIP (PLCC)
Package Pinouts
.. .. ....
1(2) D .
1(2)
2(3) E
2(3) >
L.>---
• • • I 1 212 1 6
11 2 010 2 414 2 221 Pill
PlD
.A
j - - C D 23(
23(27)
27)
.,,,
0K7.:122(26)
0000
a=
0280
:a=
'tj=
DUE 22
OLMC 22
X0R-2560
XOR-2560
... -r122(26)
3(4)
3(4) ACl-2632
AC1-2632
"" J
OLMC21
OLMC 21 ,..r,2121(25)
(25)
"., "'--': XOR-2561
XOR-2561
401 .--..
4(5) ACI-2633
ACl-2633
"40
0640
:a= OLMC
OLMC20
20 =:l
--.::J 02
20(24)
0(24)
XOR-2562
MR-2562
5(6)
5(6) D "" ACl-2634
AC1-2634
,."
!!! IC ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! = CILMC19
OLMC 19 n v
J-G1
9(23)
19(23)
-=-
-
1240
1240 XOR-2563
XOR-2563
6(7)
6(7)
.---.. i i i i i i i i i ni i i i i i i i i 11 1 0 1 • M= • i i i i i i i i i i i i
mossiminommilenommon t o s o m onn a o i sl n s m o i l w l ACl-2635
ACI-2635
k I"80
I I I I I I I I I I I I I I I I 11111111111111111111N
M
1280
gigEmmemellimili•ilinitimmi ,_
ilEMEMEMENIEMMIIIIIMPIPc M C 18
OLMC 18 18(21)
1580 XOR-2564
X0R-2564
7(0))0
1580
gnillIMIIIMIMIIIIIIII - ACl-2636
ACI-2636
7(9 k-7—Iiiiiiiiiiini
60, Iiiiiiiiiiiiiiimul I i i i i i i i i i i i i i i r
"" glimmemenemenmeming= .0-
OLMC 17
0ilfi1111111:iiiiiiiiissimislimiligm = MAC 17 — dv) o D -Y"'l1
1 7 ( 27(20)
0)
8(10))D
8(10
1880
1880
iiiiiiiiiiiiiiiiiiiiiiiiiriiiiiiinolL
1.-atimamosomuswoomoolooesmilen1•I m. .
XOR-2565
XOR-2565
ACl-2637
ACI-2637 J
1320111111111111111111111111111111111M1
"" FIERIERELIELI"Ll"!1"EMEME--
:::=:::211=:::=:•:=Eirdireirmancramms OLMC 16
OLMC16 v 16(19)
22" =8= XOR-2566
XOR-2566
9(11))8
9(11 2200l n a n a s o n l i k AnommosounnasseaumnI!.m ACl-2638
AC1-2638
2240111111E1111111111111111111111111111
2240
LIMEHIETI• !I!!!!! MITEMBEE--
OLMC 15
OLMC15 15(18)
K=315(18)
10(12)
10(12)
,--,. .."
2620 i i i i i i i i i i i i i i i i i
II.M o s i o o nm m m u m . u n n
i i i i i i i i i i i i i r l . "
o os no m o n felloonot:41
i
XOR-2567
XOR-2567
ACl-2639
ACI-2639
I -a 14(17)
110. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 111111111111111 I I I I I I ..... C314(17)
11(13),--,.
11(13) mel ono ommemoon emounolegalumelo • moust4
-a 13(16)
C l 1306)
1113
2703
fI4.U8EII ELECTRONIC8IGNAlURE
64-USERB.fCIlIONIC SIGNATUREFU8EB
FUSES
l&:7iC.·....
M
bits 7IByts 6
M LL
B y . . _,:01
t e
2030, 2031
1 'Byte 0
SYN-2704
SYN-2704
ACO-2705
AC0-2705
88 8 8
B8 BB
2-31
2-31 4 / 9 1 . 1 R e v 4/91_Rev.A
. A
L/Semiconductor
Lattice
Corporation
GAL201/8B
Specifications GAL20VBB
GAL201/8A
GAL20VBA
SIMPLE MODE
In the Simple mode, pins are configured as dedicated inputs or Pins 1 and
Pins are always
and 13 are always available
available as
asdata
datainputs
inputs into
intothe
theAND
AND
as dedicated, always active, combinatorial outputs. array. The "center"
array. ''center two
two macrocells
macrocells (pins
(pins 18
18 && 19)
19)cannot
cannotbe beused
used
in the
in the input
input configuration.
configuration.
in this
to
the common 141_8
14L8 and 16P6 devices with
with many permutations
permutations ofof The
TheJEDEC
JEDECfuse
fuse numbers
numbers including
includingthe
the UES
UESfuses
fusesand
andPTD
PTDfuses
fuses
generic output polarity or input choices. are
are shown
shown on
on the
the logic
logic diagram
diagram onon the
thefollowing
following page.
page.
All outputs in the simple mode have a maximum of of eight

eight product
product
terms that can control the logic. In addition, each
logic. In each output
output has
has
polarity.
...... _--------------_. __ ._------.----------

Combinatorial
Output with
with Feedback
Feedback Configuration
Configuration
Vee
V cc for
for Simple
Simple Mode
Mode
-- SYN=1.
SYN=1.
-ACO=O.
- AC0=0.
-- XOR=O
XOR=0 defines
defines Active
Active Low
Low Output.
Output.
-- XOR
XOR=1 .. 1 defines
defines Active
Active High
High Output.
Output.
-- AC1
AC1=0 =0 defines
defines this
this configuration.
configuration.
-- All
All OLMC
OLMC except
except pins 18 &
pins 18 & 19 can
can be
be configured
configuredto
to
this
this function.
function.
Combinatorial Output Configuration
Configuration for
for Simple
Simple Mode
Mode
-- SYN=1.
SYN=1.
-ACO=O.
- AC0=0.
-- XOR=O
XOR=0 defines
defines Active
Active Low
Low Output.
Output.
-- XOR=
XOR=11 defines
defines Active
Active High
High Output.
Output.
-- AC1 =0 defines
AC1=0 defines this
this configuration.
configuration.
-- Pins 18 &
Pins 18 & 19 are
are permanently
configured to
to this
this
.'-------._.---------------------------------_.: function.
function.
Dedicated
Dedicated Input Configuration
Configuration for
for Simple
Simple Mode
Mode
-SYN .. 1.
-ACO-O.
-- XOR
XOR=0 ..Odefines
defines Active
Active Low
Low Output.
Output.
-- XOR=1
XOR=1 defines
defines Active
Active High
High Output.
Output.
- AC1
AC1=1 =1 defines
defines this
this configuration.
configuration.
.._---------------------------.--------------,. --All
All OLMC
this
OLMC except
except pins 18 &
pins 18 & 19
19 can
can be
be configured
configured to
to
this function
function..
Note: The development software configures all of the architecture control

control bits
bits and
and checks
checks for
for proper
proper pin
pin usage
automatically.
2-32
2-32 4f91.Rev.A
4/91.Rev.A
I,
::j
Lattice® GAL201f8B
Specifications GAL20V8B I.;
1.1
1 Ind ISemiconductor
Semironductor
Corporation
GAL20V8A Ii

DIP (PlCC)
Package Pinouts
. ....
1(2)
1(2) LJ
0 '
2(3) LJ
2(3)
, • • ,.
" 8 1 2 1 6 .. 1M 211
2
II
40
.A
j 23(27)
rCJ23( 27)
11111•1.11L1
.... !!!!!!!!!!1!!•!!!!!"EMILSIMEIMME OLMC 22
OLMC 22 N I b
.... i i i n i i i i i i i i i i i i i i i i i i i i::a=:::t XOR·2560
i i i a . 0011-2560
AC1-2632
AC1·2632
J ... 22(26)
-cl22( 26)
.A
3(4)
3(4) 0
"..
0280 1 1 1 1 1 1 1 1 1 1
0320
WEN HEREPIEHEMEMELTEnr47 •• • 0I-MC
1111 0 111111 0 111 a l
OLMC 21
21
XOR-2561
XOR·2561
n
J .. -cl2121(25)
(25)
....
0600
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 P E E ::::a=:::::::I
....•01•
A C 1 -AC1·2633
2633
4(5)
4(5) LJ 10.. i m e e m 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1
....
0940
....
MIME 11011111111111111111111111
MELSEMEMEMEMEHEMEHLIMEmeml .0.
111111111MILitinitilliiiiiiii110-
OLMC 20
XOR·2562
AC1·2634 J
n n220(24)
0(24)
5(6))L..J
5(6 .....
....
0960
1111111111111111111111111111111111m1
MENELHEMEHIEHLIPIERIELEWIr4: In OLMC °WC 19
19 h
XOR-2563
XOR·2563 0 119(23)
9(23)
'240
i i r i i i i r i i E • i i i i i ! i " E 2::a=:::t
E'- AC1-2635
AC1-2635
::;,
J
6(7)
6(7) D
"t'4'
'2" "1"11"1"111
IIIIIIIIIIIIIII I 11111111111110111=
1 momonim. ;$
Jb..
1280
OLMC 18
I H I M E I B M M I R I M I N I M h a — OLMC18 X0R-2564
XOR·2564 8(21)
"""'118(21)
iiiiiiiEhEiliEricao•-:„Eram:::=SE=
7(9)
7( 9) L....J
" 1560
..
iiiiiiiiiiiiiiiiiiiiIIMINIIIIiiiiiiii
lomollootoomomi taoloomounmoomoommososomm$1
::::a=:::::::I AC1·2636
AC1-2636
"..
1600
IIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIII
-0- OISIC 17
OLMC 17
X0B2565
XOR·2565
n -C"] 117(20)
7(20)
(B80 1 1 41 1" 111 "1 1
"SO
1 11 111 21 49 111 9B 1E 1 : 1" 2! : :: : 1 21: 1
se 1m1t •1pm
1 1• 1 1 1 : 1 3 1 1 r 7 AC1-2637
AdI-2637 J
8(10
8(10)) IIP. M E I M E N E M I I I I I M I N E M I L K I I I
""
1920
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
HINEEMEMEMEMBEEMEME
== 1111111111111111,1111111EllisilElialikri=
OLIC 16
OLMC 16
XOR-2566
XOR·2566
AC1-2638
AC1-2638
n
J ... -nl16(
6(19)
9)
22,.
2200
9(1 1)
9(11) —1..iAnannommEnammonnol mnino
iiiiiiiiiiiiiiiiiiiiiiiiiiilliiiiiiiiii
n
s
lg
m
Jb,. . . .-
2240
2240
1111111111111011111111111111 1111111111
I M E H I M I H I M I H E M E M E M B E :.1.n1 OLMC 15
OLMC 15
25"2
mainsidainsirmialEMELEIREEL:1 9::::::=1 X0R-2567
XOR·2567
AC1-2639
15(18)
15(18)
10(1 2)D
10(12)
0iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiir .A
AC1-2639
11(1 3)
11(13)
ilimmilummilimilffilU
.11mul.11111111111..11.1u...1"."111 R I '
III* s o i n o m m o i o u s m o l l s s o s s o s s o u t i m a s •es m e gill
....
I -CJ 14(17)
13(16)
84-USER
134-USERElECI'RONIC
ELECTRONICSIGNATURE
SIGNATUREFUSSS
FUSES
2'"
2703
1:\=,··....
Byte71Byte
101 L
B y t .. . e
2830, 2e31
1IByte
SYN·2704
SYN-2704
ACO·2705
ACO-2705
8S S S
B
B BB
2-33
2-33 4 / 9 1 . R e v .4191.Rev.A
A
[JJ
.l.I
tattice®
Lattke®
Semiconductor
C o r p Corporation
oration
GAL20118B
Commercial
Commercial
ABSOLUTE MAXIMUM RATINGS')
RATINGS(l) RECOMMENDED OPERATING
COND.
Supply voltage Vcc — 0 . 5-0.5 to +7V
Vee ....................................... Commercial Devices:
Commercial Devices:
— 2 . -2.5 5 to Vee
Vcc +1.0V Ambient
Ambient Temperature
Temperature (T(TA) 0
A ) •••••••••••••••••••••••••••••••• 0 to
to 75°C
75°C
Off-state output voltage applied ........ — ,.2-2.5
. 5 to Vee
Vcc ++1.0V
1.0V Supply
Supply voltage
voltage (Vee)
(Vcc)
— 6 5 -65 to 150°C with
with Respect to
to Ground ......................
+ 4 . 7+4.75 5 to to +5.25V
+5.25V
Power Applied ........................................
— 5 5 -55 to 125°C
1.Stresses above
above those listed under the "Absolute Maximum
Maximum
Ratings" may cause permanent damage to the device. These These
are stress only ratings and functional operation ofof the
the device
at these or at any other conditions above
above those
those indicated
indicated in
in the
the
programming, follow
follow the
specifications).
Specified)

CONDITION MIN.
MIN. TYP."
TYP.3 MAX.
MAX. UNITS
UNITS
VIL Input Low Voltage Vss-0.5

Vss – 0.5 -- 0.8
0.8 VV
2.0 - VCC+1
Vcc-1-1 VV
ilL' Input or 1/0
I/O Low
Low Leakage Current OV VIN 5 VIL
DV5_ VIN Vit. (MAX.)
(MAX.) -— -— -100
–100 p.A
!LA
IIH
ilH Input or 1/0
I/O High Leakage Current 3.5V VIN 5 Vee
3.5V S VIN Vcc -- -- 10
10 ;.LA
!LA
VOL Output Low Voltage 10L=MAX. Yin
lot_ = MAX. Vi n = VIL
VII_or VIH1-I
or V1 -— -
— 0.5
0.5 VV
loH = MAX. Vin
MAX. Vi n = VII_
VIL or VIH
or V11-I 2.4
2.4 -— -— VV
10L
i0L Low Level Output Current -— -— 24
24 mA
mA
10H
–3.2 mA
mA
los2
i0S2 Output Short Circuit Current Vcc=5V VOUT== 0.5V
Vcc = 5V VOUT TA= 25°C
0.5V TA= 25°C -30
–30 -— -150
–150 mA
mA
Icc
1CC Operating Power
Power Supply
Supply Current VIL=
Vit.. = 0.5V VIH = 3.0V
0.5V Vii-l= ftoggle == 25MHz
3.0V toggle 25MHz -— 75
75 115
115 mA
mA
Outputs
Outputs Open
Open (no
(no load)
load)
1) The leakage current is due to the internal pull-up resistor on
on all pins. See Input
pins. See Input Buffer
Buffer section
secfon for
for moreJnformation.
mo e information.
2) One output at a time for a maximum duration of of one
one second. Vout = 0.5V
was selected
selected to
to avoid
avoid test
test problems
problems caused
caused by
bytester
tester
Guaranteed but not
ground degradation. Guaranteed not 100% tested.
3) Typical values are
are at Vcc = 5V
5V and TA == 25°C
and TA 25 °C
CAPACITANCE (TA =
(TA = 25°C, ft = 1.0 MHz) =
SYMBOL PARAMETER
PARAMETER MAXIMUM"
MAXIMUM* UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
C,
CI Input Capacitance 88 pF
pF Vcc=
Vee = 5.0V,
5.0V, V,
VI == 2.0V
2.0V
Clic
CliO 1/0
I10 Capacitance 88 pF
pF Vcc == 5.0V,
Vcc V'iO
5.0V, V1 10== 2.0V
2.0V
"Guaranteed
*Guaranteed but not 100%
100% tested.
2-34 4/91.Rev.A
4/91.Rev.A
flJ
LLattice'
•AC
UJtticeGP
Semironductor
Semiconductor
C0i'p(X'8t/01l
Corporation
GAL,201/8B
Commercial

OVer Operating Conditions
Conditions
TEST -7
·7 -10
·10
PARAMETER
UNITS
CONDI.
COND'. MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX.
tpd 11 Input or 110
Input I/0 to
to Combinational Output I 88outputs switching
switching 33 7.5
7.5 33 10
10 ns
ns
I 11output switching
switching -— 77 -— -— ns
ns
tco 11 Clock to Output Delay 22 S5 22 77 ns

ns
tcf2 -— Clock to Feedback Delay -— 33 -— 66 ns
ns
tsu -— Time, Input
Setup lime, or Feedback
Input or Feedback before Clockt
Clocki 77 -— 10
10 -— ns
ns
th -— Hold Time,
lime, Input or Feedback after
after Clockt
Clock')' 00 -— 00 -— ns
ns
83.3 -— 58.8
S8.8 -— MHz
MHz
External tco)
f max33
tcf)
100
100 -— 62.5
62.S -— MHz
MHz

with 100
100 -— 62.5
62.S -— MHz
MHz
No Feedback
twh4
twh -— Clock Pulse Duration, High 5
S -— 88 -— ns
ns
twt'
twi's -
— Clock Pulse Duration, Low S5 -— 88 -— ns
ns
ten 22 Input or 110
Input I/O to
to Output 33 99 33 10
10 ns
ns
22 OE.!.
0E1 to Output 22 66 22 10
10 ns
ns
tdis 33 Input or 1/0
Input I/O to
to Output 22 99 22 10
10 ns
ns
33 OEt
0E1 to Output 1.S
1.5 66 1.S
1.5 10
10 ns
ns
1) Refer to Switching Test Conditions sectIOn.
section.
2) Calculated from fmax with internal feedback. Refer
Refer to
to fmax
fmax Descriptions
section.
3) Refer to fmax
imax Descriptions section.
4) Clock pulses of widths less than the specification may be detected as
as valid

CONDITIONS
GND to 3.0V +5V
+5V
Input Rise and Fall limes
Times 3ns 10%-90%
3ns 10*/0 – 90%
1.5V
Output Timing Reference Levels
OutpU1liming 1.SV
1.5V 1
Output Load See
See Figure
O.SV from steady-state active
3-state levels are measured 0.5V
level.
FROM OUTPUT (010)
FROMOUTPUT (0/0) --+---..- TEST
TESTPOINT
POINT
UNDER TEST
UNDERTEST
(see figure)
figure) CL
R2
Test Condition RI
Hi R2
R2 CL
CL
1 2000
2000 3900 SQpF
50pF
2 Active
Active High .0
00 3900
3900 SOpF
50pF
3
Active
Active
Low
Active Low
Active High
High
Active Low
-
2000
2000
.0
2000
3900
3900
3900
3900
3900
50pF
50pF
SpF
5pF
5pF
5pF
C
CL INCLUDESJIGA
LlNCLUDESJIG NDP
AND ROBET
PROBE OTALC
TOTAL APACITANCE
CAPACITANCE
2-35 4/91.Rev.A
4/91.Rev.A
1£ Lattice® Semiconductor
SemiconduGwr
Corporation
Specifications GAL201113A
GAL20V8A
Commercial
Commercial
ABSOLUTE RATINGS(1) RECOMMENDED OPERATING
COND.
vee .......................................
Supply voltage Vcc — 0 . 5-0.5 to ++7V
7V Commercial
Commercial Devices:
Devices:
— 2 -2.55 to to Vcc +1.0V
Vee + 1.0V Ambient Temperature
Ambient Temperature (TA) 0
(TA ) •••••••••••••••••••••••••••••••• to 75°C
0 to 75°C
Off-state output voltage applied ..........— 2-2.5 . 5 toto Vee
Vcc +
+1.0V
1.0V Supply voltage
Supply voltage (Vee)
(Vcc)
— 6 5 -65 to to 150°C with Respect
with Respect to
to Ground
Ground ......................
+ 4 . 7+4.75 5 to to +5.25V
+5.25V
— 5 5 -55 to 125°C
Power Applied ........................................
1.Stresses above those listed under the· the "Absolute Maximum
Absolute Maximum
the device. These
These
are stress only ratings and functional
functional operation of the
the device
device at
at
these or at any other conditions above those indicated in the the
Specified)

CONDITION MIN.
MIN. TYP.2
TYP.2 MAX.
MAX. UNITS
UNITS
VIL Input Low Voltage Vss -0.5

Vss-O.5 -— 0.8
0.8 VV

2.0 -— VcC+1
Vcc+1 VV
IlL
ilL Input or 1/0
input I/O Low Leakage Current OV VIN 5 VII_
OV 5 VIN VIL (MAX.)
(MAX.) -— -— -10
-10 J.,4
J.lA
IIH Input or 110 leakage Current
I/O High Leakage VIH 5 VIN
VIH VIN _c_VCC
Vee -
— -— 10
10 p_A
J.lA
VOL Output Low
Low Voltage loL =
10L = MAX.
MAX. Vi
Yinn=
= VIL
Vit. or
or VIH
VIH -
— -— 0.5
0.5 VV

loH == MAX. Vin
MAX. Vi VIL or
n == VII_ VIH
or VIH 2.4
2.4 -— -— VV
10l
i0L Low Level Output Current
low -— -— 24
24 rnA
mA
10H High Level
level Output Current -— -— -3.2
-3.2 rnA
mA
los'
lost Output Short Circuit Current VOUT=
Vcc = 5V Va
Vcc=5V l i ' = 0.5V
0.5V T,TA- =, 25°C
25°C -30
-30 -— -150
-150 rnA
mA
Operating Power VIL
ViL =. 0.5V
0.5V VVIH
H = 3.0V
3.0V toggle =
f,oggl8 - , 15MHz
15MHz L·25
L -25 -— 75
75 90
90 rnA
mA
ICC
Icc Supply Current Outputs
Outputs Open (no
(no load)
load) flO9gl8 = 25MHz
toggle --, 25MHz LL -101-15
-10/-15 -— 75
75 115
115 rnA
mA
f'099I8 15MHz
fioggie = 15MHz 0·15/-25
0 -15/-25 -— 45
45 55
55 rnA
mA
1) One output at a time
time for
for aa maximum duration of
of one second. Vout
Vout == 0.5V
0.5V was
was selected
selected to
to avoid
avoid test
test problems
p oblems caused
caused by
by tester
tester
tested.
2) Typical values are at Vcc = - 5V
5V and TA = 25 ·C
and TA *C
=
(TA = 25°C, f1= 1.0 MHz)
CAPACITANCE (TA MHz) =
SYMBOL PARAMETER
PARAMETER MAXIMUM-
MAXIMUM UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
C,
Ci Input
pF VVcc
cc == 5.0V,
5.0V, V,
Vi == 2.0V
2.0V
Cu,
ClIO 1/0
I/O Capacitance
Capacitance 10
10 pF
pF Vee
Vcc== 5.0V, VIIO == 2.0V
5.0V, VL,0 2.0V
'Guaranteed
'Guaranteed but not 100%
tested.
2-36
2-36 4191.Rev.A
4/91.Rev.A
GAL20118A
Specifications GAL20V8A
.lJ
L ISeicot nd.uctor®'c
SemioonducUJr
CorporaUon
Corporation
e
Commercial
Commercial
AC CHARACTERISTICS
Over Recommended
Conditions
TEST -10
-10 -15
-15 -25
-25
PARAMETER
PARAMETER DESCRIPTION
DESCRIPTION UNITS
UNITS
CONDI.
COND'. MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX.
tod
tpd 1 Input or va
input or I/0 to
to Combinational Output
Combinational Output 33 10
10 33 15
15 33 25
25 ns
ns
tco
teo 1 Clock to
Clock to Output Delay 22 77 22 10
10 22 12
12 is
ns
'Liz2
tel Clock to
Clock to Feedback Delay
Delay -
— 77 -— 88 -— 10
10 ns
ns
tsu Time, Input or Feedback

Setup Time, before Clocki
Feedback before 10
10 -— 12
12 -— 15
15 -— ns
ns
th Hold Time, Input or

Hold or Feedback after
after Clocki
Clockt 00 -— 00 -— 00 -— ns
ns
11 Maximum Clock
Maximum Frequency with
Clock Frequency with 58.8
58.8 - — 45.5
45.5 -— 37
37 - — MHz
MHz
External too)
fmax33
fmax 11 Maximum Clock
Maximum Clock Frequency with
with 58.8
58.8 -— 50
50 -— 40
40 -— MHz
MHz
Feedback, 1/(tsu + tel)
Internal Feedback, tcf)
11 Maximum Clock Frequency
Maximum Clock Frequency with
with 62.5
62.5 -— 62.5
62.5 -— 41.7
41.7 -— MHz
MHz
No
No Feedback
twh4
twh Clock Duration, High
Clock Pulse Duration, High B
8 -— 88 -— 12
12 -— ns
ns
twl4
tw14 Clock
Clock Pulse Duration, Low
Low B
8 -— 88 -— 12
12 -— ns
ns
ten 22 Input va to
Input or I/O Output Enabled
to Output Enabled -
— 10
10 -— 15
15 -— 25
25 ns
ns
22 OE.!. Output Enabled
0E1 to Output -— 10
10 -— 15
15 -— 20
20 ns
ns
tdis 33 Input va to
input or I/O Output Disabled
to Output -— 10
10 -— 15
15 -— 25
25 ns
ns
3 OEi
OET to
to Output Disabled
Disabled -— 10
10 -— 15
15 -— 20
20 ns
ns
1) Refer to Switching Test Conditions section.

2) Calculated from fmax with internal feedback. Refer to
feedback. Refer to fmax
section.
3) Refer to Imax
fmax Descriptions llection.
section.
4) Clock pulses of widths
widths less than
than the specification
specification may be detected as valid clock
clock signals.

GND to 3.0V +5V
+5V
3ns 10'/0 – 90%
1.5V
1.5V
1
Output Load See
See Figure
3-state levels are measured 0.5V from steady-state active
from steady-state FROM OUTPUT (010)
FROMOUTPUT (0/0) ---+----+--TEST
TESTPOINT
POINT
level.
UNDER TEST
UNDERTEST
Output Load Conditions (see figure)
Cl
Test Condition R,
RI Rz
R2 CL
CL
11 2000 3900
3900 500F
50pF
2 Active
Active High ...
00 3900
3900 50pF
50pF
Active
50pF
3 Active
Active High e.
00 3900
3900 5pF
5pF C
CL INCLUDES
JIGAND PROBE TOT
TOTAL CAPACITANCE
ALCAP ACITANCE
Active Low
Active Low 2000 3900
3900 5pF
2-37 4191.Rev.A
4/91.Rev.A
Lattice® GAL20118A
.l..J oScmiconductnr
Semiconductor
C o r p Corporation
ration Industrial
Industrial
COND.
Supply voltage Vcc — 0 . 5-{).5 to +7V

Vee ....................................... +7V Industrial
Industrial Devices:
— 2 . -2.5
Input voltage applied ........................... 5 to to vee
Vcc +
+1.0V
1.0V Ambient Temperature
Ambient Temperature (TA) — 4 0-40 to
(TA) ............................ to 85°C
85°C
Oft-state output voltage applied ..........
Off-state — 2-2.5 . 5 to Vcc +1.0V
Vee + 1.0V Supply voltage
(Vcc)
with Respect to
to Ground
Ground ......................
+ 4 . 5+4.50 0 toto +5.50V
+5.50V
— 5 5 -55 to 125°C
Power Applied ........................................
Maximum
Ratings·
These
functional operation
operation of the device
device at
these or at any other conditions above those indicated in in the
the
operational sections of this specification is not
not implied (while
OVer
Over Recommended Operating Conditions (Unless
(Unless Otherwise
Specified)

CONDITION MIN.
MIN. TYP."
TYR, MAX.
MAX. UNITS
UNITS
VIL Input Low Voltage Vss-O.S

Vss –0.5 -— 0.8
0.8 VV
2.0 -— VcC+1
Vcc+l VV
IlL Input or 110
I/O Low
Low Leakage
Leakage Current OV
CVSVIN
VIN S Vil (MAX.)
VII_ (MAX.) -— -— -10
–10 RA
J-lA
IIH Input or VO
I/O High Leakage Current VIH
Vit-i SVIN
VIN S Vee
VOC -— -— 10
10 J-lA
1.1.A
VOL Output Low

Low Voltage
Voltage 101.
lot. -= MAX. Vi
Yinn -= Vil
Va. or
or VIH
VII-, -— -— 0.5
0.5 V
lok ..
= MAX. Vin.= VIL
MAX. Vin Vit. or VIH
or VII-1 2.4
2.4 -— -— VV
10L
i0L Low Level Output Current
Curren: -— -— 24
24 mA
mA
10H
i0H High Level Output Current -— -
— -3.2
–3.2 mA
mA
los'
i0S1 . Output Short Circuit Current Vccz
Vcc = 5V YOUTz= 0.5V
5V VOUT TA=- 25·C
0.5V TA 25°C -30
–30 -— -150
–150 mA
mA
Operating Power VIL=
Vit. = 0.5V VIH=3.0V
0.5V VIH = 3.0V floggle
toggle = 25MHz LL ·15/-25
-15/-25 -— 75
75 130
130 mA
mA
Icc
iCC Supply Current Outputs load) floggle
Outputs Open (no load) toggie ..
= 15M Hz
15MHz a0 -20/-25
-20/-25 -— 45
45 65
65 mA
mA
time for
one second. Vout ..= 0.5V
was selected
selected to
to avoid
avoid test
test problems
problems caused
caused by
by tester
tester
2) Typical values are at Vcc =- 5V and TA
TA"225
5 ·C
'C
=
(TA = 25°C, ff = 1.0 MHz)
CAPACITANCE (TA
SYMBOL PARAMETER
PARAMETER MAXIMUM-
MAXIMUM* UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
C, Input Capacitance 88 pF
pF Vee
Vcc== 5.0V,
5.0V, V,
V, == 2.0V
2.0V
Coo 110
I/O Capacitance 10
10 pF
pF Vee
Vcc== 5.0V,
5.0V, VIIO=
Vuo = 2.0V
2.0V
. Cito
"Guaranteed 100% tested
tested..
2-38 4/91.Rev.A
4/91.Rev.A
[JJ
.l..tI
:Lattice
I AILattice®
Semiconductor
C o r p Corporation
oration
GD
GAL20118A
Industrial
Industrial
-15
·15 -20
·20 -25
-25
PA R A M ETER
TEST DESCRIPTION
OESCRIPnON UNITS
UNITS
CONDI.
CONO'. MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX.
15 33 20
20 33 25
25 ns
ns
tco
teo 11 Clock to Output Delay 22 10
10 22 11
11 22 12
12 ns
ns
tcf2 Clock to Feedback Delay -— 88 -— 99 -— 10

10 ns
ns
tsu Time, Input or Feedback before Clocki

Setup lime, 12
12 - — 13
13 -
— 15
15 - — ns
ns
th Hold Time,
lime, Input or Feedback after Clocki
Input or Clocki 00 -— 00 -— 00 -— ns
ns
11 Maximum Clock Frequency withwith 45.5
45.5 -— 41.6
41.6 -— 37
37 -— MHz
MHz
tco)
fmax33
fmax 1 Maximum Clock Frequency with with
Internal Feedback, 1/(tsu + tel)
tcf)
50
50 -— 45.4
45.4 -— 40
40 -— MHz
MHz

62.5 -— 50
50 -— 41.6
41.6 -— MHz
MHz
External Feedback
twh
twh' Clock Pulse Duration, High
High 88 -— 10
10 -— 12
12 -— ns
ns
twr
twt' Clock Pulse Duration, Low 88 -— 10
10 -— 12
12 -— ns
ns

to Output
Output -— 15
15 -— 20
20 -— 25
25 ns
ns
22 OEJ.to
15 -— 18
18 -— 20
20 ns
ns
tdis 33 Input or 110
I/0 to
to Output
Output -— 15
15 -— 20
20 -— 25
25 ns
ns
3 OEi
° E t to Output -— 15
15 -— 18
18 -— 20
20 ns
ns
section.
!) Calculated from fmax with internal feedback. Refer to fmax
fmax Descriptions
section.
i) Refer to fmax
fmax Descriptions
Descriptions section
section..
.)•) Clock pulses of widths less than the specification may be detected as valid
valid clock
clock signals.
signals.

GND to 3.0V +5V
+5V
Input Rise and Fall Times
Times 3ns 10%-90%
3ns 10% – 90%
Input Timing
liming Reference Levels 1.5V
1.5V
Output liming
Timing Reference Levels 1.5V
1.5V
Output Load See
See Figure
i·state O.SV from steady-state active
i-state levels are measured 0.5V FROM OUTPUT (0/0)
FROMOUTPUT (0/0) - - - . . - - -......- TEST
TESTPOINT
POINT
weI.
?Nei. UNDER TEST
UNDERTEST
>utput
CL
Test Condition Rl
111 R2
R2 CL
CL
112
11
2 Active
Active High ..
200n
2000
.0,
3900
39011
3900
390f1
50DF
50pF
50pF
50pF
3
3
Active
Active Low
Active High
Active High
Active Low
..
2000
200c1
,..
20on
2000
3900
3900
3900
390c1
3900
SOpF
50pF
5pF
5pF
5pF
C
CLINCLUDES
JIGAND PROBE TOT
TOTAL CAPACITANCE
ALCAP ACITANCE
5pF
2-39
2-39 4 / 9 1 . R e v .4/91.Rev.A
A
!lJ:Lattice-
LLattice*
1.1 Corporation
Semiconductor
Semiconducwr
GAL-20118B
GAL-201/8A
GAL20V8A
SWITCHING WAVEFORMS
WAVEFORMS
INPUTor
INPUT or
I/0FEEDBACK
LIO FEEDBACK
INPUTor
INPUT or
VOFEEDBACK
LIO FEEDBACK
\\\\\\\
M S 0 VALID INPUT
CLK
ClK
4—tc 04.
\\\\\\\\\\\\\\\\\\
\\\\\\\\\\\il==
ipd REGISTERED
REGISTERED
OUTPUT
OUTPUT
COMBINATORIAL
COMBINATORIAL 4----litmax
OUTPUT
OUTPUT (external tebic)
Combinatorial Output R e g i s t e r Registered

e d Output
Output
INPUT
INPUTor
OE
OE
110 FEEDBACK
VOFEEDBACK
4—ten t eI kr-01. te
OUTPUT OUTPUT
OUTPUT
- Input QrllOto
or I/0 to $utput
Output EioableJDlsable
Enable/Disable O E OE to
to Output
Enable/Disable
twh t y i I .---1110
elK
CLK
4-1/ i max internal tebk)
elK
CLK
4-Id 4 tsu
REGISTERED
REGISTERED
FEEDBACK
FEEDBACK
Clock Width
Width
fmax with
fmax with Feedback
Feedback
2-40 4/91.Rev.A
4/91 Revd!'
flJILattice®
'Lattioo*
Semiconductor
SemioonductlJr
C o r pCorporauon
oration
GAL-20118B
GAL201/8A
GAL20V8A
1fmax DESCRIPTIONS
fmax DESCRIPTIONS
CLK
elK
····
, • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • __
..
• • • _o __ o _ . _ _ _ ,
· elK
CLK
LOGIC
LOGIC
REGISTER
REGISTER 111.
ARRAY
A R R AY
LOGIC
V
ARRAY
·'.. ---_ ... __ ..................... _---_ ............ .. REGISTER
I0Il1"1---10
14 u---."II4"f----
t Ico---.t
C -----1101
'max with External Feedback 1/(tsu+tco)

fmax
tct
Note: fmax with
with external feedback is calculated from measured tpd
tsu and tco.
lsu
frnax with
fmax with Internal
Internal Feedback
Feedback 1/(tsu+tcf)
li(tsu+tcf)
CLK
CLK
Note: tcf
calculated value,
value, derived
from
[................................. ·············1 the

the period of fmax
value
value of tcf
tot is
fmax w/internal
is used
w/internal feedback
used primarily
primarily when
(tot -. 1lfmax
feedback (tcf
when calculating
tilmax -- tsu).
calculating the
tsu). The
the delay
delay from
The
from
· . clocking
clocking a register
register to
to aacombinatorial
output (through
(through registered
registered
LOGIC feedback),
feedback), as as shown
shown above. For example,
above. For example, the the timing
timing from
from clock
clock
REGISTER
REGISTER
ARRAY -11110- to
to aa combinatorial
output isis equal
equal to tot ++ tpd.
to tcf tpd.
• • • • • • • • 00 _ •• _ ••••••••• _ • • • • • _. _____ • _. _ ••••• _.'
fmax Without Feedback
Note: fmax with

with no feedback
feedback may be less than 1ltwh + twl. This
than 1/twh This
is to allow for aa clock
clock duty cycle of other than 50%.
2-41
2-41 4191.Rev.A
4/91.IRev.A
Lattice®
VI:!!!!!/
i d ISemiconductor
Specifications GAL20118B
horporatJon
Corporation GAL201/8A
GAL20V8A
ELECTRONIC SIGNATURE OUTPUT REGISTER PRELOAD
OUTPUT PRELOAD
An electronic signature (ES) is provided in every GAL20V8AIB

GAL20V8NB Whentesting
When testing state
state machine
machinedesigns,
designs, all
allpossible
possiblestates
statesand
andstate
state
device. ItIt contains 64 bits of reprogram mabie
mable memory
memory that
that can
can transitions must
verified inin the
the design,
design, not
not just
just those
those required
required
contain user defined data. Some uses Include
Some uses include user 10ID codes,
codes, in the
in the normal
normal machine
machine operations.
operations. This is is because,
because, in in system
system
revision numbers, or inventory control. The The signature data is operation, certain
operation, certain events
events occur
occurthat
thatmay
maythrow
throwthe the logic
logicinto
into an
an
always available to the user independent of the the state of the
the se-
se- illegal state
illegal state (power-up,
(power-up, line
linevoltage
voltage glitches,
brown-outs, etc.).
etc.). To
To
curity cell.
curitycell. test aadesign
test design for
forproper
propertreatment
treatmentof ofthese
theseconditions,
conditions, aawaywaymust
must
be provided
be provided to tobreak
breakthe
thefeedback
feedback paths,
paths, and
andforce
force any
anydesired
desired
NOTE: The
The ESES isis included in checksum calculations. Changing
Changing (i.e.,
(i.e., illegal)
illegal) state
state into
into the
the registers. Then the
registers. Then the machine
machine can can be
be
the ES will
will alter
after checksum. sequenced
sequenced and andthe
theoutputs
outputstested
testedfor
forcorrect
correctnext
nextstate
stateconditions.
conditions.
SECURITY CELL GAL20V8A/Bdevices

GAL20V8AIB devices include
includecircuitry
circuitrythat
thatallows
allowseach
each registered
registered
output to be
output to be synchronously
synchronously set set either
either high
high oror low. Thus, any
low. Thus, any
present
present state
state condition can be
condition can be forced
forced for
for test
test sequencing.
sequencing. If
The security cell is provided on all GAL20V8AIB
GAL20V8NB devices to to pre-
pre-
necessary,
necessary, approved
approved GAL
GALprogrammers
programmerscapable
capableof ofexecuting
executingtext
text
vent unauthorized copying
copying of the array patterns.
patterns. OnceOnce pro-
vectors
vectors perform
perform output
output register
register preload
preload automatically.
automatically.
grammed, the circuitry enabling array is disabled, preventing
further programming or verification
verification of the array. The
The cell can only
be erased by re-programming the device, so the the original
original configu-
configu- INPUT BUFFERS
INPUT BUFFERS
ration can never be examined once this cell cell is programmed.
programmed. Sig-
nature data is always available to to the
the user. GAL20V8A
GAL20V8Aand and GAL20V8B
GAL20V8B devices
devices are
are designed
designed with
withTTLTTLlevel
level
compatible
compatible input
input buffers. These buffers
buffers. These buffers have
characteristically
high
high impedance,
impedance, andand present
present aa much
much lighter
lighter load
load to
tothe
thedriving
driving
LATCH-UP PROTECTION logic
logic than
than bipolar
bipolarTTL
TTL devices.
devices.
GAL20V8AIB
GAL20V8A/B devices are designed with an an on-board charge The
The GAL20V8B
GAL20V8B input input and
and I/O
I/O pins
pins have
have built-in
built-in active
active pull-ups.
pull-ups.
pump to negatively bias the the substrate. The negative bias
bias isis of
of suf-
suf- As
As a result,
result, unused
unused inputs
inputs and
and I/O's
VO'swill
willfloat
floatto
toaaTTL "high" (logi-
TTL''high" (logi-
ficient magnitude to prevent input undershoots from causing
causing the cal
cal "1"). In contrast,
"1"). In contrast, the the GAL20V8A
GAL20V8A does does not
not have
have active
active pull-
pull-
circuitry to latch. Additionally,
Additionally, outputs
outputs are
are designed with
with n-<:hannel
n-channel ups
ups within
within their
their input
inputstructures. Lattice recommends
structures. Lattice recommendsthat thatall
allun-
un-
pull-ups instead of the traditional p-<:hannel
p-channel pull-ups
pull-ups to
to eliminate
eliminate used
used inputs
inputs and
and tri-stated
tri-stated 110
I/Opins
pins for
forboth
both devices
devices bebeconnected
connected
any possibility of SCR induced latching. to
to another
anotheractive
active input,
input, V ce' or
Vcc, orGround. Doing this
Ground. Doing thiswill
willtend
tendto
toim-
im-
prove
prove noise
noise immunity
immunity and and reduce
reduce Icelc, for
forthe
the device.
device.
DEVICE PROGRAMMING
"lYplcallnput
Typical Input Pull-up
Characteristic
GAL devices are programmed using a Lattice-approved Logic Logic
Programmer, available from a number of manufacturers. Com-
plete programming of the device takes
takes only a few
few seconds.
seconds. Eras-
./
ing of the device is transparent
transparent to the user, and is done automati-
cally as part of the programming cycle.
automati-
. L
.
u
·20
./
i ./
.5
-40
-60
-60 ----
o0 1 . 1.0
0 2 . 2.0
0 3 . 0 4 . 0 50
Input
Input Voltag'
Voltage (Volts)
(Volts)
2-42 4191.Rev.A
4/91.RevA
1 4 1 hSemironductor
gctor®
GAL201t8B
Corporation
GAL20V8A
POWER-UP RESET
go%/
Vee
Vcc
0V
OV
t pr
V
V IH
IH ...-......-+"',....-,-,--,.1,---------
elK
CLK VALIDCLOCK
VALID SIGNAL
CLOCK SIGNAL
VIL
VIL
t mm
INTERNAL
INTERNAL INTERNAL
INTERNALREGISTER
REGISTER
REGISTER
REGISTER RESETTO
RESET TOLOGIC
LOGIC00
Q·OUTPUT
0-OUTPUT
FE EDBACK/EXTERNAl
FEEDBACK/EXTERNAL
OUTPUT REGISTER
REGISTER MMMIZY EXTERNAL REGISTER
EXTERNALREGISTER
OUTPUT
OUTPUT = LOGIC 1
LOGIC
Circuitry within the GAL20V8A and GAL20V8B provides a reset reset The
The timing
timing diagram for for power-up
power-up is is shown
above. Because of
signal to
to all registers during power-up. All
All internal registers
registers will the
the asynchronous
asynchronous nature
nature of of system
system power-up,
power-up, somesome conditions
conditions
a
have their 0 outputs set low after a specified
specified time (t REsET'45p.s
RESET must
must be be met
met to guarantee
guarantee a valid power-up power-up resetreset of the
of the
MAX). As a result, the state on the registered output pins (if(if they
they GAL20V8A
GAL20V8A and and GAL20V8B.
GAL20V813. First, First, the
the Vee
\ice rise
rise must
must bebe mono-
mono-
are enabled through OE) will always be high on power-up,
power-up, regard-
regard- tonic. Second, the
tonic. Second, the clock
clock input
input must
must become
become aaproper
properTIL
TTLlevel
level
less of the programmed polarity of the output pins. This feature
pins. This within
within the
the specified
specified time (tpR ' 100ns MAX).
time (tpR, MAX). The registers
registerswill
will reset
reset
can greatly simplify state machine design by providing
providing a known
known within
within a maximum
maximum of oftRESET
tREsETtime.
time. AsAs inin normal
normal system
system operation,
operation,
state on power-up. avoid
avoid clocking
clocking the
the device
device until
until all
all input
input and
and feedback
feedbackpathpath setup
setup
times
times have beenbeen met.
met.
PIN
PIN PIN
Feedback
Vee Active
ActivePull-up
Pull-up
Active Pull-up Vcc
Chait
Cirmit
Circuit (GAL20VSB
(GAL2OVEonly)only)
(GAL20V81:3only) .__y. __ __
...
Vee
• Tr V c c i-S l
e V r eVref
ta f l
Vcc Vret V c c Control
Control
: ESD
ESD
: Pro1ection
Protection
.i---------.------ --.'.
Circuit
Data
Data
I I
':._--- _eo!
PIN
PIN
PIN
PIN Output
Output
: ESD
ESD
j Protection
Protection
: Circuit
..
._-----------_.-
Feedback
Feedback
(ToInput
(To InputBuffer)
Buffer)
=3.2V
Typ. Vref = Typ.
Typ. Vref
Vref •= 3.2V
3.2V
lYpicallnput
Typical Input Typical
Typical Output
Output
2-43 4/91.Rev.A
4/91.1Rev.A
[JJ :LattiOO@
L Lattke® Semiconductor
Semironductor
Corporation
C<KpcratkJn
Specifications GAL201/8B
Tpd vs Vee
Normalized Tpd \Ice Normalized Teo
Normalized Tco VB
vs Vee
%roc Normalized Tsu
Normalized Tsu vs
vs Vee
Vcc
r-T-i-;:::=r=::J 1.2
1.2 1.2
1.2
I·····
1.2
--+--+-1
P
1--
T H-AL
PTH·>L
I····· RISE
II""" PT H , L
PTH.>L}
Il
1 .......
1.1 1.1
1.1
PT L->H I
1.1
I - FALL
J!
N
PTL->H FAle - PT L , H
PTL·>H
!. . . 11
tr-===::j::',;';;' ]
'" '"
.......... . ......
l'
...... 1
r- ..........
.....
j2 ", ",
:1€
•.
0,99 +-----jf__--+---f----l •.
09 •.0.9
9
•.•
0.8
...
4,50 4 _ 74.75
5 5 , 0 5.00
0 5 2 525
5 5.50
•.•
OR +---f__---+---+----l ...
0,3
4.50
4.50 4 7 4.75
5 5 . 05.00
0 5 2 5.25
5 5.50
5.50 4 . 5 04.50 4 . 74.75
5 5 . 05.00
0 5 2 5.25
5 5.50
Supply Voltage (V)

Supply (V) Supply VoHage
Supply Voltage (V) Supply VoHage
Supply Voltage (V)
(V)
Normalized Tpd vs Temp

Normalized Normalized Teo
Normalized Tco vs
vs Temp
Temp Normalized Tsu
Normalized Tsu vs
vs Temp
Temp
1.3
13 1.3 1.4
1.2
1.2
••••.
P T PTH.>L
H >L. I 1.2
12 " " ' RISE 1.3
1.3 ......... PTH->L l /
-0 ,;;:2" o L
/ .." ,
"0
1.1 --PTL.>HI - FALL 1.2
.,;.;- " --PTL.>HJ
- PT L A H
- 11.1•
-g / -
-g 1l
'
1.1
1
V §
1
r-- E
,.'
. ........ . /
...
1
0.9 ", 0 00.9
...
0.8 ..•
0.8
:z 0.9
0.9
0.8
I-'
L
0.7
0.7
·55
55 0 2 5 2.
9 0 9. 12'
125 - 5
•.
0.7
5
7
.s. 0 2 5 25
Temperature (deg.
C)
9 0 . 1 2 125
5
•. 7
0.7
.s.
-55 0 2 5 25 9 0 . 12.
125
Temperature
Temperature (deg.
(deg. C)
C)
Delta Tpd vs ## of
Delta of Outputs
Outputs Delta
Delta Teo vs ## of
Too vs of Outputs
Outputs
Switching
Switching Switching
Switching
p I-"""
_ -0.5 ,.'
,.'
V
] : -0.5
.'
.. , ,.'
c:.:- P
g " V
V
... f/"
"
"0
-, ./ -1
./
13
-1.5
V 0 _ 1.5
V ••••. RISE}
--FAeL --FALL
-2 -2
2 3 4 5 6 7 8 2 3 4 5 6 7 8
Number of Outputs Switching

Number Number of
Number of Outputs
Outputs Switching
• 111•11151111111•1
Delta
Delta Tpd vs
vs Output
Delta Teo
Too vs
vs Output
Output Loading
Loading
,.
10
j..... RISEl
RISE
/'
••••. . RISE
RISE I
/ '
£.6 --FALLI
- FALL g6 6
I --FALLl
- FALL M E M
,
V o
g 44 M
-:-;., EE
J;! /.
/.
/- "
2
0 wrammEn /.
-2 -22
0 5 050 1 0100 O 2 0200

0 I S 150 0 2 5250
0 3 0300
0 0 5 050 1 0tOO
0 1 5150
0 2 0200
0 2 5250
0 300
300
Output
Output Loading (pF) Output
Output Loading
Loading (pF)
(pF)
2-44 4/91.Rev.A
4/91.1Rev.A
!JJ
.l.J
:LattiOO@
Semiconductor
Corporation
Corporation
r
I I d lSemiconductor
k l
GAL201/8B
Typical Characteristics ,
Vol vs 101
Volvs lol Voh vs Ioh
Vohvs loh Voh vs loh
Vohvs loh
at
/
4.50
,-
---
4
-
.......... 4.25
---
O.7e,
0,75 4,25
:E L 3
t-.
r- :E 4.00
00-
---
0.5 .J:4_00
./
/' :fZ
00-
3.75
0.25
025 3.75
,/
L 3.50
3_50
0.00 2 020.00
00 4 40.00
0 00 6 60.00
0 00 8 80.00
0 00 1 0100.00
0 00 0.00 1 10.00
0.00 0 00 2 20.00
0 00 3 30.00
0 00 4 40.00
0 00 5 50.00
0 00 660.00
0 00 0.00 1 . 01.00
0.00 0 2 0 2.00
0 3 0 3.00
0 4 . 04.00
0
lol (mA)
101 loh(mA)
10h(mA) loh(mA)
10h(mA)
Normalized
Normalized Icc vs Vee
Vcc Normalized Icc
Normalized !cc vs
vs Temp
Temp Normalized Icc
Normalized Inc vs
vs Freq.
Freq.
1.20
1.20 1.20
1.20 1.30
1 30
"""- .......... 1.20

1.20
--
1.10
1.10 1.10
1.10 ,,/'
118 V 8 11 L
""- 13 11.10
.10
I""
'"C
al i.00
] 1.00
al
1
]
1.00
1.00
/r'
EE1,00 1.00
2 0.90 0.90
0.90
:!i!btS
0.90
0.90
V
,.0
0.80
4,50 4 . 74.75
4.50 5 5 , 05.00
0
Supply Voltage
Vottage (V)
(V)
5 2 5.25
5 5.50
5.50 . 5
0.80
080
5 - 2 5 0
Temperature
2 525
7 575 1 0100
'"
0 1 2125
5
0.80
25
25 5 0 50
Frequency (MHz)
Frequency
7 5 75 100
100
Delta !cc
Icc vs Yin (1 input)
Vin (1 input) ·Input
Input Clamp (Vlk)
(Vik)
5 0
10
10
20
20
/
30
30
/
<-4040 /
I\ .§."
50
60
SO
/
J \ 70
70
80
/
/
"-
J
80
0
r--.. 90
90
100
100
1/
0.00
0.00 00.50
. 5 0 1 1.00 1.50
.00 I S O 22.00
0 0 22.50
. 5 0 33.00
0 0 33.50
. 5 0 44.00
00 -2.00
2 00 I -1.50
50 1 -1.00
00 0 -0.150
50 0.00
0,00
VineY)
Vin (V) Vik(V)
Vik (V)
2-45 4/91.Rev.A
4/91.Rev.A
[JJ
.l.J
LB.tuce
Semlronductor
Corporation
CorporaUon
e
GAL20118A
Normalized Tod
Nonnalized Tpd vs. Vcc
Vee Normalized Tsu
Normalized Tsu va.
vs_ Vee
Vcc Normalized T
Normalized co YS.
Tco vs Vee
Vcc
1.3
-- -----
12 1.2
•••
- - !
...
8 IA
'.0
u01
- -
.
13.• 0.0
.,...
0.1
4.50 4 . 7 4.75
5 5 , 0 &.00
0
Supply Voltage (V)
(V)
5 2 IJIi
5 ..
5,50
o
. ...
450 4 7 ..7$
5 6 5 1.00
0 5 . 26.25
Supply Voltage (V)
Supply
5 ....
6.50
07
4,50 4 7 4.71
5 1 0
Supply Voltage
Supply Voltage(V)
(V)
..000 1 2 ...
1 ....
6.50
Normalized Tpd VS. Temperature

vs Temperature NonnaJized
Normalized Tsu
Tsu VB. Temperlllure
vs Temperature Normalized
NormalizedTeo vs.Te"ll8rature
TcoYS. Temperature
•1.3
.3 '.3
1.3
1.3
12
.,..,.... 1.2
12
.,..,.... '.1.22
... ., .---
V "' "'
"&. •.• :.
1,2 11
f!!. 881.•.•
I-
74,to 1.0 i.!::!3 10
'.0
/ I- /
/ / L
I
16In
E 0.9
'6
O.t
Z 0.8 /
iii
E
08
Z
u0 9
/ (5 so
ut.0
... L
V
0.8 00..6
/ / /'
.
0.7
0.7 0.7
0.7 0.8
0.6 0.6
06 '.1
-50
-50 - 2 -25
5 0 0 2 525 ..
50 7 575 100
,00 '25
125 ..5()
-50 .a
-25 0 2S
25 so
50 75
75 100
100 125
125 -50 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5
Ambient Temperature (OC)

(sC) Ambient
Ambient Temperlllure
Temperature (OC)
(CC) ArnbientTe"ll8rature
Ambient Temperature(OC)
(sC)
Normalized Icc
Nonnalized vs. Vee
tooYS. Vcc
Norma ized Tpd
Normalized Tod vs. , or
VI. C of OUlPU11
Outputs Swhchlng
Switching Delta Tpd
Delta Tpd vs. Output Loading
vs. Output Loading
5 I13
l
/
00
1.00
/ '.2
.
1,2
/ / ... ./
"8.
0.18
099
-.E-.. !l8 1,
l-
I .... 026
./
V X. / '0
i '.0o
/
I- Is
§
,V
os
D.t
.... V" Z V
094
/ 0"0.8
V /'
0.12
092
'oIOUIPUlI
0 of Outputs
M
IOLVS.
loL vs. VOL
100
Output Loading
Output
200
203
Loading Capacitance
Capacitance (pI)
(pf)
10Hvs.
ICIt VOH
Vs. VOH
3 0 0300
-.0
0.7
02
'.4.50
50 us
415
Normalized
Normalized Icc
5
Supply
0
Supply Voltage
Icc YS'
Voltage(V)
(V)
vs. Temperature
Temperature
5.00
0 525 5.50
5.50
-
250
250 ·.10
'ISO 13
200
200 u
---r-. - -- r---.. . . .
<" .50 / <"
;t—
·'00
100
....... .!l8
1.1
.§.
...
.2100
)V §.
E
§2
"-
.........
i
..E ...
In
0
50
50
/ ·10
9
:---.....
V
OJ
00
o
o
"-.. '.7
07
......
.so IH 50 7'$ 100 12$
2 3 4 2 4 -25 0 71 125
VOL
V O L (V)
(V)
VCIt(V)
VOH (V) Ambient Temperature (OC)
Ambient Temperature (SC)
2-46 4/91.Rev.A
4/91.1Rev.A
a;J
,lJ
tattice®
I I d ISemiconductor
S i r e t ctoTt ®
Corporation
GAL181110
GAL
High Performance EZCMOS
High
18V10
E2CMOS PLD
Generic Array
Generic
PLD
Array Logic™
Logien'

FUNCTIONAL DIAGRAM
BLOCK DIAGRAM
- Amax
• HIGH = 62.5 MHz E2CMOS•
PERFORMANCE ElCMOS- TECHNOLOGY
-— 15 ns Maximum Propagation Delay I/CLX
IICLK
=
- Fmax 62.5 MHz
1/010
—10ns Maximum from
-10ns from Clock Input
input to Data OUtput
Output I/OIQ
-— TTL
TIL Compatible 16 mA Outputs
-— UltraMOSx
UHraMOS- Advanced CMOS Technology INPUT
INPUT
1/0/0
I/O/a
• LOW POWER CMOS
-— 75 mA Typical !cc
lYplcallcc
1/010
I/OIQ
• ACTIVE
ACTIVE PULL-UPS ON ALL PINS INPUT
INPUT
• E2
EI CELL TECHNOLOGY
-— Reconfigurable
logic 11010
I/OIQ
-— Reprogrammable Cells
INPUT
INPUT
— 100% Tested/Guaranteed 100'2k
-100% 100% Yields
-— High Speed (50ms)
Speed Electrical Erasure (SOms) 1/010
I/OIQ
• TEN OUTPUT LOGIC MACROCELLS INPUT
INPUT I/0/0
I/OIQ
-— Uses Standard 22V10 Macrocells
-— Maximum Flexibility
FlexlbllHy for Complex Logic
logic Designs
• PRELOAD
PRELOAD AND POWER-ON RESET OF REGISTERS 110/0
1/010
-100% TestabllHy
— 100% Functional Testability INPUT
INPUT
• APPLICATIONS
APPLICATIONS INCLUDE: IIO/Q
1/010
-— DMA Control
-— State Machine Control
INPUT
INPUT
-— High Speed Graphics Processing 11010
I/OIQ
-— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION 11010
I/OIQ
INPUT
INPUT
DESCRIPTION
PACKAGE
PACKAGE DIAGRAMS
DIAGRAMS
The GAL 18V1 0, at 15 ns maximum propagation delay
GAL18V10, delay time,
time, com-
com-
bines a high performance CMOS process with with Electrically Eras-
(1:2) floating gate technology to provide the highest perform-
able (E2) perform-
ance 20 pin PLD PLD available
available on the market. CMOS
CMOS circuitry
circuitry al-
al-
lows the GAL 18V1 0 to
GAL18V10 to consume much less power when com- PLCC
PLCC DIP
DIP
pared to its bipolar counterparts. The E2
counterparts. The E2 technology
technology offers
offers high
I/CLK Vee
Vcc
speed (50ms) erase times, providing the ability to reprogram or or II 1 / CWCLX v.. I /IiOIQ
L I K Vec 0/0
reconfigure the device quickly and efficiently. I/OIQ
I/01Q
2 20
By building on the popular 22V1 0 architecture, the
22V10 the GAL 18V1 0
GAL18V10 IiOIQ
V010 IIO/Q
I/0/0
allows the designer to be immediately productive, eliminating the
the
learning curve. The generic architecture provides maximum de- 1 IIO/Q
MWO I/O/Q
I/0/0
sign flexibility
flexibility by allowing the Output Logic Macrocell (OLMC) GAL18V10
GAL18V10
to be configured by the user. The
The GAL 18V1 0 OLMC is fully
1 IiOIQ
MX0 I/O/a
I/0/0
GAL18V10 fully com- Top
patible with the OLMC in standard bipolar and 1 Top View
View IIO/Q
I/0/0
and CMOS 22V1
22V10 0 de-
de- IiOIQ
WW10
vices. IIO/Q
I/0/0
1 IiOIQ
1/010
reprogram mabie cells allow
allow complete
complete 110/0
I/0/0
AC, DC, and functional testing during manufacture. As As aa result, IiOIQ CIIID 1/0/0
MNO GND IIO/Q IXVO
IIO/Q 11010
IiOIQ
result, I/O/a
1/010 IIO/Q
I/0/0
LATIICE
LATTICE is able to guarantee 100% field programmability and
functionality of all GAL- products. LATTICE
GAL° products. LATIICE also guarantees
guarantees 100 aND
GND 1/010
erase/rewrite
erase/rewrite cycles
cycles and data retention
and data retention in
in excess
excess of
of 20
20 years.
years.
copyright
Copyright 01991 Lattice Semiconductor
Semiconductor Corp. GAL and
Corp. GAL and UnraMOS are ragiltered
UltraMOS are registeredtrademarlca of Lattice
trademarks of SemiconductorCorp.
LatticeSemiconductor Generic Array
Corp. Generic ArrayLogic
Logicand
andE'CMOS
PCMOSare
aretr&damar"" ofLattice
trademarksof Lattice
Semiconductor Corp. TThe specifications herein are subject to
h e opecllcatlons to change
change wIthou1
without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Moore Ct.,

5555 N.E. Moore Ct., Hillsboro, Oregon
Oregon 97124 U.S.A.
U.S.A. A p r i April
l 1991.Rev.A
1991.1:lei/A
Tel.
Tel. (503) 681-01180r
(503) 681-0118 or 1-800-FASTGAL; FAX (503)
1-800-FASTGAL; FAX 681-3037
(503)681-3037
2-47
2-47
[jJ
'L Lattire
Lattice'
Semiconductor
Semironductor
Corporation
4D
GAL181110
Specifications GAL 18V1 0
GALIBVIO ORDERING INFORMATION

GAL18V10

Tpd (ns) Tsu (ns) Teo (ns) Icc
ice (mA) Ordering ##
Ordering Package
Package
15
15 10
10 10
10 115
115 GAL18V10-15LP
GAL 18V10-15LP 20-Pin Plastic
20-Pin Plastic DIP
DIP
115
115 GAL18V10-15LI
GAL 18V10-15LJ 20-Lead PLCC
20-Lead PLCC
20 12 12
12 115
115 GAL18V10-2OLP
GAL18V10-20LP 20-Pin Plastic
20-Pin Plastic DIP
DIP
115
115 GAL18V10-20LJ
GAL18V10-20LJ 20-Lead
20-Lead PLCC
PLCC

Tpd (ns) Tsu (ns) Teo (ns) Icc
lee (mA) Ordering #
Ordering Package
Package
20
20 12 12
12 125
125 GAL18V10-20LPI
GAL18V10-20LPI 20-Pin
20-Pin Plastic
Plastic DIP
DIP
125
125 GAL18V10-20LJI
GAL1EIV10-20LJI 20-Lead
20-Lead PLCC
PLCC
XXXXXXXX -Xxx.
xxxxxxxx X XX XX X
X
Device Name
GAL18V10 Device
Speed (ns) L...-_ _ _ Grade lank =

Grade BBlank = Commercial
Commercial
II =
= Industrial
Industrial
L = Low Power Power

Power L...-_ _ _ _ Package PP =
Package P Plastic
l a s t i c DIP
DIP
J == PLCC
PLCC
2-48
2-48 4 / 9 1 . 1 i e v 4J91.Rev.A
. A
[JJ 'LllttiooQP
SeIIlironductor
Corporation
Specifications GAL
GAL18111
18V1 00

The GAL18V1
GAL 18V1 0 has a variable number of product terms per The GAL
The GAL18V10 has aa product
18V1 0 has product term
term for
forAsynchronous
Asynchronous Reset
Reset (AR)
(AR)
OLMC. Of the ten available OLMCs, two two OLMCs have access and aa product term
and term for
for Synchronous
Synchronous PresetPreset (SP). These two
(SP). These two
to ten product terms (pins 14 and 15), and the
the other
other eight OLMCs
OLMCs product terms
product terms are
are common
common to to all
all registered
registered OLMCs.
OLMCs. TheTheAsyn-
Asyn-
have eight product terms each. In addition toto the
the product terms
terms chronous Reset
chronous Reset sets
sets all
all registered
registered outputs
outputs to
to zero
zero any
any time
time this
this
available for logic, each OLMC
OLMC has an additional product-term dedicated product
dedicated product term
term is
is asserted.
asserted. The
The Synchronous
Synchronous Preset
Preset sets
sets
dedicated to output enable control. all registers
all registers to
to a logic one
one on
on the
the rising
rising edge
edge ofof the
the next
next clock
clock
pulse after
pulse after this
this product
product term
term is
is asserted.
asserted.
The output
output polarity
polarity of
of each
each OLMC
OLMC can be be individually
individually pro-
pro-
grammed to be true or inverting, in either combinatorial or reg-
reg- NOTE: The AR
NOTE: AR and
and SP
SP product
product terms
terms will
will force
force the
the QQ output
output ofof
istered mode. This
This allows each output to be individually config-
config- the flip-flop
the flip-flop into the
the same
same state regardless
regardless of of the
the polarity
polarity of
of the
the
gured as either active high or active low. output. Therefore,
output. Therefore, aa reset
reset operation,
operation, which
which sets
setsthethe register
registeroutput
output
to aa zero,
to zero, may result
result in
in either aa high
high or low
low atat the output
output pin,
pin,
depending on
depending on the
the pin
pin polarity
polarity chosen.
chosen.
AR
o
4 TO 1
Q
MUX
SP
2 TO 1 I - - - - - - - - - - - - - l
MUX
GAL18V10
GAL1EIV10 OUTPUT LOGIC
LOGIC MACROCELL (OLMC)
(OLMC)
OUTPUT LOGIC MACROCELL CONFIGURATIONS

Each of the Macrocells ofof the
the GAL 18V1 0 has two primary func-
GAL18\110 func- NOTE:
NOTE: In registered
registered mode,
mode, thethe feedback
feedback isis from the /0
from the /0 output
output
110. The modes
tional modes: registered, and combinatorial I/O. modes and
and of
of the
the register,
register, and
and not
not from
from the
the pin;
pin; therefore,
therefore, aa pin
pin defined
defined as
as
the output polarity are set by two bits (SO and Si),S 1), which
which are
are registered
registered isis an
an output
output only,
only, and
and cannot
cannot be
be used
used for
for dynamic
dynamic
normally controlled by
by the
the logic Each of
logic compiler. Each these two
of these two pri-
pri- 110,
I/O, as
as can
can the
the combinatorial
combinatorial pins.
pins.
mary modes, and the bit settings required to enable them, are
them, are
described below and on the the following page. COMBINATORIAL //0
COMBINATORIAL I/O
In
Incombinatorial
combinatorial mode mode thethe pin
pin associated
associated withwith an
an individual
individualOLMC
OLMC
REGISTERED is
is driven
driven byby the
the output
output ofof the
the sum
sum term
term gate.
gate. Logic
Logic polarity
polarity ofofthethe
In registered
registered mode the output pin associated with an an individual output
output signal
signal at at the
the pin
pin may
may bebe selected
selected by by specifying
specifying that
that thethe
OLMC is driven by the 0 output of of that
that OLMC's D-type flip-flop.
flip-flop. output
output buffer
buffer drive
drive either
eithertrue
true (active
(active high)
high) or
orinverted
inverted (active
(active low).
low).
Logic polarity of the
the output
output signal at
at the
the pin may be selected by by Output
Output tri-state
tri-state control
control is is available
available as as an
an individual
individual product-term
product-term
specifying that the
specifying that the output
output buffer
buffer drive either true
drive either (active high)
true (active high) for
for each
each output,
output, and may be
and may be individually
individually setset by
by the
the compiler
compiler as as
or inverted (active low). Output tri-state
or tri-state control is available
control is available asas either "on"
either "on" (dedicated
(dedicated output),
output), "off"
"off" (dedicated
(dedicated input),
input), or
or "product-
"product-
an individual product-term for each OLMC, and can
an individual can therefore
therefore term
term driven" (dynamic 110).
driven" (dynamic I/O). Feedback
Feedback into into the
the AND
AND array
array isis from
from
be
be defined by a logic equation. The flip-flop's /0 output is fed
The D flip-flop's the
the pin
pin side
side of of the output enable
the output enable buffer.
buffer. Both
Both polarities
polarities (true
(true andand
back into the
back into AND array,
the AND array, with
with both
both the true and
the true and complement
complement of of inverted) of
inverted) of the
the pin
pin are
are fedfed back
back into
into the
the AND
AND array.
array.
the feedback available
the feedback available as
as inputs
inputs to the AND
to the AND array.
array.
2-49 4/91.Rev.A
4/91.Rev.A
[JJ Lattice
LLattice®Semiconductor
Semioonductor
Corporation
GP
GAL181110
REGISTERED MODE
t o n A 1 1 1 1 1
• AR
AR
•
• o Q•
Q o Q
• D Q
•
C K • CL K •
DM"
SP
SP SP
SP
ACTIVE LOW
LOW ACTIVE
ACTIVE HIGH
HIGH
so =
So = 0 So= 11
So
SI = 0 SI = 0
COMBINATORIAL MODE
SE
ACTIVE LOW
LOW ACTIVE
ACTIVE HIGH
HIGH
=0
So =
So So= 11
So
=
S, = 1 =
S, = 1
2-50
2-50 4/91.Rev.A
4/91.Rev.A
[J
.l.t
tl1ttiOO®
Lattke®
Semiconductor
Semiconductor
C o r p Corporation
oration
Specifications GAL
GAL18111
18V1 0
GAL113V10
GAL 18V10 LOGIC DIAGRAM /JJEDEC
E D E C FUSE MAP
0 44
• 12
'2 1 6 , . 2 020 2 4 24 2 8 28 32
0000
0000 AS'lNCHRONOUS
ASYNCHRONOUSRESET
RESET
(TO.AU.
(TO ALLREGISTERS)
REGISTERS)
0036
0036
• 1111111111111111111111111111111111011 OlMC 19
0324
0324
= 1 3 4 5 6
E r X 7
3457
19
19
0360
0360 EMEMEMEMENEHEM -
raiiralii-aliraiii-airalliffilliEn:§:::t OLMC 18
OLMC '8 J 18
18
2 0 -
0648
l i i i 11111111.1"11111"311111111111111111111
111 3 V e
I n ' 3:49 !LJ

'-----
1 . 1 1
111. 1.11 1 1 1 • 1
4r}J
0684
0664
I f l I 1111111111111•11111111111
M11111111111111
•1
11111 OLIAC 19
17
17
=tiP
...,
0972
0972 I I = I I I I I I M M I , 3460 I I I I
5'
3 - 1008 > I I I I I 1 1 1 1 1 M 1 1 1 . 1 1 1 M I I M I I M I I I M O I • 3.1;1
'008 -
1298 I I I 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 L =.>--
m . o L m sOLMC
C '8
i6 J 16
16
'296 0-
5'
4
- ""'"
'332 -OLMC '7
1 3 3 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I I C : M ; C : 1 7 I J
I I
15
15
16921111011111111"1111111111111RJ1111-,2
'892
.... 1111 0-
172611111111111111110111111111c,mc. 1
5
'728
-0l.MC ,.
so 14
14
:R: 3488
2088 5'
. .67
2088 1 1 1 1 1 1 1 1 1 1 1 1 1 1 i . I I 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ' 3 t
6
2'"
-OLMC 13
=>-- J
.,
2124 I I I I I I I I I I I I I I I I I I I I 111111111 / 11111 OLMC 13
So 13
13
2412
2412 .. 88
3468
Si
.3469
.69
7 -
2448
2448 1 1 3 1 1 1 1 1 1 1 1 1 3 1 1 1 1 1 A
-
M E ! R i M i n i a l l e a l M i l e e i f : 4 7 1 1 1 . 1 1 . 0 . ' ' =- OLMC 12
OLMC 12 J 12
12
2736
:B:
.,
SI
a4713
347'
SO . 4 7 0 11
8 -
8 1 0
2m
2772
1 1 111111111111151110111110
l i f f i l t=11,
FAMITANIMPTAMITA rotilai-erlla l jW.4C11l
IdW 0 J 11
liP
J::8"" 11
3080
3060 I s'2
3473
J
3096
30
1 1 1 1 1 1 1 1 1 1 1 1 M o s : 9
OLMC.
t:l--I
99
3384
33
1 1 1 1 1 1 M s. .'75
3420
3420 S Y N C H R O SYNCHRONOUS
N O U S PRESETPRESET
(TO
(TOAl..L
OIL REGISTERS)
REGISTERS)
3476,3477
3476. 3477 ...8 e Electronic
0 5 8 4 0 Signature
Signature 3 5 3...83538,3539
, 3 5 3 0
·· .,
Byte 7 !Byte 6 18y1e 5 IByle 4 'Byte 3 1Byte 2 'Byte I 'Byte 0
2-51
2-51 4191.Rev.A
4/91.Rev.A
[JJ
1..1
'Lattlce
latLattice® Semiconductor
Semironductor
Corporation
qp
GAL181110
Commercial
Commercial
RECOMMENDED OPERATING COND_
COND.
Supply voltage Vcc - 0 . 5 -0.5 to

Vee ........................................ to ++7V
7V
Commercial Devices:
Commercial
Input voltage applied ............................
- 2 . 5-2.5 to to Vee
Vcc +1.0V
+1.0V Ambient Temperature
(TA) ............................. to +75°C
0 to +75°C
Off-state output voltage applied ...........- 2 .-2.5 5 toto Vcc Supply voltage
(Vcc)
Vee +1.0V
Storage Temperature ..................................
- 6 5 -65 to to 150°C with Respect
with Respect to
to Ground
Ground .....................
+ 4 . 7+4.75 5 to to +5.25V
+5.25V
- 5 5 -55 to
Power Applied ......................................... to 125°C
1.Stresses
1. Stresses above those listed under thethe "Absolute Maximum
Maximum
Ratings" may cause permanent damage to
Ratings' to the
the device. These
These
functional operation ofof the
the device
at these or at any other conditions above those indicated in
the operational sections of this specification is
is not
not implied
implied
the programming
(while programming, follow the programming specifications).
specifications).

CONDITION MIN.
MIN. TYR'
TYP" MAX.
MAX. UNITS
UNITS

Input Vss -0.5
Vss-O.5 -— 0.8
0.8 VV
VIH Input High Voltage

Input 2.0
2.0 -— Vcc+1
Vcc+1 VV
IL'
IlL' i n p t or 1/0
Inp'Jt I/0 Low Leakage Current
Current OV
OVS5 Y,N
Vie S5 V,L
V. (MAX.)
(MAX.) -— -— -100
-100 pfik
IiH
IIH Input or I/O
1/0 High Leakage Current 3.5V
3.5V :;;5 Y,N
Vie :;;5 Vee
Vcc -— -— 10
10 p.A
VOL Output Low Voltage lot.= MAX. VYin
i n ., V,L or
= VIL, or V,H
Vie -— -— 0.5
0.5 VV
VOH Output High Voltage be = MAX. VYin

10H= i n = VII_
V,L or
or V,H
Vie 2.4
2.4 -— -— VV
IOL
10L Low Level Output Current -— -— 16
16 mA
mA
10H High Level Output
Output Current
Current -— -— -3.2
-3.2 mA
mA
los2
10S2 Output Short Circuit Current Vcc =
Vee = 5V VOUT == 0.5V
5V VOUT TA == 25·C
0.5V TA 25°C -50
-50 -— -135
-135 mA
mA
-
ICC
Icc Operating Power
Power Supply
Supply Current V,L=
Vit.= 0.5V
0.5V ViV,H=3.0V
e = 3.0V -— 75
75 115
115 mA
mA
ttoggle =
ftoggle = 15Mhz Outputs
Outputs Open
Open
1) The
The leakage current is due to the
the internal pull-up
pull-up on
on all
all pins. See
See Input Buffer
Buffer section
section for
for more
more information.
information.
2) One output at a time for a maximum duration of one second. Vout =
second. Vout = 0.5V
0.5 Vwas
was selected
selected to
to avoid
avoid test
test problems
problems caused
caused by
by
tester ground degradation. Guaranteed
Guaranteed but not
not 100% tested.
3) Typical values
values are at Vcc = 5V and TA
TA =
= 25
25 ·C
'C
(TA = 25°C, f =
CAPACITANCE (TA =
= 1.0 MHz)
SYMBOL PARAMETER
PARAMETER MAXIMUM'
MAXIMUM* UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
C,
C, Input
pF VVcc
cc == 5.0V,
5.0V, V,
V, == 2.0V
2.0V
Cuo
ClIO 110
I/O Capacitance 10
10 pF
pF Vcc == 5.0V,
Vee 5.0V, Vuo
VIJO -= 2.0V
2.0V
"Guaranteed
"Guaranteed but not
not 100% tested.
tested.
2-52
2-52 4/91.Rev.A
4/91.RevA
L/Lattice-Semiconductor
Semiconductor
Corporation
GA1_181110
Specifications GAL 1 BV1 0
Commercial
Commercial
Over Operating Conditions
Conditions
-15
-15 -20
-20
TEST DESCRIPTION
PARAMETER
PARAMETER UNITS
UNITS
COND.' MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX.
to Combinatorial Output -— 15
15 -— 20
20 ns
ns
tco 11 Clock to Output Delay -— 10

10 -— 12
12 ns
ns
tcf2 -— to Feedback Delay

Clock to -— 77 -— 10
10 ns
ns

or Feedback
Feedback before
before Clocki
Clockt 10
10 -
— 12
12 -— ns
ns
th -— Hold Time, Input or Feedback after

after Clocki
Clocki 00 -— 00 -— ns
ns
11 Frequency with
Maximum Clock Frequency 50
50 -— 41.6
41.6 -— MHz
MHz
External Feedback, 1/(tsu +tco)
+tco)
frnax33
fmax 11 Maximum Clock Frequency with 58.8
58.8 -— 45.4
45.4 -— MHz
MHz
Internal Feedback, 1/(tsu + tet)
tcf)
62.5 -— 62.5
62.5 -— MHz
MHz
No Feedback
No
twh4 -— Clock Pulse Duration, High
High 88 -— 88 -— ns
ns
twl4
ns
ten 2 Input or 110
I/O to Output Enabled -— 15
15 -— 20
20 ns
nli
I/O to
to Output Disabled -— 15
15 -— 20
20 ns
ns
tar 1 Input or 110
I/O to
to Asynchronous Reset
Reset of
of Register -— 20
20 -— 20
20 ns
ns
tarw -— Asynchronous Reset Pulse Duration 10
10 -— 15
15 -— ns
ns
tarr -— Asynchronous Reset to
to Clocki Recovery
Recovery Time 15
15 -— 15
15 -— ns
ns
tspr -— Synchronous Preset to Clocki Recovery Time
Clockt Recovery Time 10
10 -— 12
12 -— ns
ns

) Calculated
Calculated from fmax with internal feedback. Refer
Refer to fmax Description
to fmax Description section.
section.
) Refer to fmax section.
tmax Description section.
) Clock pulses of widths less than the specification may bebe detected as valid
valid clock
clock signals.
signals.
2-53
2-53 4 / 9 1 . R e v .4191.Rev.A
A
rIJ Lattice®
Lature
Semiconductor
SemiaHlducwr
Corporation
CorporaUOn
qp
Specifications GAL
GAL181110
18V1 0
Industrial
Industrial
ABSOLUTE MAXIMUM RATINGS')
COND.
Supply voHage
V co ........................................ to ++7V
7V
Industrial Devices:
Industrial
Input voltage
Input voltage applied - 2 . 5-2.5 to
applied .•.....•.......•........•.•. to Vee
Vcc +1.0V
+1.0V Ambient Temperature
Ambient Temperature (TA) - 4 0 -40 to
(TA) ..........•..•.......•...... to 85°C
85°C
Off-state output
output voltage
voltage applied
applied .........•.
- 2 .-2.5 5 toto Vcc +11.0V
.0V Supply voltage
(Vcc)
Off·state Vee +
Storage Temperature
Storage - 6 5 -65 to
Temperature •................•.............•.. to 150°C
150°C with Respect
with Respect to
to Ground
Ground .................•..•.
+ 4 . 5+4.50 0 toto +5.50V
+5.50V
Ambient Temperature
Ambient Temperature withwith
Power Applied
Power Applied ................................•......•.
- 5 5 -55 to to 125°C
125°C
1. Stresses above those listed under the the "Absolute Maximum
Maximum
Ratings" may cause permanent damage
Ratings· damage to the device.device. These
These
functional operation of the the device
device
at these or at any other conditions above those indicated indicated in
the operational sections of this specification is not implied
(while programming,
programming. follow the programming specifications).
DC CHARACTERISTICS
Over Recommended
Conditions (Unless Otherwise
Specified)
SYMBOL PARAMETER
PARAMETER CONDITION
CONDITION MIN.
MIN. TYP.3
TYP.' MAX.
MAX. UNITS
UNITS

Vss-O.5 -— 0.8
0.8 VV
VIH
2.0 -— Vcc+l
Vcc+1 VV
!ILI
IlL' 110 Low Leakage Current
Input or I/O Current OV
OVS5 VIN 5 V,l
Y,N S Vit. (MAX.)
(MAX.) -— -— -100
–100 p.A
!LA
IIH
11H Input or VO Current
3.5V S 5 Vee
Y,N S
5 VIN VcC -- -- 10
10 !LA
p•A
VOL Output Low Voltage 10l .. MAX.
loi.= in =
MAX. VYin = V,l
VILor
or V,H
VIH -— -
— 0.5
0.5 VV
VOH Output High Voltage 10H=

loH = MAX. Yin
MAX. Vi V,l or
n == Vii_ V,H
or VIN 2.4
2.4 -— -— VV
10L
16 mA
mA
10H
i0H High Level Output Current
Current -— -— -3.2
–3.2 mA
mA
105
10S22 Output Short Circuit Current Vee
Vcc == SV VOUT == O.SV
5V VOUT TA= 25°C
0.5V TA= 25°C -50
–50 -— -135
–135 mA
mA
Icc
ICC Operating Power Supply Current V,l=
VIL = O.SV V,H =
0.5V VIN = 3.0V
3.0V -— 90
90 125
125 mA
mA
'haggle =
floggle = 15Mhz Outputs
Outputs Open
Open
1) The
the internal pull-up on
on all
all pins. See Input
Buffer section
section for
for more
more information.
information.
2) One output at a time for a maximum duration of one second. Vout Vout == O.SV
0.5V was
was selected
selected toto avoid
avoid test
test problems
problems caused
caused by
by
tester ground degradation. Guaranteed not 100% tested.
Guaranteed but not
3) Typical values Vcc = SV
values are at Vcc 5V and TA = 25°C
TA= 25 'C
CAPACITANCE (TA =
CAPACITANCE (TA 25°C, f .-=
25°C, 1 x.•1.0 MHz)
MHz)
SYMBOL PARAMETER MAXIMUM*
MAXIMUM* UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
C,
C, Input
pF Vee
Vcc == S.OV. V, =
5.0V, V, = 2.0V
2.0V
ClIO I/O Capacitance 10
10 pF
pF Vee
VG, == S.OV.
5.0V, Vue
V,,0 == 2.0V
2.0V
Cvo
*Guaranteed but not
100% tested.
2-54
2-54 4/91Rev
ILattice®
Semiconductor
Semiconductor
GAL18111
C o r p Corporation
oration Industrial
Industrial
Recommended Operating Conditions
Over Recommended
-20
-20
TEST DESCRIPTION
PARAMETER UNITS
UNITS
COND.1
COND.' MIN. MAX.
MIN. MAX.
tpd 11 Input or I/O
Input I/0 to
to Combinatorial
Output -— 20
20 ns
ns

12 ns
ns
tcf2
tot2 -— Clock to Feedback Delay -— 10
10 ns
ns

Input or Feedback before
before Clocki
ClockT 12
12 -— ns
ns
th -— Hold Time,
lime, Input or Feedback alter
Input or after Clocki
Clockt 00 -— ns
ns
41.6 -— MHz
MHz
li(tsu + tco)
External Feedback, 1/(tsu too)
tmax33
fmax 11 Maximum Clock Frequency with with 45.4
45.4 -— MHz
MHz
tcf)
with 62.5
62.5 -— MHz
MHz
No
No Feedback
High 88 -- ns
ns
twl4
tw14 -— Clock Pulse Duration, Low 88 -— ns
ns
ten 2 Input or I/O

I/0 to
to Output
Output Enabled -— 20
20 ns
ns
tdis 3 Input or 110
I/0 to
20 ns
ns
tar 11 Input or 110
I/0 to
to Asynchronous
Asynchronous Reset of Register
Register -— 25
25 ns
ns
tarw -— Asynchronous Reset Pulse Duration
Duration 15
15 -— ns
ns
to Clocki Recovery Time
ClockT Recovery Time 15
15 -— ns
ns
tspr -— Synchronous Preset to Clocki Recovery lime
12 -— ns
ns

2) Calculated
Calculated from
from fmax with internal
internal feedback.
him( Description
Description section.
section.
3) Refer to fmax Description section.
4) Clock pulses of widths less than the specification may be
be detected as valid
valid clock
clock signals.
signals.
2-55 4/91.Rev.A
4/91.11ev.A
Lattice® GD
GAL181110
18V1 0
.l.J CorporaUon
Semiconductor
Corporation
Specifications GAL
SWITCHING WAVEFORMS
INPUT01
INPUT or
VOFEEDBACK
110 FEEDBACK \\\\\\\ VALIDINPUT
tpd
INNT
1 / 0
INPUTor
INPUT or
110 FEEDBACK
FEEDBACK
4-to u
If
1h
CLK
ClK
COMBINATORIAL
COMBINATORIAL
OUTPUT
OUTPUT
: REGISTERED
REGISTERED
t co—Or•
OUTPUT
OUTPUT
(external tott4t)
Reg Istered Output

Registered
INPUT
INPUTor01
I/0 FEEDBACK
110 FEEDBACK
OUTPUT
OUTPUT
ClK
CLK
411-1/ hoax (internal icibh)-111.
Input or I/O to Output Enable/Disable 4— tot 10 t s u --aro
REGISTERED
REGISTERED
FEEDBACK
FEEDBACK MMU
fmax
fmax with
with Feedback
Feedback
411-- tw h —101— twl

t w I--OP
ClK
CLK
Clock Width
INPUT
INPUT01
or
110
VOFEEDBACK
FEEDBACK
DRIVING
DRIVINGSPSF
INPUT
INPUToror
tc0m=
VOFEEDBACK
I/0 FEEDBACK CLK
CLK
DRIVINGAR
DRIVINGAR
41-- too
REGISTERED
REGISTERED
OUTPUT
tarw tau* REGISTERED
REGISTERED
OUTPUT
OUTPUT \\
OUTPUT
Synchronous
Synchronous Preset
Preset
1111 - - - tar
ClK
CLK
Asynchronous Reset
2-56 4/91.Rev.A
4/91 .1Rev.A
LLattice®
J,.,J Senlioonductor
SemironduGtor Specifications GAL
GAL18111
18V1 0 I
Corporation
I,
firm
fmax DESCRIPTIONS
DESCRIPTIONS
LOGIC
lOGIC
ARRAY
A R R AY
CLK
elK
, _____ . ___________ .. ___________ .... -0--------.-
REGISTER
REGISTER
roo
-------------------------------
LOGIC
ARRAY
elK
CLK
V
------------:
REGISTER
REGISTER
- !
1oI1..1----lou---+.I
tsu .....tI - - - - C - - O H .,------------------ ... ---------------.-._----_ ...
fmax with External Feedback 1/(1su+tco)
1/(tsu+tco)
tcl 01
tpti
Note: fmax with feedback is cal-
with external feedback cal-
culated from measured tsu and too.
and tco.
fmax with Internal
fmax Internal Feedback
Feedbackli(tsu+tcf)
1/(1su+tcf)
elK
CLK Note: tcf
Note: tcf is
is aa calculated
calculated value,
value, derived
derived byby sub-
sub-
,.. -------------------------------- ------------,. tracting tsu
tracting tsu from
from the
the period
period ofof fmax
fmax w/internal
wtinternal
··· .. feedback (tet
feedback (tot == 1/1max
1lfmax -tsu). The value
tsu). The value ofof tet
tcf
isis used
used primarily
primarily when
when calculating
calculating the
the delay
delay from
from
lOGIC
LOGIC clocking a register to a combinatorial
clocking combinatorial outputoutput
REGISTER
ARRAY f--+-"-' (through
(through registered
registered feedback),
shown above.
above.
For
For example, the the timing
timing from
from clock to aa com-
clock to com-
·---------._._-------_ ... _---_._---------.-------. binatorial output
binatorial output isis equal
equal to tcf + tpd.
to tet tpd.
fmax
f max With No
No Feedback
Note: fmax with
with no feedback may be
1ltwh + twl. This
less than lttwh This is to allow for
a clock duty cycle of other
other than
than 50%.

GND to 3.0V +5V
+5V
Input Rise and Fall Times 3ns
3ns 10%-90%
10%—90%
1.5V
1.5V FROM
FROMOOUTPUT
UTPUT(O/Q)
(0/0) TEST POINT
TESTPOINT
Output Load See Figure
Figure UNDER TEST
UNDERTEST
3-state levels are measured 0.5V from steady-state active Cl
level. R2

Test Condition RI
Rl R2
R2 CL
CL
1 300n
300Q 390n
390c1 50pF
50pF CL INCLUDES
LIN CLUDESJIG AND P
JIGAND PROBE TOTAL
ROBETOT CAPACITANCE
ALCAP ACITANCE
2 Active High ..
00 390n
390c2 50pF
Active Low 300n
300O 390n
3900 50pF
3 Active High c.
00 390n
390c1 5pF
5pF
Active Low 300n
300Q 390n
390Q 5pF
5pF
2-57 4!91.Rev.A
4/91.Rev.A
I1 Semiconductor
Corporation
Specifications GAL
GA1_181110
18V1 0
ELECTRONIC SIGNATURE OUTPUT REGISTER PRELOAD
An electronic signature (ES) is provided in every GAL GAL18V10

18Vl0 Whentesting
When testing state
state machine
machinedesigns,
designs, all
all possible
possiblestates
states and
andstate
state
device. ItIt contains 64 bits
bits of reprogram
reprogrammable that can
mabie memory that can transitions must
verified inin the
thedesign,
design, not
not just
justthose
those required
required
contain user-defined data. Some Some uses include user
user 10
ID codes, in the
in the normal
normal machine
machine operations.
operations. This is because
This is becausecertain
certainevents
events
revision numbers, or inventory control. The The signature data isis may occur
may occur during system operation
during system operation that
that throw
throw the
the logic
logic into
into an
an
always available
available to the user
user independent
independent of the state of the illegal
illegal state
state (power-up,
(power-up, line line voltage
voltage glitches,
brown-outs, etc.).
etc.).
security cell. To
To test
test aa design
design for
for proper
proper treatment
treatment of of these
these conditions,
conditions, aa way
way
must
must bebe provided
break thethe feedback
feedback paths,
paths, and
and force
forceanyany
desired (i.e.,
desired (i.e., illegal)
illegal) state
state into
into the
the registers.
registers. Then the the machine
machine
SECURITY CELL can
can bebe sequenced
sequenced and and the
the outputs
outputs tested
tested forfor correct
correct next
next state
state
conditions.
conditions.
A security cell is provided in every GAL 18Vl 0 device to prevent
GAL18V10
unauthorized copying of thethe array patterns. Once
Once programmed,
programmed, The
The GAL 18Vl 0 device
GAL18V10 device includes
includes circuitry
circuitry that
that allows
allows each
each reg-
reg-
this cell prevents further read access to the functional
functional bits in
in the
the istered
istered output
output to
to be
be synchronously
synchronously set
set either
either high
high oror low. Thus,
low. Thus,
device. ThisThis cell can only be erased
erased by re-programming the any
any present
present state
state condition
condition can
can be
be forced
forced for
for test
test sequencing.
sequencing.
device, so the original configuration can never be examined once IfIf necessary, approved
approved GAL GAL programmers
programmers capable
capable of of execut-·
execut-
this cell is programmed. The
The Electronic Signature
Signature is always avail- ing
ing test
test vectors
vectors perform
perform output
output register
register preload
automatically.
able to the user, regardless of thethe state of this control cell.
cell.
BUFFERS
INPUT BUFFERS
LATCH-UP PROTECTION
GAL
GALA 18Vl
8V100 devices
devices are
are designed
designed with
with TIL
TTLlevel
level compatible
compatible input
input
GAL 18Vl 0 devices are designed with an
GAL18V10 an on-board charge pump pump buffers. These buffers
characteristically high
high impedance,
impedance,
to negatively bias the
the substrate. bias is of
substrate. The negative bias of sufficient
sufficient and
and present
present aa much
much lighter
lighter load
load to
to the
the driving
driving logic
logic than
than bipo-
bipo-
magnitude to prevent input undershoots from causingcausing the the cir-
cir- lar
lar TIL
TTL devices.
devices.
cuitry to latch. Additionally,
outputs are designed with
with n-channel
pullups instead of the traditional p-channel pullups to to eliminate
eliminate The
The input
input andand 110
I/O pins
pins also
also have
have built-in
built-in active
active pull-ups.
pull-ups. As aa
any possibility of SCR
seR induced latching. result,
result, floating
floating inputs
inputs will
will float
float to
to a TIL
TTL high
high (logic
(logic t). However,
1). However,
Lattice
Lattice recommends
recommendsthat that all
all unused
unused inputs
inputs and tri-stated 110
and tri-stated I/Opins
pins
be
be connected
connected to to an
an adjacent
adjacent active
active input,
input, Vcc,
Vcc, oror ground.
ground. Do-
Do-
ing
ing so
so will
will tend
tend to
to improve
improve noise
noise immunity
reduce Icc
Iccfor
forthe
the
DEVICE PROGRAMMING device.
device.
GAL devices are programmed using a Lattice-approved Logic

from a number of
of manufacturers (see
(see the
the typical
Typical Input
input Current
Current
the GAL Development Tools section). Complete
Complete programming
programming
of the device takes only a few
few seconds. Erasing
Erasing of
of the device
is transparent to the user, and is done automatically as part
part of
of .:!. /'
the programming cycle.
cycle. ;;;
·20
-20
./
"
u
./
/'
... ·40
-40 ...-
= ·60
-60
o0 1 . 1.0
0 2 . 2.0
0 3 . 3.0
0 4 . 4.0
0 5.0
5.0
Input
Input Valtage
Voltage (Va Its)
(Volts)
2-58
2-58 4191.Rev.A
4/91.1Rev.A
[JJLaWOOQP
'L Lattices Semiconductor
Semiconducwr GAL18111
..,
Corporation
POWER-UP RESET
Vcc
Vee
OV
DV
nJ.
i
i
t pr
V IH t'"TT"T"mCT""T-rTT""\Ir---------
V IR
ClK
CLK VALID
VALIDClOCK
CLOCKSIGNAL
SIGNAL
VIL
V IL
t rase
INTERNAL
INTERNAL INTERNAL REGISTER
INTERNALREGISTER
REGISTER
REGISTER RESET
RESETTO
TO LOGIC
LOGIC00
Q·OUTPUT
0-OUTPUT
ACTIVE lOW
ACTIVELOW
OUTPUT REGISTER
OUTPUTREGISTER
ACTIVE HIGH
ACTIVEHIGH
OUTPUT REGISTER
OUTPUTREGISTER
Circuitry within the GAL18V10

GAL 18V1 0 provides a reset signal to all must
must bebe met met to guarantee
guarantee a valid valid power-up
power-up reset reset of the
the
registers during power-up. All
All internal registers will have their a GAL
GALA 18V1
8V10. o. First,
First, the
the V IX rise
Vcc rise must
must be
be monotonic. Second, the
monotonic. Second, the
outputs set low after a specified time (t 0IIESET This
45I1S MAX). This
ESET,' 45us clock
clock input mustmust become
become aa proper
properTTL
M . level
level within
within the
the specified
specified
feature can greatly simplify state
state machine design by by providing time (tpR ·,, 100ns MAX).
time (tf,A MAX). TheThe registers
registers will
will reset
reset within
within aa maxi-
maxi-
a known state on power-up. mum
mum ofof ttnEsET time.As
RESET time. As in
in normal
normal system
system operation,
operation, avoid
avoid clocking
clocking
the
the device
device until
until all
all input
input and
and feedback
feedbackpath
path setup
setuptimes
times have
havebeen
been
The timing diagram for power-up is shown above. Because
Because of met.
met.
the asynchronous nature of system power-up, some conditions

SCHEMATICS
outPut _ _ _
PIN
Dltl V I PIN
PIN
Feedblck ..
Vee AClive
ActivePull·up
Pull-up
Active Pull-up Circuh
Circuit
(Vaal Typical 3 , 2 V )
Circuit ..:r.....
i Vraf
V r et i
V cc
__.+ ..... Tri·Stata
Tri-State (VroITypicol.UV)
(Vrof Typical . 3 . 2 V )
ll l;
c Control
Control
Vret
ESD
Protecticn
Circuit
: :
Output
Output t.....
... j PIN
PIN
... Dill
De t a PIN
PIN
ESD
PIC/1000CCI Feedback
Feedback
Circuit
(ToInput
(To Input Butler)
Input Output
Output
2-59
2-59 4191.Rev.A
4/91.Rev.A
'L
isLattice® Semiconductor
Sem/conductor
Corporation
Corporation
GA1_181110
Normalized Tpd vs. Vcc
Vcr; Normalized Tsu vs.
Normalized vs. Vcr;
Vcc Normalized Teo
Normalized Too VI.
vs. Voc
Vcc
•.3,....---r----.----r--....,
13 1.3
1.3
1.2+-_
72 _ -+-__+ __-+__-i 1.2
12
). =
X''' .........
:.r:---+----+---+---;
- 8 IA
81.1
F, 11
iil
- - --
1.1
F
1, ...........b -
I- •••••••••
........ ......
l-
)"F. , ......... i.11
,!!! I1
..
0.9
..........
.......... •
0.9-1---+--+---+----l
0.9 0.'
- r
O 0 9
...
0.4 PT H
PT H·.L 0.8
O•• .•;Hlr 0.1
08
I·····
P T PTLL->H
. , H
•••••••••- PT L .v H
II·····PTH .• I
P T H - s IL
0.7
4.5 4 . 7 4,75
5 5 5 5 2 5.25
5 5.5 0.7L---l...--JL==4==::..J
0.7 0.7
0.7
4.5 4 7 5
4.5 5 5 . 2 5 4.75 5 5.25 5.5
5.5 4 . 54.5 4 7 4.75
5 5 5 5 2 5.25
5 5.5
5.5
Supply Vollage (V)
Supply Voltage (V)
Supply
Supply VoI1age
Voltage (V)
(V)
Supply Voltage
Sl4JPly Voltage (V)
(V)
,..
13
Normalized Tpd va.
vs. Temperature
Temperalure
...
1.3
Normalized Tou
Normalized Tsu VI.
vs. Temperalure
Temperature ,..
1.3
Normalized Too vs.
NormalizedTeo vs. Temperature
Temperature
'.2
1.2 1.2 V '.2
1.2
......
./V
/'
In 11.1
::::I 1 L 8n 1,.. 1• k--'"
./ V {!
lL
I-
] , L
V"
1 ·,
12 0 . 9
./ V 1V 00.9
.•
./ V 10.
z
In
Vs 0 , I9 L
V-
0.1 V
0.8 0.1
0.8 0.1 V
0.7
0.7 0.7
0.7 o.0.7'7
-50 - 2 .25
-50 5 0 0 2 525 5 050 5 75 100
100 t25
125 ·55
-55 . 2 -25
5 0 0 2 525 10
5 0 7 571 1 0tOO
0 1 2125
5 .55 - 2.zs
-55 5 0 0 2 525 5 0 so 7 75
5 100
100 125
125
fit--2 Ambient Temperature
Tempe ature (OC)
( C) Ambient
Ambient Temperalure
Temperature (OC)
(tC) Ambient
AmbientTemperature
Temperature(OC)
*C)
Delta Tpd VI.

Della vs.* Outputs Swilching
of Outputs
II 01 Switching
DeRa Tpd vs.
Delta Tpd Output Lolding
vs. Output Loading Normalized
NormalizedIa: vs.Va:
lacVI. Vcc
.010 '.3
1.3
V v /' 1.2
12
- / 10'
.-t, -'" ./ 1.1 ...
8
a
V 11 I• IL:
It
3
In
2 / lE
o 0.'
Z
0.9
/ 0 ..
0 .......
Wt.. 8
/I 01 OIAputs
of Outputs
...... ..... .V 100
100
Output Loalng
OUlpui
2 0 200
0
Loading Capacitance
Capacitance (pf)
(pf)
3 0 300
0
- 0.7
07
4.5
4.5 4 7 .US
5 5
Supply
Supply VoRage
5
Voltage (V)
(V)
5 2 525
5 5.5
...
250
IOLVS.
loL vs. VOL (OH VS. VOH
4 5 0 ...-_ _-.-_'O_H_VS.-.V_O_H_-r_ _....,
·'50
'.3
Normalized los va.
Normalized Icc vs. TTemperature
empereture
I 1 I
200 12 .... .....".........
. v6 Torspecaeoe I _
_"..T........
.",-- --
200
"-.
. vs. " r O t r. O f l a a i r e
Aro
<.50 150
1
·'00
8 ..
!.
V
-
,
oJ
.2'"
2 loo ! ............
50 / 0.2
....
.....
V
0.e
0.7
0.7
0 22 3
• 4 .u
55 - 2 .zs
5 0 0 2 6IS 10
S O 71
7 5 1 0100
0 1 2U!&
6
VOL
V O L (V)
(V) VOH(V)
VOH (V) Ambient
Ambient Temperature
Temperature (OC)
(CC)
2-60 4J91.Rev.A
4/91.1Rev.A
fIJ
J.."
Lattice
Lattice®
Semiconductor
Semiconductor
Corporation
Corporation
®
GAL221110B
GAL22V10B
GAL221/10
GAL22V10
High E2CMOS PLD
PLD
DIAGRAM
• HIGH
HIGH PERFORMANCE E2CMOS• TECHNOLOGY
E2CMOS·TECHNOLOGY
11C1.1(
IICLK
-— 10 ns Maximum Propagation Delay I
I'
-— Fmax ==105 MHz 11010

1I0IO
-— 7 ns Maximum from Clock Input to Data Output INPUT
INPUT
-— UltraMOS*Advanced
UHraMOS· Advanced CMOS Technology 11010
11010
INPUT
INPUT
• ACTIVE
ACTIVE PULL-UPS ALL PINS
PULL·UPS ON ALL
• COMPATIBLE
COMPATIBLE WITH STANDARD 22V10 DEVICES INPUT
INPUT 11010
1I0I0
-— Fully Function/Fuse·Map/Parametrlc
Function/Fuse-Map/Parametric Compatible
with Bipolar and UVCMOS 22V10 Devices
INPUT
INPUT 11010
1/010
• 50% REDUCTION IN POWER VERSUS BIPOLAR
• E'E2 CELL TECHNOLOGY
INPUT
INPUT 1/010
11010
-— Reconfigurable
-100% INPUT
INPUT 1/010
11010
(<100ms)
INPUT
INPUT
11010
11010
• TEN
TEN OUTPUT LOGIC MACROCELLS
for Complex
Complex Logic Designs
INPUT
INPUT
• PRELOAD
PRELOAD AND POWER-ON RESET OF
POWER·ON RESET OF REGISTERS 11010
11010
INPUT
INPUT
• APPLICATIONS
APPLICATIONS INCLUDE: OLIAC C> , 0 1/010
vcdo
-— DMA Control
-— State Machine Control INPUT
INPUT
-— High Speed
Speed Graphics Processing Ole C 0 I1/010
/0/0
-— Standard Logic
Logic Speed Upgrade INPUT
INPUT
RESET
• ELECTRONIC
ELECTRONIC SIGNATURE FOR IDENTIFICATION
DESCRIPTION
PACKAGE
PACKAGE DIAGRAMS
DIAGRAMS
The GAL22V1
GAL22V10B, OB, at 10ns
lOns maximum propagation delay
delay time,
time, com-
com-
bines a high performance CMOS process with Electrically Eras-
able (E2) floating gate technology to provide the highest perform-
perform- DIP
DIP
ance available of any 22V10 device on the the market. CMOS
CMOS cir-
cuitry allows the GAL22V1
GAL22V10 0 to consume much less power
power when
when
PLCC
PLCC
1/CLK Vcc
Vcc
compared to bipolar 22Vl22V100 devices. EE2' technology offers high
high IIO/Q
V0/0
«lOOms) erase times, providing the ability to
speed (<looms) to reprogram
reprogram 0
or reconfigure the device quickly and efficiently.
flexibility by
by
/ --
!!
.. IIOIQ
) IKVO
IIO/Q
V0/0
IIO/Q
I/0/0
allowing the Output Logic Macrocell (OLMC) to to be

be configured
configured by 1 IIOIQ
UV() IIO/Q
V0/0
the user.
user; The
The GAL22V1
GAL22V10 0 is fully function"use
function/fuse map/parametric 1 IIOIQ
1/0t0 IIO/Q
110/0
compatible with standard bipolar and CMOS 22Vl0 Me GAL22V10/B
GAL22V10/B
22V10 devices.
devices. NC 1 Me
NC
IIO/Q
1/0/0
IIOIQ
Top
Top View
View
reprogram mabie cells allow complete ) IIOIQ
It0/0
IIO/Q
110/0
AC, DC, and functional testing during manufacture. As As a result,
result, IIOIQ
eon IIO/Q
I/0/0
LATTICE is able to guarantee 100% field programmability and —— IIO/Q
110/0
g 2
functionality of all GAL· products. LATTICE
GAL® products. LATTICE also guarantees
guarantees 100 K !1 IIO/Q
V0/0
erase/rewrite cycles and data retention in
in excess of 20 years.
years.
GND 1
Copyright
Copyright CI991
01991 Lattice Semiconductor Corp.
Lattice Semiconductor GAL.
Corp. G A L E'CMOS
PCIAOS and
and UhraMOS
UnraMOS are
are registered
registered trademarks of Lattice
trademarks of Semiconductor Corp.
Lattice Semicor1ductor Generic Array
Corp. Generic Array logic
Logic Isisaatrademark of Lattice
trademarkof LatticeSeniconduc·
Serniconduc-
tor h e apecllcationa
tor Corp. TThe specifications herein are subject
sul*ect to change without
without notice.
LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Ct., Hillsboro, Oregon 97124 U.S.A.
97124 U.S.A. A p r i April
l 1991.Rev.A
1991.11ev.A
Tel.
Tel. (503) 681-0118 or
(503) 681'()118 or 1-800-FASTGAL; FAX (503)
1-800-FASTGAL; FAX 681-3037
(503)681-3037
2·61
2-61
fJJ
1..J
tatticeGl
ILattice®
t Semiconductor
Semiconductor
Corporation
Corporation
GAL221/10B
GA1.221110
GAL22V10
GAL221t10/B ORDERING INFORMATION
GAL22V10/B

Tpd (ns) Tsu (ns) Too (ns)
Teo icc (mA)
Icc (rnA) Ordering #
Ordering Package
Package
10
10 7 7 130
130 GAL22V10B-10LP
GAL22V1 OB-1 OLP 24-Pin Plastic
24-Pin Plastic DIP
DIP
130
130 GAL22V10B-10LJ
28-Lead PLCC
15 10 88 130
130 GAL22V10B-15LP
GAL22Vl0B-15LP 24-Pin Plastic
24-Pin Plastic DIP
DIP
130
130 GAL22V1013-15t1
28-Lead PLCC
15 12 88 130
130 GAL22V10-15LP
24-Pin Plastic DIP
DIP
130
130 GAL22V10-15LJ
GAL22V10-15W 28-Lead PLCC
28-Lead PLCC
25 15 15
15 130
130 GAL22V10-25LP
24-Pin Plastic DIP
DIP
130
130 GAL22V10-25LJ
GAL22V10-25W 28-Lead PLCC
28-Lead PLCC

Tpd (ns) Tsu (ns) Tco
The (ns) Icc
icc (rnA)
(mA) Ordering #
Ordering Package
Package
15 10 88 150
150 GAL22V10B-15LPI
GAL22V10B-15LPI 24-Pin Plastic
24-Pin Plastic DIP
DIP
150
150 GAL22V10B-15LJI
GAL22V10B-15LJI 28-Lead
28-Lead PLCC
PLCC
20
20 14
14 10
10 150
150 GAL22V10-20LPI
GAL22V10-20LPI 24-Pin Plastic
24-Pin Plastic DIP
DIP
150
150 GAL22V10-201,.11
GAL22V10-20LJI 28-Lead PLCC
28-Lead PLCC
25 15
15 15
15 150
150 GAL22\110-25LPI
GAL22V10-25LPI 24-Pin Plastic
24-Pin Plastic DIP
DIP
150
150 GAL22Vl0-25LJI
GAL22V10-25LJI 28-Lead
28-Lead PLCC
PLCC

DESCRIPTION
xxxxxxxx
XXXXXXXX -Xxx
X XX XX X
X
Device Name
GAL22V10 Device Name
-
GAL22V1OB
GAL22V10B
Speed (ns) ' - - - - - - Grade

Grade BBlank
Commercial
II == Industrial
= Low
LL = Low Power
Power Power
Power _ _ _ _ _ _ _ _---1 1...------ Package
Package PP == Plastic
Plastic DIP
DIP
J == PLCC
PLCC
2-62
2-62 4 / 9 1 . R e v . A
4191.Rev.A
[JJ
1.J
LatticeGD
Semiconductor
Semiconducwr
INdISrecot
Corporation
Corporation
Specifications GAL221110B
GAL221110
GAL22V10
OUTPUT LOGIC
lOGIC MACROCELL
MACROCEll (OLMC)
(OlMC)
The GAL22V1
GAL22V10 0 has a variable
variable number
number of product terms per per The GAl22V1
The GAL22V10 hasaa product
0 has productterm
termforforAsynchronous
AsynchronousResetReset(AR)
(AR)
OLMC. Of the ten available OLMes,
OLMCs, twotwo OLMCs havehave access
accessto to and a product
and product term
term for
for Synchronous
Synchronous PresetPreset (SP). These two
(SP). These two
eight product terms (pins 14 and
and 23), two
two have
have ten
ten product
product terms
terms product
product terms
terms are
are common
commonto to all
all registered
registered OLMCs.
OLMCs. TheTheAsyn-
Asyn-
(pins 15 and 22), two have twelve
twelve product terms (pins
product terms (pins 16 and
and 21),
21), chronous Reset
chronous Reset sets
sets all
all registers
registersto tozero
zero any
anytime
timethis
thisdedicated
dedicated
two have
have fourteen product
product terms (pins
(pins 17 and 20), and
and two
two productterm
product term is
is asserted.
asserted. The
The Synchronous
Synchronous Preset
Presetsets
sets all
all reg-
reg-
OLMCs have sixteen product
product terms (pins 18 and
and 19). In addition
addition istersto
isters to aalogic
logicone
oneononthe
the rising
risingedge
edgeof ofthe
thenext
next clock pulseafter
clock pulse after
to the product terms available for each OLMC has
for logic, each has an
an ad- this product
this product term
term is
is asserted.
asserted.
ditional product-term dedicated to output
output enable
enable control.
control.
NOTE:
NOTE: The AR AR and
and SP
SP product
product terms
terms will
will force thea
forcethe Qoutput
outputofof
The output
output polarity of each OLMC can can be individually
individually programmed
programmed the
the flip-flop
flip-flop into the same state regardless of the polarity
polarity of
of the
the
to be true or inverting, in either combinatorial
combinatorial or registered
registered mode.
mode. output.
output.Therefore,
Therefore, aa reset
resetoperation,
operation,which
whichsets
setsthe
theregister
registeroutput
output
This allows each output to be individually
individually configured
configured as either to
to a zero,
zero, may
may result in either
result in either aa high
high or
or low
low at the output
at the output pin,
pin,
active high or active low. depending
depending on on the
the pin
pin polarity
polarity chosen.
chosen.
AR
o
44 TO
TO 1t
a MUX
MUX
CL K — 0
SP
SP
2 TO t ( -_ _ _ _ _ _ _ _ _ _....1
2 TO 1
MUX
MUX
GAL22V10 OUTPUT LOGIC

LOGIC MACROCELL
MACROCELL (OLMC)
(OLMC)
lOGIC MACROCELL
OUTPUT LOGIC MACROCEll CONFIGURATIONS
Each ofof the
the Macrocells
Macrocells ofof the
the GAL22V10
GAl22V10 has has two
two primary
primary NOTE:
NOTE: InIn registered
registered mode,
mode, the
thefeedback
feedback is
isfrom the10
fromthe /0 output
outputofof
functional
functional modes: registered, and combinatorial
combinatorialI/O.
I/O. The
The modes
modes the register, and
the register, and not
not from
from the
the pin;
pin; therefore,
therefore, a pin
pin defined
defined asas
and by two
and the output polarity are set by two bits
bits (SO and S1), which
and Si), which are
are registered
registered is
is an
an output
output only,
only, and
and cannot be used
cannot be used for
for dynamic
dynamic
normally controlled by the logic
logic compiler. Each of
compiler. Each of these
these two
two 110,
I/O, as
as can
can the
the combinatorial
combinatorial pins.
pins.
primary modes, and the bit settings required to
settings required to enable them,
them, are
described below and on the following page.
following page. COMBINATORIAL 110
COMBINATORIAL I/O
In
Incombinatorial
combinatorial modemodethe thepin associatedwith
pin associated withananindividual
individualOLMC
OLMC
REGISTERED is driven by
isdriven bythe output of
the output ofthe
the sum
sum term
term gate.
gate. Logic polarityof
Logicpolarity ofthe
the
In registered
registered mode the output pin associated with with an individual
individual output
output signal
signal at the the pin
pin may
may bebe selected
specifying that
that the
the
OLMC is driven by the a Q output of that
that OLMC's
OLMC's Ootype
0-type flip-flop.
flip-flop. output
outputbuffer
bufferdrive
driveeither
eithertrue
true (active
(active high)
high)ororinverted
inverted(active
(activelow).
low).
Logic polarity of the output signal at
at the
the pin may be be selected by by Output
Outputtri-state
tri-state control
control is is available
availableas as an
an individual
individualproduct-term
product-term
specifying that the output buffer drive
drive either true
true (active high)
high) or
or for
for each
each output,
output, andand may
may be be individually
individually setset by
bythe
the compiler
compileras as
inverted (active low). Output tri-state control is Is available as as an
an either
either"on"
"on"(dedicated
(dedicated output), "off"(dedicated
output), "off" (dedicated input),
input),or
or"product-
"product-
individual product-term for each OLMC, and can can therefore
therefore be term
term driven"
driven" (dynamic
(dynamic I/O).
I/O). Feedback
Feedback into intothe AND array
theAND arrayisisfrom
from
defined by a logic equation. The
The D0 flip-flop's /Q outputis
/0 output isfed
fed back
back the
the pin side of
pin side of the
the output
output enable
enable buffer.
buffer. Both
Both polarities
polarities (true
(trueand
and
into the AND array, with both the true
true and complement
complement of of the
the inverted)
inverted) ofof the
the pin
pin are
are fedfed back
back into
into the
theAND
AND array.
array.
feedback available
available as
as inputs to the
the AND
AND array.
array.
2-63 4191.Rev.A
4/91.RevA
U..l..J lLatlioo°
/L/ L/tcoycuoctr;
SemiconducUJr
Corporation
Corporation
GAL221110B
Specifications GAL22V10S
GAL221/1 0
GAL22V10
REGISTERED MODE
AR AR
•
•
•
o Q • oD Q Q 0 0 '
•
•
C K o • C K 5
SP
SP SP
SP
ACTIVE LOW ACTIVE

ACTIVE HIGH
HIGH
5.=0
so = 0 5S0 =
=1
S == 0
5, S, = 00
5,
COMBINATORIAL MODE
•
. 111111111
•
• •
• •
• •
• •
• •
• •
IOW
ACTIVE LOW
LOW A C T I V EACTIVE HIGH
HIGH
So =
50 =0 So=
50 = 11
5, = 1 S, = 1
5,
2-64 4/91.Rev.A
4/91.Rev.A
Lattice®
I la ILattice® Specifications GAL22V10B
Semiconductor GAL221/10
Corporation
Corporation GAL22V10
GAL22V10 LOGIC DIAGRAM /JEDEC
JEDEC FUSE MAP
DIP
11(2)
(2) r >
22 36
:: i 1=i i = : : : = : : : = ; R 1 . 1 1 1 1 . 1 1 1
0002 ASYNCHRONOUS
ASNISCHRONOLISRESET
RESET
ITO
( M AALL
L L AEQlSTERS)
REGISTERS)
0044
1
....016-006 :l ai iIli *mom wypimm.=aimi amirtz. =de-
wilipinEgmhir
23(27)
23 (27)
2440
!WI' I 1! PI P I M IIIMEME11111111111111M._ov-0-111
.... : • -:— - •- : : : = • 22 (26)
22 (26)
22(3)
(3) 11E11=1 .."
0124
&Rai i i i i t i _ _-
I I I I I I I U I I u I I ••2UIIIlIIISflIUropor4-010i
... 1 21(25)
21 (25)
5812
LJ
..II
1"; 551S
OIlS21I3
33(4)
(4) '--
)486
1416 1 1 1 1 1 1 : 1 1 1 1 E 1 E 1 1 1 1 1 1 : 1 1 : 1 1 1 0 : 1 1 1
ra:;o;o 1
:'LJ
20(24)
20 (24)
2";!
..,.
51
J-=
44 (5) '--
J
:"U
19
So 19(23)
19 (23)
551810
S1
2817
iliwiramirilibliiiiiiiiiiiiiriiiiii i t 1--
. H I
E l
i
m Ioni
a falmi
ilmilimilimpliimilo
5(6)
"200 ..._________..._..._....._..._
• • •-••-• •• • ••-•:=;;IR...,:z7mr-m1 5 :..'"' U
818
SI
51
I 2819
18 (21)
18(21)
1408
"'"
6(7)
.
16-
,365,2 In • • mom ,IRIE:0! ilpmillnim
i n i . 1 1 . 1 1 1
iirEi:=::— •-----. • ••• •••—•_i.:_...T=.-. N o lWiO...Gr17mJ

I M P i 1 1 1 1 L i g I f
!:F:•• ...582,0 17 (20)

17(20)
U
SO
i=1 5."
3221
S1
SI
77 (9)
"'.
-
43"
fi a;c;; 1
0812,2
so 16 (19)
16(19)
I 5...
.... SI
58233 LJ
-
...
IIII 1111 lit 1111
8(10)
8 (10) * T I M M 161-11•110
-
Q. h i l l 111111 M -
"
15 J 15(18)
15(18)
-t!U
SO
5224
5'" SI
99(11)
(11)
.....8 M C P I W I C EIMIIIIIMPER.1111M
".;
11E1E—= =I'B So
c , •
1 14 (17)
14(17)
5770 .26
10(12) ." SNISCHR0490US PRESET
11 (13) 111111101111111111 11111111111111111111 ( M A L L REGISTERS)

13(16)
13(16)
Elecronic Skoakme 5 . 1
Bo, l e o . l a r . 5104. • IDA. 3 Isyte l o w IByle
2-65 4/91.Rev.A
4/91.13ev.A
jllLattJoo"
.l...I
Lattice
Semiconductor
Semi(X)lJductor
Corporation
GAL221110B
Commercial
Commercial
ABSOLUTE MAXIMUM RATINGSm

COND.
Vee ........................................ to +7V Commercial Devices:
Commercial
Ambient Temperature
(TA ) ••••.••••••••••••••••.••••••• to +75°C
0 to +75°C
Input - 2 . 5-2.5 to to Vcc
Vee ++1.0V
1.0V Supply voltage
voltage (Vcc)
Supply (Vee)
Off-state output voltage applied ...........- 2 .-2.5 5 toto Vee
Vcc ++1.0V
1.0V with Respect to Ground
Ground ......................
+ 4 . 7+4.75 5 to to +5.25V
+5.25V
with Respect to
- 6 5 -65 to 150°C
- 5 5 -55 to
1. Stresses above those listed under the "Absolute Maximum Maximum
Ratings· to the
the device.
device. These
These
are stress
stres:: only ratings and functional operation of the the device
at these or at any other conditions above those those indicated
indicated in
in
(while programming,
specifications).
DC
Over Recommended Operating Conditions (Unless Otherwise Specified)

CONDITION MIN.
MIN. TYR'
TYP.' MAX.
MAX. UNITS
UNITS

Low Voltage Vss-0.5
Vss -0.5 -— 0.8
0.8 VV

2.0 -— Vcc+1
Vcc+l VV
ill:
IlL' Input or I/O
1/0 Low Leakage Current OV:s; V,N:S;VII_
OV 5. VIN V,L (MAX.)
(MAX.) -— -— -100
-100 J.Ak
J.lA
I
11H
IIH •Input or I/O
Input or 110 High Leakage Current 3.5V:s;
3.5V 5 Y,N
VIN :s;5 Vcc -- -- 10
10 p.A
J.lA

lot_ = MAX. Yin
MAX. Vi n = V,L
\lit_ or
or V,H
VN -— -— (Is
0.5 VV

10H Yin
MAX. Vi n = VII_
V,L or
or V,H
\Ilk 2.4
2.4 -— -— VV
10L
101_ Low Level Output Current -— -— 16
16 mA
mA
10H
iCH High Level Output Current -— -— -3.2
-3.2 mA
mA
los2
10S2 Output Short Circuit Current Vcc
Vcc == 5V VOUT
5V Va n - == 0.5V
0.5V TTA
A == 25°C
25°C -30
-30 -— -130
-130 mA
mA
ICC Operating Power Supply Current VIL
VIL = 0.5V
0.5V VVIH
I H =3.0V
- 3.0V -— 90
90 130
130 mA
mA
floggle
ttoggle = 25Mhz Outputs Open
25Mhz Outputs Open
1) The
The leakage current is due to the internal pull-up on
on all
all pins. See Input
Buffer section
section for
for more
more information.
information.
2) One output at a time for a maximum duration of one one second. Vout = 0.5V
was selected
selected to
to avoid
avoid test
test problems
problems caused
caused by
by tester
tester
Guaranteed but 100% tested.
but not 100'/0 tested.
3) Typical values are at Vcc = 5V and
and TA
TA = 25 ·C
'C
(TA = 25°C, ff = 1.0 MHz)

CAPACITANCE (TA MHz)= =
SYMBOL PARAMETER
PARAMETER MAXIMUM"
MAXIMUM" UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
C,
Ci Input
pF Vee
Vcc== 5.0V.
5.0V, V,
Vi == 2.0V
2.0V
C,,,,
ClIO 110
I/O Capacitance 88 pF
pF Vee
Vcc == 5.0V. V,/o = 2.0V
5.0V, V,,c)= 2.0V
"Guaranteed but not
"Guaranteed but not 100%
100% tested.
tested.
2-66
2-66 4/91.Rev.A
4/91.1Rev.A
[JJ
1.J
LattiOO-
LLattice®
Semiconductor
Semironducwr
Corporation
CorporaUon
GAL22111 DB
Specifications GAL22V1 OB
Commercial
I
I
Over Recommended
Conditions
-10
-10 -15
-15
UNITS
PARAMETER
COND.' MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX.
tpd 11 Input or 110
Input I/O to
to Combinatorial Output 33 10
10 33 15
15 ns
ns
tco
teo 11 Clock to Output Delay 22 77 22 88 ns
ns
tcf22
tcf -— Clock to Feedback Delay -— 2.5
2.5 -— 2.5
2.5 ns
ns
tsul
or Feedback
Feedback before ClockT
Clocki 77 -— 10
10 -— ns
ns
tsu,
tsu. -— Setup Time, SP before Clocki 10
10 -— 10
10 -— ns
ns
th -— Hold Time, Input or

Hold or Feedback after
after Clocki
Clocki 00 -— 00 -— ns
ns
71.4 -— 55.5
55.5 -— MHz
MHz
External 1/(tsu + teo)
External Feedback, 1/(tsu tco)
fmax33
fmax 11 Maximum Clock Frequency with with 105
105 -— 80
80 -— MHz
MHz
tcf)
with 105
105 -— 83.3
83.3 -— MHz
MHz
No
No Feedback
twh4
twh -— Clock Pulse Duration:
Duration, High 44 -— 66 -— ns
ns
twt'
ns
ten 22 Input or VO
I/0 to
to Output
Output Enabled 33 10
10 33 15
15 ns
ns
tdis 33 Input or VO
I/0 to
to Output
Output Disabled 33 99 33 15
15 ns
ns
tar 11 Input or I/O to
to Asynchronous Reset of
Asynchronous Reset of Register 33 13
13 33 20
20 ns
ns
tarw -— Asynchronous Reset Pulse Duration 88 -— 15
15 -— ns
ns
tarr
tarr -— Asynchronous Reset to Clocki Reeovery Time
ClockT Recovery Time 88 -— 10
10 -— ns
ns
tspr -— Synchronous Preset to Clocki Recovery
Recovery Time
Time 10
10 -— 10
10 -— ns
ns

section.
2) Calculated
Refer to
to fmax
fmax Description section.
the specification
specification may
may be detected as
as valid
signals.
2-67
2-67 4/91.Rev.A
4/91.Rev.A
/lJ Lattice®
.l..J Lattice·Semiconductor
SemiconducWi'
Corporation
Corporation
Specifications GAL22111
GAL22V10
Commercial
ABSOLUTE MAXIMUM RATINGSm

COND.

Vee ........................................ to +7V Commercial
Commercial Devices:
Input voltage
Input voltage applied - 2 . 5-2.5 to
applied ............................ to Vcc
Vee + +1.0V
(TA) ••••••••••••••••••••••••••••• to ++75°C
0 to 75°C
Off-state output voltage applied ........... - 2 .-2.5 5 to Vee
Vc, ++1.0V
1.0V Supply voltage
Supply voltage (Vcc)
(Vee)
- 6 5 -65 to to 150°C with Respect to
with to Ground
Ground ......................
+ 4 . 7+4.75 5 to to +5.25V
+5.25V
- 5 5 -55 to
1. Stresses above those listed under the "Absolute Maximum
the device.
device. These
These
are stress only ratings and functional operation of the the device
at these or at any other conditions above those
at those indicated in
Specified)

CONDITION MIN.
MIN. TYR,
TYP.. MAX.
MAX. UNITS
UNITS
VIL
VIL Input Low Voltage Vss--0,5
Vss 0.5 -— 0.8
0.8 VV

2.0 -— Vco4-1
VcC+1 VV
IlL' Input or I/O

110 Low
Low Leakage Current OV 5 VIN
OV:;; 5 Vii.
VIN :;; (MAX.)
Vil (MAX.) -— -— -150
-150 AA
IIH
IiH Input or I/O
110 High Leakage Current 3.5V:;; VIN :;;5 Vcc
3.5V 5 VIN Vcc -— -— 10
10 AA
VOL Output Low Voltage l a = MAX.
10l= Yin
MAX. Vi n = Vil
VIL or VIH
or V11-I -— -— 0.5
0.5 VV
VOH Output High Voltage lok == MAX.

10H MAX. Vi n = VIL
Yin or V1H
Vilor VIH 2.4
2.4 -— -— VV
IOL
16 mA
mA
10H
IOH High Level Output Current -— -— -3.2
-3.2 mA
mA
los2
1032 Output Short Circuit Current Vcc
Vcc == SV
5V VVOUT
a i l = O.SV TA =
0.5V TA = 25°C
25°C -so
-50 -— -135
-135 mA
mA
ICC Operating Power
Power Supply
Supply Current VIL
VIL = 0.5V
0.5V VVIH
I H =3.0V
= 3.0V -— 90
90 130
130 mA
mA
ftoggle
f l o g & = 15Mhz Outputs Open
15Mhz Outputs Open
1) The
The leakage current is due to the internal pull-up on
pins. See input Buffer section
section for
for more
more information.
information.
2) One output at a time for a maximum duration of one
one second. Vout = O.SV
was selected
selected to
to avoid
avoid test
test problems
problems caused
caused by
by tester
tester
ground degradation. Guaranteed tested.
are at Vcc = 5V and TA
3) Typical values are TA = 25°C
25 'C
CAPACITANCE (TA
(TA = 25
25'C, =
C, ft = 1.0 MHz) =
MAXIMUM" UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
C,
pF V cc =
Vcc = 5.0V.
5.0V, V,
Vi == 2.0V
2.0V
Ct,c,
ClIO 110
I/O Capacitance 10
10 pF
pF Vee
Vcc == 5.0V,
5.0V, VI10 == 2.0V
V„0 2.0V
·Guaranteed
not 100'/0 tested.
2-68 4/91.Rev.A
4/91.Rev.A
[JJ :LatticeGl
.I..JILattice®
Semiconductor
Semioonductor
C o r p Corporation
oration
GAL22V10
Commercial
AC
Over Conditions
-15
·15 -25
·25
UNITS
PARAMETER
COND.' MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX.
tpd 11 Input or I/O to Combinatorial Output
110 to 33 15
15 33 25
25 ns
ns
tco 11 to Output Delay

Clock to 22 88 22 15
15 ns
ns
tcf2 -— Clock to Feedback Delay -— 55 -— 13

13 ns
ns

or Feedback before
before Clocki
Clock)' 12
12 -— 15
15 -— ns
ns
th -— Hold Time, Input or Feedback after Clocki
Hold ClockT 00 -— 00 -— ns
ns
11 Maximum Clock Frequency withwith 50
50 -— 33.3
33.3 -— MHz
MHz
External too)
f max33
tcf)
58.8
58.8 -— 35.7
35.7 -— MHz
MHz

62.5 -— 38.5
38.5 -— MHz
MHz
No
No Feedback
twh
twh' -— Clock Pulse Duration, High 88 -— 13
13 -— ns
ns
tw14
twl' -— Clock Pulse Duration, Low 88 -— 13
13 -— ns
ns
ten 22 Input
Input or I/O
110 to
to Output
15 33 25
25 ns
ns
tdis 3 Input or 110
I/0 to
to Output Disabled 33 15
15 33 25
25 ns
ns
tar 11 Input or 110
Input I/0 to Asynchronous Reset
Reset of
of Register
Register 33 20
20 33 25
25 ns
ns
15 -— 25
25 -— ns
ns
ClockT Recovery 15
15 -— 25
25 -— ns
ns
tspr -— Synchronous Preset to Clocki Recovery Time
12 -— 15
15 -— ns
ns
Refer to Switching Test Conditions section.

11)).Refer
Calculated from fmax with internal feedback. Refer to
2) Calculated to fmax
fmax Description
section.
4) Clock pulses of widths less
less than
than the specification may be detected as
as valid
valid clock
clock signals.
2·69
2-69 4191.Rev.A
4/91.RevA
II
fM Lattioo
L!Lattice 'Semiconductor
'Semiconductor
Corporation
Corporation
e
GAL22111 OB
Industrial
Industrial
RATINGS')
ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING
COND.
Vee ........................................ to +7V
+7V Industrial Devices:
Industrial
Input voltage applied ....•.•....•••.••.••...•..•.
- 2 . 5-2.5 to Vcc Vee + +1.0V
Ambient Temperature (TA) - 4 0 -40 to
(TA) ............•...•.....•..•.. to85°C
85°C
Off-state output voltage applied ..•......•• - 2 .-2.5 5 toto Vee
Vcc ++1.0V
1.0V Supply voltage
(Vee)
Storage
Sto rage Temperature ...........••.•....•.••...........
- 6 5 -65 to 150°C with Respect
with Respect to
to Ground
Ground •...............•.....
+ 4 . 5+4.50 0 toto +5.50V
+5.50V
Ambient with
Power Applied ..•.............•....•.•...•.•...........
- 5 5 -55 to to 125°C
1. Stresses above those listed under the the "Absolute Maximum
Ratings·
Ratings" may cause permanent damage to the the device. These
These
the device
at these or at any other conditions above those indicated in in
(while programming, follow
follow thethe programming specificatiol'1s).
specifications).
Specified)

CONDITION MIN.
MIN. TYP.s
TYR' MAX.
MAX. UNITS
UNITS
VIL Input Low Voltage Vss-O.5

Vss –0.5 -— 0.8
0.8 VV
2.0 -— VCC+1
Vcc+l VV
IlL'
IILI Input or 1/0
I/O Low
Low Leakage Current OV::s; VIN::S;
OV s VIN VIL (MAX.;
5. VIL (MAX ; -— -— -100
-100 p.A
IlA
IIH Input or I/O
110 High Leakage Current 3.5V::s;
3.5V 5 VIN
VIN :5s; Vee
Vcc -- -- 10
10 IlA
gA

km...= MAX. Vin
MAX. Vi n .. VIL or
= VII_ or VIH
Vii-i -— -— 0.5
0.5 VV
VOH Output High Voltage 100
loH ... MAX. Vi
Vinn = Vii_
VIL or VIH
or VIH 2.4
2.4 -— -
— VV
IOU
lOll Low Level Output Current -— -— 16
16 mA
mA
10H High Level
Level Output
Output Current -— -— -3.2
–3.2 mA
mA
los2
10S2 Output Short Circuit Current Vee-
Vcc = SV VOUT == 0.5V
5V VOUT 0.5V TTA
A == 25°C
25°C -30
–30 -— -130
–130 mA
mA
ICC Operating Power Supply Current VIL=0.5V
VIL = 0.5V VVIH
I H =3.0V
= 3.0V -— 90
90 150
150 mA
mA
ftoggle
ftoggie = 25Mhz Outputs Open
25Mhz Outputs Open
1) The
The leakage current is due toto the
the internal pull-up on all
section for
for more
more information.
information.
2) One output at a time for a maximum duration of one second. Vout Vout =
= O.SV
0.5V was
was selected
selected to
to avoid
avoidtest
test problems
problems caused
causedby
bytester
tester
Guaranteed but not 100"/0100% tested.
tested.
3) Typical values are at Vcc
Vee ..
= 5V and TA TA ..= 25°C
25 'C
CAPACITANCE (TA
(TA = 25°C, =
25 C, f = 1.0 MHz) =
SYMBOL PARAMETER MAXIMUM'
MAXIMUM' UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
pF Vee
Vcc== 5.0V,
5.0V, V,
Vi =. 2.0V
2.0V
110
I/O Capacitance pF
. ClIO
C,,0 88 [DP Vcc == 5.0V,
Vcc 5.0V, V'IO
V„0 == 2.0V
2.0V
Guaranteed but not 100"A
"Guaranteed 100% tested.
2-70
2-70 4191.Rev.A
4/91.Rev.A
l..J ILattice'
Semiconductor
Semloonductor
GAL221/10B
C o r p Corporation
oration Industrial
Industrial
AC
OVer Conditions
-15
-15
TEST DESCRIPTION
DESCRIPnON UNITS
UNITS
PARAMETER
COND.' MIN. MAX.
MIN. MAX.
to Combinatorial Output 33 15
15 ns
ns
tco 1 Clock to Output Delay 22 88 ns

ns
'kV
tcf2 -— Clock to Feedback Delay -— 55 ns
ns i
tsut
tsu -— Time, Input or
Feedback before
before Clocki 10
10 -— ns
ns I
tsu,
tsu. -— Time, SP before Clocki
Setup lime, ClockT 12
12 -— ns
ns
th -— Hold Time,
Clocki 00 -— ns
ns
55.5 -— MHz
MHz
tco)
fmax33
Id)
66.6
66.6 -— MHz
MHz

with 66.6
66.6 -— MHz
MHz
No
No Feedback
twh4
twh's -— Clock Pulse Duration, High 66 -— ns
ns
twt'
ns
ten 22 Input or 110
I/O to
to Output
15 ns
ns
to Output
Output Disabled 33 15
15 ns
ns
tar 1 Input or 1/0
I/O to
to Asynchronous
Asynchronous Reset
Reset of
of Register
Register 33 20
20 ns
ns
15 -— ns
ns
to Clocki Recovery lime
10 -— ns
ns
tspr
ispr -— Synchronous Preset to Clocki Recovery
Recovery lime
Time 12
12 -— ns
ns
SWitching Test Conditions section.

1) Refer to Switching section.
2) Calculated
Calculated from
from fmax with internal feedback. Refer
Refer to
3) Refer to fmax
t a m Description section.
the specification may be detected as valid
2-71
2-71 4 / 9 1 . R e v 4191.Rev.A
. A
[JJ 'Lattioo*
.1_Lattice®
.J"J Semiconducwr
, Semiconductor
Corporation
CorporaUolJ
GAL221/1
Specifications GAL22V10
Industrial
Industrial
COND.
Supply voltage Vee 5 -0.5 to +7V
Vcc ........................................
- 0 . Industrial
Industrial Devices:
Input voltage applied .........................
- 2 . '" 5-2.5 to Vee Vcc + 1.0V
+1.0V Ambient
Ambient Temperature (T (TA) – 4 0 -40 to
A ) •••••••••••••••••••••••••••• to 85°C
85°C
Off-state
Oft-state output voltage applied ...........- 2 .·2.5 5 to Vcc
Vee + 1.0V
+1.0V Supply
Supply voltage
voltage (Vee)
(Vcc)
Storage Temperature - 6 5 -65 to 150°C with
with Respect to
to Ground ......................
+ 4 . 5+4.50 0 toto +5.50V
+5.50V
Power Applied .........................................
- 5 5 -55 to 125°C
1. Stresses above those listed under thethe "Absolute
"Absolute Maximum
Ratings may
Ratings· may cause permanent damage to to the
the device.
device. These
These
are stress only ratings and functional operation
operation of
of the
the device
device
those indicated inin
follow the
DC
Over Recommended
Specified)
SYMBOL PARAMETER
PARAMETER CONDITION
CONDITION MIN.
MIN. TYR'
TYP.' MAX.
MAX. UNITS
UNITS
VII_
VIL Input Low Voltage Vss-O.S
Vss –0.5 -— 0.8
0.8 VV

2.0 -— Vcc+l
VCC+1 VV
IILI
tiL' Input or 110
I/O Low Leakage Current OV
DV5S_VIN
Y,N 5S_V,L
VIL (MAX.)
(MAX.) -— -— -150
-150 p.A
itA
IIH
ilH 110 High Leakage Current
Input or I/O 3.5V
3.5V 5s_VIN
Y,N 5S_VCC
Vee -
- -- 10
10 itA
plk
VOL Output Low

Low Voltage 10L=
la_ = MAX. Yin = V,L
MAX. Vin Vli_ or
or V,H
VIH -
- -- 0.5
0.5 VV
VOH Output High Voltage IOH = MAX.

lou .-- Vin
MAX. Vi n = VIL
V,L or
orV,H
V11-1 2.4
2.4 -— -— VV
tOL
IOL Low Level Output
Output Current -— -— 16
16 mA
mA
tOH
–3.2 mA
mA
los2
10S2 Output Short Circuit Current Vee=5V VOUT =
Vcc = 5V VOUT = 0.5V TA =
0.5V TA = 25°C
25°C -50
–50 -— -135
–135 mA
mA
VIL = 0.5V VVIH
I H =3.0V
= 3.0V -— 90
90 150
150 mA
mA
ftoggle
ftoggie == 15Mhz Outputs
Outputs Open
Open
1) The
The leakage current isis due
due to
to the internal pull-up on all
all pins. See Input Buffer section
pins. See section for
for more
more information.
information.
2) 'One
One output at
at a time for
for a maximum duration of one one second. Vout
Vout =
= 0.5V
0.5V was
was selected
selected to
to avoid
avoid test
test problems
problems caused
caused by
by tester
tester
Guaranteed but not not 100%
100'/0 tested.
tested.
are at Vcc
Vee =. 5V
5V and TA = 25
and TA 25 ·C
'C
CAPACITANCE (TA
(TA = 25°C, ff 11.0 =
. 0 MHz)
MHz) =
SYMBOL PARAMETER
PARAMETER MAXIMUM"
MAXIMUM* UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
C,
C, Input
pF Vcc-= 5.0V,
Vee 5.0y, V,
V, -= 2.0V
2.0V
Coo
Coo 1/0
I/O Capacitance 10
10 pF
pF Vee
Vcc== 5.0V, VIIO == 2.0V
5.0V, VoD 2.0V
*Guaranteed but not
'Guaranteed 100% tested.
not 100'/0 tested.
2-72
2-72 4/91.Rev.A
4/91.Rev.A
LILattice®
l.J Semiconductor
SemiconducUJl'
GAL22V10
Corporation Industrial
Industrial
AC
Over Recommended
Conditions
-20
-20 -25
-25
TEST DESCRIPTION
PARAMETER
PARAMETER UNITS
UNITS
COND.
COND.' MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX.
tpd 11 I/O to
Input or 110 to Combinatorial Output
Output -— 20
20 -— 25
25 ns
ns
tco 11 to Output Delay

Clock to -— 10
10 -— 15
15 ns
ns

Clock to -— 88 -— 13
13 ns
ns

Setup lime, or Feedback before
before Clocki 14
14 -— 15
15 -— ns
ns
th -— Hold Time,
ClockT 00 -— 00 -— ns
ns
41.6 -— 33.3
33.3 -— MHz
MHz
f max'3
45.4 -— 35.7
35.7 -— MHz
MHz
tcf)
with 50
50 -— 38.5
38.5 -— MHz
MHz
No Feedback
twh" -— Clock Pulse Duration, High

High 10
10 -— 13
13 -— ns
ns
twl" -— Clock Pulse Duration, Low 10
10 -— 13
13 -— ns
ns
ten 22 Input or 110

I/O to
to Output Enabled -— 20
20 -— 25
25 ns
ns
tdis 3 Input or 1/0
Inpu1 I/O to
20 -— 25
25 ns
ns
tar 1 Input or 1/0
I/O to
to Asynchronous
Asynchronous Reset of Register -— 25
25 -— 25
25 ns
ns
Duration 20
20 -— 25
25 -— ns
ns
to Clocki Recovery lime
20 -— 25
25 -— ns
ns
Recovery lime
Time 14
14 -— 15
15 -— ns
ns

section.
2) Calculated
Calculated from fmax with internal feedback.
fn.= Description
section.
widths less than the specification may be detected
detected as valid
signals.
2-73 4191.Rev.A
4/91.1RevA
[jJ
1..;
'Latlice
LLattice®
Semiconductor
SemiconductJJr
Corporation
GAL221/1 OB
GA1_221110
GAL22V10
SWITCHING WAVEFORMS
INPUTDr
INPUT or
INPUTor
INPUT Dr
VOFEEDBACK
VO FEEDBACK \\\\\\\\\{AW",," VALIDINPUT I/OFEEDBACK
VOFEEDBACK
\\'J\\';= :
COMBINATORIAL
COMBINATORIAL CLK
ClK
OUTPUT
OUTPUT
REGISTERED
REGISTERED
OUTPUT
OUTPUT
4 - 1 / fmax
(external tdbk)
Registered
Registered Output
Output
INPUTor
INPUT Dr
VOFEEDBACK
VOFEEDBACK
4— tdis 4-ten
OUTPUT
OUTPUT
ClK
CLK
tmax (internal t d b k ) ÷
Input or 1/0
I/O to Output Enable/Disable 1 1 - I Ct t - 0 1 1 '
REGISTERED
REGISTERED
FEEDBACK
FEEDBACK
fmax
fmax with
with Feedback
Feedback
tw t wI—11110.
twl
ClK
CLK
Clock Width
INPUT
INPUTorDr INPUT
INPUTor
or
VOFEEDBACK
I/0 FEEDBACK VOFEEDBACK
VO FEEDBACK
DRIVINGAR
DRIVINGAR DRIVING
DRIVING SP
SP
tar w tar r
ClK
CLK
REGISTERED
REGISTERED
OUTPUT
OUTPUT " a
4 11 - - - - tar
REGISTERED
REGISTERED
OUTPUT
OUTPUT \\\\\\\\\\\\\\
ClK
CLK
Synchronous
Synchronous Preset
Preset
Asynchronous Reset
Reset
2-74 4191.Rev.A
4/91.Rev.A
i
[JJ
!
.l.J
'Lattice
L/Lattice'
Semiconductor
Semironductor
e GAL221110B
Specifications GAL22V10S
Corporation GAL22111 0
GAL22V10
fmax DESCRIPTIONS
CLK
ClK elK
CLK
,._----------_ ..... _- --_ ... _------- ._._--.. ----
I0
LOGIC
LOGIC
lOGIC
V
REGISTER
REGISTER
ARRAY
ARRAY
A R R AY
REGISTER
""I
..I----Isu
t t C - - 1 1 1 0 1
tct
fmax with External Feedback 1/(1su+tco)
1/(tsu+tco)
tpd o l
Note: fmax with
with external
external feedback is
tco.
calculated from measured tsu and tco.
f max with
fmax with Internal
internal Feedback
1/(tsu+tcf)
OK
ClK Note: tcf is a calculated
Note: calculated value,
value, derived by
subtracting tsu from
subtracting from the period of fmax f max wI
w/
internal feedback
internal feedback (tcf = = 1/fmax - tsu).
tsu). The
The
value of tcf
value of tcf is
is used
used primarily
primarily when
when calculating
calculatingthe
the
LOGIC
lOGIC
REGISTER
delay
delay from
from clocking
clocking aa register
register to
to aa combinato-
combinato-
ARRAY
A R R AY
rial
rial output (through
(through registered
feedback), as as
shown above.
shown above. For example, the timing
For example, timing from
from
.-----------------------_._._----------_._-------. clock
clock to
to aa combinatorial
output isis equal
equal to tcf ++
totcf
tpd.
tpd.
Note: fmax with
with no feedback may may bebe less
less
1ltwh + twl.
than 1/twh for aa clock
twl. This is to allow for clock
duty cycle of other than 50%.
Input Pulse Levels . GNDto

GND to 3.0V
3.0V +5V
+5V
3ns 10%-90%
10%—90'Yo
1.5V
1.5V FROM
FROMOOUTPUT
UTPUT(O/Q)
(0/0) TEST
TESTPOINT
POINT
Output Load See
See Figure UNDER TEST
UNDERTEST
from steady-state active C
level. R2

figure)
Test Condition R1
Ill R2
R2 CL
CL
11 300n
3000 390n
3900 50pF
50pF CL INCLUDES
l IN CLUDESJIG AND P
JIGAND PROBE TOTAL
ROBETOT CAPACITANCE
ALCAP ACITANCE
2 Active High
Active High .0 390n
3900 50pF
50pF
Active Low 300n
300U 390n
3900 50pF
50pF
3 ,Active
Active High .0 390n
390K2 5pF
5pF
Active Low 300n
3000 390n
3900 5pF
5pF
2-75 4/91.Rev.A
4/91.Rev.A
[D; Semiwnductor
tattiOO®
L/Lattice'
.l..J Semironductor
Corporation
GAL221110B
GAL221110
GAL22V10
ELECTRONIC SIGNATURE REGISTER PRELOAD
An electronic signature (ES) is provided in every GAL22V1
GAL22V10 0 When testing
When testing state
state machine
machine designs,
designs, allallpossible
possible states
states and
and state
state
device. ItIt contains 64 bits of reprogram
reprogrammable
mabie memory that
that can
can transitions must
verified in
in the
the design,
design, notnot just
just those
those required
required
contain user-defined
user-defined data. SomeSome uses include user ID codes, inthe
in the normal
normal machine
machine operations.
operations. This is is because
because certain
certain events
events
revision numbers,
numbers, or inventory control. The
The signature data is may occur
may occur during system
system operation
operation thatthat throw
throw the
the logic
logic into
into an
an
always available to the user independent of thethe state of
of the
the se-
se- illegal state
(power-up, line
line voHage
voltage glitches,
brown-outs, etc.).
etc.). To
To
curity cell. test aa design
test design for
for proper
propertreatment
these conditions,
conditions, aaway
waymust
must
be provided
be provided to to break
break the
the feedback
feedback paths,
paths, and and force
force any
any desired
desired
The electronic signature is an additional feature not present
present in in (i.e., illegal)
(Le., state into
illegal) state into the
the registers.
registers. Then
Then thethe machine
machine can can bebe
other manufacturers
manufacturers' 22V10
22V1 0 devices. To To use
use the
the extra feature
feature ofof sequenced and
sequenced and the
the outputs
outputstested
tested for
forcorrect
correct next
nextstate
stateconditions.
conditions.
the user-programmable electronic signature it is necessary to to
choose a Lattice 22V1
22V10 when compiling
0 device type when compiling aa set
set of
of logic
logic The GAL22V10
The GAL22V10 device
device includes
includes circuitry
circuitry that
that allows
allows each
each reg-
reg-
equations. In
In addition,
addition, many
many device programmers have two istered output
istered output to
to be
be synchronously
synchronously setset either
either high
high or
or low.
low. Thus,
Thus,
separate selections for the device, typically a GAL22V1
GAL22V10 and aa
0 and any present
any present state
state condition
condition can
can be
be forced
forced for
fortest
test sequencing.
sequencing. IfIf
GAL22V10-UES (UES (UES == User
User Electronic
Electronic Signature)
Signature) oorr necessary, approved
necessary, approved GAL
GALprogrammers
programmerscapable
capable ofof executing
executing test
test
GAL22V10-ES.
GAL22V1 O-ES. This allows users to maintain compatibility
compatibility with vectors perform
vectors perform output
output register
register preload
automatically.
existing 22V10
22V1 0 designs, while still having the
the option
option to
to use
use the
the GAL
GAL
device's extra feature.
feature. INPUT BUFFERS
GAL22V10
The JEDEC map for the GAL22V1 64 extra
0 contains the 64 extra fuses
fuses GAL22V10 devices
GAL22V10 devices are
are designed
designed with
with TTL
TTL level
level compatible
compatible in-in-
the electronic signature, for a total of 5892 fuses.
for the fuses. However, put buffers.
put buffers. These buffers have
These buffers have aa characteristically
characteristically high high im-
im-
the GAL22V10 device can still be programmed with with a standard
standard pedance, and
pedance, and present
present aa much
much lighter
lighter load
load to
to the
the driving
driving logic
logicthan
than
22V10
22V1 0 JEDEC map (5828 fuses) with any qualified
qualified device pro- bipolar TTL
bipolar TTL devices.
devices.
grammer.
The input
The and I/O
input and I/O pins
pins also
also have
have built-in
built-in active
active pull-ups.
pull-ups. AsAs aa
result, floating
result, floating inputs
inputs will
will float
floatto
to aa TTL
TTL high
high (logic
(logic 1).
1). However,
However,
SECURITY CELL Lattice recommends
Lattice recommends thatthat all
all unused
unused inputs
inputs and
and tri-stated
tri-stated I/O
I/0 pins
pins
be connected
be connected to to an
an adjacent
adjacent active
active input,
input, Vcc,
\ice, or
or ground.
ground. Doing
Doing
A security cell is provided in every GAL22V1
A GAL22V10 0 device toto prevent
prevent so will
so will tend
tend to
to improve
improve noise
noise immunity
immunity and and reduce
reduce Icc!cc for
forthe
the
unauthorized copying of the array patterns. Once programmed,
Once programmed, device. (See
device. (See equivalent
equivalent input
input and
and I/O
I/O schematics
schematics on on the
thefollowing
following
this cell prevents further read access to the functional
functional bits
bits in
in the
the page.)
page.)
This cell can only be erased by re-programming the
device. This the
device, so the original configuration can never be examined once once
this cell is
is programmed. TTheh e Electronic Signature is is always
always Typical
Typical Input Current
Current
available to the user, regardless ofof the
the state of this
this control
control cell.
cell.
;(
LATCH-UP PROTECTION -=- /"
./
--
" ·20
-20
GAL22V10 devices are designed with an on-board
on-board charge
charge pump
pump "
<J
./
to negatively bias the substrate. The negative bias
bias is
is of
of sufficient ·40
/"
magnitude to prevent input undershoots from
from causing
causing the
the circuitry
circuitry "c.
to latch. Additionally,
with n-channel
n-channel pullups
pullups "
-60
•60
instead ofof the traditional p-channel
p-channel pullups
pull ups to eliminate any
o0 1 . 1.0
0 2 . 2.0
0 3 . 3.0
0 4 . 4.0
0 5.0
50
possibility of SCR
SCR induced latching.
Input
Input Voltage
Voltage (Volts)
(Volts)
DEVICE PROGRAMMING
GAL devices are

are programmed using a Lattice-approved Logic Logic
Programmer, available from aa number
number of
of manufacturers
manufacturers (see
(see the
the
the GAL
the GAL Development Tools
Tools section). Complete programming
programming of of
the
the device takes
takes only a few Erasing of
few seconds. Erasing of the
the device is is
transparent
transparent to
to the user, and
the user, and is
is done automatically as
done automatically as part
part of
of the
the
programming
programming cycle.
2-76 4/91.Rev.A
4/91.Rev.A
I,
I,.'
[JJ
I
1A1ttiOO-
.l..J!Lattice®
GAL...221/10B
Specifications GAL22V10S I
Semiconductor
Semiconductor
C o r p Corporation
oration GA1.221110
GAL22V10 !
POWER-UP RESET
9 0 7
Vcc
OV
OV
t pr
V IH
VIH
CLK
CLK VALID CLOCK
VALID CLOCK SIGNAL
SIGNAL
V IL
VIL
t rese
INTERNAL
INTERNAL REGISTER
REGISTER
REGISTER RESETTO
RESET TO LOGIC
LOGIC00
0-OUTPUT
Q.OUTPUT
ACTIVE LOW
ACTIVE LOW
OUTPUT REGISTER
OUTPUT REGISTER
ACTIVE HIGH
ACTIVE HIGH
OUTPUT REGISTER
OUTPUT REGISTER
Circuitry within the GAL22V10 provides aa reset reset signal to all

all be
be met to guarantee
guarantee a valid
valid power-up
power-up reset
reset ofof the
the GAL22V1
GAL22V10. o.
registers during power-up. All
All internal registers will have their
theirQ First,
First, the
the Vee
Vcc rise
rise must
must be
monotonic. Second, the clock
clock input
input
outputs set low after a specified time (t RRESET'
ESET, 4511s This
45I1S MAX). This must
must become
become a proper
proper TIL
TTL level
level within
within the
the specified
specified time (tpR',
time (tpR
feature can greatly simplify state machine design by providing
providing a 100ns
100ns MAX).
MAX). The registers
registers will
will reset
reset within
within aa maximum
maximum of oftR EsET
RESET
known state on power-up. time.
time. As
As inin normal
normal system
system operation,
operation, avoid
avoid clocking
clocking the
the device
device
until
until all
all input
input and
and feedback
feedback path
path setup
setup times
times have
have been
been met.
met.
The timing diagram for power-up is shown above. Because of
above. Because of the
the
asynchronous nature of system power-up, some conditions must
must
Output
Output _ _ _ _
PIN'I N
P > e>--f6= Data
Data V I PIN
PIN
Feedback
Feedback ..
Vee
Vc c Adive
Active Pull·up
Pull-up
Active Pull-up Circuit
Circuit
(Yror
( V W Typica'
Typical .3.2V)
3.2V) Circun Vee
V cc
.. .Y. ....
TTri-State
ri·State vrel!
Vr e l M e l Typicat.
(Vref Typical 33.2V)
.2V)
Control
Control
c Vret V c c
ESD
Protection
f
Circuit
Output
Output
Data
Data PIN
PIN
PIN
Feedback
Feedback
(To
(ToInput
inputBuffer)
Butter)
Input Output
Output
2-77 4/91.Rev.A
4/91 .Rev.A
[JJ
L.l.J
tatUOOGl
Lattice
SemicondUCUJr
ISemiconductor
Corporation
CorporatiOn
GAL22111 DB
OB
Normalized Tpd vs Vcc

Normalized Vee Normalized Teo
Normalized Too vs
vs Vee
Vcc Normalized Tsu
Normalized Tsu VI
vs Vee
Vcc
•., 2 '.2
1.2
I····· PTH·.L I·····

a r s e
. I·····
--
1
...
' P T 1-1,L P T
ROlE
I l--PTL.•H
r---k·
1.1
I
1.1
I FALLJ
".
...... ".
— PT L-,H
PTL->H
". " . FALL
.!! — PT L , H
]' •.•
0.9 +---If---+---+----I
'" '" '"
]
j
•.•O.+---If---+--+---I
". ".
". l'... 0,9
.-=:--
'. :--
'. '"
•.•
0.1
u.
4.50
__I__--I----+----l
4.75
4.75 5 0 5.00
0
Voltage (V)
Supply Voliage
5 2 5 u.
550 4 - 5
•.•
0 u. 4 . 7 5 '.711 5 . 05.00
0
Supply Voliage
Supply Voltage (V)
(V)
5 2 5 5 5 u.
0 4 . 5
...
OA
0".50 4 , 74.75
5 5 . 05.00
Supply Voliage
Supply
0
Voltage (V)
(V)
5 2 5 ....
530
Normalized Tpd vs Temp Normalized Teo

Normalized Tco vs Temp
Temp Normalized Tsu
Normalized Tsu vs
vs Temp
Temp
1.3 rr==::r:::::::;;T-i-i 1.3

1.3 14
1.4 rr==:r:::::::;;T-i-,
1.' PTH·.L [H---+--..-l
•••••' P T '.2
1.2 — R I S E 1.33 I .,:;..
_ ....... PTH-:..L
PT H , 4 _
....
"&. 1.1 11IL Irt-:::;:;:::t·...··..;......-"'·1
PT L , H 1.1
7.7 — FA L L /- .!!,2, 1.2 12
— _ PT L , H
_ H PTL.• ,H---. ••'-7-"'-1
,./" -E 1.1
il
,g.
o 0.9 •.•
'73
o 0.9 ..• ..-- il

IE 1 +---If---o:::.of""'---+---l
.:."
...
:li! •.• .. '
0 9 +--,:,;:;:r---t--i--l
••
•.• +---1---+---+---1
OA OA
•.• +---If---+---+---I
OA
•.
0.7
...
7 -I---I----4---I----l
.55 0 2
TemperBlure
5 .. .. ...
9 0
•.
0.77
...
-55 0 2
Temperalure
5 . . ,..
C)
9 0 1 2 5
•.0.7
.•.
7 -1---11----4---1----1
55 0 2
Temperalure
5 .. . ...
Temperature (deg.
(deg. C)
C)
9 0 125
Delta Tpd vs # of Outpuis

Delta Outputs Delta vs ## of Outputs
Tco vs
Delta Teo
Switching
Switching Switching
Switching
,.,--- ,/
"..-
_.0.5
-0 5 _-0.5
.17., -0,5
g
'" ......- .' g
o
., k-:' .' --::
..2-
.g
2
.,
.. '
!1·····Rlse} .g
II'"'' Rise} RISE
c!: .1 .• c!: .1.'
II--FALL II--FALL
. ,.
— FA L L FALL
·2
.2 i i ., I 9 I
3 4 1 7 I 9 • 1 1.0 22 3 3 4 .. 55 6 a 7 I 9 1 0
Number of Oulpuls
Outputs Swhching
Switching Number
Number of
of Outpuls
Outputs Swhching
Switching
Delta
Delta Tpd
Tpd vs Output Loading Defta Too vs
Delta Teo vs Output
Output Loading
"
1. ..... Rise
. RISE
./ ,.
12
12
ID R I S E
LV
./
a — --FALL
— FA L L
./
./
" --FALL,
— FA L L
V .
.. ..
-g
V V
-2 4
0 V. /.
0 /-" 0 L'
., :/ ·2 :/
50
55 0 100
0 1 5150
0 2 0200
0 2 5250
0 300
3oo 0 5 050 1 0100
0 1 5150
0 2 0200
0 2 52SO
0 300
300
Outpul Loading (pF)

Output Loading Output
Output Loading (pF)
(pF)
2-78
2-78 4191.Rev.A
4/91.Rev.A
flJSemiconductor
'Lattioo·
i
Lattice° GAL22V1 OB
.J..J Corporation
Semiconductor
Corporation Typical Characteristics E l i
I
Vol vs lel
VB 101 Voh vs
Voh vs Ioh
loh Voh vs toh
Vohvsloh
3 ....
4,50
I
•2.5
.5
v 4
....
--
425
I ' r--.....
V 2-. 3 .........
r--
25-
4.00
\ ......
// .• 2
r----. :--
I-'
... V 375 -••••••••
V ...... 0 ....
3.50
0,00
0.00 2 020.00 40.00
00 S O 00 6 0 10.00
.00 10.00
90 00 1 0100.00
0.00 0.00
0.00 1 10.00
0 00 10.00
20 00 330.00
0 00 S40.00
O 00 5 50.00
0 00 10.00
0000 0.00
0.00 1 . 01.00
0 2 . 02.00
0 3 . 01.00
0 4.00
lol (mA)
101 loh(mA)
loh(mA) loh(mA)
loh(mA)
Normalized Icc vs Vee

Normalized Vcc too vs Tamp
Normalized Ice
Normalized Temp Normalized Icc
Normalized Ice vs
vs Freq.
Freq.
....
l!
1.20
1.20
1.10
1.10
/ l!
u.
1.20
1.10
"to
.........
120
1.10
V
/v
/
'" ""-
-0
il
]..t9 1'.0.
.00
/ il
70e'?.1.00 1.00
./ i ./
0.10
0.90
./ 0.10
0.90
........ 0.'0
0.90
0.10
050
4.50
4.50 4 , 74.75
5 5 . 05.00
0
Supply Voltage (V)

5 2 5.25
5 ,.50
5.50
u.
090
... ...
.55 . 2 5 0
Temperature
25 1$ 1 0100
25 7 5 0
" 125
125
u.
0,90
0 .. 25 5
Frequency
0 50
Frequency (MHz)
(MHz)
7 5 '00
100
Ice vs Vin (1 input)

Delta !cc Input) Input Clamp (Vlk)
Input (Vik)
5 0 f"'""
20
20
••
10
/
30
30
/
. 1 /
'1"50
,
.9 22
\ E 50
!l!! eo
60
/
\ /
, r-
70
J 70
eo /
.....
..
SO
/ to L
,
100
0.00
0,00 0 0.50
, 5 0 1 .1.00
0 0 1 1.50
. 5 0 22.00
, 0 0 22.50
. 5 0 33.00
. 0 0 33.50
. 5 0 .··4.00
4.00 -2.00
-2 00 -1.50 -1.DO -0.50 0.00
0.00
Vin(V)
Vin (V) Vik(V)
Vik (V)
2-79
2-79 4191.Rev.A
4/91.Rev.A
isLattice® GAL221110
.l.J Semiconductor
SemiconducUJr
Normalized Tpd vs Vcc
Vee Normalized Tsu vs. Vcc
Normalized Vee Normalized vs._
Normalized Tco vs. Vcc
13
13 13
1.3 1.3,
13 _ _- ._ _ _.Teo -_ Va;
- ._ _- - ,
12
S2 12
1.2
t1 22 t _ - - _ + - - - t _ - - _ + - - _ ;
-
"&. 1.1 .........
-
II 811
fE"
1.1
.......... ,,;---+---t---t----;
..........
- r---
I-
] ,' ] ......... ........
..........
15Co 'faCo ....... .......... I P=9---t----;;:;f;=:;;::;;J
E
l5 0.' § r--
r
z 09
0 0.9 6 0.9t_--_+---t_--_+--_;
09
2
Z
08
0.8
--
wwwww PPT
I·····
P T
T H
H·,L
PT 1.81
08t----t----H
0.8 P11,8
- - PT t·, H l-
.. I.....
l·)oH
0.7 1 P T H L
PTH·, I
0.7
45 4 7 04.75
5 5 , 5 . 2 5%1
5 ,.,5 O.7L--L_-t=:::r=:=J
07
4.5 4 . 7 5
4.5 5 5 . 2 5 5.5
4.75 5 5.25 5.5
0.7
0.7'":-_ __:':::---"':---_:':::---:<
4 . 54.5 4 7 4.75
5 5 5 5 2 5.2S
5 5.5
5.5
Supply Voltage (V)
Supply Voltage
Supply Voltage (V)
(V) Supply Voltage
Supply Voltage (V)
(V)
Normalized Tpd vs. Temperature Normalized Tsu

NormaJized Tsu vs. Temperature
Temperature Normalized Teo
Normalized Too va.
vs. Temperature
Temperature
13
1.3 3
1.3 1.3
1.3
1.2 1.2
1.2 V 1.2 2
13.1.1I
"8.1. ./
V 11I
1. ./
V 88 I.I ,/
I-'
1—
I-
V ,..,
7.1 , ./ I
V" >-
] I ./
V ,/
jg 0,9 . /V
(;EC,o09
.•. /
1
2 0.9
0.9 ./ . ./ o.•
z
o..V
0.8 o.0.8 .V
o.08
o.0.7
7 07
O. 7 o.0,77
-SO - 2·25
.5O 5 0 02
25 50
55 0 7
755 1 0100
0 125
125 -55
·55 - 2-25
5 0 o 2 525 5 050 75
75 1 0100
0 125
125 ·55 •25
·25 0 2 5 5 0 7 575 100
100 125
125
Ambient Temperature
Tempe ature ((oG)
C) Ambient Temperature tOe)
Ambient ('C) Ambient Temperature (OC)
Ambient Temperature (*C)
Delta Tpd vs.#

v s . / of Outputs Switching
Tpd vs. Output Loading
Delta Tpd
Delta Loading Normalized
Normalized Icc vs. Vee
!cc YS. Vcc
10
10 1.3 3
V v :/
/ 12
12
- .-" V ....
.s
....'!!
"8.'
,/'
V
/
.ll
"0
1.1
1
L
2 o160,9
0.9
Z
L 008
.•
·2
V 0,77
Max.·8 Max.' 4 100
100 2 0 0
200 3 0 0
300 4.5 4 7 ".75
4.5 5 5 5 5 2 525
5 5.5
5.5
#of Outputs Output Loading Capacitance
Output Loading Capacitance (pf)
(p1) Supply
Supply Voltage
Voltage (V)
(V)
loL vs.
IOL VS. VOL
VOL
ION VS., _V_O_H_--,,--_
VON Normalized
250
250 .ISO . -_ _ _,--_IO_H_V_S _-, Normalized Icc
Ico vs.
vs. Temperature
Te m p e r a t u r e
T
1 I I
j-
--
S u n T..........
IceVS.T emp.... 1._
."',
200
200 12-P'..,-.-t---+-..; .....
U l i t n.
lab vs TM!peI"ature
76erwows0os
-100
:;(150 ".-- ·100 o 1.1 p-.c:t-""<:-t---+---i--t--+---t
1 •'? .l.! •••••
.s
-'
too
.Q1oo V l,··,
t. t--+--t--t--1r-..:.i-"':.!'.F.?''t---t
50
50 / .50
·50
....
.....
V
08
O't----j----t---t--__ir_--t---f---,
0.7+-_+-_-+_-+_......__1-_+-_-1
2 , 4
0.7
•56 . 2.2$
·5$ 5 0 0 2 52S S O
50 7 6
7& 1 0100
0 \25
VOL (V)
VOL (V) VOH (V)
VOH Ambient
Ambient Temperature
Te m p e r a t u r e (OC)
(.C)
2-80
2-80 4/91.Rev.A
4/91.1Rev.A
[JJ
Ii
LatUce®
L/Semiconductor
Lattice®
Semiconductor
Corporation
High
GAL26C1112
GAL26CV12
E2CMOS PLD
PLO
Generic Array Logic™
Generic Logic'

DIAGRAM
"'-" < C I I NINPUT

PUT
• HIGH PERFORMANCE ElCMOS·
E2CMOS' TECHNOLOGY
— 15 ns Maximum Propagation Delay
-15 -- 1 .,.,
-— Fmax == 62.5 MHz IFUT
—10ns Maximum from Clock Input
-10ns Input to Data Output
Output II)
-— TTL Compatible 8 mA Outputs aMc
.,.,
-— UltraMOS®
UltraMOS· Advanced CMOS Technology IFUT
• ACTIVE
ACTIVE PULL-UPS ON ALL PINS .,.,
N'UT
• LOW POWER CMOS
-— 90 mA
mA Typlcellcc
Typical icc .,.,
N'UT
• E2
E2 CELL TECHNOLOGY
-— Reconfigurable
logic
.,.,
N'UT
-100%
OLMC
IIQQ
-— High Speed Electrical Erasure (50ms) IFUT
-— 20 Year Data Retention •rimirtfi

.,.,
• TWELVE OUTPUT LOGIC MACROCELLS IFUT
-— Uses Standard 22V10 Macrocells

for Complex Logic
Logic Designs
.,.,
INPUT
• PRELOAD
PRELOAD AND POWER-ON RESET OF REGISTERS
-100%
— 100'3/0 Functional Testability INPUT "'"
• APPLICATIONS
-— DMA Control ....T "'"
-— High Speed Graphics Processing IIQQ
-— Standard Logic Speed Upgrade INPUT
• ELECTRONIC
INPUT "'"
DESCRIPTION
The GAL26CV12, at 15 ns maximum propagation delay time, time, PACKAGE DIAGRAMS

PACKAGE DIAGRAMS
combines a high performance CMOS process with with Electrically
Erasable (E2) floating gate technology to provide the highest per-
per- DIP
DIP
PlD available on the market. E2
formance 28 pin PLD E2 technology
technology of·
of-
fers high speed (50ms) erase times, providing the ability to
to repro·
repro- PLCC
PLCC LiCLK
gram or reconfigure the device quickly and efficiently. 1/0/0
1/0/0
By building on the popular 22V1

22V100 architecture, the GAL26CV12 0
Q Q :s 1/0/0
L/0/0
allows the designer to be immediately productive, eliminating the
the ---g-gg
Q Q 1/0/0
1/0/0
The generic architecture provides maximum de·
learning curve. The de- /A111111111211111128
1111111111 1/0/0
I/0/0
sign flexibility
flexibility by allowing the Output Logic
logic Macrocell (OLMC)
(OlMC)
1/0/0
to be configured by the user. TheThe GAL26C
GAl26CV12 \112 OlMC
OLMC is fully vo/O
I/0/0
1/0/0
compatible with the OlMC
OLMC in standard bipolar and
and CMOS 22V1
22 \1100 vcc Vee
Vc vOla
1/0/0
1/0/0
devices. GAL26CV12
GAL26CV1 2 GND
GND
1/0/0
reprogram mabie cells allow
allow complete
complete Top
Top View
View GNO vo/O
1/0/0
AC, DC, and functional testing during manufacture. As As aa result,

result, 1/0/0 vo/O
I/0/0
LATTICE is able to guarantee 100% field 1/0/0
field programmability and 1/0/0
V0/0
functionality of all GAL· LATTICE also guarantees 100
GAO products. LATTICE ---QQQQ
– – c o c a vOla
1/0/0
erase/rewrite cycles
cycles and data retention in
in excess of 20
20 years.
years. gggg
QQQQ 1/0/0
1/0/0
" -_ _----T" 1/0/0

1/0/0
copyright
Copyright C1991 Lattice Semlccnductor
01991 Lattice GAL and UkraMOS
CCIp. GAL
Semiconductor Corp. trademarks of lattice
UltraMOS are registered trademarks Lattice Semicondudor
Semiconductor Corp. Generic Array
Corp. Generic Array Logic
Logic and
and E'CMOS
PCMOS are
are trademarks oflattice
trademarks of Lattice
SemlcondUdor
Semiconductor Corp.
Corp. TTheh e opecWlcatlons herein are
specifications herein are subject
subJOd to
to change
change without
without notice.
notice.
LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124 U.S.A.
97124 U.S.A. April
April 1991.Rev.A
1991.1:lei/A
Tel. (503) 681-0118or
Tel. (503) 681-0118 or 1-800-FASTGAL; FAX (503)
1-800-FASTGAL; FAX (503) 681-3037
681-3037
2-81
2-81
fIJ
.1J
tatlioo"'
ILattice®
Semiconductor
SemiamqucWr
C o r p Corporation
oration
Specifications GAL26CV12
GAL26C1112
GAL26CV12 ORDERING INFORMATION

(ns)
Tpd (n5) Tsu (ns)
T5U (n5) Too (n5)
Tco (ns) icc (mA)
Icc Ordering ##
Ordering Package
Package
15 10 10
10 130
130 GAL26CV12-15LP
GAL26CV12-15LP 28-Pin Plastic
28-Pin Plastic DIP
DIP
130
130 GAL26CV12-15LJ
GAL26CV12-15LJ 28-Lead PLCC
28-Lead PLCC
20 12 12
12 130
130 GAL26CV12-20LP
GAL26CV12-20LP 28-Pin Plastic
28-Pin Plastic DIP
DIP
130
130 GAL26CV12-201—I
GAL26CV12-20LJ 28-Lead PLCC
28-Lead PLCC

Tpd (ns) Tsu (ns) Tco (ns) Icc
icc (mA) Ordering
Ordering # Package
Package
20 12
12 12
12 150
150 GAL26CV12-20LPI
GAL26CV 12-20LPI 28-Pin Plastic
28-Pin Plastic DIP
DIP
150
150 GAL26CV12-201_,J1
GAL26CV12-20lJI 28-Lead PlCC
28-lead PLCC
xxxxxxxx
XXXXXXXX -Xxx
X X X X
GAL26CV12 DDevice
e v i c e Name
Speed (ns)
(n5) ' - - - - - Grade
Grade B Blank
Commercial
II == Industrial
Industrial
L = Low Power PPower

ower ' - - - - - - Package
Package PP == Plastic DIP
DIP
J == PLCC
PLCC
2-82
2-82 4/91.Rev.A
4/91.Rev.A
I Ilia-Ike®
l i m d Semiconductor GAL26C1112
Corporation
The GAL26CV12 has a variable
variable number of
of product
product terms per The GAL26CV12
The GAL26CV12 has a product product term
term for
for Asynchronous
Asynchronous Reset
Reset
..J
OLMC. Of the twelve available OLMCs, two OLMCs have ac- (AR) and a product
(AR) product term
term for for Synchronous
Synchronous Preset
Preset (SP). These
(SP). These i'\
access
cess to twelve product terms (pins 20 and 22), two have access two product terms
two terms areare common
common to to all
all registered
registered OLMCs.
OLMCs. The
The
to ten product terms (pins 19 and 23), and the other six OLMCs Asynchronous
Asynchronous ResetReset setssets all
all registered
registered outputs
outputsto
tozero
zero any
anytime
time
have eight product terms each. In addition to the product terms this
this dedicated
dedicated product
product termterm isis asserted.
asserted. The
The Synchronous
Synchronous Preset
Preset
available for logic, each OLMC has anan additional product-term sets
sets all
all registers
registersto
to aa logic
logicone
oneon onthe
the rising
rising edge ofthe
edge of the next
next clock
clock
dedicated to output enable control. pulse after this
pulse this product
product term term is asserted.
asserted.
The output
output polarity
polarity of each
each OLMC
OLMC can be individually
individually pro- NOTE:
NOTE: The AR AR and
and SP
SP product
product terms
terms will
willforce the a
force the C)output
output of of
grammed to be true or inverting, in either combinatorial or reg- the
the flip-flop
flip-flop into the
the same state
state regardless
regardless of of the
the polarity
polarity of
of the
the
This allows each output to be individually config-
istered mode. This config- output.
output. Therefore,
Therefore, a reset
resetoperation,
operation,which
whichsets
setsthe
theregister
registeroutput
output
gured as either
either active high or active low. to
to a zero,
zero, may
may result
result in
in either aa high
high or
or low
low at
at the output
output pin,
pin,
depending
depending on on the
the pin
pin polarity
polarity chosen.
chosen.
Dim
• AR
1
D
44 TO
TO 11
Q
MUX
MU X
• CL K - a
•
SP
SP
22 TO
TO 11 t-------------'
MUX
MUX
GAL26CV12
GAL26C1/12 OUTPUT LOGIC
LOGIC MACROCELL (OLMC)
(OLMC)
OUTPUT LOGIC MACROCELL CONFIGURATIONS

Each of the
the Macrocells of the GAL26CV12 has two two primary func-
func- NOTE:
NOTE: In In registered
registered mode,
mode, thethe feedback
feedback is is from
from the /0 output
the /Q output
tional modes: registered, and combinatorialI/O.
combinatorial I/O. The modes and
and of
of the
the register,
register, and
and not
not from
from the
the pin;
pin; therefore,
therefore, a pin
pin defined
defined as
as
the output polarity are set by two bits (SO and 51),S1), which are registered
registered is is an
an output
output only,
only, and
and cannot
cannot bebe used
used for
for dynamic
dynamic
normally controlled by the logic
logic compiler. Each
Each of these
these two pri- VO,
I/O, as
as can
can the
the combinatorial
combinatorial pins.
pins.
mary modes, and the bit settings required to enable them, are are
described below and on the the following page. COMBINATORIAL 1/0
COMBINATORIAL I/O
In
Incombinatorial
combinatorial mode modethethe pin
pin associated
associated withwith ananindividual
individualOLMC
OLMC
REGISTERED is driven by
is driven by the
the output
output ofof the
the sum
sum term
term gate. Logic polarity
gate Logic polarity ofofthe
the
In registered mode the output pin associated with with an
an individual output
output signal at the the pin may be
pin may be selected
specifying that
that the
the
OLMC is driven by the a 0 output of that OLMC's OotypeD-type flip-flop.
flip-flop. output
output buffer
bufferdrive
drive either
eithertrue
true (active
(active high)
high) or
orinverted
inverted (active
(activelow).
low).
Logic polarity of the output signal at the pin may be selected by by Output
Output tri-state
tri-state control
control isis available
available asas an
an individual
individual product-term
product-term
specifying that the output buffer drive either true true (active high) for each
each output, and and may
may be be individually
individually setset byby the
the compiler
compiler as as
or inverted (active low). Output tri-state
tri-state control is available as as either
either ·on"
"on" (dedicated
(dedicated output),
output), "off"
"off" (dedicated
(dedicated input),
input), or
or"product-
"product-
an individual product-term for each OLMC, and can can therefore
therefore term
term driven" (dynamic
(dynamic I/O).
I/O). Feedback
Feedback into into the
theANDAND array
array isisfrom
from
be defined by a logic equation. The
The D 0 flip-flop's 10
/0 output is fed the
the pin
pin side of of the
the output
output enable
enable buffer.
buffer. Both
Both polarities
polarities (true
(true and
and
back into the AND array, with
with both the true
true and complement of inverted)
inverted) of the the pin
pin are
are fedfed back
back into
into the
the AND
AND array.
array.
the feedback available as inputs to the the AND array.
2-83 4/91.Rev.A
4/91.Rev.A
flJ
/L
.l.J
'Lattice
Lattice®
Semiconductor
SemiconducUJr
Corporation
Corporation
e
GAL26C1112
REGISTERED MODE
AIL
AR AR
o Q o 0
Q
• CU< •
• CLK •
1.1111
SP
SP SP
SP
ACTIVE LOW ACTIVE

ACTIVE HIGH
HIGH
So
so =0
= So=
So=1
1
S,
Si =0 S,
Si =0
=0
COMBINATORIAL MODE
ACTIVE LOW A C T I V EACTIVE HIGH

HIGH
So =
So = 0 =
So = 11
So
=
S, = 1 S,
S1=1 =
1
2-84
2-B4 4/91.Rev.A
4/91.1Revik
[JJ
'L 'Lattice
LLattice®
Semiconductor
Semiconductor
Corporation
Corporation
oo
GAL26C1112
GAL26C1/12
GAL26CV12 LOGIC DIAGRAM I/ JEDEC FUSE MAP
1 f>
4 2 6 3 2 4
28
RSTNCHRONOUS RESET
:ThIMIMIMIMIMIMIMINIMIMIIIM
oo. 0 0 ALL RESISTERS,
:iiEi•i-Eig,iii-iiE-iiii--!iiE-iiii-iigiiii-iiiagli-a-PIE -Vrille 27
9459iiiii illililliiillithilluilkilliimilialialla411 i 1 . I I
0123 iiit illi111111P111111111111INIM•Ill
-•:;-..e- so 26
:Liiiiiliiilliliiiliiiiiiiiiiiiiiiiiiiiiiiiiiiiiiffliil 6 3 0 S
630
9.9 M E M M O I M M M E M . M . M . M . M . P M M M
: = 9 . 6 . * . " . . . . . . . . A M I N .
so 25
4PIE i i 630
450 I N I I I I I I I M I M M I N I 1 1 1 1 1 1 1 1 1 1
• • 2 . . 6 9 6 6 , 4 = 9 ! : =
•
24
1972
! ! ! .
pip!! put hipilloptillmil • 11•

P R A M 1 1 . 0 1 1 0 . 1 1 1 1 1 M 1 1 1 ! W W I
1924
23
MEPM!RPMIMPUIIIUIIIUIIIUIIIUI IAIMU
22
Him
1;1= '1=i1 =111=i 1 mem i m I ini i
1III.=Jrrc--
3172 1111111•11101111111•11100111•111111EME!IU!! 0160000
So 20
6356
SI 20
3796 6357
9 _ _
—MEMEMIMPIPMEMIENIIMINRIPI1EI!
10
•••••••• !
9
19
'W.M.M.M.M.M.M.M.M.M.M.M.M
4420
i i I M H P W 4 1 1 = 1 M 1 1 1 . 5 1 1 P l i P i l i g i r a i i i E i R = M M N M I OUC 10
H:::lo-t---18
18
11Ellimmornumilinum
49 36
P P M ! •1111111111111101.1011M_
••• giumr770
__ • _ 17
12 011
MIIPMEP •MEM•M•H
••—•—• =.=.=:: • stuour—.1
• M O M iiiiIiiiIiii1I i i
- 16
13 6365
, 111111i11111 U 111111111111111111111111!II i
- • - • 15
0 6
SI
14 6367
8282 -Itti-tttt-ttlt--tItt-IItt-#!t--t/tl--tttt-tttI-tlift-t1f1t--iffl--ttlt---<>----- SVNCHRONOUSPRE8ET

S T R O T T O R O U S PRESET
(TOAlLREQlBTERSf
TO A011E043000
1I'6369.
I8,UU3 B. .3 0EtectronicSi;na1ure
3 0 9 3 4 ; 1 byre . 9 9 3 9 . 901
11Br1tIIBr1rSIa,.419r1131a,.
s•f. 21.".'
I82.1 tBraD
s.mo
i :
2-85
2-85 4/91.Rev.A
4/91.Rev.A
ILattice®
Semiconductor
e GAL26C1/12
C o r p CorporatiOn
oration Commercial
Commercial
COND.
Supply voltage
V cc ........................................ to ++7V
7V Commercial
Commercial Devices:
Input voltage
voltage applied - 2 . 5-2.5 to to Vee
Vcc 4-1 .0V Ambient Temperature
(TA) ............................. to +75°C
0 to +75°C
Input applied ...........•.•••.•.......... + 1.0V
Off-state output
output voltage
voltage applied
applied ..•........
- 2 .-2.55 to to Vcc +1.0V Supply voltage
(Vee)
Off-state Vee +1.0V
Storage Temperature - 6 5 -65 to to 150°C with Respect
with Respect to
to Ground
Ground .......•.............
+ 4 . 7+4.75 5 to to +5.25V
+5.25V
Storage Temperature .................................. 150°C
Ambient Temperature
Power Applied
Power Applied ........•..•..•........•......••...•.....
- 5 5 -55 to to 125°C
125°C
11.. Stresses above those listed under the· the "Absolute
Absolute Maximum
Maximum
Ratings· to the device.
device. These
These
the device
device
at these or at any other conditions above those those indicated in
the operational sections of this specification is is not implied
implied
(while programming,
OVer Otherwise Specified)
Specified)

CONDITION MIN.
MIN. TYR'
TYP." MAX.
MAX. UNITS
UNITS
VIL Input
Input Low Voltage Vss -0.5
Vss-O.5 -— 0.8
0.8 VV

2.0 -— Vcc+1
Vcc+1 VV
ILI
ilL' Input or I/O
110 Low Leakage Current OV VIN S5 Vit.
OVS5 VIN VIL (MAX.)
(MAX.) -— -— -100
-100 p.A
J.LA
IiH
IIH Input or I/O
110 High Leakage Current
Current 3.5V VIN _S•cVCC
3.5V _S_VIN Vee -— -— 10
10 J.LA
11.A
VOL
VOL Output Low Voltage lot, = MAX. YYin
10L= i n == VIL
Vii. or
or VIH
VIH -— -— 0.5
0.5 VV
VOH Output High Voltage Yin

loe = MAX. Vi
10H= n == VIL
VII. or VIH
or VIH 2.4
2.4 -— -— VV
10l
IOL Low level
Level Output Current -— -— 88 mA
mA
10H
IOH High Level
Level Output
Output Current -— -— -3.2
-3.2 mA
mA
los2
10S2 Output Short Circuit Current Vcc
Vcc =5V VOUT == 0.5V
= 5V VOUT TA =
0.5V TA = 25·C
25°C -50
-50 -— -135
-135 mA
mA
VIL = 0.5V VVIH
I H -3.0V
= 3.0V -— 90
90 130
130 mA
mA
ftoggie =
ftoggle Outputs Open
= 15Mhz Outputs Open.
1) The
The leakage current is due to the internal pull-up
pull-up on
on all
all pins. See
See Input Buffer section
section for
for more
more information.
information.
2) One output at a time for a maximum duration
duration of one
one second. Vout
Vout == 0.5V
0.5V was
was selected
selected to
to avoid
avoid test
test problems
problems caused
caused by
by
Guaranteed but
but not
not 100% tested.
tested.
Vee = 5V and TA =
3) Typical values are at Vcc = 25 ·C
'C
CAPACITANCE (TA
(TA = 2SoC, =
25°C, f1= 1.0 MHz) =
SYMBOL PARAMETER
PARAMETER MAXIMUM"
MAXIMUM* UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
C,
C, Input
pF Vee
Vcc == 5.0V.
5.0V. V,
V, == 2.0V
2.0V
C,,c,
C"" 110
I/O Capacitance 10
10 pF
PF Vee
\ice =- 5.0V. VIlO == 2.0V
5.0V, V,,,0 2.0V
""Guaranteed 100% tested.
tested.
2-86
2-86 4/91.Rev.A
4/91.1Rev.A
/llLattice
idLattice®·
.1..; Semiconductor
Semiconductor
Corporation
Corporation
GAL26CIl1 2
Commercial
Commercial
AC SWITCHING CHARACTERISTICS .
Conditions
-15
-15 -20
-20
PARAMETER
UNITS
CONE):
COND.' MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX.
tpd 11 Input or I/O
1/0 to Combinatorial Output
Output -— 15
15 -— 20
20 ns
ns

10 -— 12
12 ns
ns
tcf2 -— Clock to Feedback Delay -— 77 -— 10
10 ns
ns
tsu -— Time, Input or Feedback before Clocki

Setup lime, ClockT 10
10 -— 12
12 -— ns
ns
th -— Hold Time,
Clocki 00 -— 00 -— ns
ns
50 -— 41.6
41.6 -— MHz
MHz
1/{tsu + tco)
External Feedback, 1/(tsu
fmax33
58.8 -— 45.4
45.4 -— MHz
MHz
1/{tsu + tcf)
Internal Feedback, 1/(tsu tcf)
with 62.5
62.5 -— 62.5
62.5 -— MHz
MHz
No Feedback
twh4 -— Clock Pulse Duration, High 88 -— 88 -— ns

ns
twl4
tie -— Clock Pulse Duration, Low 88 -— 88 -— ns
ns
ten 2
2 Input or I/O to Output Enabled -— 15
15 -— 20
20 ns
ns
15 -— 20
20 ns
ns
to Asynchronous Reset of
of Register
Register -— 20
20 -— 20
20 ns
ns
10 -— 15
15 -— ns
ns
15 -— 15
15 -— ns
ns
tspr -— Synchronous Preset to ClockT
Clocki Recovery
Recovery lime
Time 10
10 -— 12
12 -— ns
ns
1) Refer
Refer to Switching Test Conditions section.
section.
2) Calculated
Calculated from to fmax
from fmax with internal feedback. Refer to fmax Description
section.
3) Refer
Refer to tmax
fmax Description section.
widths less than the specification may be detected as
as valid
valid clock
clock signals.
signals.
I,
I
2-87
2-87 4 / 9 1 . R e v . A
4/91.Rev.A
Lattice°
!IJ tattJooe
Semiconductor
SemiconducUJr
C o r p Corporation
oration
GAL26C1112
Industrial
Industrial
ABSOLUTE MAXIMUM RATINGSen
COND.
Vee ........................................ to +7V Industrial
Industrial Devices:
- 2 . 5-2.5 to to Vee
Vcc ++1.0V
1.0V
Ambient Temperature
Ambient Temperature (T(TA) - 4 0 -40 to
A) ••••••••••••••••••••••••••• to 85°C
85°C
Off-state output voltage applied ...........- 2 .-2.5 5 to Vcc Supply voltage
(Vcc)
Ott-state Vee +1.0V
- 6 5 -65 to 150°C with Respect
with Respect to
to Ground
Ground ......................
+ 4 . 5+4.50 0 to to +5.50V
+5.50V
- 5 5 -55 to 125°C
Power Applied .........................................
1.Stresses
1. Stresses above those listed under the the "Absolute
"Absolute Maximum
at these or
or' at any.
any pther
other conditions above those indicated in in
the operational sections of this
this specification
specification is not implied
follow the
the programming
programming specifications).
Specified)

CONDITION MIN.
MIN. TYR,
TYP." MAX.
MAX. UNITS
UNITS
VIL
VIL Input Low Voltage Vss – 0.5
Vss-O.5 -- 0.8
0.8 VV
VIH Input High Voltage

Voliage 2.0
2.0 -— Vcc+1
Vcc+l VV
I1L1
IlL' Input or I/O
110 Low Leakage Current OV VIN $5 V1L
OV$V1N VIL (MAX.)
(MAX.) -— -— -100
–100 p.A
IIH
illl 1/0 High Leakage Current
Input or I/O 3.5V
3.5V $5 VIN
Vs 5_ Vcc
$ \IOC -— -— 10
10 RA
VOL Output Low

Low Voltage lot_ - MAX. VYin
10L= i n = Vii_
VIL or VIH
or V1H -— -— 0.5
0.5 VV
VOH Output Hign

High Voltage
Voltage loH = MAX.
10H= MAX. Vi
Yinn = V'L
Vii. or
or V1H
V'H 2.4
2.4 -— -— VV
10L
IOL Low Level Output Current -— -— 88 mA
mA
10H
–3.2 mA
mA
los·
10S2 Output Short
Short Circuit
Circuit Current Vcc =5V
Vee = 5V VOUT = 0.5V
VOUT = 0.5V TA
TA == 25°C
25°C -50
–50 -— -135
–135 mA
mA
ICC Operating Power Supply Current VIL
VIL = O.SV
0.5V VVIH =3.0V
IH = 3.0V -— 90
90 150
150 mA
mA
ftoggle
ftoggle =- 1SMhz Outputs Open
15Mhz Outputs Open
1) The
The leakage current is due toto the internal pull-up
pull-up on
on all pins.
pins. See
See Input
Input Buffer section
section for
for more
more information.
information.
2) One output at a time for aa maximum duration of oneone second. Vout
Vout == O.SV
0.5V was
was selected
selected to
to avoid
avoid test
test problems
problems caused
caused by
by
Guaranteed but
tested.
3) Typical values are at Vcc = SV
5V and TA == 25°C
25 *C
CAPACITANCE (TA
(TA = 25°C, =
25°C, ft = 1.0 MHz)
MHz) =
MAXIMUM* UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
C,
C, Input
pF Vee
Vcc == S.OV, V, =
5.0V, V, = 2.0V
2.0V
Cuo
Coo 110 Capacitance
I/O Capacitance 10
10 pF
pF Vee
Vcc == 5.0V, \cc =
5.0V, V,/O = 2.0V
2.0V
"Guaranteed
2-88
2-88 4191.Rev.A
4/91.Rev.A
Ii
[J;l
.l.J
lxlttiooe
idLattice®Semiconductor
Semiconductor
Corporation
GAL26C1112
Industrial
Industrial
!
Over
TEST
-20
-20
UNITS
COND.' MIN. MAX.
MIN. MAX.
tpd 11 Input or I/O
Input I/0 to
to Combinatorial Output
Output -— 20
20 ns
ns
12 ns
ns
Clock to -— 10
10 ns
ns
before Clocki
Clocki 12
12 -— ns
ns
th -— Hold Time,
Clocki 00 -— ns
ns
41.6 -— MHz
MHz
tco)
f max'3
45.4 -— MHz
MHz
tcf)
with 62.5
62.5 -— MHz
MHz
No Feedback
twh4
twh -— Clock Pulse Duration, High 88 -— ns
ns
twt'
ns
ten 2 Input or 110
I/0 to
to Output Enabled -— 20
20 ns
ns
tdis 3 Input or 1/0
I/0 to Output Disabled -— 20
20 ns
ns
tar 1 Input or VO
I/0 to Asynchronous
Asynchronous Reset of
of Register
Register -— 25
25 ns
ns
15 -— ns
ns
tarr - Asynchronous Reset to
15 -— ns
ns
tspr -— Synchronous Preset to
to Clocki Recovery
Recovery lime
Time 12
12 -— ns
ns

section.
2) Calculated
Calculated from fmax with internal feedback.
feedback. Refer to
section.
3) Refer to fmax
fn.= Description section.
section.
as valid clock
clock signals.
signals.
2-89
2-89 4/91.Rev.A
4/91.Rev.A
Lattke® GAL26C1112
Semiconductor
Corporation
SWITCHING WAVEFORMS
INPUTor
INPUT or
\\\\\\\\\["'''"M
INPUTor
INPUT
VALIDINPUT VOFEEDBACK
110 FEEDBACK
VOFEEDBACK
110 FEEDBACK
4-ts u th
4-tpd -10
CLK
ClK
COMBINATORIAL
COMBINATORIAL
OUTPUT
OUTPUT \\\\\\\\S\\S\-s= : REGISTERED
REGISTERED
c0
OUTPUT
OUTPUT
4 1 - 1 / fmax
(external tdbk)
Reg Istered Output

Registered Output
INPUTor
INPUT or
VOFEEDBACK
110 FEEDBACK
4-too -01.
OUTPUT
OUTPUT
ClK
CLK
11 fmax (intorno!
41-1/tmax (Internal idbk)
fdbk) -Om
Input or I/O
1/0 to Output EnablelDlsable
Enable/Disable 11--- tot 0 4 t s o
REGISTERED
REGISTERED
FEEDBACK
FEEDBACK
fmax
fmax with
with Feedback
Feedback
4 - - tw h t w twlI — 4
ClK
CLK
Clock Width
INPUT
INPUTor
or
VOFEEDBACK
VO FEEDBACK
DRIVING
DRIVING SP
SP
INPUT
INPUTor
0/
VOFEEDBACK
VOFEEDBACK ClK
CLK
DRIVINGAR
DRIVINGAR
REGISTERED
REGISTERED
tarw tau* REGISTERED
REGISTERED
OUTPUT
OUTPUT \\\\\\\\\\\\\\
OUTPUT
OUTPUT
Synchronous
Synchronous Preset
Preset
4 1 — tar
ClK
CLK
Asynchronous Resat
Reset
2-90 4/91.Rev.A
4/91.Rev.A
.1.J
I i Slejecond°uctor°
SemioonducUJr
GAL26C1/12
C o r p Corporation
oration
fmax SPECIFICATIONS
CLK
ClK CLK
CLK
.J
··................................ -_ ..._......... _...............
· . LOGC
I
LOGIC V
lOGIC
111'REGISTER ARRAY
ARRAY
ARRAY REGISTER
REGISTER
·................................................................... _...
.. ••
... -...... -........................................................... .
tct
with External Feedback 1/(tsu+tco)
fmax with
tpd o l
Note: fmax with external feedback
with extemal feedback is cal-
cal-
tco.
culated from measured tsu and teo.
fmax
fmax with
with Internal
internal Feedback
1/(tsu+tcl)
CLK
ClK Note:
Note: teftcf is
is aa calculated
calculated value,
value, derived
derived by by sub-
sub-
................ _... __ ........................................... .
·· . ..
tracting
tracting tsu
tsu from
from the
the period
period of of fmax
f max wlintemal
wiinternal
....
feedback (tef
feedback (tcf -- 1lfmax
lifmax -- tsu).
tsu). The
The value
valueofof tef
tcf
·· LOGIC
isis used
used primarily
primarily when
when calculating
calculatingthe thedelay
delayfrom
from
i. LOGIC
ARRAY
ARRAY - O p p
REGISTER
REGISTER i. clocking
clocking a register
register to to aa combinatorial
combinatorial oUtput output
(through
(through registered
shownabove
above.•
.For
For example,
example, the the timing
timing from
from clock
clock to to aa com-
com-
·......................................................................... binatorial
binatorial output
output is is equal
equal to tcf ++ tpd.
to tef tpd.
Note: fmax with
with no feedback may be
litwh + twl. This is
less than 1ltwh is to
to allow for
for
a clock duty cycle of other than 50%.

GND to 3.0V +5V
Times 3ns
3ns 10%-90%
10% - 90%
Input liming
1.5V
Output liming
1.5V FROM
FROMOOUTPUT
UTPUT(QlQ)
(0/0) TEST
TESTPPOINT
OINT
Output Load See
See Figure UNDER
UNDERTTEST
EST
0.5V from
from steady-state active
level. R2

see figure)
II ure
Test Condition RI
R1 Rz
R2 CL
CL
11 4700 3900
3900 50pF
50pF C INCLUDES
ClLINCLUDESJIG AND
JIGANDPPROBE
ROBETTOTAL
OTALCCAPACITANCE
APACITANCE
2 Active High 00
00 3900
3900 50pF
50pF
Active Low
3900 50pF
50pF
3
3 Active
Active High 0.
00 3900
3900 5pF
5pF
3900 5pF
5pF
2-91
2-91 4 1 9 1 . R e v 4191.Rev.A
. A
LILattice
Semiconductor' GAL26C1112
.l..J Corporation
Corporation

An electronic signature (ES)

(ES) is provided in every GAL26CV12 When
When testing
testing state
state machine
machinedesigns,
designs, all
all possible
possible states
statesand
andstate
state
device. ItIt contains 64 bits of reprogram mabie
mable memory that
that can
can transitions
transitions must must bebeverified
verified in
in the
the design, notjust
design, not justthose
those required
required
contain user-defined data. SomeSome uses include user 10
ID codes, inthe
in the normal
normal machine
machineoperations.
operations. ThisThis is
is because
becausecertain
certainevents
events
revision numbers, or inventory control. The The signature data
data is
is may
may oocur
occur during systemsystem operation
operation that
that throw
throwthe
the logic
logicinto
into an
an
always available to the user independent of the state of the illegal
(power-up, line line voltage
voltage glitches,
brown-outs, etc.).
etc.).
security cell.
cell. To
To test
test aa design
design forfor proper
propertreatment
treatment of ofthese
these conditions,
conditions, aaway
way
must
must be provided
breakthe the feedback
feedback paths,
paths, and
and force
force any
any
desired
desired (i.e.,
(i.e., illegal)
illegal)state
state into
into the
the registers. Then the
registers. Then themachine
machine
SECURITY CELL can
can be be sequenced
the outputs
outputs tested
tested for
for correct
correct next
next state
state
conditions.
conditions.
A security cell is provided in every GAL26CV12 device to to pre-
pre-
vent unauthorized copying of the array patterns. Once Once pro- The
The GAL26CV12
GAL26CV12 device
device includes
includes circuitry
circuitrythat
that allows
allows each
eachreg-
reg-
read access to
grammed, this cell prevents further read to the
the functional
functional istered output to
istered output to be
be synchronously
either high
high or or low. Thus,
low. Thus,
bits in the device. This
This cell can
can only
only be erased by re-program- any
any present
present state
state condition
condition can
can be
be forced
forced for
for test
test sequencing.
sequencing.
ming the device, so the
the original
original configuration can never bebe ex- ifIf necessary,
necessary, approved
approved GALGAL programmers
programmers capable
capable of of execut-
execut-
amined once this cell is programmed. The The Electronic Signature ing
ing test
test vectors
vectors perform
perform output
output register
register preload
automatically.
is always available to the user, regardless of the state
state of
of this
this
control cell.
INPUT BUFFERS
LATCH-UP PROTECTION
GAL26CV12
GAL26CV12devices
devicesare
aredesigned withTTl
designed with TTLlevel
levelcompatible
compatibleinput
input
highimpedance,
impedance,
GAL26CV12 devices are designed with an on-board charge charge
and
and present a much
much lighter
lighter load
load to
to the
the driving
driving logic
logic much
much less
less
pump to negatively
negatively bias
bias the
the substrate. The negative bias is of
of
than
than bipolar TTL
TTL logic.
logic.
sufficient magnitude to prevent input undershoots from causing
the circuitry to latch. Additionally,
outputs are designed with n-
n-
channel pullups instead of the traditional p-channel pullups to The
The input
input andand I/O pins
pins also
also have
have built-in
built-in active
active pull-ups.
pull-ups. As aa
to
eliminate any possibility of SCA
result,
result, floating
floating inputs
inputs will floatto
will float to aaTTL
TTL high
high(logic
(logic 1). However,
1). However,
SCR induced latching.
Lattice
Lattice recOmmends
recommendsthat that all
all unused
unused inputs
inputs and
andtri-stated
tri-stated 110
I/Opins
pins
be
be connected
connected to to an
an adjacent
adjacent active
active input,
input, Vee,
Vcc, or or ground.
ground. Do- Do-
ing
ing so
so will
will tend
tend to
to improve
improve noise
noise immunity
reduce Icc I = for
forthe
the
DEVICE PROGRAMMING device.
device.
GAL devices are programmed using a Lattice-approved Logic Logic

number of
Programmer, available from a number of manufacturers (see the
the Typical
Typical Input
Input CUrrent
Current
the GAL Development Tools
Tools section). Complete
of the device takes only a few
few seconds. EraSing
Erasing of
of the
the device
is transparent
transparent to the user, and is done automatically asas part
part of
of /"
the programming cycle. ./
-20
/'
/"
U. -40
-60
-60
o0 1 1.0
0 2 . 2.0
0 3 3.0
0 4 . 4.0
0 5.0
50
Input
Input Voltag'
Voltage (Voltl)
(Volts)
2-92
2-92 4191.Aev.A
4/91.Rev.A
[JJ
.l.J
:LaUiOOC
Lattices
Semiconductor
Semioonduewr
Corporation
GAL26C1112
POWER-UP RESET
Va:
Vcc
OV
OV / 7
4 - tpr—O.
V IH
V IN E s z s ......
rT"T"T"rh'TT"T'T" v II,.--------
CLK
CU( VALIDCLOCK
VAUD CLOCKSIGNAL
SIGNAL
VIL
V IL ...l...I...l..I-+'-'L...L.l.J..l..lI,'-_ _ _ _ _ _ __
tress ---110.
INTERNAL
INTERNAL INTERNALREGISTER
INTERNAL REGISTER
REGISTER
REGISTER RESETTO
RESET TOLOGIC
LOGIC00
Q-OUTPUT
0-OUTPUT
OUTPUT
ACTIVELOW
ACTIVE
OUTPUTREGISTER
LOW
REGISTER v
ACTIVE HIGH
ACTIVEHIGH
OUTPUT REGISTER
OUTPUTREGISTER
Circuitry within the GAL26CV12 provides a reset

reset signal
signal to
to all
all reg-
reg- must
must bebe met
met to guarantee
guarantee a valid
valid power-up
power-up resetreset of the
the
isters during power-up. All
All internal
internal registers will have their Q GAL26CV12.
GAL26CV12. First, First. the
the V cc rise
Vc, rise must
must be
be monotonic. Second.
monotonic. Second,
outputs set low after a specified time (tRRESET' 45JLS MAX). This
ESET, 45).LS This the
the clock
clock input
input must
mustbecome properTIL
become aa proper TTLlevel
levelwithin
withinthe
thespeci-
speci-
feature can greatly simplify state machine design by providing
by providing fied
fied time (tp5,10Ons
(tPR • 100ns MAX). TheThe registers
registers will
will reset
reset within
within a maxi-
maxi-
a known state on power-up. mum
mumof!";sETtime.Asin
of tREss. time. As in normal
normalsystem
system operation.
operation,avoid
avoidclocking
clocking
the
thedevice
device until
until all
all input
inputand
andfeedback
feedbackpathpathsetup
setuplimes
timeshave
havebeen
been
The timing diagram for power-up is shown above. Because
Because ofof met.
met.
the asynchronous nature of system power-up,
power-up. some
some conditions
conditions
PIN I
PIN e>----f6=
>
Output
0.1.
Date
Flldb.ek
PIN
Vee ActvePull-up
Acive Pull-up
Actin Pul-up Cicuit
Citcult
(VroITypiell.3.2V)
Neer Types!. 3.2V) Circuit Vee •.. Y.....
........... .-.................
i
:
Vee: c: Vret
Tri•S late
Control
Vcc
I I Vr el
Viti
('Irel
(VrerTypieli. 3.2V)
Typical .3.2V)
:: ::
i CIIcI*
:
:
i
:........::
: : Oulpul
Output
PIN
: •• u .................... :
Dill
Data PIN
PIN
FIIcIIIck
(To InpuiBuIlar)
Input
Input Output
Output
2-93 4191.Rev.A
4/91.Fiev.A
[J;1:LaWcc
LILattice Semiconductor
Semironductor
Corporation
CorporaUon
e GAL26C1112
Normalized Tpd YS
NormaUzed vs. Voc
Vee Nomalized Tsu vs. Vcc
Normalized Tsu YS. Vee Normalized TToo vs. Vee
Voo
I .3 1.3. ._ _-,-_ _--r_ _ _. -_ _,
1.3
1.3
1.2
Normalized CD VI.
2 12
1.2+----i---+---t---i 122
1 ........
...... .....
-
g 8 1.1
........... ....iil 1.1 m::-:---t---t---t-----j
E0.9
,
- "--
I
m
1
,
D.9+----+---f---i---i
°9
••••••••
..........
••••••••••••••••
iJ:j.n 11
1i
Z
L.8
0 09
0.1 Pt H
'T •x•L
H.,.L t-
-
0.8 .•HHlr 0.8
06
I·····
•••••••• P T L. H
Il····· PTH·.L
P T L PT. L-:.oH
H
07 1 P T 11 . .
J
0.7
4.75
4.75 5 5 5 2 S.2!5
Supply Voltage (V)
5 ...55 0.7
4.5
4.5 4 75
4.75 5 5. 2 55.25 5.5
5.5
0.7
0.7
4 . 54.5 4 7 4.75
5 5 5 5 2 5.25
5 5.5
5.5
Supply Voltage
S\4lPly Voltage (V)
(V) Supply Voltage
Supply Voltage (V)
(V)
.. 3
Normalized Tpd vs. Temperature
Normalizad
1.3
'.3
Normalized TTsu
Normalized vs. T
su lIS. Temperature
emperalura
13
1.3
Normalized Teo
Normalized TooVI.
vs. Temperalure
Temperature
1.2 :/ 12
,...
..,. V
'.2 1.2 1.2
"8. •.• 1.1 ./

V 8 •.•1
V l/
l-
L
V'
1'
T'a ./
I60.9· ,
2 o.09
t ./
V 2 0.9 ./
V To
.L.
V
IV V
Z
0.8
D. ..I
0.8 V 0.8
0.'
o.0.7
7 0.7
0.7 0.7
0.1
-50
-SO .25
·25 0 0 2 52S 5 050 7 575 100
100 125
125 ..ss
-55 .25
-25 0 0 2 525 5 0so 7 575 1 0100
0 125
125 -55
-55 . 2·25
5 0 0 2 525 5 050 7 5
75 100
100 125
125
Ambient Tempe ature (OC)
Temperalure ( C) Arnbient Temperature
Ambienl Temperature (OC)
CC) Ambient Temperature
Ambient Temperature (OC)
(CC)
Della Tpd ...

Oeha vs. 11t of
of Outputs
Outputs Switching
s..nching
Delta Tpd
Oehe Tpd VI.
vs. Output
Output Loading
Loading Normalized lee
Normalizad !cclIS.
vs. Vee
Vcc
0 .010 13
1.3
v L 12
V V
12
.. , ..... /'
V
5111.., V
---- !
"8.4
I-
V . /
:g 2
d 2 / 1zE0o. 9
o t
/' 05
0.8
V
-3
M .... ••
htax. •
•ir of Outputs
.... ••• Mo,.
·2
0 1 0 0100 2 0 200
0 3 0 300
0
Loading Capacitance
Output Loading
OutpoA Capacitance (pi)
(p()
400
o.07.7
44.5
.• 475
4.75 5
Suppty
5
Supply Vohage
Voltage (V)
(V)
5 . 2 5.25
5 ...5.5
loL vs.
IOl YS. VOL
VOL .,.1.. 1OH vs. VOH
50. -_ _--r_I_O_H_VS.,._V_O_H_..._ _- . Normalized k::c
Normalized vs. Temperature
!cc VI. Temperature
250 12
I
200
12 ....
e • • • cklc
c va.
vt, T-,,*Mln
Te m p e r a . *
I t s va.
lab 31. TTempetatare
.............
1§
.too
"00 i"'o,..---+----t---t----1 II8 1,.,1
,
"' ...
'
i"o..
.
8
1 ...........
. ...,,- -60+----+---""'d---t----1
40 2 .•
09
" ....••••.„.....
/
0.'
09
•.077
2 22 45 - 2-25
·&5 5 so 7 5
0 0 2 52S S O 75 1 0100
0 125
125
VOL
VOL (V) VOH(V)
VON(V) Ambient
Ambient Temperature
Temperature (OC)
(cC)
2-94 4191.Rev.A
4/91.Rev.A
!llLatUce
1..1
Lattice®
Semiconductor
SemiconduGUJr
Corporation
Corporation
s
High-Speed Asynchronous E2CMOS
High-Speed
FUNCTIONAL BLOCK
FUNCTIONAL
E2CMOS PLD
Generic Array
Generic
BLOCK DIAGRAM
DIAGRAM
PLD
GAL20RA10
GAL2ORA1 0
Array Logic1'M
LogicTm
FEATURES
• HIGH
HIGH PERFORMANCE ElCMOS·
E2CMOSI TECHNOLOGY
— 12 ns Maximum Propagation Delay
-12 Delay /PL 0
-— Fmax ==71.4 MHz I

-— 12 ns Maximum from Clock Input to Data Output
-— TTL Compatible 8 rnA
mA Outputs INPUT 0 - - 0 =
INPUT
-— UttraMOS°
UHraMOS- Advanced
Advanced CMOS Technology
• 50% to 75•Y•
75% REDUCTION IN POWER FROM BIPOLAR - E
INPUT 0 - 1 - 8 —
INPUT
-— 75mA
75rnA Typ Icc
• ACTIVE PULL-UPS ON ALL PINS
INPUT D - - - C 1 —
INPUT I......'I-C!-..,.....O LOIQ
• E'
E2 CELL TECHNOLOGY
-— Reconfigurable
Reconflgurable logic
Logic
-100%
INPUT 0 - - C =
INPUT =l....
-— High Speed Electrical Erasure «50
(<50 ms)
ms)
-— 20 Year Data
Data Retention INPUT
INPUT 0 - - - C f
• TEN OUTPUT LOGIC MACROCELLS

MACRO CELLS
-Independent
— Independent Programmable Clocks INPUT
INPUT
-— independent
Independent Asynchronous Reset and Preset
-— Registered or Combinatorial wHh
with Polarity
-— Full Function and Parametric Compatibility with
with INPUT
INPUT
PAL20RA10
PAL2ORA10
• PRELOAD
PRELOAD AND POWER-ON RESET OF ALL REGISTERS
REGISTERS INPUT
INPUT
-100%
— 100% Functional TestabllHy
Testability
• APPLICATIONS
APPUCATIONS INCLUDE: INPUT
INPUT
-— Standard Logic
logic Consolidation
-— Multiple
MuHlple Clock logic
Logic Designs INPUT
INPUT a r - - D 1......'t-C'""r"iO IIOoQ

a /OE
DESCRIPTION
PIN
PIN CONFIGURATION
CONFIGURATION
The GAL20RA
GAL20IRA10 10 combines a high performance CMOS process
with electrically erasable (E2)
(f?) floati{lg
floating gate technology toto provide
provide
the highest speed performance available in the PLD PlD market. DIP
DIP
Lattice's E2CMOS
!?CMOS circuitry achieves power levels as as low as 75mA
typical fccwhich
Icc which represents a substantial
substantial savings in power when
when
PLCC
PLCC
compared to bipolar counterparts.
counterparts. E E2' technology offers high /PL Vee
speed (<50ms)
(<SOms) erase times providing the ability to reprogram, I/0IO
reconfigure or test the devices quickly and efficiently.
...
II: 1 IIO/Q
/7: - 2 E
8 21
The generic architecture provides maximum design flexibility by I/0IO
by I C VOIQ
80/0
allowing the Output logic
Logic Macrocell (OlMC)
(OLMC) to
to be
be configured
configured by VOIQ
3 1/0/0 I/0IO
the user. The
The GAL2ORA10
GAL20RA 10 is a direct parametric compatible E '010
1 I/0/0 I/0IO
GAL20RA10
GAL2011A10
CMOS replacement for for the PAL20RA 10 device.
the PAL20RA10 N C NC I NC
I NC I/0IO
t
Top View
Top View 3 8VOIQ
0/0
complete I IIOIQ
VOIQ
311010
AC,DC, and functional testing during manufacturing. Therefore,
Therefore, I/0IO
E ) VOIQ
11010
LAmCE
LATTICE guarantees 100% field programmability and functionality
of all GAL products. LATTICE
LATTICE also guarantees 100 erase/rewrite
cycles and that data retention exceeds 20 years.
I
. ..
z
0
(!
Il0l0
I/O/Q
GND
GNO /OE
Ccpyright
Copyright 01991 Semiconductor Corp.
01991 Lattice Semiconductor Corp. GGAl.
A L E'CMOS
PCMOS andand UltraMOS
UltraMOS are
are regllta...,
registered _trademarks 01 Lattice SamiconductDfCorp.
of Laniel Generic Alray
Semiconductor Corp Generic Logic Isis aa trademark
Array Logic trademark 01
ofLanice
Lattice
Serricondu_
Semiconductor Corp. PAPAL Is a reglsle""
L is registered trademark of Advanced
trademark 01 Micro DavIces.
Advanced Mitro Devices, Inc. The specifications and
The spocIIcatlons and Inlormalion
information herein
herein are
are subject
subject to
to change
change wRhout
without notice.
notice.

LATTICE SEMICONDUCTOR CORP., 5555
5555 N.E.
N.E. Moore Ct., Hillsboro,
Moore Ct., Hillsboro, Oregon
Oregon 97124,
97124, U.S.A.
l 1991.Rev.B
1991•Rev.13
Tel. (503) 681-0118;
Tel. (503) 681-0118; 1-800-FASTGAL;
1-800-FASTGAL; FAX
FAX (503)
(503) 681-3037
681-3037
2-95
2-95
[]JLattioo
Lattice°
Semiconductor
I n d ISemiconductor
Caporation
Corporation
e
Specifications GAL20RA
GAL2ORA110
0
GAL2ORMO ORDERING
GAL20RA10 ORDERING INFORMATION
Tpd (ns) Tsu (ns) Tco (ns)

Teo icc (mA)
Icc Ordering ##
Ordering Package
Package
12
12 44 12
12 100
100 GAL20RA 10-12LP
GAL2ORA10-12LP 24-Pin
24-Pin Plastic
Plastic DIP
DIP
100
100 GAL20RA 10-12W
GAL2ORA10-12LJ 28-Lead
28-Lead PLCC
PLCC
15 7 15
15 100
100 GAL20RA 10-15LP
24-Pin Plastic
Plastic DIP
DIP
100
100 GAL20RA10-15W
GAL2ORA10-151-1 28-Lead
28-Lead PLCC
P LCC
20 10 20 100
100 GAL2ORA10-20LP
GAL20RA 10-20LP 24-Pin
24-Pin Plastic
Plastic DIP
DIP
100
100 GAL20RA 10-20W
28-Lead PLCC
PLCC
30 20
20 30
30 100
100 GAL20RA 1O-3OLP
24-Pin Plastic
Plastic DIP
DIP
100
100 GAL20RA 1O-3OW
28-Lead PLCC
PLCC
Tpd (ns) Tsu (ns) Tco (ns)

Teo Icc (mA) Ordering #
Ordering Package
Package
20 10
10 20
20 120
120 GAL20RA 10-20LPI
GAL2ORA10-20LPI 24-Pin
24-Pin Plastic
Plastic DIP
DIP
120
120 GAL20RA 1O-20LJI
GAL2ORA10-20LII 28-Lead
28-Lead PLCC
PLCC
X XX XX X
XXXXXXXX -XXX X
GAL2ORA10 DDevJee
GAL20RA10 e v i c e Name
Speed (ns) L...-_ _ _ Grade

Grade BBlank
Commercial
II = Industrial
Industrial
Power
L = Low Power Power L...-_ _ _ _ Package PP == Plastic
Package Plastic DIP
DIP
J == PLCC
2-96 4/91.Rev.B
4/91.1Rev.B
.l.Jd CorporaUon
i f i f f
Semiconductor
Corporation
Specifications GAL2ORA1
GAL20RA 100
OUTPUT LOGIC MACROCELL (OLMC) ASYNCHRONOUS RESET AND

AND PRESET
PRESET
The GAL2ORA10
GAl20RA10 consists
consists of
of 10
10 D
D flip-flops
flip-flops with
with individual
individual Each GAL20RA
Each GAL2ORA10 macrocell has
10 macrocell has an an independent
independent asynchronous
asynchronous
asynchronous programmable reset, preset and clock clock product reset and preset control
reset control product
product term. term. The reset and
The reset and preset
preset
terms. TheThe sum of four product terms and an Exclusive-OR product terms
product terms are
are level
level sensitive,
sensitive, andand will
will hold
hold the
the flip-flop
flip-flop in
in the
the
provide a programmable polarity D-inputto
D-input to each flip-flop. An
An reset or
reset or preset
preset state
state while
while the
the product
product termterm isis active
active independ-
independ-
output enable term combined with the dedicated output enable enable ent of
ent of the
the clock
clock or
orD-inputs.
D-inputs. It should
should be be noted
noted that
that the
the reset
reset and
and
pin provides tri-state control of each output. Each OLMC has a
Each OlMC preset term
preset term alter
alter the
the state
state of
ofthe
theflip-flop
flip-flop whose
whose output
output is is inverted
inverted
flip-flop bypass, allowing any combination of registered or com- by the
by the output
output buffer.
buffer. A reset
resetof
of the
theflip-flop
flip-flop will
will result
result inin the
the output
output
binatorial outputs. pin
pin becoming
becoming a logiclogic high
high and
and aa preset
preset will
will result
result inin aalogic
logic low.
low.
The GAL2ORA10
GAL20RA 10 has 10 dedicated input pins and 10 program-
110 pins, which can
mable I/O can be either
either inputs,
inputs, outputs, or dynamic
dynamic RESET PRESET
I RESET PRESET FUNCTION
FUNCTION
I/O. Each
Each pin has a unique path to
to the
the logic array. All
All macrocells
macrocells 00 00 Registered
Registered function
function of
of data
data product
product term
term
have the same type and number of data and and control product terms,
terms, 11 00 Reset register
Reset to "0"
register to "0" (device
(device pin
pin -= "1")
"1")
allowing the user to exchange IIOpin
I/O pin assignments without restric-
restric- 00 11 Preset register
Preset register to "1"
"1" (device pin =
(device pin = "0")
"0")
tion. 11 11 Register-bypass (combinatorial output)
Register-bypass (combinatorial output)
CLOCKS
INDEPENDENT PROGRAMMABLE CLOCKS CONTROL
COMBINATORIAL CONTROL
An independent clock control product term is provided for each each The
The register
register in
in each
each GAl20RA
GAL2ORA10 10 macrocell
macrocell may
may bebe bypassed
bypassed
GAl20RA
GAL2ORA10 10 macrocell. Data
Data is clocked into the flip-flop
flip-flop on the by
by asserting
asserting both
both the
the reset
reset and
and preset
preset product
productterms. While both
terms. While both
active edge of the clock product term. The
The use ofof individual
individual clock
clock product
product terms
terms are
are active
active the
theflip-flop
flip-flop is
is bypassed and thethe 0-
D- input
input
control product terms allow up up to
to ten
ten separate clocks. These These is
is presented
presented directly
directly totothe
the inverting
inverting output
output buffer.
buffer. This provides
provides
clocks can be derived from
from any pin or combination of of pins
pins and!
and/ the
the designer
designer thethe ability
ability to
to dynamically
dynamically configure
configure any
any macrocell
macrocell
or feedback from other flip-flops. Multiple
Multiple clock sources allow a as
as aacombinatorial
combinatorial output,
output, or ortotofix
fix the
the macrocell
macrocell asascombinatorial
combinatorial
number of asynchronous register functions to to be
be combined into only
only byby forcing
forcing both
both reset
reset and
and preset
preset product
productterms
terms active. Some
active. Some
a single GAL20RA1
GAL2ORA10. O. This
This allows the designer toto combine dis- dis- logic
logic compilers
compilers willwillconfigure
configure macrocells
macrocells as as registered
registered or
or com-
com-
crete logic functions into a single device. binatorial
binatorial based
based on on the
the logic
logic equations,
equations, others
others require
require the
the de-
de-
signer
signer toto force
force the
the reset
reset and
and preset
preset product
product terms
terms active
active for
for
PROGRAMMABLE POLARITY combinatorial
combinatorial macrocells.
macrocells.
The polarity of the D-input to each macrocell flip-flopflip-flop is individually
programmable to be active high or This is accomplished with
or low. This with PARALLEL
PARALLEL FLIP-FLOP PRELOAD
a programmable Exclusive-OR gate on on the D-input
D-input ofof each
each flip-
flip-
flop. While
While any
anyone The
The flip-flops
flip-flops of a GAl20RA
GAL2ORA10 10 can
can be be reset
reset oror preset
preset from
from the
the
one of the
the four logic function product terms are are
active the D-input to the flip-flop ,will 110
I/O pins
pins by
by applying
applying a logic
logic low
lowto
to the
the preload
preload pin
pin (1)
(1) and
and applying
applying
will be low if the
the Exclusive-OR
bit is set to zero(O)
zero(0) and high ifif the
the Exclusive-OR bit is set to to one(1
one(1). ). the
the desired
desired logic
logic level
level to each I/O
toeach pin. The 110
I/Opin. I/O pins
pins must
must remain
remain
It should be noted that the programmable polarity only valid
valid for
for the
the preload
preload setup
setup and
and hold
holdtime.
time. All 1 0 flip-flops
10 flip-flopsare
are reset
reset
only affects
affects the
data latched into the flip-flop on the active edge of the clock product or
or preset
preset during
during preload,
preload, independent
independent of of all
all other
otherOlMC
OLMC inputs.
inputs.
term. The
The reset, preset and preload will alter the the state
state of
of the
the flip-
flip-
flop independent AA logic low
low on
on anan I/O
I/O pin
pin during
during preload
preload will
will preset
preset the theflip-flop,
flip-flop,
independent of thethe state of programmable polarity bit. The The
ability to program the aa logic high
high will
will reset
reset the
the flip-flop.
flip-flop. The output
output of of any
any flip-flop
flip-flop to
to be
the active polarity of of the
the D-inputs can be be used
used
to reduce the total number of product terms used, by allowing the preloaded
preloaded mustmust be be disabled. Enabling the
disabled. Enabling the output
output during
during preload
preload
DeMorganization of the logic functions. This This logic reduction is will
will maintain thethe current
current logic
logic state.
state. ItIt should
should be be noted
noted thatthat the
the
accomplished by the logic compiler, and does does not require the the
preload
preload alters
alters the state of
the state of the
theflip-flop
flip-flop whose
whose output
output is is inverted
inverted by by
designer to define the polarity. the
the output
output buffer.
buffer. A reset ofthe
reset of theflip-flop
flip-flop will
will result
result inin the
the output
output pin
pin
becoming
becoming aa logic
logic high
high and
and aa preset
preset willwill result
result inin aa logic
logic low. Note
low. Note
that
that the
the common
common outputoutput enable
enable pin pin (13)
(13) will
will disable
disable all all 110
0 outputs
outputs
OUTPUT ENABLE of
of the
the GAl20RA
GAL2ORA10 10 when
when heldheld high.
high.
The output of each GAL2ORA10
GAl20RA 10 macrocell is controlled
controlled by the
"AND'ing" of an independent output enable product term term and a
common active low output enable pin(13). The The output is enabled
enabled
while the output enable product term is active and the output
enable pin(13) is low. This
This output control structure allows several
output enable alternatives.
2-97 4/91.Rev.B
4/91.Rev.B
L!Lattice°
Semiconductor GAL2ORA1
Specifications GAL20RA 100
Corporation
OUTPUT LOGIC
lOGIC MACROCELL
MACROCEll DIAGRAM
DIAGRAM
P1 1
E
AR
PL P D
D
Effi
> AP
XOR (n)
XOR
OUTPUT LOGIC
lOGIC MACROCELL CONFIGURATION (REGISTERED
MACROCEll CONFIGURATION (REGISTERED with
with POLARITY)
POLARITY)
PL t - - - - - - - - - - ,
oet-----I
AR
AR
P
PL D 1-----+-<
L P PO
o
Q C:1
> AP
XOR (n)
OUTPUT LOGIC
lOGIC MACROCELL
MACROCEll CONFIGURATION
CONFIGURATION (COMBINATORIAL
(COMBINATORIAL with
with POLARITY)
POLARITY)
XOR (n)
2-98 4/91.Rev.B
4/91.11ev.B
[fJ
.LJ
'LlltIiOOGl
Lattice®
Semiconductor
Semironductor
C o r p CorporaUon
oration
GAL2ORA10
GAL2ORM 0 LOGIC DIAGRAM

GAL20RA10
DIP
DIP (PLCC)
(PLCC) Package Pinouts
(2) ........
1 (2) (D -'"
::::: "" 0 44 8 12
12 16
16 20
20 24
24 28
28 32
32 36
36
PL
PL
0 -2EE-
2 (3)
(3) r--..
- 280
.... 280 1
EMIIESEMEREMEISSEEFEEFEEtil 5311 OLMC • 23
1
i M M U U M O M E M E M M I M M E S M . M . . ; 1 1 :
iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiirail
XOR • 3200 f2:ra 23(27)
23 (27)
320
rispramr.:E:=Fge:::=:::=Huspic:::==c1S OLMC • 22
I.J.-•-•••3 -a
D 222 ((26)
2 26)
-
(4) ........
3 (4)
600 :::=;:iiIIIESFERESIEHIEIIMISEME=z111
onol lommilioummu
n m
nomemulemogli: XOR ·3201 W
7 :1= :1: : =I :i =i i: i=i :i :i i: i= i: i:i:i=i i: i: i: i=i1i i1 M
640
640 ENVIL
: = = = = = • = •
••• OLMC . 21 I.:l -
- km-iiiiiiiii1Iiiiiiiiiiiiiiiiiiiiiiiiiimmill
sonsm••••••••••••••••••••••=•••mo•••••••••Cwwm 21
21 (25)
92 0 : = 1 3 : 2 1 1 1 2 : : = : : : = : : = : : = : : : = = • • • • •
(5) ........
4 (5)
820
moluni iniummonmemosummourimon XOR • 3202
uo Ei"OLMC
01101111016•11•••••1••••=••=0•EIMMIEM•E=MMMICONIMEI- • 20
• 0 0 111 • • • • = • • • • • • • • • • • • • • • • = m m a l l o m P l u i m m v • E m n i o •
o i m m • • • • • • • • • • • • • • m e . m m o m m m o n • m o n o m m e o= u Nl o Oo nMo
r.:lE -
D 220
0 ((24)
24)
1 1 1 : = : = = = = = = = : : : = : : = ! : = I I : = • • = C
55 (6)
(6) D
1240 nimilimmoll
1240 lommensmoomiu
m m meri n XOR • 3203
k—iiiiiiiiiiiiii Iiiiiiiiiiiiiiiiiiiiiill.
1280
1280
RESIEMELSEHEMERE:EL:•="lialinlEEBBE OLMC·19 """J - 1193 ((23)
6 (7)
(7) D
1560
: = = = = = = : : : o r a n r e : : = : : • • = : : = : : = CMS
nosm•••=••••••••mmono•••••••••••••••tomoontannum
momminninsegspanummumnimuunumali:
kalminsoossoasssossen . m ass sown mg!
D
XOR ·3204
-=.J- 23)
1600lom
1600 mummmilimimmimil -
-=.J -.... 1818(21)
0••••••••MOSMOOMMOIMM•INEMIIME••Strn••=1•111EMMOInn=>OLMC·18
10,100•NIMMMOMMIDEMOINDOOMMOMMIMEniemommemnello•m••••••••01mom0
r.:1 (21)
4 : = 11 : = : : = 1 : 1 = 1 : 11111 : = 1 : = 1 : 1 2 : : : = • • =
1880
1880
(9) D - 1 1 1 0 . oss1111•111•111•11111111119
7 (9) 11•111•1111•111•111611116711:
n i o s o l o s s o o s t s s e s s o m .sinsillsa XOR • 3205
H2O
1820 I I I I I I I I I I I I I I I I I I I I I iliiiiiii
- - - - - - - - - - - - - - - - - - - - . . . - - = . . . . >OLMC . 17
17
17 (20)
(20)
8 (10) .........
2200 -=:J
-
2200 i r n i i i i i M l i n n i M M E M E I I n U M M E I M M I N I :
klitilt=11MNIIIIIMINIME9111•011•1991•111 1 • 8 9 W I I I I E 1 1 0 X O 3206
R XOR •• 3 206
2240 1 1 1 1 1 1 1 1 1 1 1 1 1 11 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2240 1 1mo•me•monommo•mmEmnommimmoomnammenosn••••••••••all
•••••••••=0.0meamonalos•m•••=mononumnommom• = m a i '
MentiNan•BEIOMMIESEMENanallm•••MlowirmalowaMMaimi = O M
• • • • • • • • • • • • • • • • • • • • • • • • • M E I M a n n e • = 0 • 8 1 1 • • = 1 1 1 • 2 • 1 • M E I
a= OLMC . 16 r.:1 -a 1616(19)
(19)
2520 • • • • • • • • • • • • • m • • • • . . . . . . • • • • • • • • • • • • • • • • • . = •• •= •2• :•
: = : : : = : : : = : : : = = = 1 2 : : = : : = : : : : : : : = •
-=:J
9 ((11)
11 )
-
......... 111111111111111111111111111•111•111•1 111111111111111Elp11:
Italmossmosossonssossossmainessollsoss o l o o om
2560 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 M 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2560
s s 1 XOR ·3207
gymesome••••••••••••mm•Emt•Eam•Emi•••=•••••••9"Eama
U S H I E M E M E M E T H E M E M S E E E = E B E E - OLMC·15 r.:1
D -a 1155 ((18)
18)
........
: = = = = : : : E : : ire U M : i t = 0 = : : : = = = • • = 1 1
2840 euelmtedummoommommommoo•••••••••••••••••••••••••smonCommo
-=:J
10 (12)
(12)
- ilt•••111111•110muummuniummumminnummi lommtu:
111111111111•1111•111111111111111111111111111111111emis
2880 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I
2880 I l l i i l l i l l
XOR • 3208
•••.•••••=::=••••:-- P A C 1 4
OLMC·14 14
14 (17)
r > - 3160
11 (13)
- 3168
ka -
011111111111111011111110110111=—Ell0 L
A
'V
XOR • 3209
aC I 13 (16)
13(16)
E
64-USER ELECllIONIC SIGNATURE
64USER ELECTRONIC SIGNATUREFUSES
FUSES
3210, 3211.....
13210.3211 ..... •...•
... 3272,
3272, 32731
3273
Byte 71
Byte Byte66 .... B
7( Byte y t •... eByte 1111'Byte
Byte 00
MM LL
SS SS
BB BB
2-99 4 / 9 1 . 1 R e v 4/91.Rev.B
. B
LLattice®
Semiconductor
GAL2ORA1
Commercial
ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING
COND.
Vee ....................................... to +7V
+7V Commercial Devices:
Commercial Devices:
- 2 . 5-2.5 to Vcc +1.0V
Ambient Temperature (T(TA) 0
A) ••••••••••••••••••••••••••••• to++75°C
0 to 75°C
- 2 .-2.5
Off-state output voltage applied .......... 5 to to Vee
Vcc ++1.0V
1.0V Supply voltage
(Vcc)
- 6 5 -65 to to 150°C with Respect
with Respect to
to Ground
Ground ......................
+ 4 . 7+4.75 5 to to +5.25V
+5.25V
- 5 5 -55 to
"Absolute Maximum
Ratings'
damage to the device.
device. These
the device
device
at these or at any other conditions
conditions above
above those
those indicated in
in the
the
programming.
programming, follow
follow the
(Unless Otherwise
Specified)

CONDITION MIN.
MIN. TYp.a
TYR3 MAX.
MAX. UNITS
UNITS

Vss -0.5 -— 0.8
0.8 VV
2.0 -— VCC+1
VCC4-1 VV
IlL'
IlL1 Input or 110
I/O Low
Low Leakage
Leakage Current OV
OVSVIN
VIN _SVII_
VIL (MAX.)
(MAX.) -— -— -100
-100 1.1.A
J.lA
IIH Input or 110
I/O High Leakage Current 3.5V
3.5V S VIN _.
V1N S VCC
Vee -- -- 10
10 J.tA
RA
VOL Output Low
Low Voltage
Voltage lot_..- MAX. Vi
lot. Vinn ..= VIL
VII_or
or VIH
V1H -- -- 0.5
0.5 VV
VOH Output High Voltage IoH
loH ..
= MAX. yVin
i n ... VIL
VIL or VIH
or V1H 2.4
2.4 -— -— VV
10L
mA
-3.2 mA
mA
105
10S22 Output Short
Short Circuit
Circuit Current Vee-5V VOUT ..= 0.5V
Vcc = 5V VOUT TA ..
0.5V TA --.25°C
25°C -SO
-50 -— -135
-135 mA
mA
ICC Operating Power Supply
Supply Current VIL-0.5V
VIL = 0.5V VVIHI H -3.0V
= 3.0V -— 75
75 100
100 mA
mA
ftoggle
h o g & ..= 15Mhz Outputs
Outputs Open
Open
1) The leakage current is due to the internal pull-up resistor on
on all
all pins. See Input
Buffer section
section for
for more
mo e information.
information.
2) One output at a time for a maximum duration of oneone second. Vout ..= 0.5V
wasselected
selected to
to avoid
avoid test
test problems
problems caused
caused by
bytester
tester
Vcc ..
= 5V
5V and TA
TA ..
= 25°C
25 c•C
CAPACITANCE (TA 25 C, f =1 1.0

(TA = 25°C, . 0 MHz)
SYMBOL PARAMETER
PARAMETER MAXIMUM"
MAXIMUM* UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
C
C,I Input
pF Vee
N./cc-= 5.0V.
5.0V, V
V,I -= 2.0V
2.0V
Coc
CliO VO
I/0 Capacitance 10
10 pF
pF Vee"
Vc, = 5.0V.
5.0V, VIiO
Vuo'"=2.0V
2.0V
"Guaranteed but not 100°A,
100% tested.
2-100 4J91.Rev.B
4/91.Rev.B
Lattice® GAL2ORA1
10
LJ Semiconductor
SemiwnductiJr
Commercial E i l
Commercial
I
.,
Corporation
OVer Operating Conditions
Conditions
-12
-12 -15
-15 -20
-20 -30
-30
.J..
TEST DESCRIPTION
PARAMETER UNITS
UNITS
COND.' MIN. MAX.
MIN. MAX. MIN.
MIN. MAX.
MAX. MIN.
MIN. MAX.
MAX. MIN.
MIN. MAX.
MAX.
tpd 1 to Combinatorial
Input or I/O to Combinatorial Output -— 12
12 -— 15
15 -— 20
20 -— 30
30 ns
ns

12 -— 15
15 -— 20
20 -— 30
30 ns
ns
or Feedback before Clock
Clock 44 -— 77 -— 10
10 -— 20
20 -— ns
ns
th -— Hold Time, Input or Feedback after
after Clock
Clock 33 -
— 33 -— 33 -— 10
10 - — ns
ns
62.5 -— 45.0
45.0 -— 33.3
33.3 -— 20.0
20.0 -— MHz
MHz
tco)
frnax22
fmax
11 Maximum Clock Frequency without
without 71.4
71.4 -— 50.0
50.0 -— 41.7
41.7 -— 25.0
25.0 -— MHz
MHz
Feedback
twh33
twh -— High
Clock Pulse Duration, High 77 -— 10
10 -— 12
12 -— 20
20 -— ns
ns
twl
twP3 -
— Clock Pulse Duration, Low 77 -— 10
10 -— 12
12 -— 20
20 -— ns
ns
ten / tdis 2,3 Input or I/O to
to Output
Output Enabled / Disabled
Disabled -— 12
12 -— 15
15 -— 20
20 -— 30
30 ns
ns
ten / tdis 2,3 OE to
to Output
Output Enabled / Disabled -— 99 -— 12
12 -— 15
15 -— 20
20 ns
ns
tar / tap
tar/tap 11 Input or I/O to
to Asynchronous.
Asynchronous Reset // Preset
Preset -— 12
12 -— 15
15 -— 20
20 -— 30
30 ns
ns
tarw/tapw
tarw itapw -— Asynchronous Reset / Preset
Preset Pulse Duration
Duration 12
12 -— 15
15 -— 20
20 -— 20
20 -— ns
ns
tarr //tapr
tapr -— Asynchronous Reset / Preset Recovery
Recovery Time
Time 77 -— 10
10 -— 12
12 -— 20
20 -— ns
ns
twp -— Preload Pulse Duration 12
12 -— 15
15 -— 20
20 -— 30
30 -— ns
ns
tsp -— Preload Setup Time 77 -— 10
10 -— 15
15 -- 25
25 -- ns
ns
thp
thp -— Preload Hold
Hold Time 77 -— 10
10 -— 15
15 -. 25
25 -— ns
ns
1) Refer to Switching Test Conditions sectIOn.
section.
2) Refer to fmax
him( Descriptions section.
3) Clock pulses of widths less than the specification
specification may be detected as
as valid
valid clock
clock signals.
signals.
Input Pulse
Pulse. Levels GNDt03.0V
GND to 3.0V +5V
+5V
3ns 10% —90%
1.5V
1.5V
Output Load See
See Figure
are measured 0.5V
3-state levels are 0.5V from
from steady-state active FROM OUTPUT (0/0)
FROMOUTPUT (0/Q) - -.....- -.....-TESTPOINT
level. TESTPOINT
UNDER TEST
UNDERTEST
(see figure)
figure)
Test Condition
1
1
2
2 Active High
Active Low
—
R1
RI
4700
4700
00
4700
R2
R2
3900
3900
3900
3900
3900
3900
CL
CL
50DF
50pF
50pF
50pF
50pF
50pF
f'
3 Active
Active High 00
00 3900
3900 5pF
5pF
-
C
C llNClUOES
L INCLUDESJIG AND PROBE
JIGAND PROBE TOTAL
TOTALCAPACITANCE
CAPACITANCE
Active Low
Active Low 4700
4700 3900
3900 5pF
5pF
2-101 4/91.Rev.B
4/91.Rev.B
t Lattice°
Semiconductor
GAL2ORA1
Industrial
COND.
Supply voltage Vcc - 0 . 5 -o.5 to
Va; ....................................... to +7V industrial Devices:
Industrial Devices:
- 2 . 5-2.5 to to Vcc
Va; + +1.0V
(TA) ..........................
- 4 0 -40 to
to +85°C
+85°C
Off-state output voltage applied .......... - 2 .-2.5 5 to to Vcc
Va; + +1.0V
1.0V Supply voltage
Supply voltage (Va;l
(Vcc)
- 6
Storage Temperature ................................. 5 -65 to to 150°C with Respect
with Respect to
to Ground
Ground ......................
+ 4 . 5+4.50 0 toto +5.50V
+5.50V
- 5 5 -55 to
1.Stresses above those listed under the "Absolute "Absolute Maximum
Maximum
Ratings·
Ratings" may cause permanent damage damage to to the
the device. These
These
device
at these or at any other conditions
conditions above those those indicated
indicated in
in the
the
programming, follow
follow the
OVer
Over Recommended
Specified)

CONDITION MIN.
MIN. TYP."
TY12.3 MAX.
MAX. UNITS
UNITS
VIL
Vss -0.5 -— 0.8
0.8 VV
2.0 -— VCC+1
Vcc-t-1 VV
IILI
IlL' Input or I/O Low
Low Leakage
Leakage Current CVS5VI
OV NS5VI
VIN VILI_(MAX.)
(MAX.) -— -— -100
-100 11A
IlA
11H
IIH Input or 110
I/0 High Leakage Current 3.5V
3.5V sVIN
VIN .5 Vex;
S_VCC -— -— 10
10 IlA
1.111/4
VOL Output Low Voltage IoL

la_ '"- MAX. Yin
MAX. Vi n '". Vi
VIL
c_or
or VIH
VIH -— -— 0.5
0.5 VV
VOH Output High Voltage loR =
IoH - MAX. Vin
MAX. Vi n= VIL or
- VII_ or VIH
V1H 2.4
2.4 - -— VV
10L
mA
-3.2 mA
mA
los2
10S2 Output Short Circuit Current Va;.5V VOUT -= 0.5V
Vcc = 5V VOW- TA _= 25·C
0.5V TA 25"C -50
-50 -— -135
-135 mA
mA
ICC Operating Power
Power Supply
Supply Current VIL.0.5V
VIL = 0.5V VVIH=3.0V
I H = 3.0V -— 75
75 120
120 mA
mA
ftoggle
h o g & ..,- 15Mhz Outputs Open
15Mhz Outputs Open
1) The leakage current is due to to the
the internal pull-up resistor
resistor on
on all
all pins. See Input
Buffer section
section for
for more
more information.
information.
time for
for a maximum duration of of one
one second. Vout
Vout ..= 0.5V was
was selected
selected to
to avoid
avoid test
test problems
problems caused
caused by
bytester
tester
are at Vcc
Vex; ..
= 5V and TA TA ..= 25 ·C
'C
CAPACITANCE (TA 25 C, f 1 1.0

(TA = 25°C, =
. 0 MHz) =
MAXIMUM" UNITS
UNITS TEST
TESTCONDITIONS
CONDITIONS
C
CII Input
pF VVcc
cc '"= 5.0V,
5.0V, VI"
Vi - 2.0V
2.0V
Coo
Clio VO
I/O Capacitance 10
10 pF
pF VVcc
cc ..=5.0V,
5.0V, V
Vuo = 2.0V
110 = 2.0V
"Guaranteed but not 100% tested.
2-102
2-102 4/91.Rev.B
4/91.1Rev.B
I 1 LAMM® GAL2ORA1
z d t Semiconductor
Industrial I
Over Conditions
TEST
-20
-20
PARAMETER
UNITS
COND.,
COND.' MIN. MAX.
MIN. MAX.
to Combinatorial
Output -— 20
20 ns
ns
teo
20 ns
ns
tsu -— Setup Time, Input or Feedback before Clock
Clock 10
10 -— ns
ns
th -— Hold Time, Input or
or Feedback
Feedback after Clock 33 -— ns
ns
33.3 -— MHz
MHz
tco)
fmax22
fmax
1 Maximum Clock Frequency without 41.7
41.7 -— MHz
MHz
Feedback
twh
twh33 -— Clock Pulse Duration, High 12
12 -— ns
ns
twl
tw133 -- Clock Pulse Duration, Low 12
12 -— ns
ns
ten/tdis
tent tdis 2,3 Input or I/O
I/0 to
to Output
Output Enabled / Disabled
Disabled -— 20
20 ns
ns
-
ten / tdis 2,3 OE to
to Output
Output Enabled /I Disabled -— 15
15 ns
ns
tar/tap
tar /tap 1 Input or I/O to
to Asynchronous
Asynchronous Reset / Preset
Reset/Preset -— 20
20 ns
ns
tarw/tapw
tarw itapw -— Asynchronous Reset / Preset Pulse Duration 20
20 -— ns
ns
tarr /tapr
/ tapr -— Asynchronous Reset / Preset Recovery
Recovery Time 12
12 -— ns
ns
20 -— ns
ns
tsp -— Preload Setup Time 15
15 -— ns
ns
thp -— Preload Hold Time 15
15 -— ns
ns
1) Refer to Switching Teat
Test Conditions sectIOn.
section.
2) Refer to 'max
be detected
detected as
as valid
signals.

GND to 3.0V +5V
+5V
3ns 10"10
10% -– 90%
90%
1.5V
1.5V
Output Load See
See Figure
3·state
3-state levels are measured 0.5V from steady·state active
from steady-state FROM OUTPUT (010)
FROMOUTPUT (0/Q) TESTPOINT
POINT
level.
UNDER TEST
UNDERTEST
Teat
Test Condition
1
2 Active High
Active Low
R1
RI
4700
00
00
4700
Fb
R2
3900
3900
3900
3900
3900
3900
CL
CL
50pF
5013F
50pF
50pF
50pF
50pF
R.
f'
3 Active High 0.
00 3900
3900 5pF
5pF
-
C
CLlNCLUOESJIG
LINCLUDESJIGANDP
AND ROBET
PROBE OTALC
TOTAL APACITANCE
CAPACITANCE
Active Low 4700
470U 3900
3900 5pF
5pF
2-103
2-103 4 / 9 1 . R e v .4191.Rev.B
B
[JJ
1..J
'Ll1ttiOO
Semironductor
I d Illecottliu.
Corporation
CorporaUon
cto;
4D
GAL2ORAI0
SWITCHING WAVEFORMS
Input or
Input or - X Input or
Input or
I/O Feedback
110 Feedback I/O Feedback
I/O Feedback
tpd tsu th
Combinatorial Clock
Clock
Output
tc 0
Registered
Registered
CombinatorIal
Output
Output
Registered
Registered Output
Output
Input or Input
Input or
or
I/O Feedback
Feedback 110 Feedback
I/O Feedback
Asserting Preset
Preset Asserting Reset
Asserting Reset
Regis tered
Registered Registered
Registered
Output Output
Output
Clock ___XXXX1= Clock

Clock ___XXX5<k=
Asynchronous Preset Asynchronous Reset
Asynchronous Reset
Input or
or OEE
I/O Feedback
Feedback
tds en—) tcils e
Output
Device Output Device Output
Device Output
Input or I/O
I/O Feedback
Feedback to Enable
Enable I/ Disable O E OE to Enable
Enable I/ Disable
Disable
' t w h t w 1 t p
Clock
PL
P
tsp ---)14—t5r)
Clock Width
All Pins
All I/O Pins 0 3 . X
_ _ /
Parallel
Parallel Preload
Preload
2-104 4/91.Rev.B
4/91.13ev.B
[JJ
.lJ
Lattice®
:Lattice*
Semironductor
u . s ISemiconductor
Corporation
GAL2013A10
fmax DESCRIPTIONS
CLK
elK CL K
ClK
:
........................................................
: ................................................ --..
. .
:
LOGIC
lOGIC LOGIC
LOGIC
REGISTER
REGISTER REGISTER
REGISTER
A R R AY
ARRAY ARRAY
ARRAY
:........................................................ --= .................. -.............. -- ......................... -...................... :

1<11"'--- h t ..I -
t a u u - -.... o ---
o tc.--.t
fmax WHh
fmax With No
No Feedback
Feedback
fmax with Note: fmax
Note: fmax with no feedback
with no feedbackmay may be
be less
less
imax with
Note: fmax feedback is cal-
with external feedback cal- than litwh ++twl.
than 1ltwh This is
twl. This isto
toallow foraadock
allowfor deck
culated from measured tsutsu and teo.
tco. duty cycle
duty cycle of
of other
other than
than 50%.
50%.
outPut
Output _ _ _
PIN[ > Data
Dall V I PIN
PIN
Feedback ..
Vee
Vc c Active PuU·up
Active Pull-up
Active Put-up Circuit
Circuit
(Vrof Typical - 3.2V) Circuit
Vcc
.... +.. * .... (Vre'Ty_ _ 3.2V)
Tri-State
Trl·State V ret Wm! Typical 3 . 2 0 1
• - -
!'' 'I
Control
Control
Vcc Vrei V cc
Output
Output
Data
Data PIN
PIN
PIN
Feedback
(To Input Buller)
Input
input Output
Output
2-105 4/91.Rev.B
4/91.1Rev.13
idLattice®
Semiconductor
Semioonductor GAL2ORA1
Corporation
CorporaUon
ELECTRONIC SIGNATURE DEVICE PROGRAMMING

DEVICE PROGRAMMING
An electronic signature word is provided in in every
every GAL20RA
GALIORA10 10 GAL devices
GAL devices are
are programmed
programmed using using aa Lattice-approved
Lattice-approved Logic
Logic
device. I Itt contains 64 bits of reprogrammable
reprogram mabie memory that Programmer, available
from a number
numberof of manufacturers
manufacturers (see
(seethe
the
contains user defined data
data. Some
Some uses include useruser ID
ID codes,
codes, the GAL
the GAL Development
DevelopmentToolsTools section).
section). Complete
programmingof of
revision numbers, pattern identification or inventory control codes. the device
the device takes
takes only
only aa few
few seconds.
seconds. Erasing
Erasing ofofthe
the device
device isis
The signature data is always available to to the
the user independent transparent to
transparent tothe
the user,
user, and
and isis done
done automatically
automatically as aspart
part of
ofthe
the
of the state of the security cell. programming cycle.
programming cycle.
NOTE: The electronic signature bits ifif programmed
programmed to
to any
any value
value
other then zero(O)
zero(0) will alter the checksum of the device.
INPUT BUFFERS
INPUT
GA1.20RA
GAL2ORA10 10 devices
devices are
aredesigned
designed with
withTTL
TTLlevel
levelcompatible
compatibleinput
input
SECURITY CELL buffers.
buffers have
high impedance
impedance
and
and present
present aa much
much lighter
lighter load
loadto
tothe
thedriving
driving logic
logicthan
thantraditional
traditional
A security cell is provided in every GAL2ORA10
GAL20RA 10 devices as as a bipolar
bipolar devices.
devices.
deterrent to unauthorized copying of the device pattern. Once
pattern. Once
programmed, this cell prevents further
further read
read access of the
the device
device GA1.20RA
GAL20RA10 10 input
input buffers
buffers have
have active
active pull-ups
pull-ups within
within their
their input
input
pattern information.
information. This
This cell can be only
only be
be reset
reset by repro-
repro- structure.
structure. As aa result,
result, unused
unused inputs
inputs and
and 1I0's
I/0's will
willfloat
floatto
to aaTTL
TTL
gramming the device. TheThe original pattern can
can never
never be
be examined
examined "high"
"high" (logical
(logical "1"). Lattice recommends
"1")_ Lattice recommends that that all
all unused
unused inputs
inputs
once this cell is programmed. The
The Electronic Signature is is always
always and
and tri-stated
tri-stated 110
I/O pins be connected
pins be connected toto another
another active
active input,
input, Vee,
Vcc,
available regardless of the
the security cell state. or
or GND. DoingDoing this this will
will tend
tend to
to improve
improve noise
noise immunity
immunity and and
reduce
reduce lee Icc for
for the
the device.
device.
LATCH-UP PROTECTION Typical Input
"TYPical Input Pull-up
Characteristic
GAL20RA
GAL2ORA10 10 devices are designed with an on-board charge
charge pump
pump -4?
C
to negatively bias the substrate. The negative bias
bias is of sufficient
sufficient .:. /'
magnitude to prevent input undershoots from
from causing
causing the
the circuitry
circuitry E /'
-20
to latch. Additionally,
with n-<:hannel
n-channel pullups
pullups ./
u
instead ofof the traditional p-channel
p-channel pullups
pull ups to eliminate any i •4 0
-40
V
possibility of SCR induced latching. .s !---
·60
SO
1.0
1.0 2 2.00 3 3.00 4 . 4.0
0 5.0
50
Input
Input Voilig.
Voltage (VolIl)
(Volts)
POWER-UP RESET
Circuitry within the GAL2ORA10
GAL20RA 10 provides a reset signal to all all asynchronous
asynchronous nature of system
nature of system power-up,
power-up, somesomeconditions
conditions must
must
registers during power-up. All All internal registers will have
have their
their aQ be
be met
met to to guarantee
guarantee aa valid
valid power-up
power-up reset
reset ofofthe
the GA1.20RA10.
GAL2ORA1 O.
outputs set low after a specified time (t R ESET, 45u.s MAX). As
RESET As a First,
First, the
the Vee
Vcc rise
rise must
must be
clockinput
input
result, the state on the registered output pins (if they
they are
are enabled) must
must become
become a proper
proper TTL
TTL level
level within
within the
the specified
specified time
time (t(tpR,
pR '
will always be high on power-up, regardless
regardless of
of the
the programmed
programmed 1100ns
COns MAX).
MAX). The registers
registers will
will reset
reset within
within aa maximum
maximum of oftR esET
RESET
polarity of the output pins. This
This feature
feature can
can greatly simplify
simplify state
state time.
time. As
As in normal
normal system
system operation,
operation, avoid
avoid clocking
clocking the
the device
device
machine design by providing a known state on power-up. The
power-up. The until
until all
all input
input and
and feedback
feedback path
path setup
setup times
times have
have been
been met.
met.
timing diagram for power-up is shown below. Because Because of thethe
Vee
Vcc
(- t —4)
Clock
Clock Valid Logic Level
Internal treset
Internal Internal Register
Register
Register Reset to Logic "0"
a-Output
Q-Output
Device Device
Device Pin
Pin
Output
Output Pin
Pin Logic
Logic "1"
"1"
2-106 4191.Rev.B
4/91.Rev.B
idLattice'
.l..J Semiconductor
SemironductlJr
GAL2ORA110
Specifications GAL20RA
.,
Corporauon
Normalized Tpd
Tpc! vvs
s Vee
Vcc Normalized Teo
Normalized Tco vs
vs Vee
Vcc Normalized Tsu
Normallzad Tsu vs
vs Vee
Vcc
1.2
I.' ...
1.2 ..•
1.2
t----+--HJ-.... I····· RSEl

P T PT 1-1-54_
H•• L
RISE
I.,
--
1.1 I I
"',,_ I--PTL->H PT L-5.H
J! I PALL
r:.:.::... ....--V
FALL
11
2L,"
j
".
..
'" '"
11
-a
j
".
'"
'" "
). 1
f-'"'
00
0.8 +---11---+--+---1 0.8
0.9 0.'
0.9
0.8 +---'I----l----I-----l 0.'

0,8 0.8
0.8
uo
430 4.75 3 0 5.00
0 5 , 2 5 5 - 5 0
' ..0 44.50
..0 ••75 5 , 0'.00
4.75 0 5 . 25.25
5 5.50
530 4.50
4.50 4.75
'.00
4.75 5 . 0 0 5 . 2 5 5 . 55.50
0
Supply Voltage
Voltage (V)
(V) Supply Voltage (V)
Supply (V) Supply
Supply Voltage
Voltage (V)
(V)
Normalized Tpd
Tpc! vs Temp Normalized Teo
Normalized Tco vs
vs Temp
Temp Normalized Tsu
Normalized Tsu vs
vs Temp
Temp
1.3
1.3 ...
1.3 '.4
1.4
I.'
1.2
•••••
P T PTH
H••L I ..•
1.2 .....
R I S RISE
E I 1.3
"0
,, --m.J
- PT 1..->H
;;:/ --FALL
- FALL I V' g 1.2
1.2
./
it
11 /
1.1
/ ]1 , 1.1
1.1
k""
,/"
.... . V V l'
---
1
jo 00.9
.9
V
0.9
Z 0.8
0,9
0.0
0.8 0.'
0.1 us
.
0.'
0.7
...
-55 0 2 5 ,.
. .,.
125 - 5
0.7
0,7
5 ... 0 2
Temperature
5
,.
9 0 . •125
20 - 5
0.7
0.7
5 .. 0 2
Temperature
5
Temperature (deg.
9
(deg. C)
C)
0 . ... 125
Delta Tpd vs #a of Outputs

Delta Outputs Delta
Delta Teo vs #a of
Tco VI of Outputs
Outputs
Switching
Switching Switching
Switching
0
..... .' ./ .......
_ -0.5
0.5
.'V' 1/ ;., "
_ -0.5
",
V
..5. ,'V ..5. , ," /V
- J! .•
La ./V
"
II·····RISE}
RISE
1/
"
V RISE
c -1.5
•I .5
Il--FALL
- FALL [--FALL
- FALL
.,
2 3 34 45 ' 6 7 8 9
I
• 1 .00
.. I 22 33 4" 55 6• 77 8• 9, 1 10
0
Number
Number of Outputs Swkching
Switching Number of Outputs
Number Outputs Switching
Delta
Delta Tpd vs Output
Delta Teo
I c o vs
vs Output
Output Loading
Loading
".0
12
./
'2
12
10
IRISE
./
••10 RISE
./
--FALLI
. .
8
- FALL
./ --FALL
- FALL I "
/ "
,/ . ,
0 V"
v.' 0'-/ '/'
.. .y'
·2
·4 ·4
so
So 1 0100
0 1 5150
0 2 0200
0 2 5250
0 3 0300
0 5 0 50 1 0100
0 I S150
O 2 0200
0 2 5UO
0 300
300
Output Loading (pF)

Output Loading (pF) Output
Output Loading (pF)
2-107 4/91.Rev.B
4/91 •Rev.B
/ALLattices
Semiconductor
Corporation
GAL2ORA 1IC
Specifications GAL20RA ()
Vol vs lot
Volvslol Voh VB
Voh vs Ioh
loh Voh vsloh
Voh vs loh
3 5 4.50
...
2.5
4
"- r--...
425
o
/ 2 :3 \
r- r-..
-
...........
---
...
:;s 1.5
/v ›,„ 2 ...:is ....
4.00
'-....
/' I'---
...
0.5 V 3.75
3.75
0.00
V
20,00
20 00 4 040.00
00 eo.OO
6000 8 010.00
00 0 . 0
0
0.00
0 5 010.00
0 0 220.00
0 00 310.00
0 00 440.00
0 00 510.00
0 00 B10.00
O 00
....
250
0.00
0.00 1 . 0t.OO
0 2 , 02.00
0 3 . 03.00
0 4.00
4.00
lol(mA)
lol (mA) loh(mA)
Ioh(mA) loh(mA)
loh(mA)
........
Icc VB
Normalized Ice vs Vee
Vcc Normalized icc
Normalized !cc VB
vs Tamp
Temp Normalized Icc
Normalized Icc VB
vs Freq.
Freq.
....
1,20 ....
1.221 1.40
- ---
130
r-.....
1.10
5.50 1.10
./
"
l! Jt
j ..
1J!0
120
2-4 5.00
11 .. 11
1.10
1.10
V
I I /"
........ 0
F, ""'r-.....
uo
•• 1 . 0 0
0.'0
0.90 0.'0
0.90
r-.........
I.......... 0.90
u.
0.80
4.50
450 4 . 74.7&
5 5 . 0s.oo
Supply
0
Supply Voltage (V)

5 2 5.21
5 $.$0
550
u.
0.80
.55 - 2 5 0
Temperature (dag.
C)
IS
25 71
75 100
100 125
125
020
I.
13
Frequency
3 0 3D
Frequency (MHz)
(MHz)
.45
Delta Icc vs Vln

Ice VB Input)
Vin (1 input) Input
Input Clamp
Clamp (Vlk)
(Vik)
5 •0.00
.00
0.00
2.00
/'
4.00
1/
4,00
!. /
,1\ dl
'.00
6.00
'.00
8.00
/
j
J "- 10.00
10.00
-
V .......... 12.00
'I
.........
.....
12.00
0
0.00
0.00 00.50
. 5 0 1 1.00
. 0 0 11.50
5 0 22.00
, 0 0 22.50
5 0 33.00
. 0 0 33.50
, 5 0 44.00
.00
14,00
·2.00
-2 00 •• .00 ....
0.00
Via (V)
Vin Vik (V)
Vik (V)
2-108 4/91.Rev.E
4/91.Rev.E
[JJ
.l..J
:LB.ttiOO®
Semiconductor
l o d klecotntluteor®
Corporation
High
GAL6001
E2CMOS FPLA
Generic Array
Generic
PRA
Array Logic™
Logic'
FEATURES FUNCTIONAL
FUNCTIONAL BLOCK
BLOCK DIAGRAM
DIAGRAM
• ELECTRICALLY
ELECTRICALLY ERASABLE CELL TECHNOLOGY
-— Instantly Reconfigurable
-— Instantly Reprogrammable Cells
Cells CLOCK
-— Guaranteed 100% Yields

• HIGH PERFORMANCE PCMOS®
E·CMOS· TECHNOLOGY
-— Low Power: 90mA Typical
90mA'TYplcal
-— High Speed: 12ns Max. Clock to Output Delay
Time
25ns Min. Setup TIme
3Ons Max. Propagation Delay
30ns
• UNPRECEDENTED
UNPRECEDENTED FUNCTIONAL DENSITY
-— 78 x 64 xx 36 FPLA
FPLA Architecture
-— 10 Output Logic Macrocells
-— 8 Burled Logic Macrocells
-— 20 Input
input and 1/0
I/O Logic
logic Macrocells
• HIGH-LEVEL
HIGH-LEVEL DESIGN FLEXIBILITY
-— Asynchronous
Asynchronous or Synchronous Clocking L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ______
-— Separate State Register and
and Input
Input Clock Pins
-— Functionally Supersets Existing 24-pin
24-pln PAL®
PAL·
and IFL"'
IFL Devices
Devices MACROCELL
MAC ROCELL NAMES
NAMES
• TTL COMPATIBLE INPUTS AND OUTPUTS
ILMC
ILMC INPUT
INPUT LOGIC
LOGIC MACROCELL
MACROCELL
• SPACE SAVING 24-PIN,300-MIL
24-PIN, 300-MIL DIP
IOLMC VO
10LMC I/O LOGIC
LOGIC MACROCELL
MACROCELL
• HIGH
HIGH SPEED PROGRAMMING ALGORITHM BLMC
BLMC BURIED
BURIED LOGIC
LOGIC MACROCELL
MACROCELL
• APPLICATIONS
APPLICATIONS INCLUDE: OLMC
OLMC OUTPUT
OUTPUT LOGIC
LOGIC MACROCELL
MACROCELL
-Sequencer
— Sequencer
....,..
— Multiple PLD Device Integration PIN
PIN NAMES
NAMES
DESCRIPTION
I.10 -- 110
I,. INPUT
INPUT 1/010
I/0/0 BIDIRECTIONAL
BIDIRECTIONAL
Using aa high
high performance
performance E2CMOSPCMOS technology,
technology, Lattice
Lattice
Semiconductor has produced a next-generation programmable ICLK
ICLK INPUT
INPUT CLOCK
CLOCK Vcc
Vee POWER
POWER (+5)
(+5)
logic device, the GAL6001. HavingHaving an FPLA architecture, known
known OCLK
OCLK OUTPUT
OUTPUT CLOCK
CLOCK GND
GND GROUND
GROUND
for its superior flexibility in state-machine design, the GAL6001
offers the highest degree of functional integration, flexibility,
flexibility, and
speed currently available in in a 24-pin, 300-mil package.
PIN
PIN CONFIGURATION
CONFIGURATION
The GAL6001 has has 10 programmable Output Logic
Logic Macrocells
Macrocells
(OLMC) and 8 programmable Buried Logic Macrocells (BLMC). DIP
DIP
In addition, there are 10 Input Logic Macrocel!s
PLCC
PLCC
Macrocells (ILMC) and
and 10
110
I/O Logic Macrocells (10LMC).
(IOLMC). Two
Two clock inputs are provided for VICLK 1
IIICLK Vee
independent control of the input and output macrocells. !5u . 0 0 I vOla
Advanced features that simplify programming and reduce

reduce test
test
- - "•'4 l!g ! 28
2 2
vOla
lime, coupled with E2CMOS reprogrammable
time, coupled reprogram mabie ceHs,
cells, enable 100% IIOIQ
)1 /0i0
1 vOla
AC, DC,
DC, programmability,
programmability, and
and functionality
functionality testing of each
each 3 IIOIQ
I/0/0
vOla
GAL6001during
GAL6001 during manufacture. This
This allows Lattice toto guarantee 3 IIOIQ
I/0/0
NC GAL6001
GAL6001 Me UOIQ
100% performance to specifications. In
In addition, data retention NC IM C
of 20
20 years
years and
and aa minimum
minimum ofof 100
100 erase/write
eraselwrite cycles
cycles are
are Top
Top View
View
IIOIQ
31 /0/0 vOla
guaranteed.
guaranteed. . IIOIQ
3 110/0
vOla
3 IIOIQ
li0/0
Programming is is accomplished using standard hardware and uO/a
- - D
software tools. InIn addition, an Electronic Signature is available - i§i l! 3 vOla
for storage of user specified data, and
and a security cell is provided uO/a
to protect proprietary designs.
GND
GND OCLK
Copyright
Copyright Cl991
Lattice Semiconductor Corp. GGAL.
A L . E'CMOS
PCMOS and
and UhraMOS
UltraMOS are are registered
registered trademarks
trademarks of of Lattice
Semiconductor Corp. Go....ie Array
Corp. Generic Logic isis aaIrade_k
Array logic trademarkofofLattice
Lattice Serriconduc-
Semiconduc-
tor Corp.
lOr PAL is a registered trademark of Advanced Micro Devices.
Corp. PAL inc. IFL
Devices, Inc. iFL is a trademark
trademark of of Slgnetics.
Signetics. The speeWlcations
specifications and information
information herein
herein are
aresubject
subject toto change
change without
without notice.
notice.

LATTICE SEMICONDUCTOR 5555 N.E.
CORP., 5555 N.E. Moore
Moore Ct.,
Ct., Hillsboro,
Hillsboro, Oregon U.SA
Oregon U.S.A. April
April 1991.Rev.A
1991.11ev.A
Tel. (503)681-0118
Tel. (503) 681-0118 or 1-800-FASTGAL;
or 1-800-FAST (503) 681-3037 2 - 12-109
FAX (503)681-3037
GAL; FAX 0 9
[JJ 'LatliOO-
IA Lattice®
Semiconductor
Semironductor
C o r p Corporation
oration
GAL6001 ORDERING
GAl6001 ORDERING INFORMATION

Tpd (ns)
(n8) Fcik (MHz)
Fclk(MHz) icc (mA)
Icc Ordering ##
Ordering Package
Package
30 27
27 150
150 GAL6001-30P
GAL6001-30P 24-Pin Plastic
24-Pin Plastic DIP
DIP
150
150 GAL6001-30J
GAL6001-30J 28-Lead PLCC
28-Lead PLCC
35 22.9 150
150 GAL6001-35P .
GAL6001-35P 24-Pin Plastic
24-Pin Plastic DIP
DIP
150
150 GAL6001-35J
GAL6001-35J 28-Lead PLCC
28-Lead PLCC
GAL6001 ORDERING INFORMATION

GAl6001
xxxxxxx - XX XX
XXXXXXX — X
GAL6001 Device Name L Grade

Grade Blank = Commercial
Blank Commercial
Package PP == Plastic
Plastic DIP
DIP
Speed (ns) Package
J= = PLCC
PLCC
2-110
2-110 4/91.Rev.A
4/91 .1=lev.P
[JJ
.l.J
Lattice®
Lattlce*
I S e m iSemironductor
conductor
Corporation
INPUT LOGIC MACROCELL
MACROCELL (ILMC) AND I/O LOGIC MACROCELL (IOLMC)
AND 1/0 (IOLMC)
rhe GAL6001 features two configurable input sections. The
rile The ILMC GAL6001,, external
the GAL6001 external registers
registers and
and latches
latches are
are not
not necessary.
necessary.
;ection corresponds to the
lection the dedicated input
input pins
pins (2-11) and the
OLMC to the I/O pins (14-23). Each configurable
Each input section is configurable Both the
Both the ILMC and
and thelOLMC
the IOLMC are are block
block configurable.
configurable. However,
However,
as a block for asynchronous, latched, or registered inputs. Pin
IS Pin the ILMC can
the can be
be configured
configured independently
independently ofof the
the 10LMC.
IOLMC. The
The
I (ICLK)
(ICLK) is used as an enable input forfor latched
latched macrocells or as three valid
three valid macrocell
macrocell configurations
configurations are are shown
shown inin the
the macrocell
macrocell
Iaclock input for registered macrocells. Configurable
Configurable input blocks equivalent diagrams
equivalent diagrams onon the
the following
following pages.
pages.
)rovide systems designers with unparalled design flexibility. With
flexibility. With
OUTPUT LOGIC MACROCELL (OLMC) AND BURIED LOGIC (BLMC)

LOGIC MACROCELL (BLMC)
Ihe outputs of the OR array feed two groups of macrocells. One
rhe When
When the
the macrocell
macrocell is is configured as aa"D
configured as "Dtype
type register
registerwith
with aasum
sum
youp of eight macrocells is buried; its outputs feed
Iroup feed back directly term
term clock",
clock", the
the register
register is
is always
always enabled
enabled and
and its
its"E"
"E"sum
sumterm
term
nto the AND array rather than to device pins. These
These cells
cells are
are is
is routed
routed directly
directly to
to the
the clock
clock input.
input. This permits
permits asynchronous
asynchronous
:alled
alled the Buried Logic Macrocells (BLMC), and and are useful for programmable
programmable clocking,
clocking, selected
selected on
on aaregister-by-register
register-by-register basis.
basis.
)uilding state machines. The
The second group of of macrocells
macrocells con-
con-
lists
;ists of 10 cells whose outputs, in addition to feeding
feeding back into Registers
Registers inin both
both the
the Output
Output andand Buried
Buried Logic
Logic Macrocells
Macrocellsfeature
feature
he AND array, are available at the device pins. Cells
Cells in this
this group
group aa common
common RESETRESET product
product term. This active
term. This active high
high product
product term
term
ue
are known as Output Logic
Logic Macrocells (OLMC). allows
allows the
the registers
registers to
to be
be asynchronously
asynchronously reset.
reset. Registers
Registers are are
reset
reset to
to a logic
logic zero. If connected
zero. If connected to to an
an output
output pin,
pin, aa logic
logic one
one
rhe and Buried Logic Macrocells are configurable on a
Ihe Output and will
will occur
occur because
because ofof the
the inverting
inverting output
output buffer.
buffer.
nacrocell by macrocell basis. Buried and Output Logic Macrocells
Buried and Macrocells
nay be set to one of three configurations: combinational,
combinational, "D-type
"O-type There
There are twotwo possible
possible feedback
feedback paths
paths from
from each
each OLMC.
OLMC. TheThe
egister with
with sum
sum term
term (asynchronous)
(asynchronous) clock", or "D/E-type
"DIE-type first
first path
path is
is directly
directly from
from thethe OLMC
OLMC (this
(this feedback
feedback is is before
beforethe
the
egister." Output
Output macrocells always have I/O 110 capability,
capability, with output
output buffer
buffer and
and always
always present). When the
present). When the OLMC
OLMC is isused
used as
as
lirectional control provided by the 10 output enable (OE) prod-prod- an
an output,
output, the
the second
second feedback
feedback path
path is
isthrough
through the
the 10LMC. With
IOLMC. With
Ict Additionally, the polarity
iCt terms. Additionally, polarity of each
each OLMC output'
output is this
this dual
dual feedback
feedback arrangement,
arrangement, the the OLMC
OLMC can be permanently
can be permanently
lelected
;elected through the
the "0"
"D" XOR. Polarity
Polarity selection is available for
for buried
buried (the
(the associated OLMC OLMC pinpin is an
an input),
input), or
or dynamically
dynamically
3LMCs, since both the true and complemented forms of their buried with
buried with the
the use
use ofof the
the output
output enable
enable product
product term.
term.
)utputs Polarity of all "E" sum
iutputs are available in the AND array. Polarity sum
erms is selected through the "E" XOR. The DIE registers
The registers used
used in
in this
this device
device offer
offer the
the designer
designer the
the ul-
ul-
timate in
in flexibility
flexibility and
and utility. The DIE
D/E register
register architecture
architecture can
can
IVhen
A/hen the macrocell is configured
configured as a "DIE
"D/E type registered", the e!T1ulate
emulate RS-,
RS-, JK-, and and T-type
T-type registers
registers with
with the
the same
same efficiency
efficiency
egister is clocked from the common OCLK and the the register
register clock
clock as
as a dedicated
dedicated RS-,RS-, JK-, oror T-register.
T-register.
mabie
?triable input is controlled by the
the associated
associated "E" sum
sum term. This
This
:onfiguration
;onfiguration is useful for building counters and state-machines The
The three
three macrocell
macrocell configurations
configurations are
are shown
shown in
in the
the macrocell
macrocell
vith state hold functions. equivalent diagrams on
equivalent diagrams on the
the following
following pages.
pages.
2-111 4/91.Rev.A
4/91.Rev.A
LILattice®
.J"", Corporation
Semiconductor
SemironductlJr Specifications GAL6001
Corporation
ILMC AND IOLMC CONFIGURATIONS
I !MK
IClK
-------------------
:__ ________________
ICLK
I NC
NC I
E Q
Q
LATCH
D
INPUT
INPUT I
PINS 2-11 , 10 INPUT
INPUT
OR
I/OOR
IJOPINS
PINS
14-23
--.+t-r-;:::==:::::;-,
I 10
MUX
MUX 410_06----
' T OTO
PINS
PINS 2·11
OR
OR
2-11 I
.
10
10
I I '/ I:L
\lOPINS
I/O PINS I io
Q AND
AND
14-23
14·23 To
TO
REGISTER
REGISTER ARRAY
ARRAY
AND
AND
, ARRAY
ARRAY
D LATCH S Y N
L __________________ I
ILMC/IOLMC Asynchronous
Asynchronous Input
Input
Generic Block Diagram
LATCH
LATCH SYN
SYN
1
ICLK
IClK IClK
ICLK
Q Q0
INPUT E
REGISTER 10
10 INPUT
INPUT 10 I
PINS 2-11
2·11 LATCH
LATCH 10
I 10 TO
TO PINS
PINS 2-11
2-11 I
10
10
OR D AND
AND I TO
TO
OR
OR D AND
\10 PINS
I/O PINS I I
ARRAY
ARRAY IJOPINS
I AND
I/O PINS ARRAY
ARRAY
14·23
14-23 14-23
14-23
Registered Input L a t c h e Latched

d Input
LATCH
LATCH SYN LATCH
LATCH S YSYN
N
o0 o0 0 o
2-112
2-112 4191.Rev.A
4/91.1Rev.P
Lattice®
L.. Semiconductor
l a ISemiconductor
Corporation
OLMC AND BLMC CONFIGURATIONS
TO AND
ARRAY :••
OE
PT * L U C
RES'"
I / 0
[)o-';-'&-IO
D . O L M C ONLY
FROM t ...... !I... FROM
FROM
OR
IUlRAY OR
OR
E ......._ ......../ ARRAY
ARRAY
CUll
OCU< ,_ - - - - - - - - - - - - - - - - - - - - - I
OCIA
OCLII
OCLK
OILIVIC/BLMC
OLMC/BLMC DIE
DIE Type
Type Registered
Generic Block Diagram
CKS(i)
CKS(i) OUTSYN(i)
OUTSYN(i)
1 o0
TO AND ............... "

TOAND TO AND
TO AND
ARRAY
ARRAY: OE ARRAY
ARRAY . •
OE
Ran
RESET PT
PT I O LIOLMC
__ ti _ " OE
1
M C RESET 101.MC
.
I ____________ PT IOLUe
I - - - - - - - - - - - - _1- - - - - - - .
:, r.l"""'II'.I,,.I, , • /
I" OLMC"
OLMC ,
I
I"
... , I " ' ... "''''''''',
OUIC"
, I:• lOR
CON O NONLY
L Y : He
. .........."'
I: XOR ONLY
R
Q ' 0 .. I
'"""" .. ,,,,,,,,,,,,,,
I OLMC ONLY
OLJAC ONLY
.................. ........................................ FROM ............ , OLMC ONLY
..
FROM FROM
OR I lCOR Vee OR
OR I
ARRAY ARRAY
ARRAY
I
E
E - ,N- CNC
I He
He
'- -- --- - - - - - - - - - - - - - - - -'
OCLK
OCLK
OCLII
D Type Register
with Sum Term Combinational
Combinational
Asynchronous Clock
CKS(i) OUTSYN(i) CKS(i)

CKS(i) OUTSYN(i)
OUTSYN(i)
o0 o0 o0
2-113
2-113 4191.Rev.A
4/91.1Rev.A
LLattice
Semiconductor
Semiconductor Specifications GAL6001
Corporation
Corporation
GAL6001 LOGIC
LOGIC DIAGRAM
lelK
ICLK
...
1
,,. 111M1•11111111•11111111111111111111111111111•111111111•111N11•1111111 = M I N A
,
[J-
.
3
"
"
1111111•11111111111111111111111111111111111•11111111•111111111111111111
M I 0.—
PM,
01.1101;
."
.. roJ-
,7 :w-
:: ,,-
•111111•1111111111111111•11111111111111111•11111111•1111M•1111111 -III'.'..'
,. 10
1111111.1111111.111111.1111111.1111111.11111111111114;
RESET
23
LMC
WHINIMMHIMHOIMEHHIMIMMOIMMIHMMIMIIII
4 IHIMEMBHIMMHEMMIIMMIIMMIIIMMHIMICH
immummul•immonnunElmillommumummommi 22
IMMEMMIEMIMIHMMEHMHEIMMEHMMINIE11114,
IMMEMEIHIMIHIMMMEMIMIIIMMEMOHEMIll
111N11111111111111111111111111111fil•1111111E1111111EUUMEEENI 21
IHNIMEHHHIMMHEMMIIIMMHEHHHUIMIMIMIEll
1111111E1 111111•1111111•11111111111111111•1111111E1111111EN•EI 20
1111111.1111111•11111111111111111111111111111111111111111111111111111.11K-4;
1111111E1
"
MIME
HMIS V I I OLMC
" . 9 1 1 1 1 1 1 1 .
1111111• 1111111111 . 4 p n i t l o u r , 18
HUME
HMO.
MIME MAC, I I l i a .
1111111E1 17
im finumminimmilmmEimummirnimmul &All II
MMEllinmiEnnnimommolounionninumeindallilda
IMIHEIHHIMENIEHEIMMINIIIIEMNIIIMMEIMIIII MAC.
lumnmenummommusionommumumnallimum • D i m i l l i h n 16
IMMIIIIIIIMENHEEMHINIMINIMMIMMHEMONITP H mulu I I
4 "la-c,--.11
11 1 1 1 1 1 • 1 • 1 1 1 1 . 1 1 1 1 1 1 . 1 1 1 1 1 1 . 1 1 . 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 . 1 1 1 1 1
MMIEBINIIIIIMEIMMIESH111111111MMEMONOLMCIS
4 meim••mmuummumemmumsommuummumou
i . . Eralill n
iiiiiiMMENEMENEEMEMEMEHMEMMEMENit0 H or "
1101111111111111111111111111 "
RESET
,.
RESET
OCLK
°ELK
2-114
2-114 4/91.Rev.J
4/91.1Rev.)
[J.J
id
t
f
LJ
'LattiOO$
Lattice®
Semironductor
Semiconductor
C o r p CorporaUon
oration
Commercial
ABSOLUTE MAXIMUM RATINGS(l)
COND.
Supply voltage Vee
Vc, .......................................
— 0 . 5-0.5 to +7V Commercial
Commercial Devices:
— 2 . -2.5 5 to Vcc +1.0V
(TA ) •••••••••••••••••••••••••••••••• to 75°C
0 to 75°C
Off-state output voltage applied ..........— 2-2.5 . 5 to Vcc +1.0V
(Vee)
— 6 5 -65 to 150°C with Respect to
with to Ground
Ground ......................
+ 4 . 7+4.75 5 to to +5.25V
+5.25V
Power Applied ........................................
— 5 5 -55 to 125°C
1.Stresses above those listed under the "Absolute
"Absolute Maximum
Ratings·
These
the device
those indicated in
inthe
the
operational sections of this specification is not
not implied (while
Specified)

CONDITION MIN.
MIN. TYP."
TYP.2 MAX.
MAX. UNITS
UNITS
VIL Input Low Voltage Vss

Vss-0.5
-0.5 -— 0.8
0.8 VV
2.0 -— VcC+1
Vcc+1 VV
IL
IlL Input or I/O
110 Low Leakage Current OV
OV5S_VIN
Y,N S V,L (MAX.)
VII_ -— -— ·10
-10 )tA
IIH
IIIH Input or 110
I/O High Leakage Current V,H
VIHSVIN
V,N S Vee
VCC -- -- 10
10 )IA
VOL Output Low Voltage 10L.
l a = MAX. Vi
Yinn -= V,L
Vit. or
or V,H
VII-1 -- -- 0.5
0.5 VV
loH = MAX. Vin
Yin =- V,L
Vit. or V,H
or VIH 2.4
2.4 -— -— VV
10L
16 mA
mA
-3.2 mA
mA
los'
10S1 Output Short Circuit Current Vcc=5V VOUT == 0.5V
Vcc = 5V VOW- -30
-30 -— -130
-130 mA
mA
ICC
Icc Operating Power Supply Current V,L
Vii.. = 0.5V
0.5V 1/V,H
11-1== 3.0V ftoggle = 15MHz
3.0V ftoggle -— 90
90 150
150 mA
mA
Outputs
Outputs Open (no
(no load)
load)
time for Vout =
for a maximum duration of one second. Vout = 0.5V
0.5V was
was selected
selected to
to avoid
avoid test
test problems
p oblems caused
caused by
bytester
tester
2) Typical values are at Vcc =- 5V and
and TA
TA = 25
25 ·C
'C
CAPACITANCE (TA =
(TA = 25°C, f1= 1.0 MHz) =
MAXIMUM* UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
C,
CI Input Capacitance 8 pF
pF VVcc
cc == 5.0V,
5.0V, V,
Vi •= 2.0V
2.0V
C
Coo . 110
I/O Capacitance 10
10 pF
pF Vee
Vcc== 5.0V, VI/O
3O== 2.0V
5.0V, Vi 2.0V
I/O
'Guaranteed but not 100% tested.
tested.
2-115 4/91.Rev.A
4/91.Rev.A
L Lattice®
Semiconductor
GAL6001
Commercial
Over Recommended
OVer Recommended Operating
Conditions
TEST
-30
-30 -35
-35
PARAMETER
DESCRIPTION UNITS
UNITS
CONDI.
COND'. MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX.
tpd1 11 Combinatorial Input to Combinatorial
Combinatoriallnpurto Combinatorial Output
Output -— 30
30 -— 35
35 ns
ns
tpd2 11 or 1/0
Feedback or I/0 to
to Combinational
Combinational Output
Output -— 30
30 -— 35
35 ns
ns
tpd3 11 Transparent Latch Input to Combinatorial
Input to Combinatorial Output
Output -— 35
35 -— 40
40 ns
ns
tcol
tco1 11 Input latch
Input Latch IClKi
'CLIO' to
to Combinatorial Output Delay
Delay -— 35
35 -— 40
40 ns
ns
tco2 11 Input Reg. IClKi
Input 'CLIO' to
to Combinatorial Output Delay
Delay -— 35
35 -— 40
40 ns
ns
tco3
tc03 11 Output DIE Reg. OClKi
Output OCLKI to
to Output
Output Delay -— 12
12 -— 13.5
13.5 ns
ns
tco4
tc04 11 Output 0D Rea.
Outout Req. Sum Term
Term ClK"t
CLKT to
to Outout
Output Delav
Delay -
— 35
35 -— 40
40 ns
ns
tsul
tsu1 -— SetupTime,
Setup Time, Input before
before Input
input Latch
Latch IClK.!.
ICLK1 2.5
2.5 -— 3.5
3.5 -— ns
ns
tsu2 -— Setup
Setup Time,
lime, Input before Input Reg.
Reg. IClKi
!CLIO' 2.5
2.5 -— 3.5
3.5 -— ns
ns
tsu3
teu3 -— Setup
Setup Time,
Time, Input or
or Feedback before DIE
Feedback before DIE Reg.
Reg. OClKi
OCLKI 25
25 -— 30
30 -— ns
ns
tsu4 -— Setup
Setup Time,
Time, Input or
or Feedback before 0D Reg.
Feedback before Reg. Sum
Sum Term
Term ClKi
CLIC!' 7.5
7.5 -— 10
10 -— ns
ns
tsu5 -— Setup Time,
Setup Time, Input Reg. IClKi
ICLKI before
before DIE
DIE Reg.
Reg. OClKi
OCLKT 30
30 -
— 35
35 -— ns
ns
tsu6 -— Setup Time, Input Reg.

lime, Input Reg. ICLKT before 0
IClK"t before D Reg.
Reg. Sum
Sum Term
Term ClKi
CLKI 15
15 -— 17
17 -— ns
ns
th1
thl -— Hold Time, Input after
after Input
Input latch IClK.!.
Latch ICLK,I, 55 -— 55 -— ns
ns
th2 -— Hold Time, Input after
after Input
Input Reg. IClKi
Reg. ICLKT 55 -— 55 -— ns
ns
th3 -— Hold Time,
lime, Input or
or Feedback after DIE
Feedback after DIE Reg.
Reg. OClK"t
°CLIO' -5
-5 -— -5
-5 -— ns
ns
th4 -— Hold Feedback after 0
Hold Time, Input or Feedback D Rea.
Reg. Sum
Sum Term
Term ClKi
CLKT 10
10 -— 12.5
12.5 -— ns
ns
fmax
fmax -— Maximum
Maximum Clock Frequency,
Frequency, OClK
OCLK 27
27 -— 22.9
22.9 -— MHz
MHz
twh12
Uhl' -— IClK
ICLK or OClK
OCLK Pulse
Pulse Duration, High 10
10 -— 10
10 -— ns
ns
twh22 -— Sum Term ClK
CLK Pulse
Pulse Duration,
Duration, High 15
15 -— 15
15 -— ns
ns
twl12
tw112 -— IClK
ICLK or OClK
OCLK Pulse
Pulse Duration, Low
Low 10
10 -— 10
10 -— ns
ns
twl22
tw122 -— Sum
Sum Term ClK
CLK Pulse
Pulse Duration,
Duration, low
Low 15
15 -— 15
15 -— ns
ns
tarw -— Reset Pulse Duration 15
15 -— 15
15 -— ns
ns
ten 2 Input or I/O
Input or I/O to
to Output
Output Enabled -— 25
25 -— 30
30 ns
ns
to Output
Output Disabled -— 25
25 -— 30
30 ns
ns
to Asynchronous
Asynchronous Reg.
Reg. Reset
Reset -— 35
35 -— 35
35 ns
ns
tarr1
tarn l -— Asynchronous
Asynchronous Reset
Reset to
to OClK
OCLK Recovery
Recovery Time
Time 20
20 -— 20
20 -— ns
ns
tarr2 -— Asynchronous
Asynchronous Reset to
to Sum
Sum Term
Term ClK
CLK Recovery
Recovery Time
lime 10
10 -— 10
10 -— ns
ns
1) Refer to
1) to Switching
Switching Test
Test Conditions
Conditions section.
section.
2) Clock pulses of widths less than the specification may be detected as valid
valid clock
clock signals.
signals.
2-116
2-116 4191.Rev.A
4/91.Rev.A
r17Latike®
L1III
i-xid Semiconductor
SemJronductor Specifications GAL6001
Corporation
Corporation
SWITCHING WAVEFORMS
INPUTor
INPUT
I/OFEEDBACK
I/O FEEDBACK
\\\\\\\ r- VALIDINPUT
VALID INPUT INPUT
INPUTor
or
110FEEDBACK
I/O FEEDBACK IS VALIDINPUT
\ \\ \ \ \ rVAlID INPUT
4-tsu2 * 4 1 1
4 - thel•2---* roo-'-------
COMBINATORIAL
COMBINATORIAL
OUTPUT
OUTPUT \\\\\\\\\\\\\ ICLK(REGISTER)
ICLK (REGISTER)
mit co2
Combinatorial Output COMBINATORIAL

COMBINATORIAL
OUTPUT
OUTPUT \\\\\\\\\\\\\\\\\\\X 4---- tsu5
INPUT
INPUTor VALIDINPUT
VOFEEDBACK
110 FEEDBACK OCLK
OCLK
4-tsui
4 - I su6
100'1=
ICLK (LATCH)
ICLK(LA TCH)
SumTerm
Sum TermCLK
CLK
4 tpd3 * 4— t col *
COMBINATORIAL
COMBINATORIAL
Registered Input
Registered input
OUTPUT
OUTPUT
Latched input
latched iInput
. t ._t.:'_
INPUT
INPUTor
or VALIDINPUT
INPUT
INPUTor
I/O
or
FEEDBACK
VOFEEDBACK
\'\\\r VALIDINPUT
VAliD INPUT I \\\\\\ VO FEEDBACK
VOFEEDBACK
t su3 t h3
t Sti4- * C t -0t
24
OCLK
CCU(
SumTermCLK
SumTermCLK
1(3°3 *
1/ hoax
REGISTERED
REGISTERED
OUTPUT
OUTPUT \\\ \\\\\\ REGISTERED
REGISTERED
OUTPUT
OUTPUT t A X
Registered Output (Sum Term ClK)

CLK) Registered
Registered Output
Output (OClK)
(OCLK)
INPUT
INPUTor
01
I/O FEEDBACK
VOFEEDBACK
tels -fp t e n-* INPUT

INPUTor
or
110 FEEDBACK
I/OFEEDBACK
OUTPUT
OUTPUT DRIVINGAR
DRIVINGAR
Input or I/O to
to Output Enable/Disable REGISTERED
REGISTERED
OUTPUT
OUTPUT
tar
41— - 0 • 4 1 1 - - tvAi SumTermCLK
SumTerm CLK
ICLKor
ICLKor
OCLK
OCLK
t arr2
t wh2 4 i v &
OCLK
OCLK
SumTermCLK
SumTermCLK
4 - t arrl
Clock Width Asynchronous

Asynchronous Reset
Reset
2-117 4191.Rev.A
4/91 Rev.A
1,/"tice®
Semiconductor
.l..J ('nporation
Cotporation
SWITCHING TEST CONDITIONS .
Input Pulse Levels GND to 3.0V

GNDto 3.0V
3ns 10% - 90% +5V
1.SV
1.SV
See Figure
3-state levels are measured O.SV
0.5V from
level. FROMOUTPUT
FROM OUTPUT(0/0)
(0/0) TESTPOINT
POINT
- -......- - - - TEST
UNDER TEST
UNDERTEST
figure) Cl
R2
Condition
Test Condition R1
RI Fb
R2 CL
CL
11 3000
300n 3900 50pF
SOpF
2 Active High
High -,
00 3900 SOpF
50pF
Active Low 300n
3000 3900 SOpF
50pF C
CL INCLUDES
JIGAND PROBETOTAL
TOTALCAPACITANCE
CAPACITANCE
3 Active High ,i,..
00 390n
3900 SpF
5pF
Active Low 300n
300n 390c1
3900 5pF
SpF
2-118
2-118 4191.Rev)
4/91.Rev./
I,
Lattice®
Semiconductor
Semironductor Specifications GAL6001
Corporation I
ARRAY DESCRIPTION BULK ERASE
BULK
GAL6001 contains two E2
The GAl6001 reprogrammable
E2 reprogram first
mabie arrays. The first Before writing
Before writing a new
new pattern
pattern into
into aa previously
previously programmed
programmed part,
part,
is an AND array and the second is an
an OR array.
array. These are
These arrays are the old pattern
the pattern must first be erased.
must first erased. TThish i s erasure done
erasure is done
described in detail below. automatically by
automatically by the
the programming
programming hardware
hardware as as part
part of
of the
the pro-
pro-
gramming cycle
gramming cycle and
and takes
takes only
only50
50 milliseconds.
milliseconds.
AND ARRAY
ANDARRAY
The AND array is organized as 78 inputs by 75 productproduct termterm REGISTER PRELOAD
PRELOAD
REGISTER
outputs. The
The 10 ILMCs,
IlMCs, 10 IOLMCs,
IOlMCs, 8 BlMCfeedbacks,
BLMC feedbacks, 10
OlMC
OLMC feedbacks, and ICLK IClK comprise the 39 inputs toto this
this array When testing
When testing state
state machine
machinedesigns,
designs, allall possible
possible states
states and and state
state
(each available in true and complement forms). 64 64 product
product terms
terms transitions must
transitions must bebe verified,
verified, not just
just those
those required
required during
during normal
normal
serve as
as inputs
inputs to the
the OR
OR array. TThe
h e RESET product term operations. This
operations. is because
This is because in in system
system operation,
operation, certain
certain events
events
generates the RESET signal described in in the
the Output and
and Buried may
mayoccur
occurthat
that cause
cause the
the logic to assume
logic to assume an an illegal
illegal state: power-
state: power-
logic There are 10 output enable product
Logic Macrocells section. There up, brown
up, brown out,
out, line
line voltage
voltage glitches,
glitches, etc.
etc. To testtestaadesign
designfor forproper
proper
terms which allow device pins 14-23 to
to be bi-directional or
ortri-state.
tri-state. treatment of
treatment ofthese
theseconditions,
conditions, aa method
method must
mustbe beprovided
providedto tobreak
break
the
the feedback
feedback paths
paths and
and force
force anyany desired
desired statestate (Le.,
(i.e., illegal)
illegal) into
into
OR ARRAY
ORARRAY the registers. Then the machine
the registers. machine can can be sequenced
the
The OR array is organized as 64 inputs by 36 sum term outputs.
outputs. outputs
outputs tested
tested for
for correct
correct next
next state
state generation.
generation.
64 product
product terms from the
the AND array serve as the
the inputs
inputs to the
the
OR array. Of
Of the 36
36 sum term outputs, 18 are data ("0")("D") terms
terms All
All of the
the registers
registers inin the
the GAl6001
GAL6001 can
can be
be preloaded,
preloaded, including
including
and 18 are
are enablelclock
enable/clock ("E") terms. These
These terms feed
feed into the the
the IlMC,
ILMC, 10lMC,
IOLMC, OlMC,
OLMC, and and BlMC
BLMC registers.
registers. In addition,
addition, the
the
10 OlMCs
10 OLMCs and 8 BlMCs,
BLMCs, one "0"
"D" term
term and one "E" term
term to
to each.
each. contents
contents ofof the
the state
state and
and output
output registers
registers can
can be
be examined
examined in inaa
special
special diagnostics mode. Programming hardware
mode. Programming hardware takes
takescare
careof of
The programmable OR array offers unparalleled versatility
versatility in
in all
all preload
preload timing
timing and
and voltage
voltage requirements.
requirements.
product term usage. This
This programmabili1Y
programmability allows from 11 to 64
64
product terms to be connected to a single sum
sum term. AA pro-
grammable OR array is more flexible than a fixed,
fixed, shared, or LATCH-UP
LATCH-UP PROTECTION
PROTECTION
variable product term architecture.
GAl6001 devices are
GAL6001 devices are designed
designed with
with an
an on-board
on-board charge
charge pump
pump
to
to negatively
negatively bias
bias the
the substrate.
substrate. The
The negative
negative bias
bias is
is of
ofsufficient
sufficient
ELECTRONIC SIGNATURE WORD magnitude
magnitude to to prevent
prevent input
input undershoots
undershootsfrom
from causing
causing the
thecircuitry
circuitry
An electronic signature (ES) is provided with every GAl6001 to
to latch. Additionally, outputs
latch. Additionally, outputs are
are designed
designed with
with n-channel
n-channel pull-
pull-
GAL6001
device. ItIt contains 72 bits of reprogram mabie memory that can
reprogrammable can ups
ups instead
instead of
of the
thetraditional
traditional p-channel
p-channel pull-ups
pull-ups to
to eliminate
eliminate any
any
contain user defined data. Some Some uses include user ID10 codes, possibility
possibility of
of SCR
SCR induced
induced latching.
latching.
revision numbers, or inventory control. The The signature
signature data
data is
always available to the user independent of thethe state of
of the
the se-
se-
curitycell.
curity cell. INPUT
INPUT BUFFERS
BUFFERS
GAL
GALdevices
devices are
aredesigned with m
designed with ITL level
level compatible
compatible input
inputbuffers.
buffers.
NOTE: The ES ES is included in checksum calculations. Changing
Changing These
These buffers,
buffers, with
with their
theircharacteristically
high impedance,
impedance, load
load
the ES will
will alter the checksum. driving
driving logic much less
less than
than traditional
traditional bipolar
bipolar devices. This
devices. This
allows
allows for
for a greater
greater fan
fan out
out from
from the
the driving
driving logic.
logic.
SECURITY CELL GAl6001
GAL6001 devices do do not
not possess
possess active
active pull-ups
pull-ups within
withintheir
their input
input
A security cell is provided with every GAl6001
GAL6001 device as as a de- structures.
structures. As As a result,
result, lattice
Lattice recommends
recommends that that all
all unused
unused in-in-
terrent to unauthorized
unauthorized copying of the array patterns. Once Once puts
puts and
and tri-stated
tri-stated 1/0 pins be
I/O pins be connected
connected to to another
another active
active input,
input,
programmed, this cell prevents further read access to to the
the AND V CC' or GND.
Vcc, Doing this
GND. Doing thiswill
will tend
tend to
to improve
improve noise
noise immunity
immunity andand
and OR arrays. This
This cell can be erased
erased only during a bulk
bulk erase reduce Icc forthe
reduce Icc for the device.
device.
cycle, so the original configuration can never be examined once
this cell is programmed. TThe h e Electronic Signature is always
available to the user, regardless of the
the state of this control cell.
cell.
2-119
2-119 4/91.Rev.A
4/91.Rev.A
flJ'Lattioo
Lattices Semiconductor
SemkxJnducUJr
Corporation
e
POWER-UP RESET
Va;
Vcc 90%7
ICLK
0"----
OV
V1F4
t PR
/-----------------
OCLK
OCLK VALID CLOCK
VALID CLOCK SIGNAL
SIGNAL
STCLK VIL
VIL ...
t RESET
INTERNAL
INTERNAL REGISTER
REG.
REG. 0 RESET
RESET TO
TO lOGIC
LOGIC 00
FEEDBACK/EXTERNAL
FEEDBACK/EXTERNAL
REG. 0
REG. Q EXTERNAL REGISTER
OUTPUT
OUTPUT OUTPUT = LOGIC 1
Circuitry within the GAL6001 provides a reset reset signal

signal to
to all
all registers
registers The
The timing
timing diagram
diagram for
forpower-up
power-upisis shown
above. Because ofthe
the
during power-up. All All internal registers will have their
their Q 0 outputs
outputs asynchronous
asynchronous nature
nature of
of system
system power-up,
power-up, some
some conditionsmust must
set low after a specified time (tResET 45I1S). As
(tRESET ,,11511s). As a result, the state be
be met
met to
to guarantee
guarantee aavalid
validpower-up resetof
power-upreset ofthe
theGAL6001.
GAL6001. First, First,
on the registered output pins (if they
they are enabled) will will always be be the
the Vee
Vcc rise
rise must
must be
clock inputs
inputs mustmust
high on power-up, regardless of the programmed polarity of the the become
become aa proper
properTTL
TTLlevel
level within
within the
the specified
specified time
time (t(tpA,
pR , 1001LS).
100p,$).
output pins. This
This feature can
can greatly simplify
simplify state
state·machine
machine design The
The registers
registers will
will reset
reset within
within a maximum
maximum of of tREsET
tfiEsel.time.
time. As As in
by providing a known statestate on power-up. normal
normal system
system operation,
operation, avoid
avoid clocking
clocking the
the device
device until
until allall input
input
and
and feedback
feedback path
path setup
setuptimes
times have
have been
been met.
met.
DIFFERENTIAL PRODUCT TERM SWITCHING (DPTS)

(OPTS) APPLICATIONS
APPLICATIONS
The number of of Differential Product Term Switching (OPTS)
(DPTS ) for
for simultaneously
simultaneously --there
there is
is no
no limit
limiton
onthe
thenumber
numberof
ofproduct
productterms
terms
given design is calculated by subtracting the total
a given total number ofof that
that can
can be
be used.
used.
product terms that are switching from a logical
Logical HI to
to a Logical
Logical LO
LO
from those switching from
from a logical
Logical LO to a logical
Logical HI within a AAsoftware
software utility is
is aV!lilable
availablefrom
from Lattice
LatticeApplications
ApplicationsEngineering
Engineering
5ns
5ns period. After
After subtracting take the
the absolute value. that
that will
will perform
perform this
thiscalculation
calculation on
on any
anyGAL6001
GAL6001 JEOEC
JEDECfile.
file. This
This
program,
program, OPTS,
DPTS, andand additional information
information may
may bebeobtained
obtainedfrom
from
OPTS I
- (P-Terms)L
DPTS = (P-Terms)LHH- (P-Terms)HL
(P-Terms)HL I your local Lattice
your local Lattice representative
representative oorr by contacting
contacting Lattice
Lattice
Applications Engineering Dept.
Applications Engineering Oept. (Tel:
(Tel: 503-681-0118
503-681-0118 or or 800-
800-
OPTS
DPTS restricts the number of product terms
terms that
that can
can be
be switched FASTGAL;
FASTGAL; FAX: FAX: 681-3037).
681-3037).
2-120
2-120 4191.Rev.A
4/91.Rev.A
[JJ:LatUoo®
I t d ISemiaJnducWr
i S
e t r er
Corporation
Corporation
In-System
ispGAL1 6Z8
ispGAL16Z8
In-System Programmable
High E2CMOS PlD
PLD
DIAGRAM
IN-SYSTEM-PROGRAMMABLE -— 5·VOLTONLY
IN·SYSTEM·PROGRAMMABLE 5-VOLT ONLY
-— Change Logic "On The Fly" In Seconds
-— Non-volatile
Non·volatlle E2
E2 Technology 00LX
sot
A M A R A . CONTROL LOGIC W O E 23
PROGRAM CONTROL SIDNALS
MINIMUM 10,000 ERASE/WRITE CYCLES CDC.
DIAGNOSTIC MODE FOR CONTROLLING

CONTROLUNG AND 22
OBSERVING SYSTEM LOGIC
HIGH PERFORMANCE E2CMOS®
E2CMOS- TECHNOLOGY 21
-— 20 ns Maximum Propagation Delay
-— Fmax == 41.6 MHz
-— 90 mA MAX Icc
!cc NC 20
E2
E2 CELL TECHNOLOGY
-100%
-— 20 Year Data Retention 19
EIGHT OUTPUT LOGIC MACROCELLS

-— Maximum Flexibility for Complex Logic Designs la
-— Programmable Output Polarity
-— Also Emulates 20-pin
2D-pin PAL®
PAL- Devices with Func·
with Full Func-
tlon/Fuse
• 01-4C 17
PRELOAD AND POWER·ON RESET OF
POWER-ON RESET OF REGISTERS nan
Testability
16
APPUCATIONS
-— Reconfigurable
Reconflgurable Interfaces and Decoders .C)
-— "Soft" Hardware (Generic Systems) DOM 15

-— Copy Protection and Security Schemes
-— Reconfiguring
Reconflgurlng Systems for Testing 10
M O G A N ) ) D ATA ) C O L O . ) ) D ATA )
ELECTRONIC SIGNATURE FOR IDENTIFICATION 11 so,

Fr REGISTER LATCH S O O 14
DC
—13
DESCRIPTION PIN CONFIGURATION

PIN CONFIGURATION
rile ispGAL-16Z8 is a revolutionary programmable

rhe Lattice ispGAL®16Z8 programmable logic
levice
fevice featuring 5-volt only in-system programmability and in-
;ystem diagnostic capabilities. This is
is made possible by
by on-chip
on-chip DIP
DIP
:ircuitry
;ircuitry which generates and shapes
shapes the
the necessary high volt-
volt- PLCC
PLCC
Ige
tge programming signals. Using
Using Lattice's proprietary UltraMOS-
echnology, this device
UltraMOS®
device provides true bipolar performance at
__ 82 "...g52uz A 9 .. DClK
DCLK
11/C1K 24 Vee
Vcc
MODE
MODE
;ignificantly reduced power levels. !a 2 1/0/0
1/0/0
/- — - 28 —
1/0/0
1/0t0
rhe ispGAL 16Z8 is architecturally and parametrically
rho 24-pin ispGAL16Z8 parametrically UO/Q
60/0
dentical to the 20-pin

20-pin GAL16V8,
GAL 16V8, but includes 4 extra
extra pins
pins to
to UO/Q
3 1/0/0 1/0/0
1/0t0
:ontrol ispGAL
;ontrol in-system programming. These pins areare not
not associated ispGAL16Z8
ispGAL16Z8
UO/Q
3 I/0/0 1/0/0
1/0/0
'lith
vith normal logic functions and
and are used only during program- NC
NC NC
NC 16Z8 1/0/0
1/0/O
ning This 4-pin interlace
fling and diagnostic operations. This interface allows an Top
Top View
View UO/Q
1 1/0/0
110/0
1/0t0
mlimited number of devices to be cascaded to form a serial
inlimited number WO/Q
I1010
UO/O
1/0/0
)rogramming
>rogramming and diagnostics loop. WO/Q
3 II010
00/0
I/0/0
Jnique test circuitry and

and reprogrammable cells allow complete
complete 14
,2E, SOl
SDI SDO
SDO
GND 12 13 I/oE
hOE
\C, DC, and functional testing during manufacture. Therefore,
Therefore, GNI)
-ATTICE
_ATTICE is able to guarantee 100% field programmability and
unctionalily
unctionality of all GAL- products.
GAL® products.
:opyright
opyright CI991 Lattice Semiconductor Corp. GAL,
01991 Lattice GAL. E'CMOS and UltraMOS
PCMOS and LlitraMOS are
are registered trademarks of Lattice
trademarks of Lattice Semiconductor
Semiconductor Corp. Goneric Array
Corp. Generic Array Logic is aa trademark
Logic Is of Lanico
trademarkof Lattice Semlconduc·
Serniconduc.
"Corp. PAL is
Dr Corp, PAL Is aa registerod
registered trademark
trademark of
of Advanced Micro Dovlcos.
Advanced Micro Inc. The
Devices, Inc. The specifications
specifications and Information heroin
and information herein are
are subject
subject to
to change
change without
without notice.
notice.
.ATTICE SEMICONDUCTOR CORP.,

.ATTICE SEMICONDUCTOR 5555 N.E.
CORP., 5555 N.E. Moore
Moore Ct., Hillsboro. Oregon
Ct., Hillsboro, Oregon 97124, U.S.A.
97124, U.S.A. A p r i April
l 1991.Rev.A
1991.Rev.A
reI. (503) 681-0118 or
Eel. (503) or 1-800-FASTGAL;
1-800-FASTGAL; FAX (503)
(503) 681-3037
681-3037
2-121
1 it„LILattice®
Semiconductor
Semiconductor ispGAL16Z8
Specifications ispGAL 16Z8
Corporation
CorporaUon
ispGAL-16Z8
ispGAL 16Z8 ORDERING INFORMATION

Tpd (ns)
(na) Tau
Isu (n8)
(ns) Tco
Too (na)
(ns) Inc (mA)
lcc(mA) Ordering #
Ordering' Package
Package
20 15
15 15
15 90
90 ispGAL16Z8-20LP
ispGAL16Z8-20LP 24-Pin
24-Pin Plastic
Plastic DIP
DIP
90
90 ispGAL16Z8-20LJ
ispGAL16Zi3-20L,J 28-Lead
28-Lead PLCC
PLCC
25 20 15 90 ispGAL 16Z8-25LP
ispGAL16Z8-25LP 24-Pin
24-Pin Plastic
Plastic DIP
DIP
90
90 IspGAL16Z8-25LJ
ispGAL16Z8-25LJ 28-Lead
28-Lead PLCC
PLCC
xxxxxxxx - xx
XXXXXXXX — XX XX XX X
1spGAL16Z8 DDevIce
ispGAL16Z8 e v i c e Name
Speed (ns) 1...-_ _ _ Grade

Grade BBlank
Commercial
L = Low Power Power

Power - - - - - - - - - ' Package PP =
Package = Plastic
Plastic DIP
DIP
JJ == PLCC
PLCC
2-122
2-122 4 / 9 1 . R e v .4/91.Rev.A
A
[jJ
tis
1.J
Lattice
Lattice
Semironducwr
Semiconductor
Corporation
Gl
1spGAL16Z8
!

macrocell. I Itt should
should be
be noted
noted that actual
actual implementation is PALArchltactur
PAL Architectures
.. 1spGAL16Z8
IspGAL16Z8
accomplished by development software/hardware com-
softwarelhardware and is com- Emulated by
Emulated by IspGAL
i5pGAL16Z8
l6Z8 Global
Global OLMC
OLMC Mode
Mode
pletely transparent to the user.
16R8
16R8 Reglstared
Registered
There are three global OLMC configuration modes possible:
OlMC configuration 16R6
16R6 Reglslared
Registered
simple, complex, and and registered. Details
Details of each ofof these
these 16R4
16R4 Reglslared
Registered
modes is illustrated
illustrated in the following pages. Two SYN
Two global bits, SYN l6RP8
16RP8 Reglalared
Registered
16RP6
16RP6 Reglstared
Registered
and ACO,
ACO, control thethe mode configuration for all macrocells, thethe 16R134
l6RP4 Registered
Registered
XOR bit of each macrocell controls the the polarity
polarity of the output in
in
any of the three modes, and the AC1 bit bit of each of the macro- l61.8
16L8 Complex
Complex
cells controls the input/output
inpuUoutput configuration.
configuration. These
These two global
global l6HS
16H8 Complex
Complex
and 16 individual architecture bits define all possible configura- 16P8
16P8 Complex
Complex
tions in an ispGAl16Z8.
ispGAL16Z8. TheThe information given on on these
these archi- 101.8
1018 Simple
Simple
tecture bits is only to give a better understanding of the the device. l2L6
12L6 Simple
Simple
Compiler software will transparently set these architecture bits bits l4L4
14L4 Simple
Simple
from the pin definitions, so the user should not need to directly l6U
161.2 Simple
Simple
manipulate these architecture bits. 10HS
10H8 Simple
Simple
l2H6
12146 Simple
Simple
l4H4
14144 Simple
Simple
The following is a list of the PAL
PALarchitectures
architectures that
that the GAL 16V8,
GAL16V8, 16H2
16142 Simple
Simple
and therefore the ispGAL16Z8,
ispGAl16Z8, can can emulate. ItIt also shows the 10P8
10P8 Simple
Simple
OlMC
OLMC mode under which the ispGAL16Z8
ispGAl16Z8 emulates the the PAL
PAL l2P6
12P6 Simple
Simple
architecture. l4P4
14P4 Simple
Simple
16P2
16P2 Simple
Simple

Software compilers support the three different global OlMC OLMC When
When using compiler
compiler software
software to to configure
configure the
the device,
device, the
the user
user
modes as different
different device types. These device types are listed must
must pay special
special attention
attention to
to the
the following
following restrictions:
restrictions:
in the table below. Most
Most compilers
compilers have thethe ability to
to automatically
automatically
select the device type, generally based on the register
register usage andand In
In registered
registered mode
mode pin'1 and pin
pin 1 and pin 13
13 are
are permanently
permanently config-
config-
output enable (OE) usage. Register
Register usage on the device forces ured
ured as
as clock
clock and
and output
output enable,
enable, respectively. These pins
respectively. These pinscannot
cannot
the software to choose the registered mode. All All combinatorial
combinatorial be
be configured
configured as dedicated inputs in in the
the registered
registered mode.
mode.
outputs with OE controlled by the product term will force force the
software to choose the complex mode. The The software will will choose
choose In
Incomplex
complex mode mode pinpin 1 and
and pin
pin 13
13 become
become dedicated
dedicated inputs
inputs and
and
the simple mode only when all all outputs
outputs are dedicated combina-
combina- use
use the
the feedback
feedback paths
paths of pin 22
of pin 22 and
and pin
pin 15 respectively. Be-
respectively. Be-
torial without OE control. The
The different device types
types listed in the
the cause of
cause of this
this feedback
feedback path
path usage,
usage, pin
pin 18
18and
andpin
pin 19
19 do
do not
nothave
have
table can be used to override
override the automatic device selection by by the
the feedback
feedback option
option in
in this
this mode.
mode.
the software. ForFor further details, refer to
to the
the compiler
compiler software
manuals. In
In simple
simple mode
mode allall feedback
feedback paths
paths ofofthe
theoutput
output pins
pins are
are routed
routed
via
via the
the adjacent
adjacent pins.
pins. In doing
doing so,
so, the twoinner-most
the two inner-most pins
pins (( pins
pins
The ispGAl16Z8
ispGAL16Z8 cancan be treated as a GAL 16V8, and tools are
GAL16V8, are 18
18 and 19) will
will not have feedback,
feedback, as as these
these pins
pins are
are always
always
provided by Lattice
lattice to
to use GAL 16V8 JEDEC files to program
GAL16V8 configured
configured as dedicated combinatorial
combinatorial output.
output. All macroceUs
macrocells are are
ispGAl 16Z8 devices.
ispGAL16Z8 always
always either
eitherdedicated
dedicated inputs
inputs or
ordedicated
dedicated outputs
outputs ininthis
this mode.
mode.
Registered Complex
Complex Simple
Simple Auto
Auto Mode
Mode Select
Select
ABEL P16V8R
P16V8R P16V8C
P1 6V8C P16V8S
P16V85 P16V8
P16V8
CUPL
MIK G16V8MS
Gl6V8MS G16V8MA
G1 6V8MA G16V8S
G16V8S G16V8
G1 6V8
LOG/IC GAL16V8 R R GAl16V8
GAL16V8 C7C7 GAL16V8
GAL16V8 C8C8 GAl16V8
GAL16V8
OrCAD-PLD "Registered"'
"Registered" "Complex"'
"Complex" "Simple"'
"Simple"' GAL16V8A
GAL16V8A
PLDeslgner
PLDesigner P16V8R2
P16VEIR2 P16V8C2
P16V8C2 P16V8C2
P16V8C2 P16V8A
P16V8A
TANGo.PLD
TANGO-PLD G16V8R
G1 6V8R G16V8C
G16V8C G16V8AS3
G1 6V8AS3 G16V8
G16V8
1) with Configuration
Used with
1) Used Configuration keyword.
keyword
Prior to
2) Prior to Version 2.0 support.
Version 2.0
3) Supported
Supported on Version 1.20 oror later.
later.
2-123 4191.Rev.A
4/91.Rev.A
!IJLattiOO-
LLattice'
1.J Corporation
Semiconductor
SemironducWr ispGAL16Z8
Specifications ispGAL 16ZB
REGISTERED MODE
REGISTERED
In the Registered mode, macroceUs
macrocells are configured as dedicated this
this mode. Dedicated input
mode. Dedicated input or
or output
output functions
functions can
can be
be Imple-
imple-
as 1/0
registered outputs or as functions.
I/0 functions. mented
mented as
as subsets
subsets of
of the
the I/O
I/0 function.
function.

to Registered outputs
Registered outputs have
have eight
eight product
product terms
terms per
per output.
output. I/0's
1I0's
the common 16R8 and 16RP4 devices devices with
with various
various permuta-
permuta- have
have seven
seven product
product terms
terms per
per output.
output.
tions
tions of polarity, I/O
110 and register
register placement.
placement.
The JEDEC
The JEDECfuse fuse numbers,
numbers, including
including the
the User
UserElectronic
ElectronicSigna-
Signa-
All registered macrocells share common clock and output en- en- ture
ture (UES)
(UES) fuses
fuses and
and the
the Product
ProductTerm
Term Disable
Disable (PTD)
(PM) fuses,
fuses, are
are
able control pins. Any
Any macroceU
macrocell can
can be configured
configured as registered shown
shown onon the
the logic
logic diagram
diagram onon the
the following
following page.
page.
or I/O. Up
Up to eight registers or up
up to
to eight I/O's
I/0's are possible in
elK
CLK
Registered
Configuration for
for Registered
Registered Mode
Mode
-SYN-O.
- SYN-0.
-ACO.1.
- AC0-1.
-- XOR-O
X0R-0 defines
defines Active
Active Low
Low Output.
Output.
--XOR.1
X0R-1 defines Active
Active High
High Output.
Output.
-- AC1-0
AC1=0 defines
defines this
this output
configuration.
-- Pin
Pin 1 controls common
common CLK CLK for
for the
the registered
registered outputs.
outputs.
-- Pin
Pin 13
13 controls
controls common
common OE OE for
forthe
the registered
registeredoutputs.
outputs.
-- Pin & Pin
Pin 1 & Pin 13
13 are
are permanently
configured asas CLK
CLK
and OE.
and OE.
:. .....................................................
OE
OF
·...........
·
_- .................................
.. Combinatorial
Configuration for
for Registered
Registered Mode
Mode
-SYN-O.
- SYN-0.
-ACO.1.
- AC0-1.
-- XOR.O
X0R-0 defines
defines Active
Active Low
Low Output.
Output.
-- XOR",1 defines Active
High Output.
Output.
-- AC1.1 defines this
AC1=1 defines this output
configuration.
-- Pin 1 &
& Pin 13 are
are permanently
configured as
as ClK
CLK
and
and OE.
....... -...............................................
Note: The development software configures aU

all of
of the
the architecture
control bits
bits and checks
checks for
for proper
properpin
pin usage
usage automaticaUy.
automatically.
2-124 4191.Rev.A
4/91.Rev.A
Lattice® ispGAL16Z8
Semiconductor
Corporation
DIP (PLCC) Package

DIP Pinouts
Package Pinouts
2 ) E .--..
1 ((2) ......,
: ) .
.......
0 4 8 1 2 116
12 6 220
0 224
4 2 28
8 PT02128
0000
0000
11111111111111111111111111111•1111111111111
1111111
OLMC 222
OLMC 2 rJ - 22 (26)
22 (26)
33 ((4)
4)
.--..
'--"
... 0224
0224
•
-=- X0R-2048
XOR-2048
AC1 2 1 2 0
ACl-2120
11111111111111111111111111111111111
0 2 56
0256
111111111111111111•11111111101111ffillelll
OLMC 221
OLMC 1 1
--t J 221
1 ((25)
25)
0480
0480 =B= XOR-2049
XOR-2049
.--..
......,
4 ((5)
5) AC1-2121
ACI-2121
111111
11111111111111111111111111111
0512
0512
nirniiiiiiini•mrniirnirnni• U . .
M E R P I N E R I M E N i i i r M EI=E
rgi
OLMC
OILMC 220
0 IJ - 20 (24)
20 (24)
5 ((6)
6)
.--..
'--'
... 0736
0736
XOR-2050
XOR-2050
AC I 2 1 2 2
ACl-2122
0768
0768
1111111M1111111111111111111111M11111......
111411 l
6 ((7)
7) - 0992
0992
SEREMESERESISEIESEMEELEMESEE
onomemmon
-,..,
OLMC
OLMC 119
9
XOR-2051
XOR-2051
ACI-2123
AC1-2123
0- 1 E 2 1 19
9 ( (22)
22)
111111611
1111111111111 I I III
1024
1024
ummonounnummolumummien IJ -
7 ((9)
9)
.--..
'--"
1248
1248
illEESSEETEMEREEMBIESISEE=SIE
-c;,-
Innommoolmam•P . 1 1 1 1 1 1 1 1 M E M E N
OLMC
OLMC 118
8
XOR-2052
XOR-2052
ACI-2124
AC1 2 1 2 4
0- I>e 1 8 ((21)
18 21)
1280
1280 IlIulIluIllullIll11111 MEM'
11111111MIIMMINIMMEMEMIMMIII "] -
8 ((10)
10) - h
1504
1504
ilismEisisigurapswilamail
iiiiiiiiiiiiiiiiiiiriiiiiiiilaiii
IIIMEM1NIMMII1IE011111111111111•11 1 • 1 1 1 1 1 1 1 • 1 1 1 1 1 • 1 1 1 1 1 1
OLMC
OLMC 117
7
XOR-2053
X0R-2053
ACI-2125
AC1 2 1 2 5
0-
-t>0 g=4 1 17
7 (20)
(20)
1536
1536
-=- IJ
1 1 ) E .--..
9 ((11) ......,
p - - - - C ; 3
1760
1760
1=UMIO...1=
=MENEM
o l p d
go
a=
OLMC
OLMC 116
6
XOR-2054
XOR-2054
ACI-2126
AC1-2126
0- 1=5 16 (19)
1792
1792 1 1 1 1 1 0
1 -
0--
1 1 1 1 1 / 1 / 1 / 1 1 1 / 1 1 1 1 M E E 1 1 1 1 1 1 1 1 1 1 / 1 1 . 1 1 1 1 1 1 1
:Q:: OLMC
= O M = go M O O =
OLMC 115
5 1".• 15 (18)
..
" W E 111
2016
2016 XOA-2055
.--.. XOR-2055
10 ((12)
12)
'--'
I-FfR ACl-2127
AC1-2127
........ OEE '-' 13
13 (16)
(16)
64 USER SIGNATURE 21
21991
1
64 U SER S I G N A T U R E FFUSES
USES
2056, 2 0 5 7 , ( U E S ) _ 2 1 1 8 , 2 11 9 SYN-2192
SYN-2192
Byte 7,10y0t o o , r . a l Byte 4 0 y t e ' B y t e a }Byte 1 lityle a
ACO-2193
AC0-2193
M lL
TC
TO - 2
2194
194
SS 0
S
B0 B
2·125
2-125 4 / 9 1 . R e v .4191_Rev_A
A
[JJ
1...1 m
S
, e iconductor
LatUce
'Lattice° Semiconductor
Corporation
Corporation
GP
Specifications ispGAL
ispGAL16Z8
16ZB
COMPLEX MODE
In the Complex mode, macrocells are configured as output only pability. Designs
Designs requiring eight liO's
I/0's can
can be
be implemented
implemented in
inthe
the
1/0 functions.
or I/O Registered mode.
Registered mode.
similarto
Architecture configurations available in this mode are similar to All macrocells
All macrocells have
have seven
seven product
product terms
termsper
peroutput.
output. One product
One product
the common 16L8 and 16P8 devices withwith programmable polarity
polarity term is
term is used
used for
for programmable
programmableoutput
outputenable
enable control.
control. Pins and
Pins 1 and
in each macrocell. 13 are
13 are always
always available
available as
as data
data inputs
inputs into
into the
the AND
AND array.
array.
I/0's are possible in this mode. Dedicated

Up to six I/O's inputs or
Dedicated inputs The JEDEC
The JEDEC fuse
fuse numbers
numbers including
including the
the UES
UES fuses
fuses and
and PTD
PTD
outputs can be implemented as subsets of the
subsets of the I/O function.
function. The fuses are
fuses are shown
shown on
on the
the logic
logic diagram
diagram onon the
thefollowing
following page.
page.
two outer most macrocells (pins 15 & 22)
22) do
do not
not have
have input ca-
ca-
...............................................
'
,,,
,
,,, Combinatorial
Combinatorial 110
I/O Configuration
Configuration for
for Complex
Complex Mode
Mode
rl -- SYN=1.
SYN= 1
-ACO.1.
- AC0=1
-- XOR
X0R-0..Odefines
defines Active
Active Low
Low Output.
Output.
-- XOR-1
XOR-1 defines Active
Active High
High Output.
Output.
-AC1=1.
-AC1=1.
-- Pins
Pins 16
16 through
through Pin
Pin 21
21 are configured
configured to
to this
thisfunction.
function.
........................................................,
,
f .... ·........ ······· . ·· . ·········· . ······ ......: Combinatorial Output Configuration

Combinatorial Output Configuration for
for Complex
Complex Mode
Mode
!
;
PeD XOR
· tL-o -- SYN-1.
SYN=1.
-ACO.1.
- AC0=1.
- XOR=O
XOR=0 defines
-- XOR=1
-AC1=1.
AC1-1.
-- Pins
defines Active
Pins 15 and
Active Low
XOR-1 defines Active
Low Output.
Active High
Pin 22
and Pin 22 are
Output.
High Output.
Output.
are configured
configured to
to this
this function.
function.
t ...............................................!
Note: The development software configures all of the

the architecture control
control bits
bits and
and checks
checks for
for proper
proper pin
pin usage
automatically.
2-126
2-126 4191.Rev.A
4191 .Rev.A
Ii
..LJ21Lattice
Semiconductor
Semiconducwr ispGAL16Z8
Corporation
CorporaUon
COMPLEX MODE LOGIC DIAGRAM

DIP Pinouts
11(2)
(2) E D -- ...
POD 2128
00 4 4 8 8 1 12
2 1t6
8 220
0 224
4 228
8
I.l...
-
0000 _
0000
!!!!!!!!ILVEHELPMENIMPIn'l•- • .......
== OLMC
OLMC 222
2 22 (26)
22 (28)
--
0224
0224 SO II• 2048
XOR-2048
33 (4)
(4) AC .'''0
0256
11111111111111111111111:;_
I.l.
0256
.......
ouo==
::8::::::
4 (5)
415) '-"
0480= OLMC
OLMC 221
1
XOR•2049
XOR-20H
AC1- 2121
AC1- 212'
t!'"
J- E D 2 12,( 2(25)
5)
0512
0512
=
.;:; •
=LIPI11•EEIRT•1!1•1 !!!!!mniral: OLMC
OLMC 220
0 n. .......-
- - - 1 4 4 ) - 1 : 3 1 2 020) 2(24)
4)
5 (6) - 0738
= XOR•2050
XOR·20S0
ACI•2122
AC,·2'22
1111111111111 0 I M E H M 1111111
I.l....
0788
0768
•!!!!!!!!!!!!!MEMERE! !!!!!!•":6111
OLMC
°LAIC 119
9 H E
...........
I I 199 ((22)
22)
6 ((7)
7) -- 0992
0992= X O R • 2 -c-0 5 I
XOR·205'
ACI•21 23
AC,·2,23
,024
1024 _
.n- h
7(9)
719) '-"
1248
11 1 1 1 1 1 w i w a
OLMC
OLMC 118
8
XOR-2052
XOR• 20 52
ACI•2124
AC1-2'24
U- 18)21)
'8 (2')
h ...
--......
1280 ....
'280
:: " t i 2 T H I M I C H E M E E . 1 . 7 1 . . OLMC
OLMC 117
7 17
17 (20)
(20)
=
,1504
504= XOR·2053
XOR•2053
AOI•2125
(10)
8110) D 4 a n n o n o m o n s u m o o n e s t i o s e s o m
lm
te
a
l
o
e AC'·2'25
IIIOIIIOIIOI1111111111
I.l...
1536
= !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!PWIm OLMCOlin 116
6 -C '6(18)
1760
780 ::
111 3 111 5 111 5 i 11 3 1111 M E R I N I E
..... XOR-20S.
XOR• 2054
AC,·2126
99 ((11)
11 ) ACI•2126
'-'
11111111111111111111111111118
1792
1792
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!•W4111
142 OLMC
OLMC 1155
I.l... -....... 15 (18)
15(18)
2016
201 6 XOR· 2055
XOR•2055
Ifl
I!i::'
10(12)
10 (12) D
E>-----td AC'·2127
AC1•2127
.,....,
C I 1 3'3 ((16)
16)
2'91
2191
U USER S
64 USER SIGNATURE FUSES
I G N AT U R E FUSES
SYN-2192
$YN•2192
2056. 2057 ( U E S ) I f S . 2111 ACO·2193
AC0•2193
··• .,•
Ilaytt 8 1 8 ' . 819,te 818yte 312818 I 18818 1188818
TC
TO • 2194
2-127
2-127 4 / 9 1 . 1 R e v 4/91.Rev.A
. A
[JJLattiOO*
Lattice®
.J..j Semiconductor
Corporation
CorporaUon
1spGAL16Z8
SIMPLE MODE
In the Simple mode, macrocells are configured as dedicated in- Pins
Pins 1 andand 13
13 are
are always
always available
available as
asdata
data inputs
inputs into
intothe
theAND
AND
puts or as dedicated, always active, combinatorial outputs.
outputs. array.
array. The center
centertwo
two macrocells
macrocells (pins
(pins 18 & 19)
18 & 19) cannot
cannotbe be used
used
in
in the
the input
input configuration.
configuration.
to
the common 10L8
10L8 and
and 12P6 devices with many permutations The JEDEC
The JEDEC fuse
fuse numbers
numbers including
including the
the UES
UESfuses
fuses and
and PTD
PTD
of generic output polarity or input choices. fuses
fuses are
are shown
shown on
on the
the logic
logic diagram.
diagram.
All outputs in the simple mode

mode have a maximum of eight eight prod-
prod-
uct terms that can control the logic. In
In addition, each
each output
output has
l·································· __ ····· __ ·· Combinatorial

Configuration for
for Simple
Simple Mode
Mode
Vee
SYN-1.
- SYN-1.
-ACO.O.
- AC0-0.
-- XOR.O
XOR-0 defines
defines Active
Active Low
LowOutput.
Output.
-- XOR.1
X01:1-1 defines Active
Active High
High Output.
Output.
-- AC1.0
AC1=0 defines
defines this
this configuration.
configuration.
-- All
All OLMCs
OLMCs can
can be
be configured
configured to
to this
this configuration.
configuration.
. . -- Pins
Pins 18 & 19 are
18 & are permanently
configured to to this
this
=---............................................................. .: function.
function.
..- ............ ---- ............................ Dedicated

Dedicated Input Configuration
Configuration for
for Simple
Simple Mode
Mode
-- SYN.1.
SYN-1.
-ACO.O.
- AC0-0.
-- XOR.O
XOR-0 defines
defines Active
Active Low
Low Output.
Output.
-- XOR.1
X0R-1 defines Active
Active High
High Output.
Output.
-- AC1.1
AC1.0 defines this
this configuration.
configuration.
--All
All OLMCs
OLMCs except
except pins
pins 18 & 19 can
18 & can be
be configured
configured to
to
this
this function.
function.
Note: The development software configures all of the

the architecture control
control bits
bits and checks
checks for
for proper
proper pin
pin usage
automatically.
2-128
2-128 4/91.Rev.A
4/91.Rev.A
Lattice®
.l.J
I S e m iSemiconductor
conductor
Corporation
1spGAL16Z8
DIP (PLCC)
DIP (PLCC) Package Pinouts I
17(2)
(2) E .......
> E> ...
v
00 • 4L 4 88 1 12162024
2 I S 2 0 2 4 228
8 PTD 212
0000
OLNIC 22
OLMC
XOR-2048
XOR-2048
IJ - I C i 222
2 ((26)
26)
0224
0224 AC - 2 1 2 0
ACl-2120
33 ((4)
4) D-
0256
IMINIERME•ILIBILTIVII OLIAC 21
OLMC
h... rO 27)28)
....
13= XOR-2049
XOR-2049 21 (25)
0480 ACI-212
ACl-2121
44 (5) D
toilliniiiiiiiini
im,— 1
Miiiiiiiiiii
n enoor o
m
tn
u
m
m
ito
m
n
o
4
I I I 1111111111111111111111111
IJ...
-
0512
;::;. OLMC 20
OLMC 20
1-
XOR-2050
XOR-2050 20 (24)
20 (24)
111111111111 3 11111111 0 1
55 ((6)
6) 0
0736
0736
eln1
• in1 1
leiI imil LitinioiElIoioioiminiaI P noil ialiIli! m i . : 4
AC1-2122
ACl-2122
111111111111111111111111111111 I.l -
-
0768
0768
OLMC 19
OLMC 19
XOR-2051
XOR•2051 v 19
09)22)
(22)
6 (7) 0
0992
0992
iiiiiiiiiiiiiiiiiiiiiiiiiiiiiii ACl-2123
Ad1-2123
11111111111101111111111111ir
opur.Trprir:r7!=
1024
1024
OLMC
°LAIC 18
XOR-2052
XOR-2052
IJ... - K J 118
8 (21)
(21)
0
1248
1248
ISiiiiiiiiiiiiimliNiL4 't:J= ACl-2124
AC1-2124
1111111110111111IIIIIIIIIIIII
7 (9)
1280
1280
III•PRIEPIRPHIIIIIITI - = OLMC
OLMC 17
XOR-2053
XOR-2053
IJ... ..... 17 (20)
77)20)
1504
1504 ACl-2125
ACI•2125
8 (10) 0 HINEMMEIREilimmii
--
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
1536
1536
MEIMIMINIIIMIIIMMI OLMC 16
OLMC 16
XOR-2054
XOR-2054
IJ... - 166 ((19)
19)
1760
1760 ACl-2126
9 ((11)
11 )
iinollimminlimmiminsillim••=4
lliiiiiiiiiiiiinfiliir---- ACI-2126
IIIIIIIIIIIIIIIIIIIIIIIII 11111
1792
1792
EIII•MINIELIMH•HI•NI
iiintbiligifigillirtMft—
OLMC
OLMC 15 11... -.....
XOR-20551 1 1
XOR-2055 1 5 ( 1158(18)
)
2016 ACl-2127
ACI•2127
HilliiiiiiiiiiiiiiiiiMIIIII
n u lo
ononsont M
ionismilosem
m I
- nom
10
10 (12)
(12 ) I".:) I- 4 '--' 13 (16)
13(16)
2191
2191
64 USER SIGNATURE FUSES
64 USER FUSES
2056 2057...,. ( L I E S ) . . . 2 1 1 8 , 2110
., .,
B y . 7 1 3 , t o B y t e a l E l V t e * 1 0 , t e 31Byto 2 I B V t s I S Y t e 0 SYN-2192
SON-2192
• L ACO-2193
AC0•2193
S S TC
TC - 2194
2194
a 8
2-129 4/91_Rev_A
4/91.Rev.A
iILattice® Lattice® Specifications ispGAL
ispGAL16Z8
16Z8
.J"J Semiconductor
Semironductor
Corporation
CorporaUon Commercial
Commercial

COND.
-0.5 to
Vo, ........................................ -0.5
Supply voltage Voo to +7V Ambient Temperature
(TA) .............................
0 to +75°C
0 to +75°C
Input voltage applied ....................... -2.5 to Vee
voltage applied V „ +1.0V
+1.0V Supply voltage
Supply voltage (V
Nodeel
with Respect
with Respect to
to Ground
Ground .....................
+ 4 . 7+4.75 5 to to +5.25V
+5.25V
Off-state output voltage applied ...........-2.5toVe,+1.0V
-2.5 to Vee +1.0V
Storage Temperature .................................. -65-65 toto 150°C
- 5 5 -55 to
11.Stresses
. Stresses above those listed
listed under the "Absolute Maximum
Ratings· damage toto the
the device. These
These
are stress only ratings and functional operation
operation of the
the device
device
at any other conditions above those indicated in
at these or at in
the operational sections of this specification is
is not implied
the programming
specifications).
Specified)

CONDITION MIN.
MIN. TYR2
TYP." MAX.
MAX. UNITS
UNITS

Vss -0.5 -— 0.8
0.8 VV

2.0 -— Vcc+l
Vee+1 VV
ilL
IlL Input or I/O
110 Low
Low Leakage Current OV
OVSVIN
Y,N S V,l (MAX.)
VII_ (MAX.) -— -— -10
-10 IlHA
A
IIH
lIH VO High Leakage Current
Input or I/O V,H S VIN
1/11-15_ Y,N 5_
s Vee
Vcc -— -— 10
10 IlIIA
A
VOL Output Low Voltage lot_ = MAX.
10L- Yin
MAX. Vi n ..
= V,L
VIL or
or V,H
VIR -- -
- O.S
0.5 VV
VOH Output High Voltage 10H-.MAX. in =

lok =MAX. VYin = V,L
Vit. or
or V,H
VII-1 2.4
2.4 -— -— VV
10L
lOL Low Level
Level Output Current -— -— 24
24 mA
mA
10H
lOH High Level Output Current -— -— -3.2
-3.2 mA
mA
los'
lost Output Short Circuit Current Vee
Vcc =SV
,- 5V VOW- =
VOUT •--, O.SV TA == 2S·C
0.5V TA 25°C -30
-30 -— -1S0
-150 mA
mA
ICC Operating Power Supply Current VIL.O.SV
V1L = 0.5V VVIH
I H -3.0V
= 3.0V -— 7S
75 90
90 mA
mA
ftoggle
ttoggie ..
= 1SMhz Outputs Open
15Mhz Outputs Open
1) One
One output at a time for a maximum duration of oneone second. Vout ..
second. Vout = O.SV
0.5V was
was selected
selected to
to avoid
avoid test
test problems
problems caused
caused by
by
not 100t3/4, tested.
Typical values are at Vee
2) Typical .. SV
Vcc = 5V and TA
TA -= 2S
25 ·C
'C
(TA = 25°C, ff .7.-

CAPACITANCE (TA = 1.0 MHz)
SYMBOL PARAMETER
PARAMETER MAXIMUM"
MAXIMUM* UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
CI Input
pF Vee
Vec == S.OV,
5.0V, V,
V, == 2.0V
2.0V
ClIO
Cvo 1/0
I/O Capacitance 10
10 pF
pF Vee
Vec == S.OV.
5.0V, VIIO
Vvo == 2.0V
2.0V
"Guaranteed but not
*Guaranteed but not 100%
100% tested.
tested.
2-130
2-130 4191.Rev.A
4/91.Rev.A
'L
IL1!Lattice
Semiconductor
Semironductor
Corporation
1spGAL1 6Z8
16Z8
Commercial
Commercial
OVer
-20
·20 -25
·25
UNITS
PARAMETER
COND.' MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX.
tpd 1 Input or I/O to Combinational Output 33 20
20 33 25
25 ns
ns
tco
teo 11 Clock to Output Delay 22 15
15 22 15
15 ns
ns
tsu -— Time, Input or Feedback before

Setup lime, before Clocki
ClockT 15
15 -— 20
20 -— ns
ns
th -— Hold lime,
Time, Input or Feedback after Clocki
ClockT 00 -— 00 -— ns
ns
with 33.3
33.3 -— 28.5
28.5 -— MHz
MHz
fmax22
fmax li(tsu + teo)
External Feedback, 1/(tsu tco)
with 41.6
41.6 -— 33.3
33.3 -— MHz
MHz
No Feedback
twh
High 12
12 -— 15
15 -— ns
ns
twl
tW133 -
- Clock Pulse Duration, Low 12
12 -— 15
15 -— ns
ns
ten 2 110 to Output Enabled
Input or I/O -— 20
20 -— 25
25 ns
ns
2 OEI. to Output Enabled
OE! -— 18
18 -— 20
20 ns
ns
tdis 33 Input or I/O
20 -— 25
25 ns
ns
3 OEi
OEt to Output Disabled -— 18
18 -— 20
20 ns
ns
I) Refer to Switching Test Conditions section.
2)
a) Refer to fmax Description section.
3)
as valid clock signals.
Input
input Pulse Levels GNDto3.0V
GND to 3.0V
Times 3ns 10%
10%-90%
— 90% +5V
+5V
Input liming
Output Timing
liming Reference
1.5V
See Figure
eve!.
eve]. FROM OUTPUT (0/0)
FROMOUTPUT (0/0) --+---......- TEST
TESTPOINT
POINT
UNDER TEST
UNDERTEST
:>utput
Dutput Load Conditions (see
(see figure)
figure) Cl
CL
R2
R2
Test Condition RI
Ri Rz
R2 CL
CL
1 200n
200f1 390n
3902 50pF
50pF
2 Active High
Active
-
—
200n
390n
3900
390n
50pF
50pF
50pF C
CllNCLUDES
LINCLUDESJIG AND PROBE
JIGAND PR08E TOT
TOTAL CAPACITANCE
ALCAP ACITANCE
-
3 Active High
Active High 390n
3900 5pF
5pF
Active Low
Active Low 200n
2000 390n
3900 5pF
5pF
2·131
2-131 4/91.Rev.A
4/91.1RevA
LLattice°
.l..i Semiconductor
Semironductnr ispGAL16Z8
Corporation
SWITCHING WAVEFORMS
INPUTor
INPUT or INPUTor
INPUT or
VOFEEDBACK
110 FEEDBACK VALIDINPUT V O FEEDBACK
110 FEEDBACK
M S I V
4-tpd --10
COMBINATORIAL
COMBINATORIAL CLK
CLK
OUTPUT \\""I"T"'<""S\ /
OUTPUT t"T"'I'""T\\
4--to 040
REGISTERED
REGISTERED
OUTPUT
OUTPUT
4 - - I/ fmax---0
(external 'Obit)
INPUT
INPUTor Reg Istered Output
Registered Output
VOFEEDBACK
I/O FEEDBACK
4-- tdis 4 . I— ten -4.
OUTPUT
\ l---- OE
OE
OUTPUT
/ \_____
4 - t o Is 40 11-- te n --OP
Input or 110
I/O to Output Enable/Disable
OUTPUT
OUTPUT
\ 1—
/ \____
OE
OE to
to Output
Enable/Disable
* - - - tw h —1044— twl
tw I - - 1 ,
\
ClK
CLK
\
Clock Width
fmax
tmax DESCRIPTIONS
................................................................ CLK
ClK
LOGIC
LOGIC
OP'REGISTER
REGISTER
- 0 . ARRAY
ARRAY LOGIC
LOGIC
REGISTER
ARRAY
ARRAY . . - - 1 0 . - O P -
10IIII/00II1----
1. 111- - - - - -- to u
t S U t leo--+l
c o
fmax
fmax With
With No
No Feedback
Feedback
fmax with External Feedback 1/(tsu+tco)
li(tsui-tco)
Note:
Note: fmax with external
fmax with external feedback
feedback is
is cal·
cal-
culated
culated from
from measured
measured tsu and teo.
tsu and tco.
2-132 4/91.Rev.A
4/91.1Rev.A
Lattice®
tid
.l.J Semiconductor
Semiconductor
Corporation
ispGAL16Z8
16Z8
I

An electronic
electronic signature
signature (ES)
(ES) iis
s provided
provided aass part
part ofof the
the When testing
When testing state
state machine
machine designs,
designs, all
all possible
possible states
states and
and state
state
ispGAL16Z8
ispGAL 16Z8 device. ItIt contains 64 bits of
of reprogrammable
reprogrammable mem-
mem- transitions must
verified in
in the
the design,
design, notnotjust
just those
those required
required
ory that can contain user defined data. SomeSome uses include user in the normal
in normal machine
machine operations.
operations. ThisThis is is because,
because, in in system
system
ID codes, revision numbers, or inventory control. The
10 The signature operation, certain
operation, certain events
events occur
occur that
that may
may throw
throw the
the logic
logic into
into an
an
data is always available to the user independent
independent ofof the
the state of
of illegal state
(power-up, lineline voltage
voltage glitches,
brown-outs, etc.).
etc.).
the security cell. To test
To test aa design
design for
for proper
proper treatment
these conditions,
conditions, aa wayway
must be
must be provided
break the
the feedback
feedback paths,
paths, andand force
force any
any
NOTE: The
The ES is included in checksum calculations. Chang-
Chang- desired (Le.,
desired (i.e., illegal)
illegal) state
state into
intothe
the registers.
registers. Then
Then the the machine
machine
ing the ES will alter the checksurn.
checksum. can be
can be sequenced
the outputs
outputs tested
tested forfor correct
correct next
next state
state
conditions.
conditions.
SECURITY CELL The ispGAL
The ispGAL16Z8 devices include
16Z8 devices include circuitry
circuitry that
that allows
allows each
each reg-
reg-
istered output
istered output to
to be
be synchronously
either high
high or
or low.
low. Thus,
Thus,
ispGAL.16Z8
The security cell is provided on the ispGAL device to
16Z8 device to prevent
prevent any state
any state condition
condition can
can be
be forced
forced for
for test
test sequencing.
sequencing.
unauthorized copying of the logic pattern. Once programmed,
Once programmed,
this cell prevents further read access toto the
the functional bits in the
device. TheThe cell can only be erased by re-programming
re-programming the the INPUT BUFFERS
device, so the original configuration can never be examined once
this cell
cell is programmed. Signature
Signature data is always available to
The ispGAL
The ispGAL16Z8 devices are
16Z8 devices aredesigned
designed with
with TIL
TTLlevel
level compatible
compatible
the user.
input buffers.
input buffers. These buffers,
buffers, with
with their
theircharacteristically
characteristically highhigh im-
im-
pedance, load
pedance, load the
thedriving
driving logic
logic much
much less
less than
thantraditional
traditional bipolar
bipolar
LATCH-UP PROTECTION devices. Because
devices. Because the the inputs
inputs are
are connected
connected to to aa CMOS
CMOS gate,gate,
there is
there is no
no inherent
inherent pull-up
pull-up structure,
structure, asas there
there is
is with
with bipolar
bipolarde-
de-
The i5pGAL16Z8
ispGAL16Z8 devices are designed with an an on-board
on-board charge
charge vices. Therefore,
vices. they cannot
Therefore, they cannot be
be depended
depended on on to tofloat
float high
high (or
(or
pump to negatively bias thethe substrate. The negative bias
bias is of to any particular
to any particular state),
state), and
and must
must be
betied
tiedto
tothe
thedesired
desired logic
logicstate.
state.
sufficient magnitude to prevent input undershoots from causing
the circuitry to latch. Additionally, outputs are designed with
with n-
n- Unused
Unused inputs and and tri-stated
tri-stated I/Os
I/0s should
should no.tnot be
be left
left floating.
floating.
channel pullups instead of the traditional p-channel pullups
pullups to
to Lattice recommends
Lattice recommends that that they
they be
be connected
connected to to Vee,
Vcc, Ground,
Ground, or or
eliminate any possibility of SCR induced latching. another driven
another driven input.
input. Doing
Doing so so will tend to
willtend to increase
increase noise
noise immunity
immunity
and
and reduce Icc for
reduce Icc for the
the device.
device.
TCCELL
TC CELL
The i5pGAL16Z8
ispGAL16Z8 devices are equipped with a TC (Tri-State(Tri-State
Control) cell which controls thethe state
state of the outputs when
when the
device is being programmed. SinceSince the
the device is programmed
programmed
while onon the circuit board, and connected to other devices, the
state of the outputs is very important. Depending on how howthe
the TC
TC
cell is programmed, the outputs will either be
be tri-stated or latched
upon entering the programming/diagnostic mode. mode.
2-133 4/91.Rev.A
4/91.Rev.A
idLattice
Semiconductor
Semiconductor ispGAL16Z8
Corporation
> 0 — = PIN
PIN I >
Tri-S1ale
Tri-State
Control
Comrol
Vcc
:CIr.... :
i................. .l
u ••
PIN
PIN
PIN
PIN
Feedback
Feedback
(To InputBuHer)
(ToInput Butler)
Input Output
Output
POWER-UP RESET
90'7
Vee
Vcc
ov
OV
tpr--10.
VIH
V IH
eLK
CLK VALID CLUCKSIGNAl
VALIDCLOCK SIGNAL
VIL
V IL
t rese
INTERNAL INTERNAL
INTERNALREGISTER
REGISTER
INTERNAL- 1 = M
REGISTER
REGISTER RESET
RESETTO
TOLOGIC
LOGIC00
Q-OUTPUT
0-OUTPUT
OUTPUT PIN
OUTPUTPIN
Circuitry within the ispGAL.16Z8

ispGAL 16Z8 provides a reset
reset signal
signal to
to all The
The timing
timing diagram
diagram forfor power-up
power-up isis shown
above. Because of
registers during power-up. AllAll internal registers will have their
their asynchronous
asynchronous nature
nature01of system
system power-up,
power-up, somesomeconditions
conditions must
must
be
be met to
to guarantee
guarantee a valid
valid power-up
power-up reset. First, the
reset. First, the Vex;
Vc.crise
rise
o outputs set low after a specified time (t AESIiT
Q 45I1S MAX). As
REs, ,' 45p.s As
a result, the state on the registered output PinS
pins (if they
they are en-'
en- must
must be monotonic. Second, the
clock input
input must
must become
become aa
abled through OE) will
will always be high on power-up, regardless
always be regardless proper
properTTL
TIL level
level within
withinthe
the specified
specified time
time (t,R, 100ns
100ns MAX).
MAX). TheThe
of the programmed polarity 01 of the output pins. This feature
pins. This feature can
can registers
registers will
will reset
reset within
within a maximum
maximum 01 of tREse,time.
time. As
As in
in nor-
nor-
greatly simplify state machine design by providing a known state state mal
mal system operation,
operation, avoid
avoid clocking
clocking the
the device
device until
until all
all input
input
on power-up. and
and feedback
feedback path
path setup
setup times
times have
have been
been met.
met.
2-134
2-134 4191.Rev.A
4/91.1Rev.A

Datasheet Levels 2 - i i 2-ii
GAL16V8A/B
GAL16V8A1B 2 - 1 2-1
GAL20V8NB
GAL20V8A1B 2 - 2 5 2-25
GAL18V10 2 - 4 7 2-47
GAL22V10/B 2 - 6 1 2-61
GAL26CV12 2 - 8 1 2-81
GAL2ORA10
GAL20RA10 2 - 9 5 2-95
..
GAL6001 2 - 1 0 9 2-109
ispGAL16Z8 2 - 1 2 1 2-121

Military Program Overview 3 - 1 3-1 I
MIL-STD-883C Flow 3 - 2 3-2
GAL16V8A/B
GAL 16V8A1B Military Datasheet 3 - 5 3-5
GAL20V8A Military
Military Datasheet 3 - 1 3 3-13
GAL2ORA10
GAL20RA 10 Military Datasheet 3 - 2 7 3-27

Quality Assurance Program 4 - 1 4-1 4
FCMOS 4 - 5 4-5

GAL Metastability Report 5 - 1 5-1 5

Avoid the Pitfalls of High-Speed Logic Design 6 - 1 6-1 6
Extending the 22V1
22V10 0 EPLD 6 - 7 6-7
In-Circuit Logic Device Can be Reprogrammed onon the
the Fly 6 - 96-9
Development Tools 7 - 1 7-1
Copyil\lg
7
GAL Product Line Cross Reference 7 - 5 7-5
Package Thermal Resistance 7 - 8 7-8
3-i
3-i
3-ii
3-ii
Program
Military Program
Overview
OvelView
CORPORATE PHILOSOPHY MIL-STD-883C
MIL—STD-883C COMPLIANCE
COMPLIANCE
Lattice Semiconductor is is committed
committed to to leadership
leadership in in MIL—STD-883C provides
MIL-STD-883C provides aa uniform
uniform and
and precise
precise method
method
performance and
performance and quality.
quality. OOur
u r family of military
military GAL
GAL forenvironmental,
for environmental, mechanical
mechanical and andelectrical
electricaltesting
testingwhich
which
devices isis consistent
consistent with
with this
this philosophy.
philosophy. Lattice
Lattice ensures the
ensures the suitability
suitability of
of microelectronic
microelectronic devices
devices for
for use
use
manufactures all devices
devices under strict Quality Assurance in military and
in and aerospace
aerospace systems.
systems. Table summarizes
Table I summarizes
guidelines. All Commercial through
All grades, Commercial through Military
Military 883C,
883C, the MIL—STD-883C,
the MIL-STD-883C, Class Class BB flow.
flow. Table
Table /III summarizes
summarizes
are monitored under a a quality
quality program
program conformant
conformant to to M
MIL-
IL- the conformance
the conformance testing
testing required
required by MIL-STD-883C,
MIL-STD-883C,
M-38510
M-3851 0 Appendix A with inspections conformant
conformant to to MIL-
M IL- Method 5005,
Method 5005, for quality
quality conformance
conformance testing
testing ofof Lattice
Lattice
1-45208. military microcircuits.
military microcircuits.
Semiconductor hashas been
been manufacturing
manufacturing GAL
GAL MIL-M-38510
MIL-M-38510
devices since
since 1984.
1984. T The
h e engineering
engineering analysis
analysis and
and MIL—M-38510,
MIL-M-3851 when used
0, when used in
in conjunction
conjunctionwith
withMIL-STD-
M IL—STD-
III
characterization during this time has been focused into
into 883C, defines
883C, defines design,
design, packaging,
packaging, material,
material, marking,
marking,
our current
current design,
design, process
process and
and manufacturing
manufacturing test
test sampling, qualification and
sampling, and quality
quality system
system requirements
requirements
procedures toto assure
assure superior
superior product
product which meet
meet all for military
for military devices.
devices.
datasheet and quality goals. I
GROUP
GROUP DATA
Complete review
review of the
the procedures and technical data Group A
Group A and B
B data
data is
is taken
taken on
on every
every inspection
inspection lot per
per
can be
be arranged
arranged at
at our facility near Portland,
Portland, Oregon.
Oregon. MIL-STD-883C, Class
MIL-STD-883C, Class B B requirements.
requirements. This data, along
This data, along
Factory audits of our documentation and processes are with Generic Group
with Group CC and
and D data
data can
can be
be supplied,
supplied, upon
upon
also welcomed. written request,
written with your
request, with your device
device shipment.
shipment. Your Lattice
Lattice
sales representative
sales representative can
can advise
advise you
you of charges
charges and
and
QUALITY AND TESTABILITY leadtime necessary
leadtime necessary for
for providing
providing this
this data.
data.
processes its GAL devices
Lattice Semiconductor processes devices to to strict
strict
conformance with
with MIL-STD-883C
MIL-STD-883C Class B. B. In conjunction
conjunction STANDARD
STANDARD MILITARY DRAWINGS
with the military flow,
flow, the inherent testability of E2CMOS
E2CMOS Lattice actively
Lattice actively supports
supports the DESC
DESC Standard
Standard Military
Military
Latticeto
technology allows Lattice to achieve aaquality
quality level
level superior
superior Drawing (SMD)
Drawing (SMD) Program.
Program. The
The SMD
SMD Program
Programoffers
offers aacost
cost
to other PLD technologies. effective alternative
effective alternative to
to source
source control
control drawings
drawings andand
provides standardized
provides standardized MIL-STD-883C product product
All GAL devices are patterned and tested dozensdozens of times
times specifications to
specifications to simplify military procurement.
procurement.
throughout the manufacturing flow. Every Every GAL device is
tested under
under worst
worst case
case configurations
configurations ttoo assure
assure Lattice recognizes
Lattice recognizesthe thegrowing
growingdemand
demand for
forSMD
SMDqualified
qualified
customers achieve
achieve 100%
100% yields. TestsTests are performed devices, and
devices, and inin response,
response, allall new
new 883C
883C product
product released
released
using the same E2 for the
E2 cell array that will be used for the final
final by Lattice
by Latticewill
willbebesubmitted
submittedto to DESC
DESCforforSMD
SMDqualification.
qualification.
patterning ofof the
the devices.
devices. T This
h i s 100%
100% "actual
"actual test"
test" Customers may facilitate
Customers this process
facilitate this process by submitting
submitting a
philosophy does away with the correlated and simulated
simulated "Nonstandard Part
"Nonstandard Part Approval
Approval Request",
Request", DDDD Form
Form 2052,
2052,to to
testing that is necessary withwith bipolar and UV (EPROM) DESC. This
DESC. form allows
This form allows you
you to
to recommend
recommend to to DESC
DESC thethe
based PLD devices. qualification of Lattice devices to
qualification to SMD
SMD status.
status.
RELIABILITY A list
A list of currently
currently available
available SMD
SMD qualified
qualified devices
devices is
performs extensive
Lattice Semiconductor performs extensive reliability
reliability testing
testing provided (see
provided (see Military
Military Ordering
Ordering Information).
Information). Contact
Contact
to product release. This testing
prior to testing continues
continues inin the
theform
form local Lattice
your local Lattice sales
sales representative
representative forthe
for thelatest
latest status
status
of Reliability Monitors that are run on an ongoing basis to to of SMD
of SMD qualifications
qualifications inin process
process with
with DESC.
DESC.
assure continued
continued process
process integrity.
integrity. AA formal,
formal, written
written
report of these
these test
test results is updated
updated regularly
regularly and
and cancan bebe
obtained from your local Lattice Sales Representative.
The reliability testing performed

reliabilitytesting performed includes extensive
extensive analysis
analysis
of fundamental
fundamental designdesign and
and process
process integrity.
integrity. TThe
he
reprogrammable nature nature of
of GAL
GAL devices
devices allows
allows for an
other
inherently more thorough reliability evaluation than other
programmable alternatives.
3-1
3-1
Mffitary Program
Military Program Overview
MILITARY
MILIT ARY SCREENING FLOW MILITARY QUALITY
MILITARY CONFORMANCE
QUALITY CONFORMANCE
(TABLE I) INSPECTIONS (TABLE II)
INSPECTIONS II)
Screen Method
Method Requirement
Requirement Subgroup M e t hMethod
Subgroup o d S a m pI Sample
l e
I Internal Visual 2010 Cond. B 100%
100% I GROUP
GROUP A: Electrical
Electrical Tests
ests
Temp. Cycling 1010 Cond. C
1010Cond. 100%
100% Subgroups 1,
Subgroups " 7,
7, 9 Applicable Device
Applicable Device Spec.
Spec. LTPD == 22
LTPD
Constant Acceleration 2001 Cond.
2001 Condo E 100%
100% Electrical Test
Electricel Test 25°C
25°C
Hermeticity
Hermeucity 1014
1014 100%
100% Subgroups 2,
Subgroups 2, 8A,
BA, 10 Applicable Device
Applicable Device Spec.
Spec. LTPD = 22
LTPD=
Fine Cond. A or B
Cond.AorB Electrical Test
Electrical Test Max. Operating
Max. Operating Temp.
Temp.
Gross Cond.C
Cond. C Subgroups 3,
Subgroups 3, 88, 11
8B, 11 Applicable
Applicable Device
Device Spec.
Spec. LTPD = 2
LTPD=2
Endurance Test 1033
1033 100%
100% Electrical
Electrical Test
Test Min.
Min. Operating
Operating Temp.
Temp.
Retention Test Unbiased
Unbiased Bake 100%
100% GROUP B:
GROUP B: Mechanical
Mechanical Tests
Tests
48
48 HRS. Subgroup 22
Subgroup 4(0)
4(0)
TA = 150°C
TA= Solvent
Solvent Resistance
Resistance 2015
2015
Pre Burn-In
Bum-In Electrical Applicable Device 100%
100% Subgroup 33
Subgroup LTPD = 10
LTPD=10
Specification
Specification Solderability
Solderability 2003
2003
Tc=
Tc = 2500
25°C Subgroup 55
Subgroup LTPD = 15
LTPD= 15
Dynamic Burn-In
Bum-In 1015Cond.
1015 Cond. D 100%
100% Bond
Bond Strength
Strength 2011
2011
Post Burn-In
Bum-In Electrical Applicable Device 100%
100% I GROUP
GROUP C:
C: Chip
Chip Integrity
Integrity Tests
Tests
Specification
Specification Subgroup
Subgroup 1
Tc = 2500
25°C Dynamic
Dynamic Ufe
Life Test
Test 1005,1,000
1005, 1,000 HRS.
HRS. 12500
125°C LTPD=5
LTPD = 5
PDA=5%
PDA = 5'/0 End
End Point
Point Electrical
Electrical Applicable
Applicable Device
Device Spec.
Spec.
Final Electrical Test Applicable Device 100%
100% Subgroup 22
Subgroup
Specification
Specification Unbiased
Unbiased Retention
Retention 1,000
1,000 HRS. 150·C
FIRS. 150°C LTPD=5
LTPD = 5
Tc=
Tc = 125°C End
End Point
Point Electrical
Applicable Device
Device Spec.
Spec.
Final Electrical Test Applicable Device 100%
100% GROUP
GROUP D:
D: EnvironmentallntearHv
Environmental Integrity
Specification
Specification Subgroup
Subgroup!1 LTPD=
LTPD = 15
15
Tc = -5500
- 55°C Physical
Physical Dimensions
Dimensions 2016
2016
External Visual
Visual 2009 100%
100% Subgroup 22
Subgroup LTPD=5
LTPD = 5
CCI
()CI Sample Selection MIL-M-38510H
MIL-M-38510H Sample
Sample Lead
Lead Integrity
Integrity 2004,
2004, Condo
Cond. B
B
Sec.
Sec. 4.5 and Hermeticity
Hermeticity 1014
1014
MIL-STD-883C Subgroup 33
Subgroup LTPD=
LTPD = 15
15
Sec. 1.2 Thermal
Thermal Shock
Shock 1011,
1011, Condo
Cond. B,
B, 15
15 Cycles
Cycles
Temp.
Temp. Cycle
Cycle 1010,
1010, Condo
Cond. C,
C, 100
100 Cycles
Cycles
Moisture
Moisture Resistance
Resistance 1004
1004
Hermeticity
Hermeticity 1014
1014
Visual
Visual Examination
Examination 1004,
1004, 1010
Endpoint
Endpoint Electrical
Applicable Device
Device Spec.
Spec.
Subgroup 44
Subgroup LTPD
LTPD == 15
15
Mechanical
Mechanical Shock
Shock 2002,Cond.B
2002, Cond. B
Vibration
Vibration 2007,Cond.A
2007, Cond. A
Constant
Constant Acceleration
Acceleration 2001,
2001, Cond.
Cond. E
E
Hermeticity
Hermeticity 1014
1014
Visual
Visual Examination
Examination 1010,
1010, 1011
1011
Endpoint
Endpoint Electrical
Applicable Device
Device Spec.
Spec.
Subgroup 55
Subgroup LTPD
LTPD == 15
15
Salt
Salt Atmosphere
Atmosphere l009,Cond.A
1009, Cond. A
Hermeticity
Hermeticity 1014
1014
Visual
Visual Examination
Examination 1009
1009
SubgroupS
Subgroup 6 3(0)
3(0)
Intemal
Internal Water
Water Vapor
Vapor 1018
1018 << 5,000
5,000 PPM,
PPM, loo·C
100°C
Subgroup
Subgroup 77 LTPD=15
LTPD = 15
Lead
Lead Finish
Finish Adhesion
Adhesion 2025
2025
Subgroup 88
Subgroup 5(0)
5(0)
Lid
Lid Torque 2024
2024
3-2
3-2
I:
Military Ordering
Information
InfolJnation
attice offers
Lattice offers the most
most comprehensive
comprehensive line line of military to use
to use the
the SMD number, where
where it exists,
exists, when
when ordering
ordering
E2CMOS Programmable
Programmable Logic Logic Devices.
Devices. L aLattice
ttice parts. Listed below
parts. below are
are Lattice's
Lattice's military
militaryqualified
qualifieddevices
devices
eecognizes thetrend
,ecognizes trend in militarydeviceprocurementtowards
military device procurement towards and their corresponding
and corresponding SMD
SMD numbers.
numbers. Please contact
Please contact
ising SMD compliant devices and encourages customers
JsingSMDcompliantdevicesandencouragescustomers your local Lattice representative
representative for thethe latest product
product
listing.
listing.
Military Products Selector Guide

DEVICE TYPE Tpd Icc
lex PACKAGE LATTICE PART ##
LATTICE SMD #
SMD#
(ns)
(n8) (mA)
10
10 130
130 20-Pin CEROIP
20-Pin CERDIP GAL161/8B-1OLD/883C
GAL 16V8B-l OLOI883C 5962-8983904RA
5962-8983904RA
130 20-Pin LCC
LCC GAL 16V8B-l OLRl883C
GAL16V8E3-10LR1883C 5962-89839042A
5962-89839042A
15
15 130
130 2O-Pin
20-Pin CEROIP
CERDIP GAL 16V8A-15LOI883C
GAL16V8A-15LD/883C 5962-8983903RA
5962-8983903RA
130 20-Pin
20-Pin LCC
LCC GAL16V8A-15LR1883C
GAL 16V8A-15LRI883C 5962-89839032A
5962-89839032A
20 65
65 20-Pin CEROIP
20-Pin CERDIP GAL16V8A-20Q0/883C
GAL 16VBA-2000/BB3C 5962-8983906RA
5962-8983906RA
65 20-Pin LCC
LCC GAL163/8A-20QR/883C
GAL 16VBA-200Rl883C 5962-89839062A
5962-89839062A
GAL16V8
GA 1.16V8
130
130 20-Pin CERDIP
20-Pin CEROIP GAL 16VBA-20LOI883C
GAL16V8A-2OLD/883C 5962-8983902RA
5962-8983902RA
130
130 20-Pin LCC
LCC GAL
GAL16V8A-20LRl883C
16 V8A-20L R/883 C 5962-89839022A
5962-89839022A
25 65 20-Pin
20-Pin CERDIP
CERDIP GAL 16V8A-25001883C
GAL16V8A-2500/883C 5962-8983905RA
5962-8983905RA
65 2O-Pin LCC
20-Pin LCC GAL 16V8A-250Rl883C
GAL16V8A-25QR/883C 5962-89839052A
5962-89839052A
30
30 130
130 20-Pin CERDIP
CERDIP GAL 16V8A-30LOI883C
GAL16V8A-3OLD/883C 5962-8983901RA
5962-8983901RA
130
130 20-Pin LCC
LCC GAL 16V8A-30LRl883C
GAL16V8A-30LR/883C 5962-89839012A
5962-89839012A
15
15 130
130 24-Pin CERDIP GAL2OV8A-15LOI883C
GAL20V8A-15LD/883C 5962-8984003LA
5962-8984003LA
130
130 28-Pin
28-Pin LCC
LCC GAL20VBA-15LRlB83C
GAL20V8A-15LR/883C 5962-89840033A
5962-89840033A
20 65
65 24-Pin CERDIP GAL2OVBA-2000/883C
GAL20V8A-20QD1883C Contact
Contact Factory
Factory
65
65 28-Pin
28-Pin LCC
LCC GAL2OVBA-200RlBB3C
GAL20V8A-200R1883C Contact
Contact Factory
Factory
130
130 24-Pin
24-Pin CERDIP GAL2OV8A-20LD/B83C
GAL20V8A-2OLD/883C 5962-8984002LA
5962-8984002LA
GAL20V8
GA L.20V8
130
130 28-Pin
28-Pin LCC
LCC GAL2OVBA-20LRlB83C
GAL20V8A-201_11/883C 5962-89840023A
5962-89840023A
25 65
65 24-Pin CERDIP
CEROIP GAL2OVBA-2500/BB3C
GAL20V8A-250D/883C Contact
Contact Factory
Factory
65
65 28-Pin LCC
28-Pin LCC GAL2OV8A-250RI8B3C
GAL20V8A-290R/883C Contact
Contact Factory
Factory
30 130
130 24-Pin CEROIP
24-Pin CERDIP GAL2OV8A-30LD/B83C
GAL20V8A-3OLD/883C 5962-8984001 LA
5962-8984001LA
130 28-Pin LCC
28-Pin LCC GAL2OV8A-30LRl883C
GAL20V8A-30LR/883C 5962-89840013A
5962-89840013A
15
15 150
150 24-Pin CERDIP GAL22Vl0B-15LO/BB3C
GAL22V10B-15LD/883C 5962-8984103LA
5962-8984103LA
150
150 28-Pin
28-Pin LCC
LCC GAL22V10B-15LR1883C
GAL22V10B-15LR1883C 5962-89841033A
5962-89841033A
20 150
150 24-Pin CEROIP
24-Pin CERDIP GAL22V10-20L01883C
GAL22V10-2OLD/883C 5962-8984102LA
5962-8984102LA
150
150 28-Pin
28-Pin LCC
LCC GAL22V10-20LRI883C
GAL22V10-20LR1883C 5962-89841023A
5962-89841023A
GAL22V10
GAL22V-10
25 150
150 24-Pin CERDIP
CEROIP GAL22V10-25LDI883C
GAL22V10-25LD/883C 5962-8984104LA
5962-8984104LA
150
150 28-Pin LCC
28-Pin LOC GAL22V10-25LRlB83C
GAL22V10-25LR/883C 5962-89841043A
5962-89841043A
30 150
150 24-Pin CERDIP
CEROIP GAL22Vl0-30LOI883C
GAL22V10-3OLD/883C 5962-B984101 LA
5962-8984101LA
150
150 28-Pin
28-Pin LCC
LCC GAL22Vl0-30LRlB83C
GAL22V10-30LR/883C 5962-89841013A
5962-89841013A
20 120 24-Pin CEROIP
24-Pin CERDIP GAL20RA 10-20L0/883C
GAL2ORA10-2OLD/883C Contact
Contact Factory
Factory
120
120 28-Pin LCC
28-Pin LOC GAL20RA 10-20LRlB83C
GAL2ORA10-20LF11883C Contact
Contact Factory
Factory
GAL20RA10
GAL2ORA1 0
25 120
120 24-Pin CEROIP
CERDIP GAL20RA 10-25LO/B83C
GAL2ORA10-25LD/883C Contact
Contact Factory
Factory
120
120 2B-Pin
28-Pin LCC
LCC GAL20RA 10-25LRI883C
GAL2ORA10-25LR1883C Contact
Contact Factory
Factory
3-3
3-3
Militaty Ordering Infonnation
Military Information
DESC Standard Military Drawing Listing
SMD #
SMD# LATTICE PART ## SMD #
SMD# LATTICE
LATTICE PART,
PART #
5962-89839012A GAL16V8A-30LR/883C 5962-8984001LA
5962-8984001 LA GAL20V8A-30L0/883C
5962-8983901RA
5962-8983901 RA GAL16V8A-30L0/883C 5962-89840023A
5962-89840023A GAL20V8A-20LR/883C
5962-89839022A GAL16V8A-20LR/883C
16VaA-20LRV883C 5962-8984002LA
5962-8984002LA GAL20V8A-20L0/883C
5962-8983902RA GAL16V8A-20L0/883C
16VSA-20LD1883C 5962-89840033A
5962-8984OO33A GAL20V8A-15LR/883C
5962-89839032A GAL16V8A-15LR/883C
16VaA-15LRI883C 5962-8984003LA
5962-8984003LA GAL20V8A-15LD/8830
5962-8983903RA GA Ll6V8A-15LD/883C
16VSA-.15LD1883C 5962-89841013A
5962-89841013A GAL22V10-30LR/8830
0-30LRI883C
5962-89839042A GAL16V88-10LR/8830
16VSB-10LRl883C 5962-8984101LA
5962-8984101 LA GAL22V10-3OLD/883C
O-30LDI883C
5962-8983904RA GAL16V8B-1OLD/883C 5962-89841023A
5962-89841023A GAL22V10-20LR1883C
O-20LRI883C
5962-89839052A
5962-S9839052A GAL16V8A-25011/883C
16VaA-25QRV883C 5962-8984102LA
5962-8984102LA GAL22V10-2OLD/883C
O-20LDI883C
5962-8983905RA GAL16V8A-2500/883C
16VaA-25QDI883C 5962-89841033A
5962-89841033A GAL22V10B-15LR/883C
5962-89839062A
5962-S9839062A GAL16V8A-200R/883C
16VSA-2OQRV883C 5962-8984103LA
5962-8984103LA GA L22V108-15LD/883C
GAL22V10B-15LDI8S3C
5962-8983906RA GAL16V8A-20QD/8E33C
16VaA-2OQD1883C 5962-89841043A
5962-89841043A GAL22V10-25LR/883C
0-25LRI883C
5962-89840013A GAL20V8A-30LR/8830 5962-8984104LA
5962-8984104LA GAL22V10-25LD/883C
0-25LD1883C
Standard Military Drawing Number Description
f
5962-XXXX X X X X
Lead
Lead Finish
Finish
A = Solder
•*A Solder dipped
dipped
Package Type
Package
R == 2O-1ead CERDIP
20-lead CEIRDIA
LL . 24-lead
24-lead CERDIP
CERDIP
22 -= 2O-pin
20-pin LCC
LCC
33 == 28-pin
28-pin LCC
LOC
Device Type
Device
Drawing
Drawing Number
Number
•• no
no other
other lead
lead finish
finish aJrrently
currently available.
available.
3-4
3-4
!IJ
/1l.J
1,/klecotnqu•ccr: :Lattice®
Semiconductor
Corporation
Corporation
G A O16V8BI883C
GAL
GAL
6118B1883C
GALI16V8AI883C
6118A/883C
High E2CMOS PLD
PLD
DIAGRAM
Vcc
• HIGH
HIGH PERFORMANCE EICMOS-
PCMOS0 TECHNOLOGY
TECHNOLOGY 1
—10 na
-10 ns Maximum Propagation Delay
Delay 20
20 —I J
-— Fmax ==62.5 MHz
to Data Output 19
19
-— TTL Compatible 24 mA Outputs 22 — 0 =
-— UltraMOS6
UltraMOS- Advanced
Advanced CMOS Technology
18
• 50% toto 75% REDUCTION IN POWER FROM BIPOLAR 18
-— 75mA Typ [cc
7SmA 1\'p Icc on Low Power Device 33 — 0 =
-— 45mA
4SmA Typ Icc on Quarter Power Device
..
17
17
• ACTIVE
ACTIVE PULL-UPS
PULL·UPS ON ALL
ALL PINS (GAL
(GAL16V8B)
16V8B)
44
• E2EI CELL TECHNOLOGY
-— Reconfigurable
Reconflgurable Logic 16
16
-100%
—100% Tested/Guaranteed 100% Yields 5
-— High
High Speed Electrical Erasure «100ms)
(<100ms)
-— 20 Year Data Retention 15
15
6 —0=
• EIGHT OUTPUT LOGIC MACROCELLS
-— Maximum Flexibility for Complex
FlexlbllHy for Complex logic
Logic Designs °LUC 14
14
-— Programmable Output Polarity 14
-— Also Emulates 2()..pln PAL- Devices with
20-pin PAL, with Full Func·
Full Func- 7
SI
tlon/Fuse
OLIAC 13
13
• PRELOAD
PRELOAD AND POWER-ON
POWER·ON RESET OF ALLREGISTERS
ALL REGISTERS
• APPLICATIONS
APPLICATIONS INCLUDE: 12
12
-— DMA Control g
-— State Machine Control 11
11
High Speed Graphics Processing
-— High 10
-— Standard
Stand,ard Logic
Logic Speed
Speed Upgrade
• ELECTRONIC
DESCRIPTION PIN
PIN CONFIGURATION
CONFIGURATION
The GAL16V8B1883C GAL16V8A1883C are
GAL16V8B/883C and GAL16V8A/883C are high perfor-
mance E2CMOS programmable logic devices processed in full CERDIP
CERDIP
compliance to MIL-STD-883C.
MIL-STD-883C. TheseThese military grade devices
combine a highhigh performance
performance CMOS process with Electrically LCC
LCC IICLK
liCLK 20 I Vee
Vcs
Erasable (E2)
(E2) floating gate technology to provide the highest
speed/power performance available in the 883C qualified PLD IIOIQ
i/0/0
market. The
The GAL1
GAL16V8B1883C,
6V88/883C, at 11Ons
Ons maximum propagation I Vooo 5rotQ
VOLK Vo
K:LK 0/0
1/010
V0/0
delay time, is the world's
worlds fastest military qualified CMOS PLD. 2 2 0 10
CMOS circuitry allows the GAL 16V8A quarter power devices
GAL16V8A devices toto rotQ
Solo I I I IIOIQ
MO
consume just 45mA typical Icc,
45mAtypical 'cc, which represents a 75%
75% savings
savings
in power when compared to bipolar counterparts.
VOIQ
V0/0 II G A L I vo/o
IIOIQ
GAL16V8A1B
GALA 6V8A/B VOIQ
V0/0 1 1 6 V 8 M 3 1 POtO
110/0
Generic architecture maximum design
architecture provides maximum design flexibility
flexibility by
by
allowing the
the Output Logic Macrocell (OLMC) to be be configured
configured by Top View
Top View rotQ
VOlo 1 I 1 / 0 t IIOIQ
0
the user.
user. TThe GAL 16V8A1883C aand
h e GAL16V8A/883C GAL16V8B/883C are
n d GAL16V8B/8E33C are
capable of emulating all standard 20-pin PALS PAL- devices with full VOIQ I IIOIQ
1/0/0
functionlfuse
function/fuse map/parametric compatibility. I I I IIOIQ
1/0/0
II O GND
N O VrOE
o i 5VOIQ
0 / 0 0VOIQ
0/0
Unique test circuitry and reprogrammable cells cells allow complete
complete GND
CND 1 0 11 I v6E
UCT
AC, DC, and functional testing during manufacture. Therefore,
Therefore,
Lattice guarantees 100°A
100% field programmability
programmability and functionality
functionality
of all GAL products. Lattice
Lattice also guarantees 100 erase/rewrite
erase/rewrite
cycles and that data retention exceeds 20 years.
Copyright CI991 Lattice
Copyright 01991 Lattice Semiconductor Corp, GAl, E'CMOS
Corp. GAL, M H O S and UhraMOS
UttraMOS are registered trademarks
trademarks 01
of Lattice
Lattice SemiconduC1or
Corp. Generic Logic isis aa trademark
Array Logic trademark01
ofLattice
LatticeSemiconduc·
Semiconduc-
tor PAL is
tor Corp. PAL of Advanced Micro Devices.
Is a registered trademark 01 Devices, Inc. The
The specifications
specifications and Information
information herein
herein are
are subject
subject to
to chango
change wtthout
without notice.
notice.
LATTICE SEMICONDUCTOR CORP., 5555 N.E. N.E. Moore Ct., Hillsboro, Oregon
Oregon 97124,
97124, U.S.A.
l 1991.Rev.A
1 9 9 1 . R e v. A
Tel. (503) 681-0118;
Tel. (503) 681-0118; 1-800-FASTGAL:
1-800-FASTGAL; FAX
FAX (503)681-3037
(503)681-3037
3·5
3-5
[lJ
LJ
tatUoo*
LLattice° Semiconductor
Semironductor
Corporation
Corporation
GAL16V8B
Specifications GAL / 883C
16V8B 1883C
ABSOLUTE MAXIMUM RATINGS01

COND.
Supply voltage Vcc — 0 . 5 -0.5 to +
Vex; ....................................... +7V
7V C aCase
s e Temperature
Temperature (T c> ..............................
(Tc) — 5 5-55 to
to 125°C
125°C
Input voltage applied .•............•..•.........
— 2 . -2.5 5 to Vcc +1.0V
Vex; +1.0V S u Supply
p p l y voltage
voltage (Vex;l
(Vcc)
— 2 -2.5
Off-state output voltage applied .......... . 5 to Vcc +1.0V
Vex; + 1.0V w i twith
h Respect
Respect to
to Ground
Ground ......................
+ 4 . 5+4.50 0 to
to +5.50V
+5.50V
— 6
Storage Temperature ................................. 5 -65 to 150°C
Case Temperature with
Power Applied ........................................
— 5 5 -55 to 125°C
"Absolute Maximum
Maximum
Ratings·
Ratings" may cause permanent damage to the the device.
device. These
are stress only ratings and functional operation of the device
conditions above those
at these or at any other conditions those indicated in
inthe
the
programming.
programming, follow thethe programming
DC
Over Recommended
Recommended Operating Conditions (Unless Otherwise
Specified)

CONDITION MIN.
MIN. TYP.·
TYP.3 MAX.
MAX. UNITS
UNITS

Vss-O.5 -- 0.8
0.8 VV
2.0 -— VCC+1
Vcc+1 VV
IlL'
IlLi Input or 110
I/O Low Leakage Current OV
OVS VIN S
5 VIN VIL (MAX.)
5 VII_ (MAX.) -— -— -100
–100 t•tk
IIH
ItH Input or 110
3.5V S
5 VIN
VIN S
5 Vee
Vcc -- -- 10
10 gA
VOL Output Low Voltage 1oL= Yin
lot_ = MAX. Vi n = VIL
Vit. or
or VIH
V1H -— -
— 0.5
0.5 VV
loH = MAX. Yin = VII_
MAX. Vin VIL or VIH
or VII-1 2.4
2.4 -— -— VV
10L
IOL Low Level Output Current - -— 12.
12 mA
mA
10H High Level Output Current -— -— -2
–2 mA
mA
los2
10S2 Output Short Circuit
Circuit Current
Current Vee-SV VOUT ..= O.SV
Vcc = 5V VOW' 0.5V T,,_2S
TA oC
= 25°C -30
–30 -— -150
–150 mA
mA
Icc
ICC Operating Power Supply
Supply Current VIL=
VIL. = O.SV VIH =
0.5V VIH = 3.0V
3.0V Itoggie = 25
ftoggle --= 25 MHz
MHz -— 75
75 130
130 mA
mA
Outputs
Outputs Open
Open (no
(no load)
load)
1) The leakage current is due to the internal pull-up on all pins. See
See Input
Input Buffer
Buffer section
section for
for more
more information.
information.
2) One output at a time for
for a maximum duration of of one
one second. Vout = O.SV
was selected
selected to
to avoid
avoid test
test problems
problems caused
caused by
by tester
tester
ground degradation. Guaranteed 100% tested.
tested.
Vcc ..- SV TA ..
5V and TA = 25 °C
*C
CAPACITANCE (TA
(TA = 25°C, f1= 1.0 =
1.0 MHz)
MHz) =
MAXIMUM* UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
C
CII Input Capacitance 10
10 pF
pF Vcc.= S.OV.
Vcc VI =
5.0V, VI = 2.0V
2.0V
Coo 110
I/O Capacitance 10
10 pF
pF Vcc =
Vcc = S.OV. V110 ..= 2.0V
5.0V, Vb.0 2.0V
'Guaranteed
3-6
3-6 4191.Rev.A
4/91.11ev.A
[IJ
'L
tattiooGP
Semironductor
Caporat/oo
Specifications GAL 16VBB I883C
TEST ·10
COND'. MIN. MAX.
tpd 1 Input or 110 to Combinational Output 2 ,0 ns
teo 1 Clock to Output Delay 1 7 ns
tcf2 - Clock to Feedback Delay - 7 ns
tsu - Setup 1ime, Input or Feedback before Clockt 10 - ns
th - Hold 1ime, Input or Feedback after Clockt 0 - ns

1 Maximum Clock Frequency with 58.8 - MHz
fmax 3 1 Maximum Clock Frequency with 58.8 - MHz

1 Maximum Clock Frequency with 62.5 - MHz

No Feedback
twh4 - Clock Pulse Duration, High 8 - ns
twl' - Clock Pulse Duratioo, Low 8 - ns
ten 2 Input or 110 to Output - 10 ns

2 OEJ.. to Output - 10 ns
tdis 3 Input or 110 to Output - 10 ns

3 OEt to Output - 10 ns

2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
4) Clock pulses of widths less than the specification may be detected as valid clock signals.

Input Pulse Levels GNDto 3.0V +5V
Input Rise and Fall1imes 3ns 10%-90%
Input 1iming Reference Levels 1.5V
Output 1iming Reference Levels 1.5V
3-state levels are measured 0.5V from steady-state active FROM OUTPUT (0/0)
level.
- - - + - - - + - TEST POINT
UNDER TEST
Cl
Test Condition
1
2 Active High
Rl
3900
co
R2
7500
7500
CL
50pF
50pF
R2
....L.
T
Active Low 3900 7500 50pF -
3 Active High co 7500 5pF CllNClUOES JIG AND PROSE TOTAL CAPACITANCE
3-7 4/91.Rev.A
!IJ 'Lattice
l..I Semlconductnr
ctor
I I a Itirnalcot ntI a
Corporation
Corporation
GD
Specifications GAL16118A 1883C

GAL 16VBA 1883C

COND.
voltage Vcc
Supply vohage — 0 . 5-0.5 to
Vee ....................................... to +7V CaseTemperature (Tc)
CaseTemperature (Tc) ...............................
— 5 5 to 125°C
to 125°C
voltage applied ...........................
Input vohage — 2 . -2.5 5 to Vcc Vee ++1.0V
1.0V Supply vohage
(Vcc)
Ott-state output voltage applied ..........
Off-state — 2-2.5 . 5 toto Vcc
Vee ++1.0V
1.0V with Respect
with Respect to
to Ground
Ground ......................
+ 4 . 5+4.50 0 to
to +5.50V
+5.50V
— 6 5 -65 to to 150°C
— 5 5 -55 to 125°C
Power Applied '" .....................................
1.Stresses above those listed under the "Absolute Maximum
Ratings* may cause permanent damage to
Ratings· to the
the device.
device. These
device
indicated in the
at these or at any other conditions above those indicated the
operational sections of this
this specification is not
not implied
implied (while
programming, follow thethe programming specHications).
DC

CONDITION MIN.
MIN. TYP.2
TYR' MAX.
MAX. UNITS
UNITS

Vss-O.5 -— 0.8
0.8 VV
2.0 -— VcC+1
Vcc+l VV
IlL
IIL Input or I/O
VO Low Leakage Current OV
OVS VIN S
:5 VIN 5 Vil
V. (MAX.)
(MAX.) -— -— -10
-10 Il1.A
LA
IIH
ItH Input or I/O
VO High Leakage Current VIH
VIH5S_VIN s VCC
VIN 5. Vee -— -— 10
10 .LA
J.LA
VOL
VOL Output Low Voltage kn. =
10l = MAX. Vi
Vinn .. Vil or
= VII_ orVIH
VIH -— -— 0.5
0.5 V
VOH
loH '"
= MAX. Vi
Vinn = VIL
Vilor
or VIH
Vik 2.4
2.4 -— -— VV
10L
12 mA
mA
–2.0 mA
mA
los'
lost Output Short Circuit Current Vcc=5V
Vcc = 5V VOUT TA= 25'C
VOUT = 0.5V TA-, 25°C -30
–30 -— -150
–150 mA
mA
ICC
Icc Operating Power Supply Current Vll
VII_..
= 0.5V VIH
VIH== 3.0V
3.0V LL -15/-201-30
-15/-20/-30 -— 75
75 130
130 mA
mA
Outputs
Outputs Open (no (no load) 0 -201-25
load) Q -20/-25 -— 45
45 65
65 mA
mA
ftoggle = 225MHz
f l o g & ,--- 5 M H z
1) One
One output at a time for
one second. Vout = 0.5V
was selected
selected to
to avoid
avoid test p oblems by
test problems by tester
testerground
ground
degradation. Guaranteed
2) Typical
Typical values are at
at Vcc ..
= 5V and TA
TA'"= 25 ·C
'C
CAPACITANCE (TA
(TA = 25°C,
25°C, ft =1.0=
1.0 MHz) =
SYMBOL PARAMETER
PARAMETER MAXIMUM"
MAXIMUM* UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
C,
C, Input
input Capacitance 10
10 pF
pF Vee'"
Vcc = 5.0V,
5.0V, V,"
Vi = 2.0V
2.0V
ClIO
Clio I/O Capacitance
1/0 10
10 pF
pF Vee"
Vcc = 5.0V,
5.0V, VIIO "= 2.0V
Vuo 2,0V
"Guaranteed
3-8
3-8 4/91.Rev.A
4/91.Rev.A
fjJ
/L/
L.;
tattiOOs
kanlicond:ctor
Semironducwr
Corporation
Corporation
® Specifications GAL16118A 1883C
GAL 16VBA 1883C
C SWITCHING CHARACTERISTICS
AC
Over Recommended
Conditions
-15
-15 -20
-20 -25
-25 -30
-30
TEST DESCRIPnON
DESCRIPTION UNITS
UNITS
ARAMETER
'ARAMETER
COND.
COND'. MIN. MAX
MIN. MAX. MIN.
MIN. MAX.
MAX. MIN.
MIN. MAX.
MAX. MIN.
MIN. MAX.
MAX.
tpd 1 I/0 to
Input or I/O to Combinational Output 33 15
15 33 20
20 33 25
25 33 30
30 ns
ns
teo
tco 1 Clock to Output Delay 22 12
12 22 15
15 22 15
15 22 20
20 ns
ns
tcf2 -
— Clock to Feedback Delay -— 12
12 -— 15
15 -— 15
15 -— 20
20 ns
ns
Setup lime, or Feedback before Clocki
ClockT 12
12 -— 15
15 -— 20
20 -— 25
25 -— ns
ns
th -
— Hold lime,
Time, Input or Feedback after Clocki
ClockT 00 -— 00 -— 00 -— 00 -— ns
ns
41.6 -— 33.3
33.3 -— 28.5
28.5 -— 22.2
22.2 -— MHz
MHz
too)
frnax33
41.6 -— 33.3
33.3 -— 28.5
28.5 -— 22.2
22.2 -— MHz
MHz
tcf)
50 -— 41.6
41.6 -— 33.3
33.3 -— 33.3
33.3 -— MHz
MHz
No Feedback

High 10
10 -— 12
12 -— 15
15 -— 15
15 -— ns
ns
twl'
tw14 -— Clock Pulse Duration, Low 10
10 -— 12
12 -— 15
15 -— 15
15 -— ns
ns
to Output -— 15
15 -— 20
20 -— 25
25 -— 30
30 ns
ns
2 OE.!.
15 -— 18
18 -— 20
20 -— 25
25 ns
ns
tdis 3 Input or 110
I/O to
to Output -— 15
15 -— 20
20 -— 25
25 -— 30
30 ns
ns
3 OEi
OET to Output -— 15
15 -— 18
18 -— 20
20 -— 25
25 ns
ns
I)Refer to Switching Test Conditions section.
I) Calculated from fmax with internal feedback. Refer
Refer to
to fmax
fmax Descriptions
section.
I) Refer to
to fmax Descriptions section.
I) Clock pulses of widths less than the specification may be detected as valid
signals.

GND to 3.0V
3.0V +5V
+5V
Times 3ns
3ns 10%-90%
10*/0 – 90%
Input liming
1.5V
Output liming
1.5V
·state
-state levels are measured 0.5V from steady-state
steady·state active
active
FROM OUTPUT (010)
FROMOUTPUT (010) ---+----+-TEST
TESTPOINT
POINT
vel.
UNDER TEST
UNDERTEST
'utput CondHlons (see figure)
lutput Load Conditions
CL
Test Condition RI R2
R2 CL
CL R2
1 3900 750.Cl
7500 50pF
50pF
22 Active High ...
00 7500 50pF
50pF
Active Low 3900 750.Cl
7500 50pF
3 Active High ..
00 750.Cl
7500 5pF
5pF C
C LlNCLUOES
LINCLUDESJIG
JIGAND
ANDPROBE
PROBETOTAL
TOTALCAPACITANCE
CAPACITANCE
Active Low 390.Cl
3900 750.Cl
7500 5pF
5pF
3-9 4191.Rev.A
4/91.Rev.A
[JJ
.lJ
tattiooGP
Lattice
Semiconductor
SemJronductor
Corporation
Corporation
GAL16118B
Specifications GAL
GAL161/8A
GAL
I 883C
16V8BI883C
I 883C
16VBA 1883C
SWITCHING WAVEFORMS
WAVEFORMS
INPUTor
INPUT or
SOFEEDBACK
VOFEEDBACK
CLK
ClK
INPUT
INPUTor
SOFEEDBACK VALIDINPUT
VOFEEDBACK 4 - to 0-4.
4-tpd REGISTERED
REGISTERED
OUTPUT
OUTPUT
COMBINATORIAL
COMBINATORIAL
OUTPUT
OUTPUT (external Id*

Registered Output
Output
INPUT or
INPUTor
OE
OE
VOFEEDBACK
SOFEEDBACK
te
OUTPUT
OUTPUT OUTPUT
OUTPUT
Input or I/O
110 to Output Enable/Disable O E OE to
to Output
Enable/Disable
ClK
CLK
tw h 1 - 1 0 .
4— I/ t max(internal icibk)
ClK
CLK
44-- tnt s o
REGISTERED
REGISTERED
FEEDBACK
FEEDBACK
Clock Width
fmax
tmax with
with Feedback
Feedback
3-10 4191.Rev.
4/91.Rev
Lattices
.l..J Corporation
Semiconductor
Semironductor
Specifications GAL16118B / 883C
GAL 16V8B 1883C
GAL16118A
GAL / 883C
16VBA I883C
fmax DESCRIPTIONS
r· . · ·. ··········. .·········. .· . · . . . . . . . . ..
CLK
ClK
elK
CLK
.........................................................
, ,
LOGIC
lOGIC ; I
0
REGISTER
REGISTER
ARRAY
A R R AY
LOGIC
V - - - - 0
ARRAY
REGISTER
REGISTER
I
1<11.....---- 014
......i -t -
c -o-- - - - 1 0 1
tmax with External Feedback 1/(1su+tco)

fmax
Note: fmax with

tsu and tco.
tco,
t
with external feedback is
li(tsu+tco)
is calculated
calculated from measured
measured
,
.....................................................
tci
lei
tpd 0
,
1
D
!
fmax with
fmax with Inlernal
internal Feedback
Feedback 1/(1su+tcf)
li(tsui-tcf)
Note: tcf
Note: tel is a calculated value, value, derived
derived byby
CLK
ClK subtracting from the period
period of fmax
fmax wI
subtracting tsu from w/
internal feedback
internal feedback (tcf = - A m a x - Isu).
1/fmax tsu), The
The
LOGIC
..,
REGISTER
value
value of
delay
rial
of tcf
delay from
tof is
is used
used primarily
from clocking
rial output
primarily when
whencalculating
clocking a register
output (through
register to
(through registered
calculatingthe
the
to aa combinato-
combinato-
feedback), as
A R R AY
- 0 shown
shown above.
above. For For example,
example, the timing
timing from
from
clock to
clock to aa combinatorial
output is
is equal
equal to tcf ++
totel
........... _.......... -.......... -..... _- ............................. _.........' tpd.
tpd.
Note: fmax with

with no feedback
feedback may be 1/twh + twl
less than 111wh
be less twl this
this
is to allow for a clock duty cycle of other than 50%.
3-11
3-11 4/91.Rev.A
4/91.Rev.A
LLattice®
L.J Semiconductor
Semironductor
Specifications GAL161/13B 883C
GAL 16V8B 1883C
Corporation
Corporation GAL161/8A
GAL I 883C
16VSA I883C
GAL16V8A/B
GAL 16V8A/B ORDERING INFORMATION (MIL-STD-883C
(MIL-STD-883C and SMD)
Ordering ##
Ordering
Tpd Tsu
Tsu Tco
Teo !cc
Icc Package
Package MIL-STD-883C
MIL-STD-883C SMD #
SMD#
(ns) (ns) (ns) (mA)
(rnA)
to
10 10
10 77 130 20-Pin CERDIP
2O-Pin CERDIP GAL16V8B-10LD/883C
GAL 16VSB-l0LD/883C 5962-8983904RA
5962-8983904RA
130
130 20-Pin LCC
2O-Pin LCC GAL16V8B-10LR/883C
GAL 16VSB-l0LRI883C 5962-89839042A
5962-89839042A
15 12
12 12 130 20-Pin CERD1P
2O-Pin CERDIP GAL16V8A-15LD/883C
GAL 16VSA-15LDl883C 5962-8983903RA
5962-8983903RA
130
130 20-Pin LCC
2O-Pin LCC GAL16V8A-15LR/883C
GAL 16VSA-15LRl883C 5962-89839032A
5962-89839032A
20 15 15 65
65 2O-Pin CERDIP
20-Pin CERD1P GAL 16VSA-200D/S83C
GAL16V8A-200D/883C 5962-8983906RA
5962-8983906RA
65
65 2O-Pin
20-Pin LCC
LCC GAL 16VSA-2OQR/883C
GAL16V8A-200R/883C 5962-89839062A
5962-89839062A
130
130 2O-Pin CERDIP
20-Pin CERD1P GAL16V8A-20LD/883C
GAL 16VSA-20LDi883C 5962-8983902RA
5962-8983902RA
130 20-Pin LCC
2D-Pin LCC GAL 16VSA-20LRI883C
GAL16V8A-20LR/883C 5962-89839022A
5962-89839022A
25 20
20 15
15 65
65 20-Pin CERD1P
2D-Pin CERDIP GAL 16VSA-250D/S83C
GAL16V8A-250D/883C 5962-8983905RA
5962-8983905RA
65
65 2D-Pin
20-Pin LCC
LCC GAL16V8A-250R/883C
GAL 16VSA-250Rl883C 5962-89839052A
5962-S9839052A
30 25
25 20 130
130 2D-Pin CERDIP
20-Pin CERD1P GAL 16VSA-3OLD/883C
GAL16V8A-3OLD/883C 5962-S983901 RA
5962-8983901RA
130
130 2D-Pin
20-Pin LCC
LCC GAL 16VSA-3OLRl883C
GAL16V8A-30LR1883C 5962-89839012A
5962-89839012A
Note: Lattice recognizes the trend in

in military device procurement
procurement towards
towards using
using SMD
SMD
compliant devices, as such, ordering by this
this number where
where itit exists
exists is
is recommended.
recommended.
xxxxxxxx
XXXXXXXX -Xxx
X XX XX X
X
GAL16V8A D e v i c e Name
GAL16V8B
Speed (n8) _ _ _ _ _ _...J
Speed (ns) L..-___ MIL Process /1883C
MIL Process 8 8 3 C == 883C
883C Process
Process
E=
L , Low Power Power
Power - - - - - - - - - - - ' ' - - - - - - Package
Package DD = CERDIP
Q = Quarter Power R=LCC
R = LCC
3-12 4/91.Rev.A
4/91.Rev.A
Lattice'
/L
.l.J
FEATURES
Semiconductor
Semiconductor
Corporation
Corporation
GAL-201/8441883C
GAL20V8AI883C
FUNCTIONAL BLOCK
DIAGRAM
High E2CMOS PLD
PLD
Generic Array Loglc™
Generic Logicm,
• HIGH
HIGH PERFORMANCE E2CMOS•
EICMOS· TECHNOLOGY Voc
-— 15
1S ns Maximum Propagation Delay
-— Fmax ==SO
50 MHz
-— 12 ns Maximum from Clock Input to Data Output MUX
-— TTL Compatible 24 mA Outputs eUr
-— UltraMOSI
UltraMOS· Advanced
Advanced CMOS Technology CH-MC
22
• 50% 75% REDUCTION IN POWER FROM BIPOLAR
SO% to 7S%
41
-— 75mA
7SmA Typ ILon
..on Low Power Device
°LUC 21
-— 45mA
4SmA Typ coon
I..on Quarter Power Device 21
• E2EI CELL TECHNOLOGY

-— Reconfigurable
Reconflgurable Logic MAC , 20
20
-— 100% Tested/Guaranteed 100% Yields 1
-— High Speed Electrical Erasure «SOms)
(<50ms) WIC 19
19
-— 20 Year Data Retention =31—,
• EIGHT OUTPUT LOGIC MACROCELLS 4

OLMC 18
-— Maximum Flexibility for Complex Logic Designs le
-— Programmable Output Polarity 7 --De
-— Also Emulates 24-pin

24-pln PAL*
PAL· Devices with Full Func-
Func- CLIC 17
tion/Fuse Map/Parametric Compatibility 17
• PRELOAD
PRELOAD AND POWER-ON RESET OF ALL
ALL REGISTERS
REGISTERS
-— 100% Functional Testability OLMC-3 16
16
9 —Ce
• APPLICATIONS
-— DMA Control OLMC 15
-— State Machine Control 10—De 16
-— High Speed Graphics Processing ,
11—De 14
Logic Speed Upgrade
-— Standard Logic NAUX
13
DESCRIPTION PIN
PIN CONFIGURATION
CONFIGURATION
The GAL20V8A1883C
GA1.20V8A/883C is a high performance E2CMOS E2CMOS program-
mable logic device processed in full compliance to MIL-STD-
MIL-STD- CERDIP
CERDIP
883C. The
The GAL.20V8N883C,
GAL20V8A1883C, at at 15ns
15ns maximum
maximum propagation
worlds fastest military qualified 24-pin CMOS
delay time, is the world's LCC
LCC
PLD. CMOS
CMOS circuitry
circuitry allows
allows the
the GAL20V8A
GAL20V8A quarter
quarter power
power 1/CLK 1 2 4 1 Vee
Vcc
device to consume just 45mA typical icc, Icc, which represents a
75% savings in power when compared to bipolar counterparts.
counterparts.
!S !l II
> _ ; IIOIQ
Generic architecture
architecture provides
provides maximum
maximum design
design flexibility
flexibility by Z2 UH 26
V0/0
V0/0
IIOIQ
L/0/0
allowing the Output
Output Logic Macrocell (OLMC) to to be
be configured
configured by V0/0
the user.
user. TThe GAL20V8A1883C is
h e GAL20V8N883C capable of emulating
is capable emulating allall IIO/Q
V0/0
GAL20V8A WOIO
V0/0
PAL·° devices with full functionlfuse
standard 24-pin PAL function/fuse map/para- GAL20V8A
metric compatibility. NC
NC NC
NC GAL IIO/Q
V0/0
Top
Top View
View WOIO
V0/0 20V8A IIOIQ
V0/0
Unique test
test circuitry reprogram mabie cells
circuitry and reprogrammable cells allow
allow complete
complete WOIO
V0/0
AC, DC, and functional testing during manufacture. Therefore,
AC, DC, Therefore, IIOIQ
V0/0
Latticeguarantees V0/0
Lattice guarantees 100%
I 00*/0 field
field programmability
programmability and functionality
functionality IIO/Q
1/0/0
Jf Lattice also guarantees 100 erase/rewrite
Df all GAL products. Lattice
::yeles
cycles and that data retention exceeds 20 years. - - gIi" 1 lg-- E;
!llg IIO/Q
V0/0
GND
GND 12 3 hoE
::cpyright
0pyright Cll991
Lanice SemioonduClor GAL.
Corp. G A L E'CMOS
E'CMOS and
and UhraMOS
UhraMOS areare registered trademarks of
registered trademarks of Lani.. Semiconductor
Lattice Semiconductor Corp. Generic Alrar
Corp. Generic Array logic
Logic isis aa trademark
trademark of
of Lanice
LatticeSenioonduc·
Semiconduc-
or
CI Corp. PAL is
Corp. PAL is a registered trademark of Micro Devlcas.
of Advanced Micfo Devices, inc. The specifications
Inc. The and informetion
spedfications and information heroin
herein are
are subject to
to change without notice.,
change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon

Oregon 97124,
97124, U.S.A.
U.S.A. April
April 1991.Rev.A
1991.Rev.A
Tel.
tel. (503) 681-0118; 1-800-FASTGAL;
1-800-FASTGAL; FAX (503)
(503)681-3037
681-3037
3-13
3-13
idLattice®
Semiconductor GAL201/8A/883C
Specifications GAL20V8AI883C
Corporation

RATINGS0) RECOMMENDED OPERATING
COND.
Supply voltage Vcc — 0 . 5 -0.5 to
V00 ....................................... to +7V CaseTemperature (Te)
CaseTemperature (Tc) ...............................
— 5 5 -55 to
to 125°C
125°C
— 2 . -2.5 5 to to V
Vcc
00 ++1.0V
1.0V Supply voltage
Supply voltage (V
(Vcc)
00)
Off-state output voltage applied ..........— 2-2.5 . 5 toto V

Vcc
00 ++1.0V
1.0V with Respect
with Respect to
to Ground
Ground ......................
+ 4 . 5+4.50 0 to
to +5.50V
+5.50V
— 6
Storage Temperature .................................5 -65 to to 150°C
— 5 5 -55 to
Power Applied •....................................... to 125°C
Maximum
Ratings· damage to to the device. These
device. These
the device
device
at these or at
at any other conditions above
above those
those indicated
indicated in
in the
the
operational sections of this
this specification is
is not implied (while
programming.
Over
Specified)

CONDITION MIN.
MIN. TYP}
TYP.2 MAX.
MAX. UNITS
UNITS
VIL
Vss – 0.5 -— 0.8
0.8 VV
2.0 -— VcC+1
Vcc+l VV
ilL Input or I/O
I/0 Low Leakage Current OV
OVS5 Y,N
VIN S V,L (MAX.)
5 VII_ (MAX.) -— -— -10
-10 Ilp.A
A
IIH
ItH VI-1S
Input or I/O High Leakage Current V,H 5V 1NS
Y,N 5 Voo
Voc -— -— 10
10 IlA
1.LA
VOL
VOL Output Low
Low Voltage 10L-MAX. Yin
lot. = MAX. Vi n ..
= V,L
VII, or V,H
Vii-i -— -
— O.S
0.5 VV
tau -MAX. Yin = VII_
= MAX. Vin V,L or V,H
or VIH 2.4
2.4 -— -— V
10L
12 mA
mA
10H
–2.0 mA
mA
105
tOSI' Output Short Circuit Current Voo
Vcc ..= SV Your -= O.SV
5V VOW- TA=
0.5V TA =2S·C
25°C -30
–30 -— -150
–150 mA
mA
Icc
1CC Operating Power Supply Current V,L-
VIL = O.SV V,H=3.0V
0.5V VIH = 3.0V LL -1S/-20/-30
-15/-20/-30 -— 7S
75 130
130 mA
mA
Outputs
Outputs Open
Open (no CI·20/-25
(no load) Q -20/-25 -— 45
45 65
65 mA
mA
toggle •-•
f'099I8 25MHz
= 25MHz
1) One output at a time for a maximum duration of one second. Vout
o one Vout ..= O.SV
0.5V was
was selected
selected to
to avoid
avoid test
test problems
problems caused
caused by
by tester
tester
Guaranteed but
2) Typical values are at Vcc =
at Vee = 5V
5V and TA
TA"= 25 ·C
*C
CAPACITANCE (TA =
(TA = 25°C, f = 1.0 MHz) =
SYMBOL PARAMETER MAXIMUM'
MAXIMUM* UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
C,
C, Input Capacitance 10
10 pF
pF Vee
Vcc== S.OV.
5.0V, V,
VI ..= 2.0V
2.0V
Coo
CK, 110
I/O Capacitance 10
10 pF
pF Vee
Vcc== S.OV.
5.0V, VIIO
V,,c,-= 2.0V
2.0V
"Guaranteed
*Guaranteed but not 100°A
100% tested.
3-14
3-14 4/91.Rev.A
4/91.Rev.A
!lJ
1.. tattiOO-
Lattice®
Semioonductor
Semiconductor
CaporatkJn
Corporation
GAL20118A/883C
AC
Over
-15
-15 -20
-20 -25
-25 -30
-30
UNITS
PARAMETER
COND.
pOND'. MIN. MAX
MIN. MAX. MIN.
MIN. MAX.
MAX. MIN.
MIN. MAX.
MAX. MIN.
MIN. MAX.
MAX.
tpd 11 Input or I/O
I/0 to
15 33 20
20 33 25
25 33 30
30 ns
ns
too
tco 11 Clock to Output Delay 22 12
12 22 15
15 22 15
15 22 20
20 ns
ns
tc12
tcf2 -— Clock to Feedback Delay -— 12
12 -— 15
15 -— 15
15 -— 20
20 ns
ns
Setup l)me, or Feedback before Clocki
Clock/ 12
12 -— 15
15 -— 20
20 -— 25
25 -— ns
ns
-— -— -— -— -—
•
th Hold Time, Input or Feedback after Clocki
Clock/ 00 00 00 00 ns
ns
41.6 -— 33.3
33.3 -— 28.5
28.5 -— 22.2
22.2 -— MHz
MHz
tmax33
fmax 11 Maximum Clock Frequency with with 41.6
41.6 -— 33.3
33.3 -— 28.5
28.5 -— 22.2
22.2 -— MHz
MHz
tcf)
with 50
50 -— 41.6
41.6 -— 33.3
33.3 -— 33.3
33.3 -— MHz
MHz
No Feedback
twh
twh' -— Clock Pulse Duration, High
High 10
10 -— 12
12 -— 15
15 -— 15
15 -— ns
ns
twt'
tw14 -— Clock Pulse Duration, Low 10
10 -— 12
12 -— 15
15 -— 15
15 -— ns
ns
ten 2 Input or 110
I/O to
to Output -— 15
15 -— 20
20 -— 25
25 -— 30
30 ns
ns
2 OEL
OEI, to Output -— 15
15 -— 18
18 -— 20
20 -— 25
25 ns
ns
I/O to
to Output
Output -— 15
15 -— 20
20 -— 25
25 -— 30
30 ns
ns
3 OEi
OE/ to Output -— 15
15 -— 18
18 -— 20
20 -— 25
25 ns
ns
2) Calculated from fmax with internal feedback. Refer to
to fmax i;)escrlptions
section.
the specification may be detected as valid clock
clock signals.
signals.
CONDITIONS
GND to 3.0V
3.0V +5V
+5V
3ns 10% – 90%
1.5V
1.5V
0.5V from
FROM OUTPUT (010)
FROMOUTPUT (0/0) --+---'--TEST
level. TESTPOINT
POINT
UNDER TEST
UNDERTEST
Output Load Conditions
Conditions (see figure)
Test Condition R1
RI R2
R2 CL
CL R2
1 3900 7500
7500 50pF
50pF
2 Active High
Active High –
GO 7500·
7500 50pF
50pF
Active Low 3900
3900 7500 50pF
50pF
3
3 Active
Active High –
GO 7500 5pF
5pF C
CL INCLUDES
LIN CLUDESJIG AND
JIGANDPPROBE
ROBETTOTAL
OTALCCAPACITANCE
APACITANCE
Active Low
Active Low 3900
3900 7500
7500 5pF
5pF
3-15
3-15 4191.Rev.A
4/91.Rev.A
fL]
.l.J
'Lattioo
Lattice
SemiCXJnducwr
1.11 Semiconductor
Corporation
Corporation
GP
GAL20118A/883C
SWITCHING WAVEFORMS
INPUTor
INPUT or
I/0 FEEDBACK
110 FEEDBACK SIMInt
INPUTor
INPUT or eLK
CLK
VOFEEDBACK
110 FEEDBACK Z S Z S V VALID INPUT 411--tc
REGISTERED
REGISTERED
440
OUTPUT
OUTPUT
COMBINATORIAL
COMBINATORiAl
OUTPUT
OUTPUT
= 0 , 1/ fmax
(external tdbk)

Registered Output
Output
INPUT
INPUToror
OE
OE
110 FEEDBACK
VOFEEDBACK
t dis 4—ten—pp + i d x-lio 4 - te n
OUTPUT
OUTPUT OUTPUT
OUTPUT
Input or I/O
110 to Output Enable/Disable O E OE to
to Output
Enable/Disable
CLK
CLK
tw h —111101--- twl
t w I —111.
v t maxinternal tdbk)
CLK
CLK
tct 0 4 ( s o
REGISTERED
REGISTERED
FEEDBACK
FEEDBACK
Clock Width
fmax
f max with
with Feedback
3-16 4/91.Rev.A
4191.Rev,A
Lattice" GAL201/8A/883C
Specifications GAL20 V8AI883C
Semiconductor
Corporation
fmax DESCRIPTIONS
CLK
ClK
.--_ ... ..................................................................
...
_
·· elK
CLK
LOGIC
lOGIC
IP' R EGISTER
REGISTER
ARRAY
A R R AY
LOGIC V
ARRAY
·.............................................................................. REGISTER
oII t
lio.. su0 + 4..lio.. t c o
oIII----lcD----.t

fmax wHh
tcf 0 . 1
Note: fmax with
with external feedback is calculated from
from measured ... tpd
tsu and tco.
fmax with
fmax with Internal
Internal Feedback
1/(tsu+tcf)

Note: calculated value,
value, derived
from
CLK
ClK
the period
the period of
of fmax
fmax wlinternal
w/internal feedback
feedback (tcf(tct - l i1lfmax
t m a x --tsu).
tsu). The
The
r............ _............ •.... •............ •.... •....................................:
·· V
.. value of tcf is used
value
clocking
used primarily
clocking aa register
register to
primarily when
when calculating
to aacombinatorial
calculating the
output (through
the delay
delay from
(through registered
from
registered
: : feedback),
feedback), asas shown
shown above.
above. For example,
example, the the timing
timing from
fromclock
clock
LOGIC
i ARRAY REGISTER
REGISTER i to aa combinatorial
to combinatorial output
output is
is equal
equal to
to tcf
tcf ++ tpd.
tpd.
................................................................ _........................,
with no feedback may be less than

Note: fmax with litwh + twl.
than 1ltwh This
twl. This
is to allow for a clock duty cycle of other than 50%.
50%•
3-17 4/91.Rev.A
4/91.1Rev.A
LLattice'
Semiconductor GAL201/8A1883C
LMborporation
Corporation
GAL20V8A ORDERING INFORMATION (MIL-STD-883C and SMD)

(MIL-STD-883C and SMD)
Ordering ##
Ordering
Tpd Tsu
Tau Too
Teo !cc
Icc Package
MlL-8TD-883C SMD #
SMD#
(ns)
(n8) (ns)
(n8) (ns)
(n8) (m A)
(mA)
15 12
12 12 130
130 24-Pin CERDIP
24-Pin GAL20V8A-15LD/883C
GAL20VSA-15LD1883C 5962-8984003LA
5962-8984003LA
130
130 28-Pin LCC GAL20V8A-15LR/883C
GAL20VSA-15LRI883C 5962-89840033A
5962-89840033A
20 15
15 15 65
65 24-Pin CERDIP
24-Pin GAL20VSA-2OQD1883C
GAL20V8A-200D/883C Contact Factory
Contact Factory
65
65 28-Pin LCC GAL2OVSA-2OQRI883C
GAL20V8A-200R18830 Contact Factory
Contact Factory
130 24-Pin CERDIP
24-Pin GAL20V8A-2OLD/883C 5962-8984002LA
5962-8984002LA
130 28-Pin LCC GAL20V8A-20LR/883C
GAL2OVSA-20LRI883C 5962-89840023A
5962-89840023A
25 20
20 15
15 65
65 24-Pin CERDIP GAL2OVSA-25Q01883C
GAL20V8A-250D/8830 Contact Factory
Contact Factory
65
65 28-Pin
28-Pin LCC
LCC GAL20VSA-25QRI883C
GAL20V8A-250R1883C Contact Factory
Contact Factory
30 25
25 20
20 130 24-Pin CERDIP GAL20V8A-3OLD/883C 5962-8984001LA
5962-8984001 LA
130
130 28-Pin
28-Pin LCC GAL20V8A-30LR/883C 5962-89840013A
5962-89840013A
Note: Lattice recognizes the trend in military device procurement towards

towards using SMD
where it exists is recommended.
compliant devices, as such, ordering by this number where recommended.
xxxxxxxx-n
XXX XXXXX X X X X X
GAL20V8A Device Name
Speed (ns) - - - - - - - '

Speed L M I L Process /1883C
8 8 3 0 -= 883C
883C Process
Process
L =- Low Power Power - - - - - - - - - - ' ' - - - - - - Package

Package D0 -= CERDIP
CERDIP
a
0 == Quarter Power R-LCC
R = LCC
3-18
3-18 4/91.Rev.A
4/91.1Rev.A
ill
LLattice®
.l.J LaWOO"
FEATURES
Semiconductor
Semiconductor
Corporation
GAL221110131883C
GAL22V10B/BB3C
GAL2211101883C
GAL22V10/BB3C
FUNCTIONAL BLOCK
DIAGRAM
High E2CMOS PLD
PLD
• HIGH
-HIGH PERFORMANCE
Fr/lax PCMOS*TECHNOLOGY
= 62.5 MHz E'CMOS* TECHNOLOGY
liCLX
I/eu<
-— 15 ns Maximum Propagation Delay
- Fmax = 62.5 MHz 1/0/0
I/OIQ
-— 8ns
8ns Maximum from Clock Input to Data Output INPUT
INPUT
-— UltraMOS®
UltraMOS* Advanced CMOS Technology ,
1/0/0
I/OIQ
INPUT E ) - - C = -
INPUT
• ACTIVE
ACTIVE PULL-UPS
PULL·UPS ON ALL PINS
PINS
• COMPATIBLE
COMPATIBLE WITH STANDARD 22V10 DEVICES INPUT
INPUT 1/0/0
UOIQ
-— Fully Function/Fuse·Map/Parametrlc
Function/Fuse-Map/Parametric Compatible
..
with Bipolar and UVCMOS 22V10 Devices
INPUT
INPUT D — i L 1/0/0
IIOIQ
• 50% REDUCTION IN POWER VERSUS BIPOLAR
BIPOLAR
• E'E' CELL TECHNOLOGY
INPUT
INPUT 1/0/0
I/OIQ
-— Reconfigurable
— 100c/0 Tested/Guaranteed 100e/o
-100% 100% Yields INPUT
INPUT
I/OIQ
1/0/0
-— High Speed Electrical Erasure (<100ms)
«100ms)
INPUT 0 - - r y - -
INPUT
• TEN
TEN OUTPUT LOGIC MACRO
MACROCELLS
CELLS I/OIQ
11010
-— Maximum Flexibility for Complex Logic Designs

INPUT I D — C 2 = k i
INPUT
• PRELOAD
POWER· ON RESET OF REGISTERS I/OIQ
11010
INPUT
INPUT 0 - - C , - 1
• APPLICATIONS
APPLICATIONS INCLUDE: I/OIQ
11010
-— DMA Control
-— State Machine Control INPUT
INPUT
-— High Speed Graphics Processing I/OIQ

110/0
-— Standard Logic Speed Upgrade INPUT
INPUT
• ELECTRONIC
DESCRIPTION
PACKAGE
PACKAGE DIAGRAMS
DIAGRAMS
The GAL22
GAL22V1 OB/883C and GAl22V1
V10B/883C 0/883C are
GAL22 V10/883C are high perfor-
perfor·
PCMOS programmable logic devices processed in full
mance E2CMOS full
MIL-STD-883C. These military
compliance to M1L-STD-883C. military grade devices CERDIP
CERDIP
combine a high performance CMOS process process with Electrically
Electrically
(EO) floating gate technology to provide the highest
Erasable (E2) LCC
LCC
I/CLK Vee
Vcc
speed performance available of any military qualified 22V10
device. CMOS
CMOS circuitry allows the GAL22V10/B to to consume C! Q 110/0
1/0/0
consume 0
_ _ Q zZ g
0
51 51
much less power when compared to bipolar 22V1
to bipolar 22V100 devices. E'P 110/0
110/12
technology offers high speed (<100ms)
«1 OOms) erase times, providing
providing the
the 22 I U2288 IIOIQ
I/010 110/0
I/0/0
ability to reprogram or reconfigure the
the device quickly and effi- IIOIQ
I/082 110/0
1/0t0
ciently.
IIOIQ
110,0 110/0
I/0/0
flexibility by GAL22V10/B
GAL22V10/B
NC NC
NC 110/0
allowing the Output Logic Macrocell (OLMC) to be configured
configured by 1 I/0/0
Top
Top View IIOIQ
1/C80
1 110/0
I/0/0
the user. The GAL22V1 OB and GAL22V1
The GAL22V10B GAL22V10 0 are fully
fully functiontfuse
functionfluse
11010
1/0/0 110/0
map/parametric compatible with standard
standard bipolar
bipolar and CMOS 1 it0t0
22Vl0 11010
U0/0
22V10 devices. 110/0
I/0/0
" - §§
c 110/0
80/0
Unique test circuitry and reprogram mabie cells
reprogrammable cells allow complete
complete – z2 'z – Q Q
AC, DC,
DC, and functional testing during manufacture. As As a result,
LATTICE is able to guarantee 100% field programmability and
result. " z Q ONO
GALl»° products.
functionality of all GAL products.
Copyright 10199
01991I Lattice
Lanice Semiconductor
Semiconductor Corp. GAL,
GAL. E'CMOS
PCMOS and UHraMOS ",e registerod
UhraMOS are registered trademarks
trademarks 01
of Lanico
Semiconductor Corp. Logic isis aa trademark
Generic Array Logic
Corp. Genetic of Lank:e
trademark of Lattice Se_uc-
Semiconduc-
tor Corp. TThe notioe.
h e specifications herein are subject to change without notice.
LATIICE
LATTICE SEMICONDUCTOR CORP., CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon
Oregon 97124 U.S.A.
U.S.A. April
April 1991.Rev.A
1991.Rev.A
Tel. (503) 681-0118 or
Tel. (503) or 1-800-FASTGAL; FAX (503)
1-800-FASTGAL; FAX (503) 681-3037
681-3037
3-19
3-19
[JJ LaWOOaD
LLattice®
.l.J Semiconductor
SemkxJnductor
Corporation
Corporation
GA1_221/1013188=
Specifications GAL22V10BI883C

COND.
Vee ........................................ to +
+7V
7V Case Temperature
Case Temperature (Te)
(Tc) ..............................
— 5 5-55 to
to 125°C
125°C
- 2 . 5-2.5 to to Vee
Vcc +1.0V Supply Voltage
Supply Voltage (Vee)
(Vcc)
Off-state
Off "state output voltage applied ...........- 2 .-2.5 5 toto Vee
Vcc ++1.0V
1.0V with Respect
with Respect to
to Ground
Ground ......................
+ 4 . 5+4.50 0 to
to +5.50V
+5.50V
- 6 5 -65 to 150°C
- 5 5 -55 to
1. Stresses above those listed under
under the
the "Absolute Maximum
Ratings·
These
are stress only ratings and functional operation ofof the
the device
at these
these or at any other conditions above those indicated in in
(while programming, follow the specifications).
DC CHARACTERISTICS
Over Recommended
Specified)

CONDITION MIN.
MIN. TYP.3
TYR' MAX.
MAX. UNITS
UNITS
VII_
Vss –0.5 -— 0.8
0.8 VV
2.0 -— VcC+1
Vcc+l VV
IlL'
ilL1 Input or 1/0
I/O Low
Low Leakage
Leakage Current OV
OV5S_VIN
VIN S VIL (MAX.)
VII_ (MAX.) -— -— -100
-100 pA
itA
IIH
11/-1 Input or 1/0
I/O High Leakage Current 3.5V
3.5V s5 VIN
VIN S Vee
VCC -- -
- 10
10 pA
itA
VOL Output Low Voltage 1oL=
lot.= MAX. Yin
MAX. Vi n = VILor
VII_ orVIH
VII-1 -- -
- 0.5
0.5 VV
lok = MAX. Vin = VII_
MAX. Vin VIL or
or 1VIH
111-I 2.4
2.4 -— -— VV
10L
i0L Low Level Output Current -— -— 12
12 rnA
mA
–2.0 rnA
mA
los2
Vcc ..= 5V VOUT == 0.5V
5V VOW- TA == 25°C
0.5V TA 25°C -50
–50 -— -135
–135 rnA
mA
VIL = 0.5V VVIH
I H =3.0V
= 3.0V -— 90
90 150
150 rnA
mA
ftoggle = 15Mhz Outputs
ftoggle ••,- Outputs Open
Open
1) The
the internal
internal pull-up on
on all
section for
for more
more information.
information.
2) One
One output at a time for a maximum duration of one second. Vout =00.5V
was selected
selected to
to avoid
avoid test
testproblems
problems caused
caused by
bytester
tester
Guaranteed butbut not 100% tested.
tested.
are at Vcc
Vee = 5Vand
5V and TATA=
= 25°C
25 °C
CAPACITANCE (TA
(TA = 25°C,
25"C, 1= =
f 1.0 MHz)
MHz) =
SYMBOL PARAMETER
PARAMETER MAXIMUM"
MAXIMUM" UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
C,I
C Input
pF Vcc
Vcc== 5.0V,
5.0V, V
V,I -= 2.0V
2.0V
C110
CliO 110
I/O Capacitance 10
10 pF
pF Vcc ..= 5.0V,
Vcc 5.0V, VIiO=
Voc = 2.0V
2.0V
<Guaranteed
3-20
3-20 4191.Rev.A
4/91.Rev.A
[JJ
.l.J
L
LB.ttiOOGl
e Semironductor
i t 'ICS;
Corporation
CorporatJon
GAL221110131883C
Specifications GAL22V10B/883C
AC
-15
-15
PARAMETER
UNITS
COND.1
COND.' MIN. MAX.
MIN. MAX.
tpd 1 va to Combinatorial Output
Input or I/O -— 15
15 ns
ns
teo
too 1 Clock to Output Delay -— 88 ns
ns
tcf2 -— Clock to Feedback Delay -— 88 ns
ns
..
tsu -— Setup lime,
Time, Input or Feedback before Clockt 12
12 -— ns
ns
th -— Hold Time,
lime, Input
Input or
or Feedback after Clockt
ClockT 00 -— ns
ns
1 Maximum Clock Frequency with with 50
50 -— MHz
MHz
/(tsu + teo)
External Feedback, 11/(tsu Ice)
!
tmax3
fmax 3 1 Maximum Clock Frequency with with 50
50 -— MHz
MHz
/(tsu + tet)
Internal Feedback, 11/(tsu tcf)
62.5 -— MHz
MHz
No
No Feedback
twh4 -— Clock Pulse Duration, High 88 -— ns

ns
twt'
ns
ten 2 va toto Output
Input or I10 Output Enabled -— 15
15 ns
ns
tdis 33 Input or va
15 ns
ns
tar 1 va to Asynchronous Reset ofof Register
Input or I/O Register -— 20
20 ns
ns
15 -— ns
ns
to Clockt Recovery lime
15 -— ns
ns
tspr -— Synchronous Preset to Clockt Reeovery lime
Clocki Recovery Time 12
12 -— ns
ns
2) Calculated
Calculated from imax
fmax with internal feedback. Refer
Refer to
to fmax
imax Description section.
section.
4) Clock pulses of widths less than the specification may bebe detected as valid clock
clock signals.
3-21
3-21 4 / 9 1 . R e v .4/91.Rev.A
A
f};l
.LJ
LBtIiOO-
IdLattice® Semia9nductor
Semiconductor
Corporation
Specifications GAL22V101883C
GAL22111 0/883C

COND.
Supply voltage Vcc - 0 . 5 -0.5 to +7V

Vex; ...................................•.... Case Temperature
Case Temperature (T
(Tc) - 5 5 -55 to
c) ............................... to 125°C
125°C
Input voltage applied ....•.......................
- 2 . 5-2.5 to Vex; V= ++1.0V
1.0V Supply Voltage
Supply Voltage (Vex;)
(Vcc)
Off-state output voltage applied ........... - 2 .-2.5 5 to to Vee
Vcc +1.0V with Respect
with Respect to
to Ground
Ground ......................
+ 4 . 5+4.50 0 to
to +5.50V
+5.50V
- 6
Storage Temperature ............•..............•......5 -65 to 150°C
- 5 5 -55 to
1. Stresses above
above those
those listed under the
the "Absolute Maximum
Ratings·
the device
device
those indicated in in
the operational sections of
of this
this specification is not implied
(while programming, follow thethe programming specifications).
Over Recommended
Specified)

CONDITION MIN.
MIN. TYP.'
TYR' MAX.
MAX. UNITS
UNITS

Vss-O.S -- 0.8
0.8 VV
2.0 -— Vc0+1
Vcc-1-1 VV
ILI
IlL' Input or I/O Low Leakage Current OV VIN S5 %/IL
OVS5. VIN VIL (MAX.)
(MAX.) -— -— ·150
-150 gA
IIH Input or I/O High Leakage Current 3.5V
3.5V s5 VIN
VIN s5 Vee
Vcc -- -- 10
10 gA
VOL
VOL Output Low
Low Voltage IoL
lot_..
= MAX. Vin
MAX. Vi n ..
= VIL
Vit. or
or VIH
1/0-1 -— -— 0.5
0.5 VV
VON
loi-i ..
= MAX. Vi
Vinn = VII_
VIL or
or VIH
VIH 2.4
2.4 -— -— VV
10L
12 mA
mA
ION
–2.0 mA
mA
105
Vcc ..= 5V VOUT-= 0.5V
5V VOUT TA =-
0.5V TA = 25°C
25°C -50
–50 -— -135
–135 mA
mA
ICC Operating Power
Power Supply Current VIL = 0.5V VVIH
VIL=0.5V I H =3.0V
= 3.0V -— 90
90 150
150 mA
mA
ftaggle Outputs Open
ftoggle -= 15Mhz Outputs Open
1) The leakage current is due to the
the internal pull·up
pull-up on
Buffer section
section for
for more
more information.
information.
2) One output
output at a time for a maximum duration of one second. Vout -= 0.5V
was selected
selected to
to avoid
avoid test
test problems
problems caused
caused by
by tester
tester
100rk tested.
tested.
3) Typical values are at Vee-
Vcc = 5V and TA
TA== 25°C
25 'C
=
(TA = 25°C, f1= 1.0 MHz)
CAPACITANCE (TA MHz) =
SYMBOL PARAMETER
PARAMETER MAXIMUM"
MAXIMUM* UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
C, Input
pF Vee
Vcc== 5.0V,
5.0V, V,
Vi -= 2.0V
2.0V
ClIO
C,0 110
I/O Capacitance 10
10 pF
pF Vee
Vcc== 5.0V, VIIO "=2.0V
5.0V, V,,,o 2.0V
3-22
3-22 4191.Rev.A
4/91.1Rev.A
f1J LattiOOGl
1 ILattice Semiconductor
SemJronductor
Corporation
Corporation
Specifications GAL22V10/883C
GAL2211101883C
Over Recommended
Conditions
TEST -20
-20 -25
-25 -30
-3D
UNITS
COND.' MIN. MAX.
MIN. MIN. MAX;
MAX. MIN. MAX. MIN.
MIN. MAX.
MAX.
tpd 1 I/0 to
Input or 110 to Combinatorial Output -— 20
20 -— 25
25 -— 30
30 ns
ns
tco
teo 11 Clock to Output Delay -
— 15
15 -
- 20
20 -— 20
20 ns
ns
tcf2
tcf2 -— Clock to Feedback Delay -— 15
15 -
- 20
20 -— 20
20 ns
ns

before Clocki
ClockT 17
17 -— 20
20 -— 25
25 -— ns
ns
th -— Time, Input or Feedback after
Hold lime, after Clocki
Clockt 00 -— 00 -— 00 -— ns
ns
31.2 -— 25
25 -— 22
22 -— MHz
MHz
tco) 3
tmax33
tcf)
31.2
31.2 -— 25
25 -— 22
22 -— MHz
MHz

33 -— 33
33 -— 25
25 -— MHz
MHz
No Feedback
twh4 -— Clock Pulse Duration, High 15

15 -— 15
15 -— 20
20 -— ns
ns
tw14
twJ4 -— - Clock Pulse Duration, Low
low 15
15 -
— 15
15 -
— 20
20 -— ns
ns
ten 22 Input or I/O to Output Enabled -— 20

20 -— 25
25 -— 25
25 ns
ns
tdis 3 Input or 110

20 -— 25
25 -— 25
25 ns
ns
to Asynchronous
Asynchronous Reset of Register -— 25
25 -— 30
30 -— 30
30 ns
ns
Duration 20
20 -— 25
25 -— 30
30 -— ns
ns
tarr -— Asynchronous Reset to Clocki Recovery
Recovery lime
Time 20
20 -— 25
25 -— 30
30 -— ns
ns
Reeovery lime
Time 17
17 -— 20
20 -— 25
25 -— ns
ns
1) Refer to Switching Test Conditions

Condltlons.section.
section.
2) Calculated Refer to
to fmax
fmax Description
section.
4) Clock pulses of widths less than the specification may be detected as valid clock signals.
3-23 4191.Rev.A
4/91•Rev.A
·. Latlioo
flJ
.J..J
Lattice'
Semiconductor
SemJconducwr
C o r p Corporation
oration
Gl
GAL22111 0B1883C
GAL22V1 01883C
GAL22V101883C
SWITCHING WAVEFORMS
INPUTor
\\\\\\\
INPUT or
INPUTor
INPUT or
VALIDINPUT I/OFEEDBACK
VOFEEDBACK
\MZESSV
\\\\\ ,
I/OFEEDBACK
110 FEEDBACK
41-ts u t b
COMBINATORIAL
COMBINATORIAL CLK
ClK
OUTPUT
OUTPUT 41-tc
REGISTERED
REGISTERED
OUTPUT
OUTPUT
411----ittmax
(external tdbk)
Registered Output
Registered Output
INPUTor
INPUT
I/OFEEDBACK
VOFEEDBACK
t dis 4—ten --01.
OUTPUT
OUTPUT
ClK
CLK
tmax (Iniernal ldbk)--00.
Input or 110
I/O to Output Enable/Disable
REGISTERED
REGISTERED
FEEDBACK
FEEDBACK
fmax
fmax with
with Feedback
Feedback
tw h twl
tw I—11110
ClK
CLK
Clock Width
Width
INPUT or
INPUT INPUT
INPUToror
VOFEEDBACK
I/OFEEDBACK I/O FEEDBACK
VO FEEDBACK
DRIVINGAR
DRIVINGAR DRIVING
DRIVING SPSP
tc0m=
411--- tar w tar r *
ClK
CLK
REGISTERED
REGISTERED
OUTPUT
OUTPUT
tar
REGISTERED
REGISTERED
OUTPUT
OUTPUT \\\\\\\\\\
ClK
CLK
Synchronous
Synchronous Preset
Preset
Asynchronous Resat
Reset
3-24
3-24 4/91.Rev.A
4/91.Rev.A
[JJ
LIlli
lx1ttiOOGl
balcottio.cer:
SemiconducUJr
C o r p CorporaUon
oration
GAL2211108/883C
GAL221/1 0/883C
GAL22V101883C
film
fmax DESCRIPTIONS
DESCRIPTIONS
CLK
elK CLK
CLK
···._e ......................... ·............... · ..................,
· .
—,--110 LOGIC
LOGIC
lOGIC ARRAY
REGISTER
REGISTER
A R R AY
ARRAY
REGISTER
·.................................................................
141114f----
14 t s . • 4 ....
tcl
tpd
Note: fmax with
with external
externalleedback
feedback is
calculated from measured tsu and tco.
too.
fmax
fmax with
with Internal
internal Feedback
li(tsui-tcf)
ClK
CLK Note: tcf is
Note: tet is a calculated
calculated value, derived
derived by
subtracting
subtracting tsu from the period period of fmax
f max wI w/
internal feedback (tof
internal feedback (tel -l i1/fmax
f max -t stsu).
u ) . The
The
value
valueof tof is
oftcf is used
used primarily
primarilywhen
whencalculating
calculatingthe
the
LOGIC
REGISTER
delay
delay from
from clocking
clocking a register
register to
to aa combinato-
combinato-
ARRAY f----+--+ rial
rial output (through
(through registered
feedback), as as
shown
shown above. For For example,
example, the timing
timing from
from
............................................ -................ ... clock
clock to
toaa combinatorial
output isis equal
equal to
totel
tcf ++
tpd.
to&
Note: fmax with
with no feedback
feedback maymay be be less
less
1ltwh + twl. This is to allow lor
than 1/twh for a clock
clock
duty cycle of other than 50%.
SO%.

GND to 3.0V +5V
Input Rise and Fall Times 3ns 10%
10%-90%
—90%
1.5V
Output Timing Reference Levels 1.SV
1.5V FROM OUTPUT (OIQ)
FROMOUTPUT (0/Q) TEST
TESTPOINT
POINT
Output Load See
See Figure UNDER TEST
UNDERTEST
O.SV from steady-state active CL
level.

(see figure)
Test Condition RI
Rt R2
R2 CL
CL
1 390'1
3900 7S0'1
7500 SOpF
50pF CLINCLUDES
CLINCLUDESJIG AND P
JIGAND PROBE TOTAL
ROBETOT CAPACITANCE
ALCAP ACITANCE
2 Active High —
00 7S0'1
7500 SOpF
50pF
Active Low 390'1
3900 7S0'1
7500 SOpF
50pF
3 Active High •,0
00 7S0'1
7500 SpF
5pF
Active Low 390'1
3900 7S0'1
7500 SpF
5pF
3"-25
3-25 4/91.Rev.A
4/91.flev.A
'L
i s I Lattice® S p e c i f i c a t i o n s GAL22V10BI883C
Semiconductor
Semiconducwr
GAL-221110131883C
Corporation G A L 2 2 1 f 1 0 GAL22V101883C
Corporation 1 8 8 3 C
Specifications
GAL22V10/B ORDERING INFORMATION (MIL-STD-883C and SMD)

SMD )
Ordering ##
Ordering
Tpd Tsu
T8U Too
Teo too
Icc Package
MlL-STD-883C SMD #
SMD#
(ns)
(n8) (ns)
(n8) (ns)
(n8) (mA)
15 12
12 88 150
150 24-Pin CERDIP
24-Pin GAL22V10B-15LD/883C
GAL22V10B-15LD1883C 5962-89841 03LA
5962-8984103LA
150
150 28-Pin LCC
28-Pin LCC GAL22V10B-15LR1883C
GAL22V10B-15LRI883C 5962-89841033A
5962-89841033A
20 17
17 15 150
150 24-Pin CERDIP
24-Pin GAL221/10-2OLD/883C
GAL22V10-20LD1883C 5962-8984102LA
5962-8984102LA
150
150 28-Pin LCC
28-Pin LCC GAL22V10-20LR/883C
GAL22V10-20LRI883C 5962-89841023A
5962-89841023A
25
25 20
20 20
20 150
150 24-Pin CERDIP
24-Pin GAL22V10-25LD/883C
GAL22V10-25LD1883C 5962-8984104LA
5962-8984104LA
150
150 28-Pin LCC
GAL22V10-25LRI883C 5962-89841043A
5962-89841043A
30 25
25 20 150
150 24-Pin CERDIP
24-Pin GAL221/10-3OLD/883C
GAL22V10-30LD1883C 5962-8984101LA
5962-8984101 LA
150
150 28-Pin LCC
GAL22V10-30LRl883C 5962-89841013A
5962-89841013A
Note: Lattice recognizes the

the trend in military device procurement towards
towards using
using SMD
SMD
compliant devices, as such, ordering by this number where itit exists
by this exists is
is recommended.
recommended.
xxxxxxxx
XXXXXXXX -XXX
X X X
GAL22V10 D e v i c e Name
GAL22V10B
Speed (n8) _ _ _ _ _ _- l
Speed (ns) ISS3C •= SS3C
MIL Process /883C 883C Process
Process
L = Low Power Power

Power ----------1 Package DD =
' - - - - - - Package = CERDIP
CERDIP
R
R..= LCC
LCC
3-26
3-26 4f91.Rev.A
4/91.Rev.A
Lattice® GAL2ORA101883C
GAL20RA 101883C
.l..I Corporation
Semiconductor Semiconductor High-Speed Asynchronous E2CMOS
High-Speed E2CMOS PLD
Generic Array
Generic
PLD
Array Logic™
Logicrm
DIAGRAM
• HIGH PERFORMANCE E2CMOS
EICMOS·E TECHNOLOGY
TECHNOLOGV
-— 20 ns Maximum Propagation Delay IPLD----------,
/FL
-— Fmax ==41.7MHz
41.7 MHz
to Data Output
-— TTL Compatible 8 mA Outputs INPUT
INPUT cum VOr0
IJO/O
UHraMOS· Advanced
-— UltraMOS° Advanced CMOS Technology
I I
• 50% REDUCnON
REDUCTION IN POWER FROM BIPOLAR INPUT
INPUT
8
r • r - r [ l IJO/Q
1/0/0
-— 75mA
75mA Typ Icc
I I
• ACTIVE PULL-UPS ON ALL
PULL·UPS ON ALL PINS
INPUT
INPUT c A o c i r — I D 1.0/0
I/0/0
• E'EZ CELL TECHNOLOGY
TECHNOLOGV
--
-— Reconfigurable
logic I
-— Reprogrammable Cells INPUT
INPUT 11010
IJO/Q
-100%
— 100% Tested/Guaranteed
Tested/Guaranteed 100% Vlelds
Yields
-— High Speed Electrical Erasure «50
(<50 ms)
ma) II
-— 20 Vear
Year Data Retention INPUT
INPUT 110/0
IJO/Q
• TEN OUTPUT LOGIC MACRO CELLS

MACROCELLS
-Independent
— Independent Programmable Clocks INPUT
INPUT E l — C r - - O L P. IJO/Q
tiOtO
-— Independent
Independent Asynchronous Reset
Reset and
and Preset
-— Registered or Combinatorial wHh PolarHy
with Polarity II
-— Full Function and Parametric Compatibility with INPUT
INPUT OLMC 11010
IJO/Q
PAL20RA10
PAL2ORA10 I I
• PRELOAD
POWER·ON RESET
RESET OF ALL
ALL REGISTERS
REGISTERS INPUT
INPUT 0 - - - I t s r - - OLIAC I/010
IJO/Q
-100%
— 100% Functional Testability I I
.•• APPLICATIONS
APPUCAnONS INCLUDE: INPUT
INPUT 0 - 4 : I t - - IJO/Q
I/0/0
-— Standard Logic
Logic Consolidation
Consolidation II
-— MuHlple
Multiple Clock Logic Designs INPUT
INPUT D — f t • - - OLMC IJO/Q
1/010
• ELECTRONIC
ELECTRONIC SIGNATURE FOR
FOR IDENTIFICATION
IDENTIFICATION
/oE
El/OE
DESCRIPTION
The GAL20RA 10/883C is a high performance E2CMOS

GAL20RA10/883C E2CMOS program-
program- PIN
PIN CONFIGURATION
CONFIGURATION
mable logic device processed in full
full compliance to to MIL -5TD-883C.
MIL-STD-883C.
With a 2Ons
20ns maximum propagation delay time, it is the the fastest
fastest
military grade 20RA
20RA1010 device on the market. In In addition to to speed
speed CERDIP
CERDIP
performance, Lattice's Electrically Erasable
Erasable (E2)
(E2) floating
floating gate
gate LCC
LCC
technology provides low power performance. The The GAL2ORA10's
GAL20RA 1O's Vee
Vec
Icc of 75mA,
typical !cc 7SmA, represents
represents a 50%50% savings in power when IIOIQ
I/0/0
compared to bipolar counterparts. E2technology
E2 technology also offers
offers high _e_20S I/O/Q
I/0/0
speed (<50ms)
(oOms) erase times providing the the ability
ability to
to reprogram or
test the devices quickly and efficiently.
A—
Z U 21 VOIQ
Ito/0
I/O/Q
I/0/0
WOIQ
I/0/0 IIOIQ
I/0/0
flexibility by WOIQ
WOO IIOIQ
I/0/0
allowing the Output Logic Macrocell (OLMC) to be
be configured by He GAL20RA10
GAL2ORA10 He
NC IIOIQ
the user. The
The GAL2ORA10
GAL20RA10 is a direct parametric
parametric compatiple
compatible 1 I/0/0
CMOS replacement for Top

Top View
View WOIQ
I/0/0
IIOIQ
for the PAL2ORA10
PAL20RA 10 device.
WOIQ
I/0/0
1/0/0
I/O/Q
I/0/0
complete WOIQ
li0/0
I/O/Q
I/0/0
AC, DC, and functional testing during manufacturing. Therefore,
Therefore,
az
LATTICE guarantees 100% field programmability and functionality 12 I/O/Q
I/0/0
of all
all GAL products. LATTICE
LATTICE guarantees data
data retention exceeds
exceeds " OND
GND 10E
/OE
20 years.
Copyright
Copyright C1991 Lattice SemIconductor
01991 Lattice Semiconductor Corp. GAL,
GAL. E'CMOS
PCMOS and UttraMOS
UltraMOS "'"
are raglstered
registered tradematks
trademarks 01
of lattice
Lattice SemlconduClor
Corp. Generic Logic Isisaatrademark
Array logic trademark01
of Lattlco
LatticeSo_uc-
Semiconduc-
tor Corp. PAL Is aa ragistored
PAL is registered trademark 01 Micro Devices.
of Advanced Micro The apeclflcationll
Devices, Inc. The specifications and information horeln are subject
herein are subject to change without
to chango without notice.
notice.
LATIICE SEMICONDUCTOR CORP

LATTICE SEMICONDUCTOR CORP.,.• 5555
5555 N.E. Moore Ct.,
N.E. Moore Hillsboro, Oregon
Ct., Hillsboro, Oregon 97124,
97124, U.S.A.
l 1991.Rev.A
1 9 9 1 . R e v. A
Tel.
Tel. (503) 681-0118; 1-800-FASTGAL;
(503) 881-0118; 1-800-FASTGAL; FAX
FAX (503)681-3037
(503)681-3037
3·27
3-27
[JJ tattiOO"
I s Lattice®
.L.I Semiconductor
Semironductor
C o r p CorporaUon
oration
Specifications GAL2ORA10 883C
GAL20RA10/883C

COND.
Supply voltage Vcc — 0 . 5-0.5 to +7V
Vee ....................................... Military
Military Devices:
Devices:
— 2 . -2.5 5 to to Vcc
Vee +1.0V Case Temperature
Case Temperature (To)
(Tc) .............................
- 5 5 -55 to
to ++125°C
125°C
Off-state output voltage applied ..........— 2-2.5 . 5 to Vcc +1.0V
(Vcc)
— 6 5 -65 to 150°C Respect to
with Respect to Ground
Ground ......................
+ 4 . 5+4.50 0 toto +5.50V
+5.50V
- 5 5 -55 to 125°C
Power Applied .........................................
''Absolute Maximum
Ratings·
These
the device
device
at these or at any other conditions above
above those
those indicated in the
the
programming.
DC CHARACTERISTICS
Specified)

CONDITION MIN.
MIN. TYP.3
TYP.3 MAX.
MAX. UNITS
UNITS
VII.,
Vss - 0.5 -- 0.8
0.8 VV
VIH
2.0 -— VCC+l
Vcc+l VV
IlL' Input or 110
I/0 Low
Low Leakage
Leakage Current OV
OVSVIN
VIN 5S_VII_
VIL (MAX.)
(MAX.) -— -— -100
-100 H.A
IIH Input or I/O
110 High Leakage Current 3.SV S VIN
3.5V 5. Vliv5S_Vee
Vcc -— -— 10
10 RA
VOL Output Low Voltage IOL
loi, == MAX. Yin
MAX. Vi n '"= VIL
V. or
or VIH
VIR -- -- O.S
0.5 VV
VOH
10H'"= MAX. Yin
MAX. Vi n '"= VIL
Vii. or VIH
or 1/1H 2.4
2.4 -— -— VV
tOL
mA
IOH
tOH High Level Output Current -— -— -3.2
-3.2 mA
mA
los2
I0S2 Output Short Circuit Current Vcc",SV Vour = O.SV
Vcc = 5V VOUT T" ..= 2S·C
0.5V TA 25°C -so
-50 -— -13S
-135 mA
mA
ICC Operating Power
Power Supply
Supply Current VIL=O.SV
VIL = 0.5V VVIH
I H =3.0V
= 3.0V -— 7S
75 120
120 mA
mA
ftoggle '" ISMhz Outputs Open
ttoggle . 15Mhz Outputs Open
1) The leakage current is due to the
the internal pull-up on
on all
all pins. See the
pins. See the Input
Input Buffer
Buffer section
section in
in the
the commercial
commercial datasheet
datasheet for
for more
more
information.
2) One output at a time for
for a maximum duration of one one second. Vout = O.SV
was selected
selected to
to avoid
avoid test
test problems
problems caused
caused by
by tester
tester
Guaranteed but not 100%1OO"k tested.
tested.
3) Typical values are at Vcc '"= SV
5V and TA
TA'"= 25
25 ·C
'C
CAPACITANCE (TA 25°C, ff = 1.0 MHz)

(TA = 25°C, MHz)
SYMBOL PARAMETER
PARAMETER MAXIMUM'
MAXIMUM" UNITS
UNITS TEST
TEST CONDITIONS
CONDITIONS
C,
C, Input
Input Capacitance 10
10 pF
pF VVcc
cc '"= S.OV.
5.0V, V,
VI == 2.0V
2.0V
ClIO
Cm 110
I/O Capacitance 10
10 pF
pF Vee
Vcc== S.OV.
5.0V, VIIO
Vm == 2.0V
2.0V
<Guaranteed
"Guaranteed but not
not 100% tested.
3-28
3-28 4191.Rev.A
4/91.Rev.A
.l.J Corpora
I L
Lattice®
Semironductor
Semiconductor Specifications GAL2ORA10 / 883C
GAL20RA 10 1883C
tion
COl'poraUon
OVer Conditions
TEST
-20
·20 -25
·25
PARAMETER
DESCRIPTION UNITS
UNITS
COND.' MIN. MAX.
MIN. MAX. MIN. MAX.
MIN. MAX.
tpd 1 to Combinatorial Output
Input or I/O to Output -— 20
20 -— 25
25 ns
ns
tco 1 to Output
Clock to Output Delay -
— 20
20 -— 25
25 ns
ns

Input or before Clock 10
10 -— 15
15 -— ns
ns
th -— Hold Time,
lime, Input or Feedback after Clock
Clock 33 -— 55 -— ns
ns
..
33.3 -— 25.0
25.0 - — MHz
MHz I
I
Feedback, 1/(tsu + tco)
External Feedback,1/(tsu tco)
tmax2
fmax 2
1 with
Maximum Clock Frequency with 41.7
41.7 -— 33.3
33.3 -— MHz
MHz
No Feedback I
twh33
twh -— Clock Pulse Duration, High 12
12 -— 15
15 -— ns
ns
twJ3
twP -— Clock Pulse Duration, Low 12
12 -— 15
15 -— ns
ns
ten!
ten / tdis 2,3 Input
Input or I/O to
-
to Output Enabled!
Enabled / Disabled -— 20
20 -— 25
25 ns
ns
ten /tdis
/ 'Nis 2,3 OE to
to Output
Output Enabled // Disabled -— 15
15 -— 15
15 ns
ns
tar/tap
tar /tap 1 Input or 110
II1Put I/O to
to Asynchronous
Asynchronous Reset // Preset
Preset -— 20
20 -— 25
25 ns
ns
tarw / tapw -— Asynchronous Reset / Preset

Preset Pulse
Pulse Duration 20
20 -— 25
25 -— ns
ns
tarr /tapr
/ tapr -— Asynchronous Reset / Preset Recovery
Recovery Time
Time 12
12 -— 20
20 -— ns
ns
20 -— 25
25 -— ns
ns
tsp -— Preload Setup
Setup Time
Time 15
15 -— 20
20 -— ns
ns
thp -— Preload Hold Time
Time 15
15 -— 20
20 -— ns
ns
1) Refer to SWitching
Switching Test Conditions section.
2) Refer to fmax Descr
Descriptions
ptions section.
be detected
detected as
as valid
valid clock
clock signals.
signals.

GND to 3.0V +5V
+5V
3ns 10%-90%
10% – 90%
1.5V
1.5V
3·state
0.5V from steady·state active
from steady-state
level.
FROM OUTPUT (0/0)
FROMOUTPUT (0/0) --+---.-- TEST
TESTPOINT
POINT
UNDER TEST
UNDERTEST
CL
Test Condition R1
RI R2
R2 CL
CL R2
11 470n
4700 390n
3900 50pF
50pF
2 Active High
Active High co
00 39an
3900 50pF
Active Low 470n
4700 39an
3900 50pF
50pF
3
3 Active High 00
co 39an
3900 5pF
5pF
C
CL INCLUDESJIGA
LlNCLUDESJIG NDP
AND ROBET
PROBE OTALC
TOTAL APACITANCE
CAPACITANCE
Active Low
Active Low 470Q
4700 39an
3900 5pF
5pF
3·29
3-29 4191.Rev.A
4/91.Rev.A
[JJ Lattice*
LLattice'
L.tI Semiconductor
SemironduCUJr
Corporation
CorporatiOn
Specifications GAL2ORA1 / 883C
GAL20RA101883C
SWITCHING WAVEFORMS
Input or Input or
Input or
110 Feedback
I/O Feedback - - X I/O Feedback
1/0 Feedback
— 4
tpd ten a( th
Combinatorial Clock
Clock
Output
Registered
Registered
Output
Output
Registered Output
Registered Output
Input or Input
Input or
or
1/0 Feedback
I/O Feedback 1/0 Feedback
I/O Feedback
Asserting Preset
Preset Asserting Ruet
Asserting Reset
Registered Registered
Registered
Output Output
Output
Clock Clock
Clock ______xxXXt=
Asynchronous
Asynchronous Preset Asynchronous Reset
Asynchronous Reset
Input or E
110 Feedback
I/O Feedback
tdis en tdis n--°
Device Output
Output Device Output
Device Output
Input or I/O Feedback to Enable I/ Disable

1/0 Feedback O E OE to
to Enable
Enable I/ Disable
Disable
4 - - twl — 4 twp--°
Clock
P
PL
tsp thr)
Clock Width
Clock Width
All Pins
1/0 Pins
All I/O
XZX
Parallel Preload
Parallel Preload
3-30 4/91.Rev.A
4/91.IRev.A
Lattice® I'
'L
I
L Semiconductor
ISemiconductor Specifications GAL2ORA10 E383C
GAL20RA101883C
GaporaUOlJ
Corporation
1firm DESCRIPTIONS
fmax DESCRIPTIONS
CL K
CLK
ClK
LK
...... ---_ ..................................................... ,
·· ...
· V
LOGIC
LOGIC LOGIC
LOGIC
A R R AY
REGISTER
REGISTER REGISTER
REGISTER
ARRAY ARRAY
--4110 ARRAY t--+--.
:............................................................... : .................................................. __ .....

,..I
..- - - .. 10-11..
11I - -t - -t t ••
fmax
tmax WHh
With No
No Feedback
Feedback
1/(tsui-tco) Note: fmax
Note: with no
fmax with nofeedback
feedbackmay maybebe less
less
with external feedback is cal-
Note: fmax with cal-
than litwh ++twl.
than 1ttwh twl. This
This is
isto
toallow foraaclock
allowfor dock
culated from measured tsu and tco.
tco. duty
duty cycle
cycle of
of other
other than
than 50%.
50%.

SCHEMATICS
PIN I >
outPut _ _ _
Data V I PIN
PIN
Feedback oil
Vee
c Active
ActivePuG-up
Pull-up
Active Pull-up Circuit
Cireuit
(Vrof 3 2 V ) Circuit
Vee
V cc
...i ....
..... Tri,S'3'.
Tr i - S t a t e V r e t N r e(V'"'
t Typic"
Typical-.3.2V)
3.2V)
Control
Control
V cc Vrel V c c
Output
Output
,'' 'I
Dala
Data PIN
PIN
PIN
Ftedbac:k
Feedback
(To
(ToInput
InputBuller)
Butler)
Input Output
Output
3-31 4191.Rev.A
4/91.Rev.A
Lattice®
L.J CorporaUon
Semiconductor
Semiconductor
Corporation
Specifications GAL2ORA10 E3133C
GAL20RA101883C
GAL2ORA10/883C MILITARY GRADE

GAL20RA10/883C GRADE ORDERING
ORDERING INFORMATION
INFORMATION
Ordering #
Ordering'
Tpd Tsu Tco icc
Icc Package
Package MIL-STD483C
MIL-STD-883C SMD #
SMD.
(ns) (ns) (ns) (mA)
(rnA)
20 10 20
20 120
120 24-Pin CERDIP
24-Pin GAL2ORA10-2OLD/883C
GAL20RA 10-20LD1883C Contact Factory
Contact Factory
28-Pin LOC
28-Pin LCC GAL2ORA10-20LR1883O
GAL20RA 10-20LR/883C Contact Factoly
Contact Factory
25 15
15 25
25 120
120 24-Pin CERDIP
24-Pin GAL2ORA10-25LD/883C
GAL20RA 10-25LD1883C Contact Factory
Contact Factory
28-Pin
28-Pin LCC GAL2ORA10-25LR/883C
GAL20RA 10-25LR/883C Contact Factory
Contact Factory
xxxxxxxx
XXXXXXXX -XXX
X X X
GAL2ORA10 Device
GAL20RA10 Device Name
Speed (ns) - - - - - -...... MIL Process

' - - - - - MIL Process /883C
I883C == 883C
883C Process
Process
L = Low Power Power - - - - - - - - - - ' Package DD == CERDIP

' - - - - - - Package CERDIP
R = LCC
R=LCC
3-32
3-32 4191.Rev.A
4/91.Fiev.A

Datasheet Levels 2 - i i 2-ii
GAL16V8A/B
GAL16V8A1B 2 - 1 2-1
GAL20V8A/B 2 - 2 5 2-25
GAL18V10 2 - 4 7 2-47
GAL22V10/B 2 - 6 1 2-61
GAL26CV12 2 - 8 1 2-81
GAL2ORA10
GAL20RA10 2 - 9 5 2-95
GAL6001 2 - 1 0 9 2-109
ispGAL16Z8 2 - 1 2 1 2-121

Military Program Overview 3 - 1 3-1
3 ,

GAL16V8A/B
GAL 16V8A1B Military Datasheet 3 - 5 3-5
GAL20V8A Military Datasheet 3 - 1 3 3-13
GAL22V10/B Military Datasheet 3 - 1 9 3-19 I
GAL2ORA10
GAL20RA 10 Military Datasheet 3 - 2 7 3-27 I
--
I
Quality Assurance Program 4 - 1 4-1
PCMOS 4 - 5 4-5

I
GAL Metastability Report 5 - 1 5-1 5 5

Avoid the Pitfalls of High-Speed Logic Design 6 - 1 6-1 6 6
Extending the 22V10
22V1 0 EPLD 6 - 7 6-7
In-Circuit Logic Device Can be Reprogrammed on the Fly 6 - 96-9
Development Tools 7 - 1 7-1 7 7
4-i
4-ii
Assurance
Quality Assurance
Program
INTRODUCTION SUBCONTRACTOR CONTROL
SUBCONTRACTOR CONTROL
Lattice views
views quality
quality assurance
assurance aas s aa corporate
corporate All subcontracted
All subcontracted operations
operations must
must be be performed
performed by
responsibility and an integral part of
of all planning
planning activities. sources exhibiting a quality
sources quality program
program commensurate
commensurate to to
Lattice's Quality Assurance organization is independent of Lattice. These
that of vendors are
These vendors are audited
audited at
at least
least once
once
from Manufacturing
from· Manufacturing andand has
has direct
direct access
access to
to top
top every yearto
every year to monitor
monitortheir
theircompliance
compliance to to Lattice's
Lattice's Quality
Quality
management, assuring sufficient authority is afforded to
management. Assurance Program.
Assurance Program. Any
Anymajor
majoraudit
auditdiscrepancy
discrepancyrequires
requires
quality issues. corrective action
corrective action and
and may result
result in
in disqualification.
disqualification.
full compliance
Lattice's quality program is in full compliance to
to the
the quality
quality DOCUMENT CONTROL
DOCUMENT CONTROL
assurance requirements
requirements of of MIL-M-38510
MIL-M-38510 Appendix
Appendix A Lattice's document
Lattice's document control
control system
system isis under
under the
the direction
direction
and all inspection system requirements of MIL-I-45208. ofQuality
of QualityAssurance
Assurance and
andhas
hasthe
theresponsibility
responsibilityof
ofassuring
assuring
that every product
product has
has adequate
adequate written
written documentation
documentation
QUALIFICATION released before
released before production
production begins.
begins.
All new products, processes and vendors must pass pass pre-
defined evaluations
evaluations before
before receiving initial
initial qualification Drawings
Drawings and and specifications
specifications relatedrelated tto o materials,
materials,
release. Majorchanges to products, processes or orvendors processes, testing,
vendors processes, testing, products
products and and subcontractors
subcontractors are are
require additional qualificaton before implementation. To maintained maintained by the DocumentDocument ControlContrOl Department.
Department. AA
continuing conformance
assure continuing conformance to
to reliability requirements,
requirements, numbering
numbering system
system identifies each each document
document by by revision
revision
a weekly accelerated monitor program is maintained on on status, function
function and and category.
category.
all processes and and wafer fabrication sites.
Any change
Any change to to existing documentation
documentation must must be be properly
properly
IN-PROCESS CONTROL approved and
approved and released
released beforebefore implementation
implementation of the the
Qualified product
product must
must be
be manufactured
manufactured under under strict change. The change
strict change. change is is implemented
implemented only only ifif approved
approved by by
quality controls that start with regulated procurement and and the
the appropriate functional
functional groups.
groups.
documented inspection plans for all incoming materials.
Sample testing and in-line monitoring as well well as statistical
statistical CONTROL
CONTROL OF OF NONCONFORMING
NONCONFORMING MATERIAL MATERIAL
feedback at
process control charts provide constant feedback at each
each All
All identified
identifiedfailuresfromqualification
failures from qualification testing,testing, inspections,
inspections,
step of the
critical stepof the manufacturing process.
process. Nonconforming customer customer returns
returns or or in-process
in-process screening
screening are are processed
processed
material i is identified, segregated,
s identified, segregated, analyzed
analyzed and and through
through Lattice's
Lattice's Failure
Failure Analysis
Analysis group
group to to determine
determine the the I
dispositioned according to procedures that also also require

require cause
cause or relevancy
relevancy of the failurefailure and
and initiate
initiate corrective
corrective I
corrective action be specified to eliminate the cause of the actions actions toto eliminate
eliminate the
the cause.
cause. All failure analysis
All failure analysis reports
reports I
defect. are
are reviewed
reviewed by by Quality
Quality Assurance
Assurance to to convey
convey awareness
awareness !
of
of any
anypotential
potentialproblems
problems and andassure
assurethat thatproper
propercorrective
corrective
CALIBRATION action
action is taken.
taken.
All critical
critical equipment involved in the manufacture, testing,
testing,
or inspection of Lattice product must
orinspectionof must meetthe
meet the requirements
requirements Lattice
Lattice has
has a Material
Material Review
Review Board
Board (MRB)
(MRB) to to investigate
investigate
of our established calibration system that is in compliance
compliance the the cause
causeof ofnonconformance
nonconforrnance and anddisposition
dispositionthe thematerial.
material.
to MIL-STD-45662. Lattice
Lattice andand customer
customer specification
specification requirements
requirements are are
thoroughly
thoroughly reviewed
reviewed during
during MRS
MRB dispositions.
dispositions. The MRS MRB
TRAINING consists ooff representatives
representatives from from Manufacturing,
Manufacturing,
Lattice manufacturing
All Lattice manufacturing personnel
personnel complete
complete aa Engineering,
Engineering, and and Quality
Quality Assurance.
Assurance.
comprehensive trainingtraining program
program and and obtain
obtain formal
formal
certification for each production operation before they are Product Product retumed
returned by by customers
customers (RMA)(RMA) shallshall be be analyzed
analyzed
allowed to manufacture
manufacture products.
products. Operators
Operators mustmust be and and dispositioned with respect to
with respect to Lattice
Lattice and and customer
customer
recertified on on aa periodic
periodic basis
basis tto assure ongoing
o assure ongoing specifications.
specifications.
compliance to all written procedures and specifications.
4-1
4-1
Assurance Program
Quality Assurance
Finished Wafer Process CQntrol

Control Points
Pointl
for Commercial/Industrial Devices
fQr
STEP
SIEf. CHARACTERISTICS CHART TYPE
CHART TYPE RESPONSIBILITY
RESPONSIBILITY
Wafer Parametric Test Test Structure Performance

Test Performance Cp, K
Cp,K Engineering
Engineering
Die Functional Test

Ole Functional, AC, DC
DC Performance . Trend
Trend Engineering
Engineering
Wafer Saw Kerf Width

Kerf X-R
X-R Production
Production
Die Attach
Ole Visual Defects
Visual PP Production
Production
Wire Bond Pull Test X-R

X-R Quality Assurance
Quality Assurance
Mold Mold Tool Temp

Mold X-R
X-R Production
PrOduction
Deflash Trim Form

Fonn Visual Defects PP Production
Production
Coplanarity (PLCC only) X-R
X-R Production
Production
Solder Plate Thickness

Thickness X-R
X-R Quality Assurance
Quality Assurance
"/'O Pb
"IoPb PP Quality Assurance
Quality Assurance
Assembly Final Visual Visual Defects PP Quality Assurance

Quality Assurance
Test Functional, AC, DC Performance

AC, DC Trend
Trend Engineering
Engineering
Topside Mark Visual Defects

Visual P
P Production
Production
Lead Straighten Splay, Lead Alignment

Splay, (PDIP only)
Alignment (PDIP only) PP Production
Production
Final OA
QA Visual Defects P
P Quality Assurance
Quality Assurance
Final QA Test Functional, AC,

AC, DC Performance P
P Quality Assurance
Quality Assurance
4-2
4-2
Qualification
Qualifica.tion
Program
INTRODUCTION
qualification programforexamining
Lattice has an intensive qualification program for examining The following table outlines the steps which
The which must be be
and testing
testing new
new products,
products, processes,
processes, and
and vendors
vendors in performed before
performed before a new
new product,
product, package
package or or process
process isis
order to insure
insure the
the highest
highest levels
levels of quality.
quality. Lattice's
Lattice's qualified. TThe
qualified. h e requirements
requirements listed
listed below
below areare general
general
Reliability Engineering Group is responsible for defining guidelines. Detailed information
guidelines. informationonon Lattice's
Lattice's qualification
qualification
and implementing
implementing this qualification program. process is
process is available
available to
to customers
customers upon
upon request.
request.
Qualification Requirements
# of
'of Duration
Duration
Test Samples New Product
New New Wafer
New Wafer Process
Process New Package
NewPackaae
125°0 C Operating Lifetest

125 300 1,000 Hours
1,000 Hours 2,000 Hours
2,000 Hours'1
(5.25V)
150°0 C Biased Retention

150 450
450 1,000 Hours
1,000 2,000 Hours
2,000 Hours'1
Bake (5.25V)
Endurance Cycling 75 10,000 Cycles

10,000 10,000 Cycles
10,000 Cycles N/A
N/A
ESD 48
48 End of
End of Test
Test End of
End of Test
Test N/A
N/A
Latch-Up Immunity End of

of Test
Test N/A
II
27 End End of
End of Test
Test N/A
Temperature Cycling 150

150 11,000 Cycles
,000 Cycles 1,000 Cycles
1,000 Cycles 11,000 Cycles
,000 Cycles
(-65 to 150°
1500 C)
Biased 85/85 (5V) 225 N/A

N/A 1,000 Hours
1,000 Hours 1,000
1,000 Hours
Hours
Autoclave (121°
(121 0 C, 15psig) 150 N/A 336 Hours
336 Hours 336
336 Hours
Hours
Lead Integrity (DIP only) 99 NlA

N/A N/A
N/A End
End of
of Test
Test
Solderability 99 NlA
N/A N/A
N/A End of
End of Test
Test
Centrifuge 75
75 N/A
N/A N/A
N/A End
End of
of Test
Test
Bond Strength 12
12 N/A
N/A N/A
N/A End
End of
of Test
Test
1. Required
Required for new assembly technologies only.
4-3
Qualification Program
RELIABILITY MONITOR PROGRAM
The Reliability
Reliability Monitor Program
Program provides for a weekly The
provides tor The Reliability
Reliability Monitor
Monitor Program
Program is isdesigned
designedto to monitor
monitorall
all
monitorof
reliability monitor of Lattice
Lattice products.
products. The program
programassures tab and
assures tab and assembly
assembly facilities
facilities as
as well as each
each process
processes, products, and packages
that all Lattice processes, packagescomply technology in
comply technology in production.
production. A summary
summaryof ofthe
theprogram
programtest
test
on aa continuing
continuing basis
basis with
with established
established reliability
reliability and and sampling plan
and and plan is
is shown
shown below.
below.
quality levels.
Weekly Reliability Monitor Program

Test # of Samples
#ofsamples Duration
Duration
125°0 C Operating Lifetest

125 LHetest (7.00V) 70
70 160 Hours
160 Hours
200°0 C Biased Retention Bake (5.25V)

200 70
70 160 Hours
160 Hours
Autoclave (121°
(121 0 C, 15psiq) 35
35 160 Hours
160 Hours
4-4
E2CMOS Testability
Improves Quality
INTRODUCTION
INTRODUCTION OTHER METHODS
OTHER METHODS ARE ARE IMPRECISE
IMPRECISE
The inherent
inherent testability
testability of
of Lattice's
Lattice's E2CMOS
E2CMOS PLDs PLDs All PLD
All PLDdevices
devices mustmustbe betested
testedto to some
somedegree
degreeto tovalidate
validate
significantly improves
significantly improves their
theirquality and reliability.
quality and reliability. By using
using functionality and
functionality and performance.
performance. Technologies
Technologies that thatare
arenot
not
electrically erasable
erasable EEPROM
EEPROM technology
technology to produce
produce erasable or
erasable or offer
offer lengthy
lengthy erase
erase times
times severely
severely constrain
constrain
GAL devices,
devices, Lattice
Lattice is able
able to perform 100% AC/DC, the test
the testflexibility.
flexibility. Since the
the normal
normal "user"
"user" programmable
programmable
functional, and parametric testing of of every single device. elements cannot
elements cannot bebe programmed
programmed during during manufacture
manufacture (all
(all
In order
order to achieve
achieve the
the highest
highest quality
quality levels,
levels, Lattice
Lattice elements must be
elements be available
available for
for end-user
end-user programming)
programming)
programs and tests each device repeatedly throughout throughout the manufacturers
the manufacturers resortresorttotousing
usingSimulated
simulatedand andcorrelated
correlated
the manufacturing process. performance of
performance of test
test rows,
rows, test
test columns
columns and and phantom
phantom or or
dummy-test arrays.
dummy-test arrays. At best, this
At best, this is
is aa statistical
statistical measure
measure
ACTUAL TEST VS. SIMULATED TEST of the
of the actual
actual device
device performance.
performance. One One needneed only
only look
look at
at
Why is "actual
"actual test" so significant?
signHicant? PLDs,
PLDs, unlike most
most the "normal"
the "normal" programming
programming yield yield fallout
fallout ofof 0.5
0.5 ->3 3%% or or
other semiconductor
semiconductor devices,
devices, have
have aa programmable
programmable the "acceptable" post-programming
the post-programming test test vector
vector && board
board
element that determines the final device functionality and yield fallout
yield fallout ofof 0.5
0.5 -> 2 2%% toto know
know thatthat this
this correlation
correlation is
is
AC/DC performance.
performance. TheseThese programmable
programmable elements
elements weak. TThe
weak. h e quality
quality systems
systems of today are are measuring
measuring
can be fabricated from metal link fuses, programmable defects in
defects in the parts
parts per million
million (PPM).
(PPM). AA six sigma
diodes ortransistors,
or transistors, volatile static
static RAM
RAM cells,
cells, UV EPROM
EPROM program requires
program requires less
less than
than 3.4
3.4 PPM,
PPM, JouriQu[ orders of
cells or
or electrically
electrically erasable
erasable EEPROM
EEPROM cells.cells. Each
Each of magnitude less
magnitude less than that achievable
than that achievable with with non-testable
non-testable
these technologies
technologies carries
carries aa different
different variability
variability of
of PLDs.
PLDs.
programming success and a variancevariance in the
the impact of
of the
the
programming success on the performance and reliability reliability ACTUAL MATRIX
ACTUAL MATRIX PATTERNING
PATTERNING
of the device. The unique capability
The capability of
of E2CMOS devices to
PCMOS devices to be
be instantly
instantly
electrically erased
electrically erased allows
allows these
these devices
devices to
to be
be patterned
patterned
common programmable
The most common programmable elements are the
the metal
metal multipletimes
multiple timesduring
during Lattice's
Lattice'smanufacturing
manufacturingtest.
test. Normal
Normal
fuse, EPROM cell and EEPROM cell. Of Of these element array cells in the programmable
array programmable matrixmatrix are patterned,
patterned,
types, only the EEPROM cell can be
be thoroughly tested
tested by
by erased & tested
erased tested again
again and
and again.
again. TThe
h e test
test rows or
the manufacturer prior to shipment to an
an end
end user OEM.
OEM. columns, phantom arrays,
columns, arrays, etc.,
etc., that
that are
are used
used with
with other
other
technologies are
technologies are not necessary with with E2CMOS devices.
E2CMOS devices.
EEPROM ALLOWS ACTUAL TEST Programmability of
Programmability of every
everycell
cell is
ischecked
checkeddozens
dozensof oftimes.
times,
the methods identified
Each of the identified above
above can be programmed.
programmed.
In this manner they are all the same. TThe h e differences Historically, the checking
Historically, checking of a successful programming
successful programming
become apparent
apparent when the erase erase times are analyzed. operationconsisted
operation consistedof of no
nomore
morethan
thanaapasslfail
pass/failverHication
verification
Metal link and One-Time Programmable (OTP) devices step. This digital,
step. digital, blacklwhite
black/white style
style check
check is
is not
notadequate
adequate
cannot be erased. UV UV EPROM devices can be erased, to assure
to assure that
that the
the cell
cell is
is programmed
programmed properly
properly with
with
however the the time
time required
required is 20-30 minutes
is 20-30 minutes (and
(and anan sufficient margin
sufficient margin tto o guarantee
guarantee long-term
long-term reliable
reliable
expensive windowed package). EEPROM EEPROM devices, on performance of the
performance the device.
device. E2CMOS devices have
PCMOS devices have anan
the other hand, offer instant erasability on on the of 50
the order of additional cell
additional cell verHication
verification step
step that
that conSists
consists of
of an
an analog
analog
ms (thousandth's
(thousandth's of a second).
second). The The advantage of this this measure (to
measure (to millivolt
millivolt accuracy)
accuracy) ofthe
of theactual
actualcharge
chargestored
stored
instant erase for manufacturing test is significant. Instant
Instant on the
on the cell.
cell. This data is
This data is used
used for
for extensive
extensive reliability
reliability and
and
erase allows instant re-patterning for additional testing.
testing. quality measurements
quality measurements and and testing.
testing.
EEPROM technology
technology hhas a s bbeen
e e n used
used fforo r PLD
PLD
manufacturing by Lattice
Lattice for more than half a decade.
decade. WORST CASE
WORST CASE AC/DC
AC/DC TESTING
TESTING
Lattice refers
refers toto their
their high
high performance
performance EEPROM
EEPROM A PLD
A PLD does
does not
not have
have aadefined
defined function
function until
until the
the engineer
engineer
technology as E2CMOS
PCMOS technology. Extensive reliability
Extensive reliability patterns the
patterns the device
device with
with his
his custom
custom pattern.
pattern. TThe he
studies ofof the
the technology
technology havehave been
been performed
performed with manufacturer, when considering
manufacturer, considering the the testing
testing ofof a PLD,
PLD,
industry-wide acceptance, including the military. must consider
must consider the
the hundreds
hundreds of of different
different architecture
architecture andand
functional variations
functional variations that
that can
can be
be created
created by
bythe
the end
end user.
user.
Eachconfiguration
Each configurationofofarchitecture
architecture brings
brings on
onaadHferent
different set
set
of
of worst case
case pattern
pattern and
and stimulus
stimulus conditions. Quick
conditions. Quick
4-5
Improves Quality
E2CMOS Testability Improves
case patterns
application of a series of worst case patterns that
that cover
cover all
all
of the permutations of input combinations, array load &
switching, and output configuration is required.
E2CMOS devices offer instant instant erasability toto address this

this
reconfiguration & & test problem. Testing
Testing each
each additional
worst case
case configuration
configuration takes fractions
fractions of a second,
second,
allowing dozens
dozens of of patterns
patterns toto be
be checked
checked to assure
assure
performance to rated speeds
performanCe speeds even
even underthe
underthe most
mostgrueling
grueling
AC pattern.
pattel1'!. TThe
h e final
firial result
result is
is· a device with defects
defects
reduced from PPLI. hundred) to
PPJ:I. (parts per hundred) to PPM
PPM (parts
(parts per
per
million).•
million) .•
4-6
I
I
Section 1: Introduction to Generic Array Logic 1 I
Introduction to Generic Array Logic _ _ _1_ _ _ -_ _ _1_ _ 1-1

Datasheet Levels _ _ _ _ 2 _ _ _ -_ _ _ _ i _ _ _i _ _ 2-ii
GAL16V8NB
GAL 16V8A1B 2 - 1 2-1
GAL20V8NB
GAL20V8A1B 2 - 2 5 2-25
GAL18V10 2 - 4 7 2-47
GAL22V10/B 2 - 6 1 2-61
GAL26CV12 2 - 8 1 2-81
GAL20RA10
GAL20RA 10 2 - 9 5 2-95
GAL6001 2 - 1 0 9 2-109
ispGAL16Z8
ispGAL 16Z8 2 - 1 2 1 2-121
Section 3: GAL Military Products 3

Military Program Overview _ _ _ _ 3_ _ _ _ - ___ 1 _ _ 3-1
GAL16V8A/B
GAL 16V8A/B Military Datasheet 3 - 5 3-5
GAL20V8A Military
Military Datasheet 3 - 1 3 3-13
GAL20RA
GAL2ORA10 10 Military Datasheet 3 - 2 7 3-27
Section 4: Quality and Reliability 4 I

Quality Assurance Program _ _ _ _ 4____ - ___ 1 _ _ 4-1
I
PCMOS
E2CMOS Testability Improves Quality 4 - 5 4-5

GAL Metastability Report _ _ _ _5_ _ _ _- _ _ _ _
1 _ _ 5-1

Avoid the Pitfalls of High-Speed Logic Design _ _ 6_ _ _ - _1_ 6-1
6
Extending the 22V1
22V10 0 EPLD 6 - 7 6-7
the Fly 6 - 96-9

Development Tools _ _ _ _ _ 7 ____ - _ _ _ _1_ _ _ 7-1 77
5-i
5-i
5-ii
GAL Metastability
Report
INTRODUCTION
INTRODUCTION ItIt is accepted [1)
[1] that
that metastable
metastable failures
failures can
can be
be accurately
accurately
modeled by
modeled by the
the equation:
equation:
The dictionary definition of metastability is "a situation that is
characterized by a slight margin of stability:
stability." When applied to
to log Failure
log Failure = log
log MAX-b(A
MAX-b(A - AO)
Ao) ( 1 ) (1)
bi-stable (digital)
(digital) logic,
logic, the
the term
term refers
refers to
to an
an undesirable
undesirable
marginally stable output state between VIL max and VIH min. In this
In this equation,
equation, MAX represents
represents the the maximum
maximum failure
failure rate
rate
for a particular
for particular environment,
environment, A is the time time delayed before
delayed before
can occur
Metastability can occur in
in bi-stable storage elements
elements (registers,
(registers, sampling the
sampling the OUT
DUT (Device
(Device Under
Under Test)
Test) output,
output, and
andAA0o is the
the
latches, memories,
memories, etc.) when
when setup
setup and/or
andlor hold times areare time at
time at which
which the
the number
number of of failures
failures starts
starts to
to decrease.
decrease. On On
times vary
violated. Since setup and hold times vary with
with temperature
temperature and
and aa failure frequency plot
failure frequency plot (such
(such as the one in FigureFigure 2),2), Ao
AO
operating voltage, among other factors, the times referred to
referred to represents the
represents the knee
knee ofof the
the curve.
curve. TheThe constant
constant bb is
is rate
rate at
at
here are not the minimax
minImax numbers printed in data sheets,
sheets, but
but which the
which the frequency
frequency of failures
failures decreases
decreases after
after the
the knee
knee isis
the actual times for
rather the for the
the given set of
of operating
operating conditions.
conditions. reached.
reached.
violated
Typical applications where such times are likely to be violated
include bus 8,
& memory arbiters, interfaces, synchronizers, and and Recall that:
Recall that:
other state
state machines
machines employing
employing asynchronous
asynchronous inputs
inputs oror
asynchronous clocks. log X"
log X = aa In
In (X), where
where aa -= log
log (e)
(e)
Metastability manifests
manifests itself in
in aa number
number of different ways. Substituting this into (1):
Substituting (1):
Common responses are (shown as they might be captured on on
a digital oscilloscope in Figure 1): runt pulse (1 a • In
a· In Failure
Failure"= a·
a • In MAX - b(A
b(A - AO)
Ao) (2)
(2)
(la),
a), decreased
output slew rate
rate (lb),
(1b), output oscillation (lc),
(1c), and increased
increased
clock-to-output time (1d).
(1d). By
By definition,
definition, the phenomenon
phenomenon of MAX is related
MAX related to the clock frequency
frequency (fCLOCK) and data
(fCLOCK) and data
metastability is statistical in nature. Not only
only is entry into the
the frequency (fDATA).
frequency (f DATA). That is,
state uncertain, but the time spent there is also variable.
MAX == (k1
MAX (kl • fCLOCK·
fCLOCK • fDATA)
f DATA) ( 3 ) (3)
Because PLDs are commonplace in today's designs, a thor- thor-
Substituting (2) and
Substituting (3) into (2) and applying
applying some
some algebra:
algebra:
ough understanding oftheir
of their metastable
metastable behavior
behavior is crucial.
crucial. In
In
some applications, output anomalies shorter than than one clock
a·
a • In
In Failure
Failure ..
= a·
a • In (k1
(kl • fCLOCK
fCLOCK •• fDATA)
f DATA) -bb(A
( A -- AO)
Ao)
may be
cycle may be acceptable,
acceptable, but but in
in applications
applications where
where the
the
register output is used as a control signal (clock, bus bus grant,
grant,
In
In Failure - In
In (k1
(kl • fCLOCK
fCLOCK •• fDATA)
fDATA) ..
= -bla(A
-b/a(A -AAO)
o)
chip
chip select,
select, etc.) for other circuitry, faults such as
as runt
runt pulses
and oscillation cannot be be tolerated.
Setting
Setting k2 ..- bla
b/a and
and rearranging
rearranging the
the equation
equation yields:
yields:
This report
report will
will not
not study
study the
the causes characteristics of
causes or characteristics
Failure ..
Failure (k1 • fCLOCK·
= (k1 fCLOCK • fDATA)e-l<2(a.aO)
fDATA)e • AO) ( 4(4))
metastability in
in great detail; excellent material has already
already
been prepared on this subject [1-5). Rather, this report will
[1-4 Rather, will
introduce aa mathematical
mathematical model
model for
for the
the metastable
metastable phe-
phe- When
When used
used with
with equation
equation (4),
(4), the
the constants
constants k1,
kl, k2, and AD,
k2, and Ao,
nomenon, discuss potential test methodologies, present and completely
completely describe
describe aa particular
particular device's
device's metastable
metastablecharac-
charac-
compare test results from various bipolar and CMOS PLDs, PLDs teristics;
teristics; they
they indicate
indicate how
how quickly
quickly aa device
device can
can resolve
resolve the
the
and discuss
discuss how to interpret the data. This report will metastable condition. Devices
metastable condition. Devices which
which transition
transition out ofof the
the
will close
with suggestions
suggestions onon how
how to
to design
design metastable
metastable tolerant
tolerant metastable region quickly are
metastable region are characterized
characterized by small AO
by a small Ao
systems. and
and aa large
large k2.
k2.
The constant k1
The constant kl is peculiar
peculiar to
to the
the test
test apparatus
apparatus (it(it can
can be
be
thought
thought of as "scaling factorj.
as a "scaling factor"). The
The maximum
maximum metastable
metastable
PERIVATION OF CONSTANTS
CONSTANTS failure rate (MAX)
failure rate (MAX) is is limited by fCLOCK;
fCLOCK; a failure
failure cannot
cannot
DERIVATION OF
occur if the device isn't clocked.
occur clocked. Likewise,
Ukewise, it is true
true that
that aa
The basic premise
premise ooff all
all metastability
metastability models
models is is that
that aa metastable failure cannot occur
metastable failure occur unless
unless data
data has
has changed.
changed.
The basic
device's output is more likely to have settled to a valid valid state So, if fDATA
So, fDATA < < fCLOCK,
fCLOCK, then MAX ..
then MAX = fDATA.
f DATA. This
This was
was the
the
than in
in time(t-n).
time(t-n). In
In fact,
fact, the
the failure
failure probability
probability case
case inin the
the test
test fixture
fixture Lattice
Lattice used
used (fCLOCK=10MHZ,
(fCLOCK=10MHZ,
in time(t) than fDATA=2.5MHz).
distribution follows an exponential curve. Figure 2 shows shows aa fDATA=2.5MHz). Substituting
Substituting MAX
MAX ==fDATA
f DATAback
back into
into equa-
equa-
typical failure frequency plot. tion (3) yields:
tion (3) yields: k1
kl =" 1/fCLOCK,
1lfCLOCK, so k1 .. 1
kl = DOns for
100ns for our
our tests.
tests.
5-1
5-1 4191.Rev.C
4/91.13ev.0
Report
GAL Metastability Report
TEST FIXTURE itit is
is in
in the
the metastable
metastable region
region (between
(between VIL
VII_max
max and
and VIH
VIH min).
min).
The comparator
The comparator output can be sampled
sampled periodically
periodically and
and
The goal of testing a particular device's metastable charac-
The used to increment
used increment an
an event
event counter.
counter.
to generate real numbers forthe
teristics is to for the constants
constants k2 k2 and
and
Ao. ToTo do
do this,
this, the
the device
device must
must first
first be
be forced
forced into
into the This method
This method of testing,
testing, though
though iitt directly
directly yields
yields MTBF
MTBF
violating setup
metastable state. This is done by intentionally violating numbers, has some
numbers, some drawbacks.
drawbacks. The The first
first isis that
that itit does
does not
not
and/or hold
hold times.
times. Once
Once metastable,
metastable, the
the output
output cancan be
be distinguish between
distinguish between the
thedifferent
different types
types ofofmetastable
metastable behav-behav-
observed on an oscilloscope or used to increment an an event ior (runt
ior (runt pulse,
pulse, oscillation,
oscillation, slow
slow risellall
rise/fall time,
time, delayed
delayed transi-
transi-
counter. tion), and
tion), and itit may
may have
have difficulty
difficulty detecting
detecting every
everytype.
type. Also,
Also,the
the
registers used
registers used in in the detector
detector circuit itself
itself may become become
Traditional Approach
Approach metastable, which
metastable, would adversely
which would adversely affect
affect thethe results.
results.
One approach FailureR
approach to characterizing a
te
(counts/Sec) a device's metastable be-
havior employs a test fixture similar to to that shown in Figure A New
A New Approach
Approach
3a. in fixture, data to
In such a fixture, to the device includes aa"jitter "jitter band"
band" The test
The test method
method used
used to
to gather
gather data
data for
forthis
this report
reportused
used the
the
so that the device sees changing data as as itit is
is clocked. The circuit shown
circuit shown in Figure
Figure 3b.
3b. The
The tester
tester employed
employed an an "infinite
"infinite
DLIT output
OUT output is fed to
to aa window
window comparator comparator to to determine
determine when when precision" variable
precision" variable delay circuit
circuit to
to control
control clock
clock placement
placement
y y
VIH
VIL
clock Teo clock Teo

1a. Runt Pulse 1 b. Decreased Slew Rate
II output
v
""
output
.:.' ".
. ::...
V IH
V IL
""
t t
clock Teo clock Teo

1 c. Output Oscillation 1d. Increased Teo
'U
(ll
..... lOB __
108
MAX
MAX ••••••_••••_•••••••••••_.
iI
r:
g 10
1066 --
1 0 4
10 -I-
I
i
4
0::
10
1022 -I-
'0
u.
I 1 I
10 0 4 40
0 3 30
10 2 20 0 660
0 5 50 0 7 70
0 8 80
0
time
t i m e (ns)
(ns)
Figure 2. Typical Failure Frequency

Figure Frequency Plot
5-2
5-2
GAL Metastability
GAL Metastability Repotf
Report
with respect to data. This arrangement allowed exact worst
exact worst time (although,
time (although, in in the
the case
case of the
the scattered
scattered points,
points, the
the
case placement
placement of the
the clock, so as to induce metastability probability is
probability is low that
that aa single
single isolated
isolated point
point represents
represents more
more
with nearly
nearly every clock pulse. than one sample).
than
Using aa digital
digital oscilloscope
oscilloscope (Tektronix
(Tektronix 11403A)
11403A) in
in point
point To generate values
To values for
for k2k2 and
and AO,
Ao, itit was
was necessary
necessary to to refer
refer
accumulate mode, metastable failures were recorded over aa to previous
to previous metastability studies
studies [1].
N. ByBy studying
studying thethe output
output
lengthy period of time. A hardcopy was then
then made and the plots of devices with
plots with known
known constants,
constants, certain
certain relationships
relationships
constants empirically obtained (details
(details below). were established.
were established. For example,
example, it was was determined
determined thatthat AO
Ao
represents the
represents the time
time from
from thethe leading
leading edge
edge of
of the
the output
output until
until
The oscilloscope approach, being visual in nature, enables
The the "dot
the "dot density"
density" starts
starts to
to decrease
decrease measurably.
measurably. ItIt should
should bebe
the designer
designer to make
make educated
educated decisions regarding maxi-
maxi- noted that
noted that AO
Ao in
in previous
previous studies
studies included
included device
device propaga-
propaga-
mum clock and data rates, as well as the suitability of using tion delays, whereas
tion whereas in in our
our test
test itit does
does not.
not.
the output
output to drive other circuitry. The
The five
five minute
minute sample
period used in our tests
tests contained approximately 750 million The time from
The from Aot\O until
until the dot density equals
equals zero
zero was
was
failures. Much
Much longer
longer sample
sample periods
periods were evaluated, but defined to be
defined be the 'lime
''time to metastable
metastable release"
release" or simply
simply
they provided nono perceptible gain in usable information. time(r). The
time(r). The relationship
relationship between
between k2k2 and
and time(r) is given
given
below in
below in (5),
(5), and shown graphically
and shown graphically in
in Figure
Figure 4.
4. Recall
Recall that
that
A slight
slight disadvantage of this approach is that extracting k2 MAX=2.5x10A6 and a=log(e).
MAX=2.5x10"6 a.log(e).
and A°
t\O values
values from
from the
the hardcopies
hardcopies is
is not
not straightforward.
Because each
each point
point on
on the
the hardcopy
hardcopy cancan represent
represent anyany k2 =. 10g(MAX)
k2 log(MAX) I/ (time(r)
(time(r) • a)
a) .,.14.73/time(r)
14.73/time(r) (5)
(5)
number of actual samples (between one and 1.5 million),
numberof million), one
one
cannot simply count the points at time(t)
time(t) for the MTBF at that
for the that
VARIABLE DELAY
VIH
TO
TO
Data COUNTER
COUNTER
I---ID 0 D 0
Shifter
DUT '373
VIL
VIL
Figure 3a. Traditional
Traditional Metastability Test Circuit
-15-
E 0
Osc.
A 7
SELECT
4- TO
TO DIGITAL
DIGITAL
OSCILLOSCOPE
OSCILLOSCOPE
D
D OO l -E
- -D
rl
0
+8
A DUT
OUT
7 X
- - r - - - SELECT
Figure 3b. Lattice

Lattice Mestability Test Circuit
5-3
Repott
INTERPRETING THE RESULTS gathered on
gathered on similar
similar devices
devices by thethe manufacturer
manufacturer [1]).
[1]). The
The
absence of
absence ofaasecondary
secondarytracetrace along
alongground
groundindicates
indicatesthat
thatthe
the
In addition
addition to examining
examining PCMOS
E2CMOS GAL devices, this study output always
output always starts
startsto
totransition
transition to
to aa high
high level,
level, even
evenwhen
whenitit
also tested
tested several
several bipolar
bipolar PAL devices as well
well as
as other finally settles
finally to a low level.
settles to This characteristic
level. This characteristic makes
makes the
the
CMOS PLDs. To insure that the results of this this study
study would device unsuitable
device unsuitable for
for use
use inin control
control path
path applications
applications (when
(when
be relevant,
relevant, all
all necessary
necessary precautions were observed:
observed: the possible). All of
metastability is possible).
metastability of the
the bipolar
bipolar parts
parts examined
examined
devices were
were of recent
recent vintage and
and were
were acquired
acquired blindly
blindly showed similar
showed similar results.
results.
through distributors; multiple samples of each device were
device were
tested and the results combined; all devices hadhad either fixed
fixed Plot 1,
Plot 1,2 and 3 are
2 and are from
from GAL16V8B-7,
GAL16V8B-7, GAL22V10B-10
GAL22V10B-10 and and
16R8 architectures or were configured to emulate the 16R8 GAL6001-30, respectively. Aside
GAL6001-30, respectively. Aside from
from thethe fact that
that setup
setup
architecture; the devices were programmed from the same same time violations
time violations may cause leo
may cause tco to increase by a small small (but
(but
JEDEC fuse map file file (the source equations and the
the JEDEC
JEDEC random) amount,
random) amount, the the outputs
outputs areare very clean and well
clean and well be-
be-
fuse map file are presented in Listing 1).1). haved. The fact that there are
haved. The are no runt runt pulses
pulses or other
other
anomalies is
anomalies is extremely
extremely significant,
significant, as as the
the GAL6001
GAL6001 notnot only
only
Plots 11 through
through 66 on the following
following pages
pages are some some of the allows
allows asynchronous
asynchronous clocking,
clocking, but
but encourages
encourages that that activity.
activity.
oscilloscope plots generated for this study. The top wavewave- Although
Although GAL6001
GAL6001 is aa muchmuch slower
slowerdevice
device asascompared
compared to to
form in each plot is the clock signal, the
the middle trace
trace is the
the GAL 16V8 and
GAL16V8 and GAL22V1
GAL22V10, 0, the
the similar
similar metastable
metastablecharacter-
character-
metastable data output and the bottom tracetrace is the
the histogram istics GAL6001 tto
istics of the GAL6001 much faster
o the much faster GAL
GAL devices
devices
of the
the accumulated samples between
between 11VV and
and 2V ofofthe
the output
output indicate
indicate that
thatthe
the inherent
inherent metastable
metastable characteristics
characteristicsof ofall
allthe
the
signal. The horizontal scale is 2ns per division, so so the
the exact
exact GAL devices have
GAL devices have consistently
consistently desirable
desirable characteristics
characteristics
clock to output time
time of the
the metastable output condition
condition can
can across
across all
all speed
speed grades. Comparing Plot
grades. Comparing Plot 1,
1,22and
and33with
with Plot
Plot
be read directly. The vertical scale is 2V perper division
division for
for the
the 44 and
and 5 shows
shows thatthat characteristics
characteristics of the GAL devices devices areare
top trace, and 1V1V per division for the
the middle trace. superior
superior to those
those ofof bipolar
bipolar PLDs.
PLDs. PlotPlot 6 illustrates
illustrates meta-
meta-
stable
stable characteristics
characteristics of of the
the TTL
TTL flip-flop
flip-flop (TISN74AS74).
(TISN74AS74).
The middle waveform in each plot plot is
is the
the metastable devicedevice
output which is the
the only signal captured in in point
point accumulate
accumulate For
For reference
reference purposes,
purposes, Plots
Plots 77through
through 99 are
are included.
included. Plot
Plot
mode. In every case, the output
output signal plot shows two two stable
stable 77 shows
shows a normal
normal (ie.
(le. non-metastable)
non-metastable) GAL 16V8B-7 transi-
GAL16V8B-7 transi-
levels after
after the
the transition.
transition. This
This is
is aa direct
direct result
result of the tion;
tion, and
and Plot
Plot 8 aa normal
normal PAL
PALI16R8-7
6R8-7transition. Plot 99isisthe
transition. Plot the
"indecision" caused
caused by by metastability;
metastability; onon some
some cycles
cycles the normal transition of the TTL
normal transition - r n flip-flop SN74AS74). For
flip-flop (TI SN74AS74). For
output settled
settled to aa high
high level, while on
on others
others itit settled
settled to
to a low
low consistency,
consistency, only
only rising
rising edges
edges have
have been
been shown.
shown. OurOurtests
tests
level. also
also covered
covered falling
falling edges
edgeswhich,
which, in
ingeneral,
general, were
were interesting
interesting
but
but did
did not
not provide
provide anyany additional
additional information.
information.
Plot 4 shows the response ofof a bipolar
bipolar PAL
PALI16R8-7.
6R8-7. Noticethe
Notice the
very well defined runt pulse (this correlates
correlates with previous data
data
15
15
12.5
12.5
I
10
10
k2in
k2 in 7 . 7.5
5
1/ns1\2
linsA2
.5
2.5
2.5 "- ......
""-
-- - r-- :-- i--
0
i--
-
22 44 66 88 110
0 112 14 116
2 14 18 2o
6 18 20 2o
20 24
24 26
26 28
28 330
0
FIgure 4. KK2 time

time (r)
Figure 4. 2 Constant
Constant
5-4
5-4
I
GAL Metastability
Report
I
i
For a more quantitative look at the phenomenon of metasta- tion, though
tion, thoughalso
alsothe
theresult
resultof
ofaasetup
setuptime
timeviolation,
violation,should
shouldnot
not
to the
bility, refer to t hetable
table beneath
beneath each plot.
plot. These tables
tables listthe
list the be confused
be with metastability
confused with (the "incorrect"
metastability (the "incorrect" data
data that
that is
measured values of the constants Ao and k2 for the the device
device captured has normal output
captured output characteristics);
characteristics); it is, pura
pure and
and
devices. Recall that
whose plot is shown, and for similar devices. that large simply, the result
simply, result of
of a violation
violation of
of specifications.
specifications.
k2 and
and small
small Ao Ao values are desirable. The numbers in the
tables correlate closely with the results of earlier tests [1,5],
[1,5], Example
Example
confirming the validity of our test method. To
To determine
determine thethe maximum
maximum clock
clock rate
rate (given
(given an
an acceptable
acceptable
error
error rate)
rate) that
that aa particular
particular device
device will
will allow
allow in
in an
an asynchro-
asynchro-
Since all current GAL devices possess very similar
similar register
register nous environment, equation (4) is used.
nous used. ForFor example,
example, the
the
and output buffer circuitry, and all are
are fabricated
fabricated using the system shown in Figure
system Figure 6 utilizes
utilizes a 9600
9600 baud (bits/sec)
(bits/sec)
same basic
basic process,
process, the
the data
data shown
shown in in Table
Table 11 for
for the asynchronous
asynchronous data stream. stream. The
The system
system clock
clock period iiss
GAL 16V8 is considered applicable to all
GAL16V8 all devices
devices and speed
speed tCOAPD-I-tSLN-A. For one
tCO+tPD+tSU+A. one failure
failure per year:
year:
grades in the GAL family.
3.2x10-8 - [(1x10-7)(1/(A+22))(9600))04lA-4'91
3.2x10-8 = [(1 x1o-7)(1/(A+22»(9600)]eo(4(Ao....1I
USING THE RESULTS Solving

Solving for
for A yields
yields A-2.22ns,
A-2.22ns, or aboutabout 2ns,
2ns, for
for aa cycle
cycle time
time
of
of 24ns.
24ns. Referring
Referring back
back toto Plot
Plot 1,
1, the
the additional
additional delay
delay ofof2ns
2ns
If aa register
H register enters the metastable
metastable state in in a system,
system, then intuitively makes sense.
intuitively makes sense. Remember,
Remember, in in terms
terms ofof setup
setup and
and
data waswas obviously
obviously unstable
unstable as as the
the register
register was
was being
being hold
hold time
time violations,
violations, the
the oscilloscope
oscilloscope plots
plots were
were made
made under
under
clocked. The
The argument over which data should have been worst
worst case failure
failure conditions;
conditions; thethe scattered
scattered dots
dots could
could rep-
rep-
captured (old
(old oorr new)
new) is is academic
academic as as the
the register
register will
will resent
resent MTBFs
MTBFs of ofdays,
days, years,
years, ororeven
evenmillenniums
millenniums in inaatypical
typical
randomly pick one or the other. SignalsSignals in most asynchro- asynchronous environment.
asynchronous environment.
nous systems are active for more than one clock cycle, so if
they areare missed
missed initially,
initially, they
they could
could bebe captured
captured on
on aa Due
Due to
to the
the extremely
extremely quick
quick metastable
metastable settling
settling times
times of
ofGAL
GAL
subsequent clock cycle. devices, relatively small increase in the cycle time
devices, a relatively time will
produce
produce a dramatic improvement
improvement inin reliability.
reliability.
It is the task of the state machine deSigner
designer to
to take
take adequate
precautions against metastability causing illegal states to to be BIBLIOGRAPHY
BIBLIOGRAPHY
entered. One way to do this this is by using
using "gray codes·
codes- when
ordering states.
states. Gray
Gray code
code state equations
equations allow onlyonly one 1.
1. D.M.Tavana
D.M.Tavana (MMI),
(MMI), "Metastability
"Metastability - A
A study
study of
ofthe
the Anoma-
Anoma-
state bit to change during a state
state.transition.
transition. Thus, the
the worst lous
lous Behavior
Behavior of Synchronizer
Synchronizer Circuits,"
Circuits," in: Programmable
Programmable
metastability could do would be to delay a state transition
transition by Array
Array Logic Handbook, Monolithic
Logic Handbook, Monolithic Memories
Memories Inc.,
Inc., 1986,
1986, pp
pp
one clock cycle. IfHmore than one bit were allowed to to change,
change, 11-13-11-16.
11-13 - 11-16.
the outcome would be purely random, and probably probably illegal.
.,
FigureS
Figure 5 shows examples of both cases. 2. K.Rubin (Force
2. KRubin (Force Computers),
Computers), "Metastability
"Metastability Testing
Testing in
PALs," Wescon187 Conference
PALs," Wescon/87 Conference Record
Record (San
(San Francisco,
Francisco,
Other solutions are to externally (or internally) synchronize November
November 17-19, 1987). Los
Los Angeles:
Angeles: Electronics
Electronics Conven-
Conven-
the asynchronous signals, or to
to increase cycle times
times to
to allow
allow tions Inc, 1987, pp
tions Management, Inc, 1611 1-10.
pp 16/1 1-10.
time for metastable outputs to settle. An example of the
the latter
solution is given below.
below. 3.
3. K.Nootbaar
KNootbaar (Applied
(Applied Microcircuits
Microcircuits Corp.),
Corp.), "Design,
"Design, Test-
Test-
ing, Application of a Metastable
ing, and Application Hardened Flip-Flop,"
Metastable Hardened Flip-Flop,"
!
Itit is worth noting at this point that state machines (synchro- ibid.,
ibid., pp 16/2
1612 1-9.
nous or or asynchronous)
asynchronous) can can fail
fail for
for reasons
reasons other
other than
than
metastability. AA not not insignificant
insignificant component
component of of aa PLD's
PLD's 4. (MMI), "Understanding
4. J.Birkner (MMI), Metastability," ibid.,
"Understanding Metastability," ibid., pp
pp
specified setupsetup time isis directly attributable
attributable to internal
internal data 1613
16/3 1-3.
skewing [2]. Data skewing is the inevitable result of differing
signal path path lengths,
lengths, loading
loading conditions,
conditions, andand gate
gate delays.
delays. 5. R.K.Breuninger, K.Frank,
5. R.K.Breuninger, K.Frank, "Metastable
"Metastable Characteristics
Characteristics of
of
Stated another way, each input to to output
output path
path has its own
own set Texas
Texas Instruments
Instruments Advanced
Advanced Bipolar
Bipolar Logic
Logic Families,"
Families," appli-
appli-
of actual
actual AC specifications. IfHinsufficient
AC specifications. insufficient setup
setup time hashas cation
cation note SDAA004, Texas
Texas Instruments, 1985.
Instruments, 1985.
passed, different "versions·
"versions" of the
the same datadata may
may be
be present
present
at thethe inputs of different registers as they are clocked.
clocked. A good
good
example of this is:
OutpuCPin19 :- Input_P1n2;
Output_Pin19 := Input_Pin2;
OutpuCPin15
Output_Pin15 :- IInput_Pin2;
linput_Pin2;
If clocked
clocked atat precisely
precisely the
the right
right moment
moment after
after an
an input
input
transition, one
one register will capture
capture old data while
while the other
other
captures new data, resulting in a system failure. This condi-
condi-
5-5
Report
SEQUENTIAL STATE ORDERING

ORDERING GRAY CODE
GRAY CODE STATE ORDERING
ORDERING
If metastability occurs
H occurs HIf metastability
metastability
while transitioning from
while from occurs while
occurs while
01, every state is a
01, transitioning from
transitioning from 01,
01,
possible next state.
possible state. the possible
the possible next
next
states are
states are 01
01 and 11.
and 11.
Figure 5.
DATA
-....... GAL16V8 GAL16V8
Tpd = 10ns -D OUTPUT
Teo =5ns Tsu =7ns

A. A.
CLOCK D I I
Figure 6.
MODULE m
metastable
etastable
TITLE
T I T L E ' 'Metastable
M e t a s t a b l e TTest
est
Pattern' JEDEC
JEDEC ffile i l e ffor:
o r : P16R8
P16R8
Pattern'
Metastability
Metastability T Test Pattern*
est P attern*
uOO Device 'P16R8'; QP20*
QP20* Q QF2048*
F 2 0 4 8 * FFO*
O*
u00 D e v i c e 11 ,16R81;
LOOOO
L 0 0 0 0 1101111111111111111111111111111*
0 1111111111111111111111111111 *
d PIN L1792
L 1 7 9 2 1101111111111111111111111111111*
0 1111111111111111111111111111 *
P I N 2 2;
;
q1,q2 C07F4*
CO7F4*
q l , q 2 P PIN
I N 12 12,19;
,19;
EQUATIONS
EQUATIONS
q1
q l : :== dd;
;
q2 : .=
q2 = dd;
;
End
End m metastable
etastable
Listing 1a.
la. Source equations Listing
Listing 1b.
lb. JEDEC file
tile
5-6
5-6
GAL Metastability
Report
Clock
....................
.. .......................................................
·· ..
··· .. ·
..
··· ··· ... .
...
2V/dlv
2Vicliv ·· ... · .
. ...
· . .
............................. ..
·· .. ..
· .
Output-t
·
..................................
. !.; ,'" .............. :.................. : ........ .
· .
1V/dlv
1V/div
· . .
............................... , .......................................................... .
··· ..
.. ...
·· .. . .
··
· .
. ...
II
· . .
.......................................................
I,
2n5/dlv
2nsidiv
Plot 1. GAL16V8B-7
Plot 1. GAL16V8B-7 Metastable
Metastable Output
Output
Part # Manufacturer
Manufacturer .t.o
Ao (n5)
(ns) k2
k2 (1/n5 2)
(1ins2)
GAL16V8B-7
GAL-I 6\18B-7 Lattice
Lattice .44
.44 5.0
5.0
5-7
5-7
Report
. ... ... ..·. .. .

·· ...................
.. .
...........................................................................
.
··· ... ... ... ... ..
.
.
..
2V1dlv ··· .. ... ... ... ... ...
.· .
.
.. .. .. .. • •••• .:. •••••••••
""I' ••.••.. ; ••••••••• ; ••••••••• ; .•••.•••• ;.... . •
··· .. ... ..
·· . .. .. ...
·· ... .. . .
· . .
................................................. ..:...............................
.· ..
. .
·· ..
·· ..
··
· ...
lv
1V/dlv
....""""....
· . .
.... ..
.
.............. .... ... ...
.............................................. ......... ,.........................

...
: ........ .
·· ...
··· ..
·
· . . .
............................................. .0
··· ....
••••••••••• ,•••••••••••••••••••••••••••
2nsidiv
2ns/div
Plot 2. GAL.22V10B-10
GAL22V10B·10 Metastable Output
Part # Manufacturer
Manufacturer Ao (ns)
6.0 (ns) k2
k2 (1/ns2)
(1ins2)
GAL22V10B-10
GAL22V1 OB-1 0 Lattice
Lattice .51
.51 5.2
5.2
5-8
5-8
GAL Metastability
Report
............................................................................................
··
·· ...
·· ...
·................
.. .
··· ..
··· .
· ...
2V/dIv
2V/dlv
· .
............................................ .....................
.
·.· ...
.
Output -+ ··· ...
·· ..
· . .
............................................
1V/dIv
1V/dlv
· ..
.................................... .........................................................
. . , . .
.. .
.... ............ .. .. ......................................
..................
·· ... . . . . . . .. . ... . . ... .
· .. ..
··· ... ...
·· . .
· . .
2ns/div
2ns/dlv
Plot 3. GAL6001-30
GAL6001-30 Metastable Output
Part # Manufacturer
Manufacturer Ao (n5)
l!.O (ns) k2
k2 (1/n5
(lins2)
2)
GAL6001-30 Lattice
Lattice .22
.22 7.3
7.3
5-9
5-9
Report
..............
.............................................................................................
··· .. ..
·· .. .
· .
. ...
: :
.
.................... . .
......... ............................. .................. .
:: . :: :
2V/di)/
2V/dlv
: :. :
. : . : ,
.........................................
.. ..
: I.'
·
...................................
. · ..l'.·..
'0: It.
.
···1···············
:
..................
:
.
Output -+ ':':<:' .j
.,. '. .
...'
1V/div
............................................
· ..
···· ...
.
··· .
.
· .
............................. .
·· ..
·· ..
·· ..
·· ...
·
............................. . , ...... ,... : .......................... .
2nsidly
2ns/dlv
Plot 4. PAL.16138-7
PAL16R8-7 Metastable Output
Part #
Part Manufacturer
Manufacturer AO
Ao (ns)
(ns) k2
k2 (1/ns2)
(1ins2)
PAL16R8-7
PAL.16138-7 AMD
AMD 1.2
1.2 2.5
2.5
5-10
5-10
GAL Metastability
Report
........................................................................ : ......... : ........ .

.. ..
Clock;
Clock
· . .
....................................... .
......... ......... ......... ............................ .
2Vicliv
2V/dlv
........ 1
Output -+
. .
..................................
..
• • !.',
1Vidly
1V/dlv
·
.............................
. .
· .
............................
I
2ns/div
2nsidiv
Plot 5. TIBPAL16116-7
TIBPAL16R6-7 Metastable Output
Part # Manufacturer Ao (ns) k2

k2 (1/ns2)
(1ins2)
TIBPAl16R6-7
TIBPAL.161R6-7 TI 1.5
1.5 1.5
1.5
5-11
5-11
GAL Report
........ : ............................... .: ......... : ......... : ......... ; ......... .: ........ .

··· .
. .. .. . ..
· ..
. ..
. .. . ..
211/cIlv
2V/dlv :· :: : : :
.
...'
. ....
. .
.............................
1Willy
W/dlv
................... ................................................................
2nsicliv
2ns/div
Plot 6. SN74AS74
SN74AS74 Metastable Output
Part # Manufacturer
Manufacturer Il.o
Ao (ns)
(ns) k2
k2 (1/ns2)
(1ins2)
SN74AS74 TI
TI .91
.91 3.5
3.5
5-12
5-12 '
GAL Metastability
Report
..................................................................................: ......... :
····· ....
.
.....
:
· . :
. .
____ .. .. .... ......... ......... .. ................ ..
. ...................
. .
................... . ......... ......... ...................
.
...
2V/div
2V/dlv
: :
: .
:
:: ::
. . .
: .............................. :......... :
: Output-+
Output
H.HH ... H....... ...Hi H ·.. H... · ............ TJ
__ ........ ..
1V/dlv
................... !............................................. !
. .
.............................. ... .. ......... . .. .... .. ......... ......... .......... . ........
···· ...
.
. .
.............................. .............. :··............................................. ..:
: :
· .
··· ...
·· ..
2ns/dlv
2nsidiv
Plot 7. Normal
Nonnal GAL.16V8B-7
GAL16V8B-7 Transition
5-13
5-13
Report
.. ....... : ......... : ......... : ......... ......... ......... ......... ......... ......... . ........ .
··· ... ...
··· ... ..
.
· . ............................... .... .....
Clock -4
....... : .................. : ............................................ .

2Vidly
2V/dlv ··
·· ....
. .................................. .
Output
Output ---
· .
............................. .....
1 \Wilt
1V/dlv
.......... .: ........................... .: ............................................ .
: .........
..
. . ...
.
. .
.
.
.. . ...
.
.. . . .
..............................
·· ..
·· ...
··· ...
··
............................. . . ............ : ............................................ .
2ns/dlv
2ns/oily
Plot 8.
S. Normal PAL-16138-7
PAL16RS-7 Transition
5-14
5-1 4
GAL Metastability
GAL Metastability Repolf
Report
Clock —>
2V1dlv
21//div
.. ......... : ......... : ......... : ......... :.....
·
.·
:
··.
..
..
:
.
.
Output
.
. ......................... .
..................................................
·· .. .. . . ........................................ .
·· .. .. ...
· .. .. ..
··· . . . . ..
· . . .
1V/dlv
........__..." ...................................................... .
· .
............................. ......... ... . ............................................. .
............................. ......... .. .............................................. .
2ns/div
2nsidiv
Plot 9. Nonnal SN74AS74

9. Normal SN74AS74 Transition
END
END
5-15
Notes
5-16
5-16
Latch-up Protection
INTRODUCTION (assuming that
(assuming that the
the beta
beta product
product of
of 0,
0, and 02
02 is
is greater
greater
The Lattice GAL family has been developed using
using a high-
high- than unity), driving
than driving both 0, and Q, into saturation
02 into and
saturation and
performance E2CMOS process. CMOS CMOS processing was effectively turning on the SCRSCR structure
structure between
between thethe
chosen for
for the
the GAL
GAL family
family to
to provide
provide maximum
maximum AC AC device supply
supply and
andground.
ground. With the
theparasitic
parasiticSCR
SCRon, on,the
the
performance withwith minimal
minimal power
power consumption.
consumption. AA CMOS inverter quickly
CMOS quickly becomes
becomes a nonrecoverable
nonrecoverable short
short
drawback common
common to to all
all CMOS
CMOS technologies
technologies is
is the
the circuit; metal trace
circuit; trace lines melt and
lines melt and the
the device
device becomes
becomes
destructive agent, latch-up. permanently damaged.
permanently damaged.
This brief
brief defines the phenomenon of latch-up,
latch-up, how
how it CAUSES OF
CAUSES OF LATCH-UP
LATCH-UP
manifests itself, and what techniques have been used to to ItIthas
hasbeen
beenexplained
explainedthat parasiticbipolar
that paraSitic bipolarSCR SCRstructures
structures
control it.
it. A Also
l s o described
described areare three
three device
device features
features are inherent in CMOS
are CMOS processing.
processing. If triggered,
triggered, the the SCR
SCR
employed in the GAL family to eliminate the the occurrence
occurrence ofof forms a very
forms very low-impedance
low-impedance path path fromfrom thethe device
device supply
supply
the results of an
latch-up as well as the an intensive investigation to the substrate, resulting
to resulting in in the
the destructive
destructive event. event. Two Two
conducted to reveal the GAL family's tolerance to to latch- conditions are
conditions are necessaryforthe
necessary for the SCR SCRto toturn
turnon:on: The
Thebetabeta
up. product of
product of 0,
Di and 02 02 must
must bebe greater
greater thanthan unity,
unity, which,
which,
although minimized, is usually the
although the case;
case; and a trigger trigger
Latch-up isis destructive
destructive bipolar
bipolar device
device action
action that
that can current
current must
must be be present.
present. The cause of
The cause of latch-up
latch-up is is best
best
potentially occur in any CMOS processed device. IItt is understoodunderstood by by examining
examining the the mechanisms
mechanisms that that produce
produce
characterized by by extreme
extreme runaway
runaway supply current and the the initial
initial injection current to to trigger
trigger thethe SCRSCR network.
network.
consequential smoking
smoking plastic
plastic packages.
packages. Latch-up Figure 2 is a schematic of
Latch-up is Figure of the
the parasitic
parasitic bipolar
bipolar network
network
peculiar to CMOS technology, which which integrates both P present
present in in a CMOS
CMOS inverter,
inverter, where
where node node "b" "b"isisthe
theinverter
inverter
and N channel transistors on one chip. output. It can
output. can bebe seen
seen that
that two
two events
events might
might trigger
trigger latch-
latch-
up: 11)) the inverter output could
up: overshoot the
could overshoot the device
device
In the doping profile of a CMOS inverter, parasitic bipolar supply,
supply, thereby
therebyturning
turningon on0033 and
andinjecting-currentdirectly
injecting current directly
(PNPN) silicon-controlled-rectifier
silicon-controlled-rectifier (SCR) structures
structures are into
into the base
base of 02; and 2) the inverter inverter output
output could
could
formed. Figure
Figure 1 shows
shows the process cross section of a undershoot
undershootthe the device
deviceground,
ground,turning
turningon on02 (:),immediately.
immediately.
CMOS inverter, as well as the the bipolar
bipolar components
components to the However,
However, a third condition
condition could
could also also trigger
trigger latch-up;
latch-up; ifif
parasitic SCR
SCR structure.
structure. In
In steady-state
steady-state conditions, the thethe supply
supply voltage
voltage to to the
the P+ diffusion
diffusion werewere to to rise
rise more
more
SCR structure remains off. Destruction results
results when
when stray
stray quickly
quickly than
than the bias, 0,
the N-well bias, C), could
could tumturn on.on. Within
Within thethe
current injects in to the base of either 0,
C), or 02
02 in Figure
Figure 1. device circuitry, overshoot
device circuitry, overshoot and and undershoot
undershoot can be
The current
current isis amplified
amplified with
with regenerative
regenerative feedback
feedback controlled
controlled by by design.
design. A problem
problem area area exists
exists at atthe
thedevice
device
Input °Output
Vcc
Vsua
1±L4.1 P+
03 01
FtwELL
02
Figura Invartar Cross-Section

Figure 1. CMOS inverter
5-17
5-17
Latch-up Protection
I/0s because external conditions
inputs, outputs and I/Os conditions are To prevent
To prevent latch-up
latch-upby bylarge
largepositive
positiveswings
swingsonthe on thedevice
device
not always perfect. Powering
Powering up can also be a potential outputs or
outputs or1/0
I/Opins,
pins, NMOS
NMOSoutputoutputdrivers
driverswerewereused. used. This
This
problem because of unknown bias conditions that may eliminates the
eliminates the possibility
possibility ofof turning
turning on on 0 023 (Figure
(Figure 2)
2) with
with
arise. an output
an output bias in excess excess of of the
the device
device supply
supply voltage.
voltage.
Figure33contains
Figure containsthe theeffective
effectiveNMOS
NMOSoutput outputdriver
driverandandits
its
processing the
With CMOS processing the possibility
possibility of
oflatch-up
latch-upis isalways switching characteristics.
always switching characteristics. Note that the
Note that the output
output does does not
not
present. The The major causes of latch-up are understood fully fully reach
reach thethe supply
supply voltage,
voltage, butbut still
still provides
provides adequate
adequate
clear that
and it is clear that if CMOS is to be used, solutions to to latch-
latch- V V0H margin for
011 margin for TTL
TTL compatibility.
compatibility.
up will have to be created. AAs s the
the technology evolves,
solutions to latch-up are becoming more creative. creative. Two of To To prevent
prevent negative
negative swings
swings onondevice
deviceoutput
outputand and I/O
I/Opins
pins
the more straightforward solutions are presented here. from forward-biasing
from forward-biasing the
substrate- bias
substrate- bias generator
the base-emitter
generatorwas
base-emitter junction
was employed.
junction of Q2,
employed. By producing
° 2, a
producingaa
One direct way to reduce the threat of latch-up is is to
to inhibit
inhibit V \cub ofapproximately
•.., of approximately-2.5v, -2.5v,undershoot
undershootmargin marginisisincreased
increased
02
C), (Figure 1) from turning
turning on.on. This has
hasbeen
been accomplished
accomplished to to about
about -3V.-3V.
by grounding the substrate and reducing the the magnitude
magnitude of of
Rsub through the use of wafers with a highly conductive To To insure
insure that
that nono undesired
undesired bias
biasconditions
conditionsoccur occurwith with P+
P+
epitaxial layer.
layer. While
While the technique is successful, the diffusions, diffusions, Lattice Lattice Semiconductor
Semiconductor has has developed
developed
wafers are more expensive to manufacture,manufacture, due to the the proprietary
proprietary Latch-Lock power-up power-up circuitry,
circuitry, illustrated
illustrated in
extra processing required to form the epitaxial layers. Figure 4. I In
Figure n short, the drain
short, the drain of of all
all P channel devices
channel devices
normallyconnected
normally connectedto tothe
thedevice
devicesupply
supplyisisnow nowconnected
connected
The extensive use of "guard rings" helps to collect stray to to an alternate supply supply that
that powers
powers up up after
after the
the device
device N-N-
inadvertently trigger
currents which may inadvertently triggerananSCRSCR structure.
structure. wellswells havehave been
been biased
biased andandthe
the substrate
substrate has hasreached
reachedits its
A disadvantage
disadvantage to to heavy
heavy use use ofof guard
guard ringsrings is is the negative clamp
the negative clamp value.
value. This prevents
prevents any any hazardous
hazardous bias bias
constraints placed on circuitcircuit design
design and
andtopological
topological layout,layout, conditions
conditions from from developing in the power-up power-up sequence.sequence.
and the resulting increase in die size size and cost. After power-up
After power-up is is complete,
complete, the the Latch-Lock
Latch-Lock circuitry circuitry
becomes dormant
becomes dormant until until a full
full power-down
power-down has has occurred;
occurred;
THE LATCH-LOCK
LATCH· LOCK APPROACH this eliminates
this eliminates the the chance
chance of of an
an unwanted
unwanted P channel channel
The intent
intent of thethe GAL
GAL family
family was to implement
implement cost- power-down power-down during during device
device operation.
operation.
effective solutions to to each major cause of latCh-Up.latch-up. The The
goal was met through three device features. To
To determine the the amount
amount of of latch-up
latch-up immunity
immunity achieved
achieved
with
with thethe three
three device
device features
features utilized
utilized in in the
the GAL
GAL family,
family,
The most susceptible areas areas for latch-up are the the device an an intensive
intensive investigation
investigationwas wascarried
carriedout. Each step
out. Each stepwas
was
inputs, outputs
outputs andand I/0s. Extreme externally
I/0s. Extreme externally applied applied
voltages may may cause
cause aa P+N P+N junction
junction to forward-bias,
forward-bias, Vee
leading to latch-up. The The inputs, by design, are safe; but
outputs and I/OsI/0s present a danger.
Vee
Vcc
SUPPLY
Input
Input
Output
01 M
Q1 E E RWELL
R WELL
V.
RSUB
°MIK0 L..-_ _ _ _ b output

b Output
tit
Von
Vat
MARGIN
Figure 2. Parasitic SCR Schematic Figure

Figure 3.
3. NMOS
NMOS Output
Output Driver
Driver
5-18
5-1 8
Protection
Latch-up Protection
conducted at 25° and 100°C;
100°C; inputs, outputs, and I/0s
VOS drivers were
output drivers were damaged
damaged in
in the
the battle,
battle, and
and still
still latch-
latch-
forced to -8V and +
were sequentially forced +112V
2Vwhile
while the
thedevice
device up was not Induced.
up induced.
underwent fast
fast and
and slow
slow power-ups;
power-ups; devices
devices were
were
repeatedly "hot socket" SWitched
switched with up to 7.0V. Based on the data,
Based data, it is evident that the GAL
evident that family is
GAL family is
completely immune to to latch-up,
latch-up, even
even when
when subjected
subjected to
to
the extreme conditions specified, no instance aa wide
under the
Even under wide variety
variety of
of extreme
extreme conditions,
conditions, including
including current
current at
at
of latch-up occurred. InIn an attempt to inputs, outputs,
to provoke latch-up, ±± inputs, outputs, and I/0s,
VOs, power-supply
power-supply rise time, hot-
rise time, hot-
forced into each output
50mA was forced output and 110
I/O pin.
pin. The device socket power-up
device socket power-up andand temperature
temperature.. .•
Vee
VLL
LLC
• • •
v'
i
!
Figure 4. Latch-Lock Power-Up Circuitry
5-19
5-19
Notes
5-20
5-20
Section 1: Introduction to Generic Array Logic
11
1-1

2-ii
GAL16V8NB
GAL16VSNB 2-1
2-1
GAL20V8NB
GAL20VSNB 2-25
2-25
GAL18V10
GAL1SV10 2-47
2-47
GAL22V10/B 2-61
2-61
GAL26CV12 2-81
2-S1
GAL2ORA10
GAL20RA10 2-95
2-95
GAL6001 2-109
2-109
ispGAL16Z8
ispGAL16ZS 2-121
2-121

3-1
MIL-STD-883C Flow
MIL-STD-SS3C 3-2
3-2
3-3
GAL16V8NB
GAL 16VSNB Military Datasheet 3-5
3-5
GAL20V8A Military Datasheet
GAL2QVSA 3-13
3-13
3-19
GAL2ORA10
3-27
Section 4: Quality and Reliability 44

4-1
4-3
PCMOS 4-5
4-5

5
5-1
.-
LatCh-up
Latch-up Protectio(l
Protection 5-17
5-17

Avoid the Pitfalls of High-Speed Logic Design
Design 6-1
6-1
Extending the 22V10
22V1 0 EPLD 6-7
6-7
the Fly 6-9
6-9
6-13
7-1 7
7-3
7-5
Package Thermal Resistance 7-S
7-8
7-9
7-16
Sales Offices 7-17
7-17
6-i
6-i
6-ii
6-ii
Uh6IUNAFFILA
AtJtJLlCA Mb
MAKE SURE
MAKE THAT YOUR
SURE THAT YOUR TURBO-CHARGED
TURBO-CHARGED LOGIC
LOGIC
SYSTEMWORKS
SYSTEM BY PAYING
WORKS By PAYING As MUCH
MUCHATTENTION
ATTENTION
To PRINTED-CIRCUIT
To PRINTED-CIRCUIT BOARD
BOARD LAYOUT
LAYOUT TECHNIQUES
TECHNIQUES
As To LOGIC
LOGIC DESIGN
DESIGN CONSIDERATIONS.
CONSIDERATIONS.
AVOIDTHE
AVOID THE PITFALLSOF
PITFALLS OF
HIGH-SPEEDLLOGIC
HIGH-SPEED OGICD ESIGN
DESIGN
M o d e r odern high-speed systems
n high-speed systems demanddemand modern modern highhigh-
speed
speed logic families.
families. Consequently, semiconduc- semiconduc-
tor houses have developeddeveloped such such product
product lines lines asas
ACT, FACT, and AS. But these systems also de- de-
mand that the lay-out lay-out of o f their boards conform
with thethe results ooff distributed-element theory,
otherwise ringing,
ringing, crosstalk,
crosstalk, and and other transmission-line phenomena render
those systems inoperative. Meeting this this second
second requirement
requirement necessitates
necessitates somesome-
thing more than a:a new product product introduction-it
introduction—it insists insists on aa changechange in the way way
logic boards are engineered. The logic-systems designer and and the the board-layout
board-layout
designer must work work hand-in-hand if if aa viable
viable high-speed
high-speed board board or or system
system isis to to be
be
produced.
In the past, logic design and and board
board layout were were usually
usually regarded as as separate
separate
parts ofof the design
design process.
process. First First the
the system
system designer
designer configured
configured the thelogic,
logic, then
then
the board engineer
engineer laid
laid itit out.
out. That approach
approach worked worked because
because slew slew rates
rates were
were soso
low (0.3 to 0.5 V Ins) that crosstalk
Vins) crosstalk wasn't
wasn't muchmuch of of aa problem;
problem; rise rise times
times were
were so so
long (4(4 tto
o 66 ns)
ns) that
that ringing
ringing
could settle
settle down before
before aaklgic logic
element couldcould change
change state; state;
and iin general, tthe
n general, assump-
h e assump- High·current
High-current LogiccircuH
SWitching Logiccircuit
tions of
of lumped-element
lumped-element circuit circuit switchingdevice
device ground
ground plane groundplane
plane
theory usually
usually wworked
orked o u t out gr
o und plane
pretty well.
For systems
systems designed
designed with with
1\
today's high-speed logic. cir-
high-speed logic,, cir-
.",- Gap", 1/8/8in.
11.
cuitry, those
those underlying asas- Gap,- 1 in.
sumptions no longerlonger hold true. true
Today's slewslew rates are on the TO MINIMIZE NOISE,
1.TO NOISE, THE THEg round
ground
order of 2 to 3 V V/I ns,
ns, rise times plane
planeshould
shouldbe befragmented
fragmentedinto intoseparate
separateareas
areasforfor
are below 2 ns ns (frequently, bebe- noisy
noisy high-eurrent
high-current devices
devicesand
andforfor sensitive
sensitivelogic
logic
low 11 ns), and transmission-line
transmission-line circuits.
circuits. For
For best
bestresults,
results, the
the number
numberof ofsignalUnes
signal lines
phenomena, such such as as ringing,
ringing, that
that cross
crossthethe gap
gapbetween
betweenthethe fragments
fragmentsshouldshouldbe be
can
can bebe aa problem
problem ffor trace
o r trace minimized.
minimized.
JOCK TOMLINSON
JOCKTOMLINSON
Lattice
Semiconductor Corp.,
Corp., P.O.
P.O. Box
Box 2500,
2500, Portland,
Portland, OR
OR 97208;
97208; (503)
(503) 681-0118.
681-0118.
Reprinted with permission from
from ELECTRONIC
ELECTRONIC DESIGN
DESIGN - November
November 9.1989
9, 1989
6-1
6-1
1,I£im:"taullij"jm$'
DESIGNAPPLICIITIONS
DESIGNINGWITH
DESIGNING WITH
HIGH-SPEEDLLOGIC
HIGH·SPEED OGIC
lengths as short as 7 in. As a result, ance
ance of transmission line that
o f any transmission that
logic designers
designers must
must take
take certain
certain Centralsystem
Central systemground
ground crosses
crosses the the separation
separation between
betweenfrag- frag-
steps: • ments. Therefore, for
ments. Therefore, f o r best
best results,
results,
boards
boards shouqd
should bebe laid
laid out
out sosothat
that only
only
• Use ground and
and power
power planes.
planes. two
two fragments
fragments are are needed.
needed. The The gapgap
•*Control
Control conductor spacings to elim-
elim- Circuitground Hardwareground
between
between thosethose fragments
fragments should should be be
inate crosstalk. kept
kept asas narrow
narrow as as possible
possible (an (aneighth
eighth
• Make
Make extensive useuse of decoupling of
of an
an inch
inch works
works well
well in
in most
mostapplica-
applica-
capacitors. Noisyground tions),
tions), and
and the
the number
number of of signal
signal lines
lines
• Pay attention to ac
ac loading. that cross the gap
that cross gap should
should be be mini-
mini-
• Terminate
Terminate lines
lines properly
properly to mini- Logiccircuits Chassis in mized.
mized. Designers
Designers should
should also also bear
bear in in
mize reflections. Harddrives,
mind
mind thatthat through-holes
through-holes and and viasvias
subtract
subtract from from the effective
effective area area of of
PLANEA
PLANE DVICE
ADVICE
relays,
• lamps,etc. the
the plane,
plane, increasing
increasing its effective im-
its effective im-
For high-speed
high-speed logic,
logic, gground
round pedance.
pedance.
planes aren't
aren't simply suggested
suggested for As
As with
with grounding,
grounding, an anentire
entire layer
reliable board performance-they
board performance—they
12. SEPARATEDEDICATED
grounds
grounds should
should be
besupplied
supplied for
for the
the logic
logic of
of the
the board
board should
should be be designated
layer
designated as as
are absolutely necessary. It's essen- circuitry,
circuitry, noisy
noisy high-current
high-current devices,
devices, and
and aapower
power plane.
plane. Even though
though itit isis atat aa
tial that one layer of the board be asas- the
the chassis.
chassis. The
The three
three should
should come
come different
different potential,
potential, the
the power
power planeplane
signed for a ground plane
plane and
and that
that it
it together
together atat one
one point,
point, the
the central
central system
system should
should be implemented in accor- accor-
cover as
as large an area as as possible. A ground,
ground, which
which isis usually
usually located
located near
near the
the dance
dance withwith the
the same
sameconcepts
concepts as as the
the
solid gground
r o u n d pplane
lane lolowers
w e r s tthe
he power
power supply.
supply. ground
ground plane.
plane. Therefore,
Therefore, ititshould
shouldbe be
ground-return-path impedance
impedance as as devices
devices as as relays, lamps, motors, and and fragmented
fragmented when necessary necessary to iso- iso-
well as
as the
the device-to-device
device-to-device ground hard drives should be separated late late noisy
noisy components
components from from delicate
delicate
pin impedance. from'
from the the logic ground. This can be logic logic circuits.
circuits.
But aa common
common ground plane for for all
all accomplished
accomplished bby fragmenting tthe
y fragmenting he
of the circuitry in a system can cause ground
ground plane plane iinto discrete areas
n t o discrete AWELL-GROUNDEDSYSTEM
areas A WELL-GROUNDED SYSTEM
problems bby coupling noise
y coupling noise ffrom
rom (Fig.i)
(Fig. 1).... In addition to properly designed
In addition designed
high-current switching devices into But fragmentation causes
But fragmentation causes prob- prob- power
power and ground planes, high-
sensitive logic inputs. Therefore, the lems
lems of of its
its own-it
own—it creates
creates discontin-
discontin- speed
speed logic
logic systems requirerequire the the es-
es-
ground plane
plane for such high-current uities iin the characteristic
n the characteristic imped- imped- tablishment
tablishment of o f a good,
good, cleanclean (low
(low-
SIGNAL LINES
SIGNALLINESB BECOME TRANSMISSION
ECOMETRANSMI LINES
SSIONLINES
F
F o ror the the transmission
transmission line
model illustrated in the di-
agram, the rise time (to
less than the line
tion delay (To).
line propaga-
propaga-
(TD). In other words, a
line
(tR) is
(A
Because
Because Ro
compared
VA)) w
( VA will
the change
Ro is so so small when
impedance,
compared to the line impedance,
the change in voltage at point A
approximately equal
i l l approximately
change iin
equal
internal voltage
voltage
A
the
the formula
Eq.2
Eq. 2
PL
formula (Eq.
Pt == (R
where
where pL,
L-Zo)
(EL—
(Eq. 2):
2):
Zo) // (R +
PL' called the
L+ Zo)Zo)
voltage re-
the voltage re-
n internal
complete TTL level transition will will (A Vint). This voltage
voltage transition flection
flection coefficient
coefficient (rho),
(rho), is thera-
is the ra-
occur before
before the pulse is received propagates
propagates down the line and is tio
tio of
of the
the reflected voltage to
reflected voltage to the
the
at the receiving end ofof the
the line
line and
and seen
seen atat point
point B B after
after the
the line
line prop-
prop- incident
incident voltage.
voltage.
reflections (ringing)
(ringing) wwill result.
i l l result. agation delay, T
agationdelay, TD.
D• After
After examining
examining Eq. Eq. 2,
2,ititshould
should
The
The voltage change at point A A on At point B, a portion
At point portion ooff the be evident that
be that-1 -1 :5:
< p P :5:
< +1. It It
the line is expressed inin Eq.1:
Eq. I: wave
wave will be be reflected
reflected back to-
back to- should
should also
also bebe evident
evident that that there
there
wards point A A in accordance with with will
will be
be no
no reflected
reflected wave wave ifif RLRI, ==
AVA --- A V , (Zo // (Ro +
= AVint(Zo + Zo»
Zo)) Zo-if
Zo—if thethe line
line is
is terminated
terminated in in its
its
Where: Vint
IT == internal voltage on characteristic impedance. Note
characteristic impedance. Note
the output of
of the driver;
driver; that
that the reflected
reflected wave wave can,can, in in
principle,
principle, bebe asas large as as the
the inci-
Ro output impedance
Ro = output impedance ooff the
the dent
dentvoltage
voltageand andof ofeither
either positive
positive
driving gate; or
or negative
negative polarity.
polarity.
RL
RL—= load
load impedance;
impedance;
This
This analysis
analysis holds
holds true
true for
for the
the
sending
sending endend of of the
the line,
line, as
as well
well as as
Zo
Zo == the characteristic line
line the
the receiving
receiving end.
end. That
That is,is,
impedance;
impedance;
Eq.3
Eq. 3
and VA== the
VA the source
source voltage
voltage at
at the
the
sending Ps
ps== (Ro
(Ro—- Zo) (Ro+
Zo) // (Ro + Zol
Zo)
sending end
end of
of the
the line.
line.
6-2
6-2
lu\1iH:"!44IiR,ilili$1
DESIGNINGWITH
DESIGNING WITH
HIGH-SPEEDLLOGIC
HIGH-SPEED OGIC
noise) system
system ground
ground ffor reliable data line cross-couples
o r reliable cross-couples or superim- creating
creating aa stub stub or aa high-frequency
high-frequency
performance. AA c clean y s t e m poses
l e a n s system poses its signal onto the clock line, antenna.
antenna.
ground ensures less noise within the the device that the clock is driving Another
Another step step that
that cancan be be taken
taken to to
system, andand tthus ensures good,
h u s ensures good, may detect an an illegal
illegal level
level transition.
transition. reduce crosstalk is to lower
reduce lower the im- im-
strong transistor margins. A Att least Methods reduce crosstalk
Methods to reduce crosstalk are pedance
pedance of those those traces
traces into into which
10% of the ground connections on the straightforward, straightforward, though not partic- crosstalk
crosstalk is especially
especially to be be avoided.
avoided.
pc card should
PC card should be be connected
connected to the the ularly elegant. The coupling can can be The
The lower
lower the impedance that
the impedance that aatrace
trace
system ground
ground tto reduce card-to-
o reduce card-to- attenuated by separating the adja- presents,
presents, the the harder
harder iitt will be be ttoo
ground impedance. cent traces asas much as as possible.
possible. The cross-couple
cross-couple aa signalsignal into into it.it.
Like the ground and power planes trouble with with this
this approach
approach is is that
that Even
Even with the use use of o f power and and
of the individual boards, the overall available board real estate often often lim- ground
ground planesplanes on on aa pc pc board,
board, decou-decou-
grounding scheme
scheme should
should piing capacitors must
piing capacitors must be be
be fragmented
fragmented with sepa- sepa- A B used
used on on thethe Vee
Vc, pins of of ev-
ev-
rate conductors
conductors provided
provided ery high-speed device.
ery high-speed device.
for the various sections of Those devices demand
Those devices demand a
the system.
system. ForFor example,
example, +2 nearly
nearly i n sinstantaneous
tantaneous
relays, lamps,
all relays, lamps, hhard ard (a)
(a) 0 change
change in in current
current whenev- whenev-
drives, and
and other
other noise-
noise- I <0
td er
er they
they switch states. states. Be- Be-
generating devices should -2
-2 cause
cause tthe h e ppowero w e r planeplane
have their
their own
own separate
separate +2 - can't
can't meet
meet that that demand,
demand, aa
ground path. The system's
system's
mechanical package (chas- (b)' (b) 0
-t- high-quality
high-quality decoupling
capacitor
capacitor is required,
decoupling
required, oth- oth-
t=
t 0+
sis, panels,
panels, andand cabinet
cabinet erwise
erwise the switchingswitching will
-2 -
doors) should have a dedi- -- cause
cause noisenoise oonn tthe Vee
h e 17(,c
cated gground.
r o u n d . AAnd,
n d , ooff +2 - plane.
plane.
course, the
the logic circuitry (e) (c) 0 A multilayer ce-
O.l-/LF multilayer
A 0.1.-1,F ce-
should have a ground of its ramic
ramic (MLC) or other other RF
own. -2
0 - I=To
-2
t = To'+
---L- quality (low-inductance)
quality (low-inductance)
Those t three grounds
h r e e grounds capacitor
capacitor should should be be placed
placed
should then come together +2
+2 - on
on every
every fast-slew-rate
fast-slew-rate de- de-
at t the
h e ccentral
e n t r a l ssystem
ystem (d)
(d) 0 vice
vice asas close
close to to the
the VeeVcc pin
pin
ground point,
point, which
which wwill ill
-2
o -I 1=
= 1.5T
1.5 Too -I--- as possible. The commer-
as possible. commer-
usually be located near the the cially available DIP sock-
cially available sock-
power supply (Fig. 2). This This +2
+2 - ets
ets w with
i t h built-in decou- decou-
common-point grounding
grounding piing
piing capacitors also also work
work
(e)
(e) I--.
technique can also be very 0 well
well inin this
this application.
application.
effective in reducing radi- - --I-
I Most
Most designers,
designers, when
-2
-2 t1=2T= 2TD+ +
ated interference
interference ((EMI EMI they
they think
think of of loading
loading at at all,
all,
andRFI).
and RFD. think in terms of dc
think de load-
load-
3. WA VE PROPAGATION along a transmission line
1 1 3 . WAV E P R O PA G AT I O N along a transmission line ing-traditionally
ing—traditionally r ere- -
TAMING CROSSTALK
TAMINGCROSSTALK occurs as follows:
occursas follows: Prior to to time
time zero,
zero, there
there is
is aasteady-state
steady-state voltage
voltage ferred
ferred tto o asas fan-out
fan-out and and
Crosstalk-the undesir- of 2.5
of 2.5 V
V de
de on
on the
the line
line (a). At tt =
(a). At = 0,
0, the
the vollage
voltage at at point
point A
A drops
dropsto to fan-in. But that type of
Crosstalk—the undesir- fan-in. B u t t h a t type o f
able 0.5 V,
V, sending
sending aa negative
negative pulse
pulse ofof -2
-2 VV toward
toward point
point B B (b).
(b). At
At tt ==
able coupling
coupling of
of aa signal
signal onon 0.5 loading
loading rarelyrarely presents
presents aa
one conductor to to one
one on
on aa T„, that
that negative
negative pulse
pulse is
is reflected
reflected from
from point
point B.B. It
It adds
adds problem
one conductor To, problem wwith i t h t otoday's
day's
nearby cond uctor-be- algebraically to
to the
the 0.5
0.5 V
Von the line
line and
andsends
sendsaa-Ui-V
-1.5-V pulse
pulse back
back state-of-the-art
nearby conductor—be- algebraically on the state-of-the-art logic logic de- de-
comes an increasingly
comes an increasingly seri- seri- toward point A (c). The
(c). The reflections
reflections then
then continue
continue as as in (d) and
and (e).
(e). vices. Much more
vices. Much more signifi- signifi-
ous problem
problem as slew ratesrates go
go up.
up. This its the possible separation separation to to anan inad-
inad- cant cant when designingdesigning w with
i t h high-
signal coupling
coupling is mademade worse if the equate amount. speed
speed logiclogic are input and and output
output ac ac
second trace has a high impedance or Ground striping, shielding, is
striping, or shielding, is an
an loading.
loading.
if the traces run parallel to one an- effective wway a y tto reduce crosstalk
o reduce crosstalk
other for more than a few inches and and it makes better use use of INPUTCAPACITANCE
of available INPUT CAPACITANCE
are spaced less than 100 to 150 150 mils board area. With ground striping, a Because
Because the the input
input capacitance
capacitance of of aa
apart.
apart. ground
ground trace trace (the (the stripe)
stripe) is is run
run bebe- device impacts the
device impacts the overall
overall perfor- perfor-
Crosstalk can be catastrophic to a tween tween the the two
two parallel
parallel tracestraces to to act
act mancemance of the the logic circuit, it i t should
should
logic board, sabotaging
logic board, sabotaging aa conceptu-
conceptu- as as aa shield.
shield. IIff ground ground stripingstriping is is be be examined
examined before particular de-
before aa particular de-
ally flawless piece
ally flawless piece ooff logic
logic design.
design. used, through holes
used, through holes to to thethe ground
ground vice vice is is selected
selected for for aa design.
design. To To en-
en-
For
For example,
example, ifif aa clock
clock line
line and
and aa data
data planeplane should
should be be placed
placed everyevery 11 to to 1.5
1.5 sure sure specified
specified performance,
performance, the the total
total
line run parallel
line run parallel to to each
each other
other for
for inches
inches along
along the the ground
ground strip strip to to elim-
elim- load capacitance tthat
load capacitance h a t aa device device
more than several
more than several inches,
inches, and
and if
if the
the inateinate the possibility of
the possibility of inadvertently
inadvertently drives-including
drives—including the the distributed
distributed ca- ea-
6-3
6-3
DESIGNAPPLICATIONS
DESIGNINGWITH
DESIGNING WITH
HIGH-SPEEDLLOGIC
HIGH-SPEED OGIC
ture
ture ofo f aa high-speed
high-speed logic board board is is
ringing, which is
ringing, which is caused
caused by by multiple
multiple
reflections
reflections from from the ends of unter-
the ends unter-
+2.5 minated transmission lines. A
minated transmission Ann un-un-
terminated
terminated line has has no no load
load imped-
imped-
ance
ance (R(Re,L== 00) ) andand is is therefore
therefore an anim-im-
u-r-----r--T---r-- pedance-mismatched
pedance-mismatched line. line. TheThe bebe-
-1.5 havior
havior of of this
this line
line when
when connected
connected to to
aa device
device withwith aa fast fast slew
slew rate
rate can can be be
understood
understood from from the following following ex- ex-
(al (bl ample:
ample: Prior to to time zero, zero, there's
there's aa
steady-state
steady-state voltage voltage of of 2.5
2.5V V dcdeat atall
all
1 4. IDEALLY, THE VOLTAGE
I I 1 4 . I D E A L L Y, T H E V O LTA G E at point B oscillates forever
M . I .1.5
5V V (a). In reality, it will be
be a damped
damped ringing (b).
forever between
between +2.5Vand-
+ 2.5 V and - points
points on
an
on the
an initial TTL
line (Fig.
the line (Fig. 3a). At
T T L voltage transition
A t tt =0 0,,
from
from 2.52.5 V V to
to 0.5
0.5 V V occurs
occurs at at point
point A A
pacitance of the trace-shouldn't
trace—shouldn't ex- ex- and layout
and lay out sections, oorr islands, o
off (Fig.
(Fig. 3b). Time TD TD later, the signal signal
ceed the device's
device's specified capacitive high-speed
high-speed logic by hand in order toto reaches
reaches point B and and is is reflected
reflected by by
load. Most
Most high-speed
high-speed logic devices
devices avoid the pitfalls of designing with the
the load
load reflection
reflection coefficient,
coefficient, PL' pe,.
have aa maximum loading
loading of
of 50
50 pF.
pF. As high-speed
high-speed logic.
logic. The
The input
input impedance
impedance of of the
the device
device
aa rule of thumb, the maximum load at
at point
point B Bisis very
very highhigh withwith respect
respectto to
on any
any logic
logic element
element should be be no TRANSMSI SO
I NLI
TRANSMISSION NES
LINES Zo;
Zo; RL
RL can
can be be approximated
approximated by by infin-
infin-
more than four
four to
to six devices
devices for
for best
best In addition
addition to the common-sense
common-sense ity.
ity. By plugging
plugging into into Eq. Eq. 22 from
from the the
speedlload performance. However,
speed/load performance. However, layout considerations discussed
layout considerations discussed so so box
box (p. 76), the
(p. 76), the reflection
reflection coefficient
coefficient
there are
are some
some high-slew-rate
high-slew-rate de-de- far, designers
designers of of high-speed
high-speed systems
systems approximately
approximately equals equals +1. In other
I n other
vices on the market thatthat have higher must have
have aatt least a basic basic under-
under- words,
words, the the voltage reflected reflected by by the
the
output drive
drive capabilities. standing
standing ooff transmission lines lines and load
load is equal to to thethe incident
incident voltagevoltage
proper termination
termination techniques (see (see (Fig. 3c) .TThe
(Fig. Sc.) h e reflected
reflected wave wave passespasses
BEWAREOF
BEWARE OFAUTOROUTER
AUTOROUTER "Signal Lines Become
"Signal Lines Become Transmis-
Transmis- back
back along
along the the signal path toward toward
The
The most common reason for not Lines,".. p.
sion Lines, 76). The reason:
p. 76). reason: As point
point A A (Fig.
(Fig. 3d).
3d).
following tthe board-layout princi-
h e board-layout princi- frequencies
frequencies go up, up, wavelengths
wavelengths Repeating
Repeating the the calculations
calculations for for the
the
ples mentioned
mentioned soso ffar is having
a r is having an come down to the point where they sending
sending end of the line (point
o f the (point A), A),
autorouter ddoo t the layout. Autor-
h e layout. Autor- are
are ooff the
the samesame orderorder asas circuit-
circuit- where
where Ro;::::
Ro 0 0,, you you getaget avalue
valuefor forthe
the
outers do
do what they were designed board dimensions. Once
board dimensions. Once tthat hap-
h a t hap- source
source reflection coefficient,coefficient, cos, Ps, of of
to do
do very well: They place traces so pens, any connection
pens, any connection between
between de- de- -1.
–1. In other words, words, there there are are reflec-
reflec-
make the most efficient use of
as to make vices considered a trans-
vices should be considered trans- tions
tions from
from the the source
source as as well
well as as the
the pc-board
pc-board real
real estate.
estate. But most mission line.
line. The
The lumped-element
lumped-element asas- load"
load„ but
but thethe source reflects reflects the the in-in-
autorouters don't
don't have thethe capability
capability sumption
sumption is is simply
simply invalid
invalid above
above that
that version
version of the the wavewave that that isis incident
incident
to determine which devices are high- point. upon it (Fig.
upon.it (Fig. 3e).
Se).
speed and
and which
which are
are not.not. This
This is
is The
The most
most common consequence of of Looking
Looking just just at atthe
the behavior
behaviorof of the
the
where the logic designer
designer mustmust step
step in failing
failing to
to consider
consider the the distributed
distributed na-na- signal
signal at at point
point B, B, the
the single-step
single-step volt- volt-
RUlES TO R
RULESTO REMEMBER
EMEMBER
T
T h ehe following
following ten
the logic
to know when
ten rules
summarize everything
rules
everything
logic designer
designer needs
needs
when designing
high-speed CMOS.
with high-speed CMOS.
4) Fragment the
4)
er planes
er
the ground
ground and
and pow-
planes to supply separate
pow-
sec-
separate sec-
tions for high-current switching
tions
devices.
devices.
8)Beware
8) Bewareof
within the
within
ofac
acloading
loadingconditions
the design.
conditions
design. Exceeding
Exceeding the
manufacturer's recommended
manufacturer's
erating
recommendedop-
erating conditions,
conditions, especially
capacitance,can
capacitance, cancause
the
op-
especially for
causeproblems.
for
problems.
5) Use
5) Use decoupling
decoupling capacitors
capacitors onon
1) Keep signal
1) signal interconnections
interconnections as
as every high-speed
every high-speed logic
logic device
device (0.1
(0.1 9) When
9) When using parallel termina-
using parallel termina-
as possible.
short as ,...F
p,F MLC
MLC type)
type) located
located as
as close
close to
to tion, put
tion, put bends
bends inin all
all high-speed
high-speed
2)
2) Use a
a multilayer PCB.
PCB. the Vee
the Vcc pin
pin as
as possible.
possible. signal runs
signal runs that
that gogo to
to more
more than
than
one
one load. Use aa termination
load. Use termination load
load
3) Provide
.3) Provide ground
ground and
and power
power 6)
6) Provide
Provide the
the maximum
maximum possible
possible at
atthe
theabsolute
absoluteend
endof ofthe
theline.
line.
planes. Discontinuities
Discontinuities in the spacing
spacing among
amongall high-speedpar-
all high-speed par-
planes should be avoided because
because allel
allel signal
signal leads.
leads. 10) Create
10) Create islands high-speed
islands of high-speed
reflections can occur from abrupt devices on the
devices on the pc
pcboard.
board. This
This sim-
sim-
Terminate high-speed
7) Terminate
7) high-speed signal
signal plifies
plifies board
board layout
layout and
and ropes-off
ropes-off
changes in the characteristic im-
pedance.
pedance. lines where
lines tR < 2TD.
where tR 2To. the
the high-speed
high-speedareas.
areas.
6-4
6-4
DESIGNAPPLICATIONS
DESIGNINGWITH
DESIGNING WITH
HIGH•SPEEDLLOGIC
HIGH·SPEED OGIC
the receiving
receiving end end (Fig.
(Fig. 5).
5). characteristic impedance of
characteristic impedance o f tthe
he
RL =
= Zo / +3.0Vdc
Zo 1+3.Dvdc In the configuration (Fig. (Fig. 5a), RI, RL line—that is,
line-that Rs +
is, Rs + Ro
Ro == ZOL'
ZOL•
10
I [> . == Zo and
and RL
principle, RL
RL is
is pulled
RL could
but TTL-compatible
pulled up to
could be
to 3 V
be tied to
TTL-compatible devices
V dc.
de. In
to ground,
devices could could
In Making Rs
Making
course,
which
Rs + + Ro equal
equal to
creates a voltage
course, creates
which puts half of
to ZOL,
ZoL, of
voltage divider,
of the
divider,
the signal ampli-ampli-
of
+5.0Vdc not then

then supply
supply thethe necessary
necessary drive. drive. tude
tude across
across the line line and
and half acrossacross
Zo 5/310
5/3Zo Solving forfor PL (Eq. 2), itit can
pL(Eq. can bebe seen
seen the
the series
series combination
combination of of Rs
Rs and
and Ro.Ro.
that pL
PL — O. Terminating aa line
= O. line in itsits Therefore,
Therefore, with the termina-
the series termina-
(b) +5.0 Vdci
impedance results in
characteristic impedance in aa tion,
tion, the amplitude
amplitude of of the
the transmit-
transmit-
5/2Zo reflection coefficient of zero, which ted
ted wave
wave is is half
half ofof what
what itit would
would be be
0.1 - means that there will be no reflec- without
without the the termination.
termination.
Zo = lo tions or distortions
distortions on the the line.
line. Other
Other Interestingly enougl), the unter-
Interestingly enough,
than the time delay, TD, TD, the line will minated
minated receiving
receiving end end ofof the
the line
line pre-
pre-
act as if it were a dc de circuit.
circuit. It's im- cisely compensates for this halving
cisely compensates
(c) portant to note that even even though de- de- of
of the
the amplitude.
amplitude. The Thereason
reasonisisas asfol-
fol-
5. THE BASIC PARALLEL vices or gates may be placed at any lows:
lows: AtA t the
the receiving
receiving end,end, thethe half-
half-
115. THEBA
termination SICP
scheme
scheme ARA
works LLbutEL
well location on the line, the terminating
resistor should be placed at the end
amplitude
amplitude wave
half-amplitude
received and a
wave is received
requires a separate 3-V
3-V supply (a). The
The half-amplitude wave is reflected. reflected.
Thevenin equivalent eliminates the need
need of the
the line. In nono case should the line But
But bear
bear in in mind
mind that
that those
those are are twotwo
for a separate supply.
supply, bnt
but dissipates be split like aa Tee
Tee to to feed
feed several de- de- separate
separate waveswaves whosewhose amplitudes
amplitudes
extra power from the regular 5-V supply vices in parallel (Fig. 6a). 6a). Instead, it it add
add at the point of of reflection. As aa
(b). The use
use of a capacitor cuts de
de should be serpentined to feed feed them result of
result of this
this addition,
addition, the
the only
only thing
thing
dissipation altogether while supplying ac
ac sequentially (Fig. 6b).
(Fig. 6b). seen
seen atat the
thereceiving
receiving end endof of the
the line
lineisis
termination (e).
(c). The
The 3-V
3-V power source shown (Fig. (Fig. aafull-size
full-size pulse.
pulse.
5a)
5a) appears at first ttoo be aa major major The
The main
main disadvantage
disadvantage of of aa series
series
age transition at at tt = 00 leads
leads to an end- drawback, but RL RI, and
and the
the power
power sup- sup- termination
termination iis s tthat
h a t tthe receiving
h e receiving
lessly oscillating signal with a total ply can be expressed as a Thevenin gate
gate or gates must be be at
at the end end of of
swing ooff 4.0
voltage swing 4.0 V—twice
V-twice the the equivalent running o off system
f f the system the line-no distributed loading is
the line—no
original level transition. The voltage power supply
supply of of 5 VV dc
de (Fig. a ) . This
(Fig. 5b). This possible.
possible. TheThe obvious
obvious advantage
advantage of of aa
doubling comescomes about
about because
because thethe variant works
works well, but the the designer series
series termination
termination over overaaparallel
parallel one one
voltage at point
point B is the the sum ofof the in-
in- should
should bear
bear in
in mind thatthat it it dissipates
dissipates is
is that aa series termination doesn't doesn't
cident andand reflected
reflected waves waves aatt that additional power.
point (Fig. 4a).
,4a). Actually, because of
the non-ideal nature of aa real circuit REDUCINGDISSIPATION
REDUCING DISSIPATION
(finite input and output
board (finite output imped-
imped- A solution
solution tthath a t dissipates less
ances, losses
losses i inn tthe transmission
h e transmission power than either of of the others usesuses
.-
lines, and
and soso forth), PL PL will bebe less
less aa capacitor to cut the de dc dissipation
than + 1, and Ps
+1, Ps will
will be greater thanthan— to zero (Fig. 5c). The recommended
recommended
1. As a result, the reflections will be- 0.1-uF MLC type. Sev-
capacitor is aa O.I-JA-F Sev-
come successively
successively smaller,smaller, causing
causing eral
eral manufacturers
manufacturers produceproduce bothboth ca-
ca-
the familiar
famiiiar damped
damped ringingringing condi-
condi- pacitor-resistor and pull-up/pull-
tion (Fig. 41)).
,4b). down termination
termination packs.packs. TheThe pull- (I)
If amplitude is large
I f the ringing amplitude up/pull-down packs usually come come in in I
enough, itit can cause the receivingreceiving de-
de- aa single
single in-line
in-line package
package (SIP) with
vice to see an illegal level transition pins
pins on O.I-in.
0.1-in, centers, while the ca-
and possibly result in spurious logic pacitor-resistor combination
combination comes comes
states occupying the logic design. In in a standard 16-pin DIP. The most
some cases,
cases, tthe amplitude ooff the
h e amplitude the common SIP SIP pull-up/pull-down
pull-up/pull-down re- re-
ringing can actually be large enough sistor
sistor values are 22011/3301),
2200/3300, 33011/ 3300/
to damage the input of the the receiving
receiving 4700
v o n combinations.
device. An alternative to aa parallel termi-
I
nation at at the
the receiving end end is
is aa series
series
1
TERMINATEYOURTROUBLES
TERMINATE YOUR TROUBLES termination at the sending end (Fig. (Fig. (b)
(b)
The
The way
way toto eliminate
eliminate ringing
ringing on
on aa 7). The
7). The idea
idea behind
behindserial
serial termination
termination
transmission
transmission line line is
is to
to terminate
terminate the
the is
is to
to make Ps Ps == 0 and PL pL == +
+1.1. To do
do 116. SEterminating
RPENTaaIN ING ISesplit
6. SERPENTINING ISessenlial
ssethe
ntial
line
line in
in its
its characteristic
characteristic impedance
impedance atat so, RL is
so, RI, is made
made equal
equal toto infinity
infinity (left
(left when
whenterminating line.
line. Never
Neversplit the
either the sending
either the sending oror receiving end.
receiving end. unterminated)
unterminated) and and aaseries
series resistor
resistor is is line
line to
to feed
feedparallel
paralleldevices
devices(a).
(a). Rather.
Rather,
The
The mostmost common
common way way to terminate
to terminate added
added atat the
the source
source toto make
make thethe over-
over- feed
feedthem
themsequentially
sequentiallywith
withaaserpentined
serpentined
line is
aa line is with
with aa parallel
parallel termination
termination atat all source impedance
all source impedance equal equal tto the
o the line
line (b).
(b).
6-5
6-5
DESG
I NAPPLICATIONS
DESIGNINGWI
DESIGNING TH
WITH
HIGH-SPEEDLLOGIC
HIGH-SPEED OGIC
require any
any connection
connection to a power words, lines
other words. lines must
must be terminat-
terminat- For
For aa typical
typical board
board constructed
constructed of of
supply. edwhen,
ed when, FR4 material,
FR4 material, eR ea (the
(the dielectric
dielectric con-con-
Transmission-line effects must be stant) is
stant) is 4.7
4.7to
to 4.9.
4.9. IfIf an
anaverage
averageeR eRofof
taken into
into consideration
consideration whenever
whenever 2T D=T
2To= TR.
R•
4.8
4.8 is used
used in thethe equation,
equation, then then ttpD
pD
delays get
line propagation delays get up to the CALCULATINGD
CALCULATING ELAY
DELAY turns
turns ooutu t to be 1.751.75 nns/ft,
s i f t , which
point where a signal transition can Taking 22ns
ns as
as aa typical
typical rise time
time for
for aa works out
works out to
to 6.86
6.86 in.lns.
inins. AsAs aa rulerule of
of
be completed before that signal can state-of-the-art high-speed
high-speed logic de- de- thumb,
thumb, then,
then,any
any line
linethat
that is
isover
over77in.
in.
travel down a line, be reflected, and vice, how long can
vice, can aa board
board trace get long should be
long be considered a trans- trans-
travel back to
to its starting point. In before
before its propagation delay gets to mission
mission line andand approached
approached accord- accord-
be 1-ns long?
be 1-ns long? For aa pc board with aa ingly.D
ingly D
continuous ground plane and aa sig-
nal
nal trace on the adjacent layer, the
propagation depends on only
propagation delay depends
one variable, the dielectric constant Jock Tomlinson,
Jock Tomlinson, senior
senior applica-
applica-
1
1 7 7.
. THE
T H E SERIES
no pulkp
S E R I E S termination needs
termination needs
pull-up supply. Ita
Its main disadvantage
disadvantage
is that itit can't handle distributed loads.
loads.
of the board
of the board material.
time is given
given by:
pD =1 .1.017
ttpD
material. That
(0.475 eR +
0 1 7 (0.475eR
That delay
+ 0.67)112
delay
0.67)1/2 ns/ft
ns / ft
tions engineer
tions engineer at Lattice,
BSEE from
BSEE
versity.
versity.
Lattice, holds
from Colorado
Colorado State
holds a
State Uni-
Uni-
6-6
6-6
architectures
arcbiteC/llre.1 I'
r
Extending the
..................................................................•...........
221710 EMU)
22V10 EPLD
......•.........•.............................•........••..•..........•......
T he 22V10
1 1 1 . he 22V 10 device
device architecture
architecture is
programmable logic devices.

is now
now one
one ooff the industry
devices. The 22V10

22V1O owes
industry standards
standards iin
n
owes its popularity to aa number

number of
of
•• architectural features
features that
that bring
bring versatility and
and flexibility to system
system design.
design. The
The
Output Logic
Logic Macro-Cell (OLMC) is perhaps the most revolutionary
(OLMC) 'is feature of the
revolutionary feature the
An extelldable
extendable
22\710 architecture.
22VIO architecture. OLMCs
OLMCs eliminate such
such architectural
architectural constraints
constraints as
as insufficient
devlce
device .... 11y
family
product-term access,
access, fixed
fixed output polarity, limited
limited three-state
three-state control, and poor
control, and poor
_llows,...
allows gate control of registered outputs. The 01.,MC
OLMC atat any
any device
device I/O
I/O pin
pin is
is functionally
functionally identical
identical
_nd 110 counts to any

any other. Additionally,
Additionally, any any 110 product
product terms terms per per OLMC
OLMC in in all
all 20-pin version ooff the
20-pin version the 24-pin
24-pin
and I/O counts
can be used
can be used as feedback path
as aa feedback path into modes,
modes, two outputs have access
outputs have access toto GAL22VlO.
GAL22V10. It It contains
containseight
eight dedi-
dedi-
the AND array.
the AND 10 product terms
10 product terms perper OLMC
OLMC in all cated input
cated input pins
pins (four
(four less
less than
than the
the
tobeboHted Asynchronous
Asynchronous resetreset isis another
another modes, another two
modes, another two have access to
have access to 22V 10) and
22V10) and 10 I/O (the
101/0 (thesame
sameasasthe
the
to be boosted
attractive feature 22VlO.
feature of the 22V10. 14
14 product terms,terms, andand the
the center
center 22VI0). The 28-pin
22V10). The GAL26CV12
28-pin GA1.26CV12
One reset signal is common
One reset common to all twO outputs have
two outputs have access
access tto o 1616 has two
has two more
more dedicated
dedicated input
input pins
pins
wIIhoat
without .....
majoror registered OLMCS and operates
registered 01.MCs operates in- product terms.
terms. Each Each OLMC'
OLMC'ss out- and two more
and two more 110 p i pins than the
n s than the
dependently of of the dedicated clock
the dedicated clock put driver has has aa unique
unique enable/dis-
enable/dis- GAL22VI0. The GAL26CVI2
GA1.22V10. The GAL26CV12 in in aa
input. This
This signal
signal isis taken
taken from
from able signal that is taken
able signal taken from
from thethe package requires
PLCC package
PLCC requires no no more
more
eIIe..... IIn
changes .. the
the AND array andand may be be generat-
generat- AND
AND array
array andand that
that may
may be be gener-
gener- space than many
space than many lower-density
lower-density
ed
ed via aa product term. Registered
Registered ated
ated via
via aaproduct
product term.
term. AllOLMCS
All 01.MCs PLDs.
PLDs.
OLMCS respond immediately
OLMCs respond immediately to a respond
respond immediately
immediately to to the
the arrival
arrival The EECMOS GGAL18VlO
T h e EECMOS A 11 8 111 0 aand
nd
board layout reset
reset signal. In addition, one pre- pre- of
of aa valid enable signal
valid enable generated
signal generated GAL26CV12
GM-26CV12 consumeconsume just 75 75 rnA
rnA
set
set signal is common to all regis- regis- externally
externally or internally. and
and 90 typical Icc,
mA typical
90 rnA Icc, respective-
respective-
tered ouics
OLMCS andand operates
operates on the the The
The three members of Lattice's
three members Lattice's ly-50 percent less
l y - 5 0 percent less power
power than
than
•• arrival of aa valid clock input. This

signal is taken from the AND AND atray
array
GAL22VI0
GAL22V10 series--the
GAL22VlO,
GAL22V10, and
series—the GAL18VlO,
GAL18V10,
and GAl26CV12—are
GAL26CV12-ere
bipolar
bipolar alternatives.
mable
mable AND
alternatives. The
AND arrays
Theprogram-
arrays are
program-
are proportional
proportional
and
and may be generated by aaproduct
be generated product high-speed,
high-speed, EECMOS PI.I>5. Each
EECMOS PLDs. Each is ro
to the
thepin countof
pin count ofeach
eachdevice.
device. The
The
term. Registered
Registered 0114Cs
OLMCS respond
respond based
based onon the
the standard
standard 22VI0
22V10 archi-
archi- arrays
arraysareare96
96 X 36, 132 44, and
132 X 44, and
only on the arrival of aa valid clock
the atrival tecture; their di/lerences
tecture; differences involve
involve the
the 122
122 XX 552 for the
2 for the GAL18V10,
GAL18VlO,
input.
input. number of 1I00,
number pins, and
lios, pins, and product
product GAL22VI0,
GA1.22V10, and and GAL26CV12,
GAL26CV12,
Along
Along with minimum of
with aa minimum ofeight
eight terms
terms offered.
offered. The GAL18VlOGAL I8V10 isis aa respectively.
respectively.
1990
1990 R e p r i n Reprinted
t e d from
from the 1990 PLD
the 1990 PLD Design
Design Guide - with
Guide — with permission
permission from
from CMP Publications.
CMP Publications. DESIGN
D E S I G N GUIDI!,
GUIDE
6-7
6-7
The first
first j jobo b that that aa designer
designer has has iinn
selecting tthe h e rright
i g h t 22V10
22V 10 device device ffor o r aa RAW DATA 1 616
RAW MULTIPLEXED INTERMEDIATE
MULTlPLllXED INTERMI!J)IATE
system is to evaluate the size and complex- INPUT -.,.......
INPUT CONTROL SIGNALS
CONTROL SIGNALS
iity
ty ooff the design
design as as well as as system speed speed
(2 BYTES)
(2 BYTES) §
and power
and power requirements.
requirements. PLDs PLDs excelexcel iin n MULTIPLEXED
MULTlPLl!XI!D 2 ::I :J
applications tthat h a t have CONTROL
CONTROL I-''--.J
have aa number number ooff Ss SSI
INPUTS
INPUTS 4 §
parts with low low gate gate counts
counts and and combin-
::I:J PROCESSED DATA
DATA
ational logiclogic that optimally fit into aa sin- sin- __ . . PItOCl!SSID
OUTPUT (I
OUTPUT (1 BYTE)
BYTI!)
gle device.
device.
The GAL 18V 10 features an equivalent
GALI8V10 equivalent
gate countcount ooff 450 tto 550 gates,
o 550 gates, along
along
Figure1.
Filllre 1. In
Inlhis example,twa
thiseumpl., two22¥10
22010deYices
devicesare
areneeded
neededto provideIlll!UP
topnnide enoughilputs
inputsInd
andIIIIpId$
outputsfer
for•astate
statelIIICIIiII.
machine.
with eighteight tto o 18 18 inputs
inputs and and one one to 110 0
outputs. TThe h e GGAL22VIO's
M 2 2 V 10's equivalent equivalent and
and performance enhancements. enhancements. identify
identify up up toto 1,024 sequential
sequential edge-iden-
edge-iden-
gate count is is 550 to 750 gates; iitt offers For
For example, suppose suppose a designer,
designer, in in a tified events.
tified events.
12 ttoo 2222 inputs
inputs and one one to 10 10 outputs. rush to build a state machine for for control
control These counters generally
These counters generally are are iimple-
mple-
The GAL26CV12
GAL26CVI2 has has anan equivalent
equivalent gate in
in aa ppipeline application, uused
i p e l i n e application, s e d t two wo mented
mented in one one ofof two
two ways-with
ways—with multi- multi-
count ooff 650 tto o 850, 114 4 tto o 26 26 inputs,
inputs, 22V
221/10s lOs ro to implement the function (Fig- (Fig- ple
ple 20V8 devices
devices or or with
with aa single
single 22VlO
22V10
and one to 12 12 outputs. IIff a design has a ure 1).I). The
The objective of o f the
the design
design is to device. If
device. I f aa 22VIO
22 VIO is used, used, enough
enough inin-
fairly low gate count and relatively small take
take 16 16 data-input bits and two control herent
herent flexibility remainsremains for for the
the imple-
imple-
requirements, t the
1/0 requirements,
1/0 GALI8VIO iiss tthe
h e GAL18V10 he bits ttoo generate eight data-output bits. mentation
mentation ooff asynchronous
asynchronous reset reset aand nd
beSt
best choice. Should Should additional inputs be In the device, 1166 data
the first device, data inputs
inputs and and synchronous
synchronous preset preset functions.
functions. For aa 10-
required withoutwithout any any additional output two
two control inputs were used used to generategenerate bit counter bbuilt
bit counter uilt w with
i t h a 221/1022VlO tthat hat
requirements, the the bestbest place
place tto o start is is four encoded
encoded outputs. outputs. Since Since tthe h e ffirst
irst generates
generates aan n ooutput
u t p u t fforo r eevery
v e r y cclock
lock
the GAL22V
Gm..22V10. 10. If I f gate
gate count, input, and device was was output-bound,
output-bound, oonly o u r of
n l y ffour of phase,
phase, which is appropriate
appropriate for for the im- im-
output requirements
requirements aare r e l alarge,r g e , t hthee the
the eeight required data
i g h t required data bbits
i t s ccould
o u l d bbee plementation
plementation ooff a ""watchdog" w a t c h d o g " ttimerimer
GAL26CV12 i is recommended. FFor
s recommended. de-
o r de- generated.
generated. TThe second device was used
h e second used function
function ffor real-time activities,
o r real-time activities, eeight ight
signs wwith larger requirements,
i t h larger requirements, some some to take the
to take the four encoded outputs ffrom
four encoded rom dedicated
dedicated inputs remain remain unused.
unused. If I f that
that
combination ooff the the three
three devices devices wwill ill the first devicedevice and and thethe two
t w o control
control inin- same counter were
same counter were built
b u i l t with
w i t h a 20-pin
20-pin
meet designdesign needs. needs. puts tto o generate the required eight data GALI8VIO,
GAL18V10, four four pins
pins of of real
real estate
estate could
could
The final stages of of the
the evaluation
evaluation cycle cycle output
output bits. bits. be
be saved
saved and power power use use cut by b y o.fw.
0 . 5 w.
often revealreveal problems
problems wwith i t h aa design.
design. The
The above design can be implemented Suppose
Suppose that that same
same 1IO-bit counter iiss
0 - b i t counter
Typically, ssuch problems include
u c h problems include tthe he in a single 26-pin device (Figure 2). The used
used to signal the the "half-full" and and "three-
"three-
omission ooff a critical critical iinput signal oorr a
n p u t signal 16
16 data-input bits and the the ttwo w o control quarter
quarter ffull" points of
u l l " points o f aa 1,024-location
1,024-location
need for for more
more. output Output signals.
signals. Such Such ad- bits
b i t s aarer e f fed e d ddirectfy
i r e c t l y i into
n t o t the he circular buffer. TTwo
circular buffer. independent event
w o independent event
justments are are bestbest accomplished
accomplished bbyy re- re- GAL26CVI2,
GA.1260/12, aand n d t the
h e r remaining
e m a i n i n g ttwo wo codes
codes will
will bebe needed
needed to to decode
decode and and gener-
gener-
patterning the fuse map of the PLD. PLD. This pins
pins can be be usedused for the required eight ate
ate single
single clock-width
clock-width pulsespulses at at these
these two two
design fix is limited by the num-
type of design num- data-output
data-output bits. N Noto t only does
does this ap- points
points ini n the buffer.
ber ooff unused PLO PLD pins available
available and by by proach
proach offer offer tthe obvious advantage
h e obvious advantage ooff Such
Such aa part requires
requires 12 12 outputs.
outputs. Pre- Pre-
the flexibility
flexibility ooff the PLD's PLD's internalinternal fuse-
fuse- reduced
reduced board space, space, iitt also saves saves more viously,
viously, multiple 22VI0 22 VIO devicesdevices or or the
the
map array. IIff the PLD PLD has has not been been ffully
ully than
than 00.5 .5 w w ooff power
power and and removes
removes aann combination
combination of of aa 22VI0
221110 component
component and and
used, aa new new fuse-map
fuse-map pattern can can often entire package delay.
entire package delay. Enough
Enough power power re- re- another
another PLOPLD havehave been
been usedused for for the
the task.
task.
be
be implemented without any board-level duction
duction can mean mean power-supply cost sav- sav- Now,
Now, the part part can
can bebe built
built withwith aa single
single
redesign. IIff additional Ito 1/0 is is necessary,
necessary, ings and and aan indirect increase
n indirect increase iin board
n board 28-pin GAL26CVI2, yyielding
28-pin GAL260712, i e l d i n g a ppower
ower
however, aadditionald d i t i o n a l partsparts usually usually aare re Performance enhancement re-
reliability. Performance savings
savings of of about
about 1 wandw and eliminating
eliminating one one
needed. sults iin n aan extension ooff the llife
n extension i f e ooff an package delay.
package delay. • •
The GAL22V
GAL22V10 10 family is well suited for already
already mature system. system.
situations iin which greater
n which greater overall overall com-com-
•• A
A 1lO-BIT
0 - B I T COUNTER
C O U N T E R DESIGN
DESIGN
plexity aand n d l olower
w e r power power consumption
consumption
must be achieved without a corresponding A second design
A second design example
example involves
involves aa
increase in device count or real estate estate use.
use. standard IO-bit counter. A 10-bit
standard 10-bit lO-bit counter
counter
With
W i t h anan extendable
extendable family, family, gate gate and 110 can
can be used tto
be used provide location-by-loca-
o provide location-by-Ioca-
count c can a n bbe e boostedboosted wwithout i t h o u t mmajor
ajor access of
tion access o f up to 1,024 addresses
addresses or to
changes iin board layout.
n board layout. provide divide-by-two
divide-by-two to divide-by-l,024
divide-by-1,024
When designers are under pressure to clock frequency
frequency reduction
reduction and
and distribu-
distribu-
produce aa design design qquickly, u i c k l y, t the design
h e design IO-bit counter can
tion. A 10-bit can also
also be
be used
used to
to
cycle is much more chaotic. Many times,
aa designer
designer w will simply grab the
i l l simply the closest
closest
part and use
part and use either
either single single parts parts or or multi-
multi-
ple parts
parts to build the circuit. When the
final product has
final product has been been in in production
production for for
aa few months, the the manufacturing-engi-
manufacturing-engi-
neering
neering groupgroup then then must must come come tto grips
o grips
with the the challenge
challenge of o f cost reduction.
reduction. IIn n
some cases,cases, thesethese cost-reduction
cost-reduction efforts efforts
can aalso l s o r eresult
s u l t i in n r ereliability
l i a b i l i t y ggains
ains rIPre Here, aa single
Figure 2. Here, sinale 260012 twa 22010s
replaces two
HeY12 replaces mlOs and deIIJS and
reduces delays
lid reduces .......·suppIJ requirements.
aid power-supply reqtlire.llb.
PROGRAMMABLE
P R O G R A M M A B L E LLOGIC
OGIC
6-8 1990
1990
I
DESIGN ENTRY
DESIGN ENTRY I
ELECTRONIC DESIGN EXCLUSIVE

ELECTRONIC DESIGN EXCLUSIVE
In-circuit logic device can be

reprogrammed on the fly
Of the multitude of ways available for recon- paths

paths where speed is
where speed is critical, so that
critical, so that even
even the
the sys-
sys-
figuring logic systems on circuit boards, none has has tem's
tem's basic logic flow flow can
can bebe altered
altered in an an instant.
instant.
ever proved entirely satisfactory. Changing
Changing dozens
dozens The chip
The chip isis the first in aa planned
planned family
family of of in-
in-
jumper settings manually can be
of DIP switches or jumper be system reprogrammable devices,
system reprogrammable devices, and
and its flexibility
flexibility
aa nightmare.
nightmare. Electrically erasable or battery- isis limited only
only byby the
the designer's
designer's imagination.
imagination. LogicLogic
backed memory can do do the job atat least in part, but designers
designers needneed notnot be
be restricted
restricted toto that
that last
last etch
etch onon
the use of memory bits is limited in most most cases
cases to the
the board,
board, andand final testing
testing nono longer
longer presents
presents so so
flow in the parts of aa system
controlling signal flow system many
many problems.
problems.
where speed is not critical. Because
Becausethe the new
new chip
chip combines
combines CMOSCMOS with with elec-
elec-
Memory bits do have their place in controlling trically erasable
erasable floating-gate
floating-gate and and high-speed
high-speed logic,
logic,
such tasks as as decoding itit runs
runs atat speeds
speeds associated
associated with bipolar
bipolar chips,
chips, butbut
I/O ports, enabling and and consumes
consumes significantly
significantly lessless power-450
power-450 mW mW max-max-
disabling features, and imum
imum and and 350 mW mW on on standby-than
standby—than do do most
most bi-
:ompatible with 5-V
':ompatible 5- V selecting aa memory
bi-
polar
polar chips.
chips. The 16Z8 is similar to the the company's
company's
,¥stems, EEPROM-
systems, an EEPROM- bank, but those
those jobs
jobs are earlier
earlier programmable logic device, device, the 20-pin
)ased chip allows
7ased mutually exclusive: De- GAL16V8.
GAL16V8. Four additional additional pinspins in the
the 16Z8 con- con-
1esigners update
lesigners to update signers have to decide trol in-system
in-system programming
programming and and diagnostic
diagnostic testing
testing
,¥stems
systems in situ, which one they want want to (Fig.
(Fig. I). A proprietary state-machine-based
state-machine–based inter- inter-
vith 100%
100% testing
testing control through the use use face
face controller
controller on on the
the chip
chip handles
handles allallprogramming
programming
of memory. and testing. It
and testing. It also
also makes
makes possible,
possible, through
through thethe four
four
Jnd
7nd observability. The
The few
few logic
logic devices
devices pins,
pins, thethe in-system
in-system observability
observability andand controllability
controllability
now using UV UV EPROM
cells cannot be reprogrammed without being re-
moved from the system. Nor, if sealed
sealed in window-
window-
less plastic packages, are such chips 100% testable.
testable.
Even with windows, they usually have to be
removed from the board for erasing and repro-
gramming, because programming
because the 12- to 21-V programming
voltage risks damage to other components on on the
the
board. Other difficulties can arise
arise too with these
these
techniques, such as
as mechanical switch failures,
failures, wire
wire
breaks or shorts, dead batteries, and mishaps
mishaps that
occur when
when technically unskilled users try their
hand at reconfiguring or fixing
fixing circuitry.
circuitry.
A new
new 24-pin chip does
does away with all those
those pit-
falls. By
By combining programmable logic circuits
with 5-V electrically erasable CMOS memory, it
opens up all kinds of options in reconfiguring aa sys-sys-
tem. The ispGAL16Z8
ispGALI6Z8 not onlyonly is reprogrammable
reprogrammable
in circuit but also is 100%
100% testable—a
testable-a big plus.
Propagation delays of aa mere 25 25 to 35 ns mean
mean that
that
the reprogrammable device can be used in data
ReprInted from ELECTRONIC

Reprinted from ELECTRONIC DESIGN August 7,
OESIGN - August 7, 1986
1986
6-9
that are such powerful diagnostic aids. state to prevent
state prevent unwanted
unwanted writes
writes at power-up.
power-up. A A user-
user-
Like the I6V8,
16V8, the new chip has aa core
core consisting
consisting of aa controlled Reset
controlled Reset signal
signal makes
makes the
the state
state machine
machine move
move to to
standard AND array plane and eight programmable outout- the normal
the normal state
state from
from any
any state
state when
when thethe Mode
Mode pin
pin is
is aa
put logic macrocells; it adds 5-V EE'CMOS
2CMOS programming logic 1,
logic I, SOl
SDI is
is aa logic
logic 0,
0, and
and DCLK
DCLK has has aa rising
rising edge.
edge.
circuitry. Each programmable output output macrocell
macrocell gives
gives the
the The four
The four interface
interface signals
signals are
are relatively
relatively simple
simple to
to gen-
gen-
designer five configuration options, among them them output
polarity (active high or active low), feedback,
feedback, combina- Typical write programming sequence
torial logic, registered outputs and input selection.
toriallogic, selection. Either
all the outputs are connected to one one Output
Output Enable
Enable signal,
signal, Enter progral'Y1"klg
Enter programming states
states from
from the
the normal
normal state
state
Step 1 Mode
Step m
Mode isis ITL Hg'1;
high: SOl m
SDI isis TR Hg'1;
high; DCLK
DCLK isisclock
clock
or separate product terms provide individual enabling Diagnostic: Preload
DIag'1ostlc: Preload state
state (just
OW passI'\g
passing thrClU\tl)
through)
controls. Step 2
Step Mode m
Mode isis TTLHg'1;
high; SDI m
SOIlsis TTLHg'1;
high; DClK
DCLK isisclock
clock
The new chip also emulates all common 20-pin archi- Program; Shift
Program: Shift state
state
tectures similar to Monolithic Memories' programmable

programmable Step 3
Step Mode isis TIL
Mode TIL low;
low; SDI
SOl isis adcI"ess
address a1d
and data
data bits;
bits;
DCLK isis clock
DCLK
array logic. Its programming software and and hardware
hardware sup-
sup- Program: Shift
Program: Shift state
state
port
port come through the standard PLD development
development pack-pack- (Load shft
(Load shift regster
register latch
latch withwith 82
82 data
data bits
bits
and 66 adctess
a1d address bits)
bits)
ages. Because
ages. Because its fuse
fuse map is compatible with that of the the (Note; SDO
(Note: data field
SDO data field isis 'don't
'don't care')
care')
older chip,
chip, the new chip accommodates the latter's soft- soft- Step 4 MMode
SteP m
o d e isis TTL high;
high; SDI m
SDllsis TTL Hg'1;
high; DCLK
DCLK isis clock
clock
ware. (Data I/O I/O is the first
first third-party
third-party vendor
vendor to
to offer
offer up-
up- Program: Read
Program: Read state
state (just
Oust passi1g
passing 1hrClU\tl)
through)
dated programming; other other companies

companies are
are expected
expected toto fol-
fol- Step 5 MMode
Step m
o d e isis TTL high;
high; SDI m
SOl isis TTLHgh;
high: DCLK
DCLK isisclock
clock
Program: Write state
Progrcrn: state
low suit shortly.) (Write beghs
(Write immediately cpon
begins irrmedately upon entering
entering
Program; write
Progrcrn: write state)
state)
SERIAL PORT SIMPLIFIES
SERIALPORT SIMPLIFIES INTERFACE
INTERFACE (Time-out write
(TIne-out write pulse)
pulse)
Step 6 MMode
Step m low; SOl
o d e isis Tit low; m
SDI isis TIL high;
high; DCLK
DCLK isis clock
clock
The
The new chip can be programmed over aa — - 55°C
55°C to Program; Read
Progrcrn: Read state
state
-—125 ° C operating (End write)
(End
125°C operating range and
and can
can undergo at at least 10,000
erase-write cycles. Given its 100% 100% reprogrammability, Step 7 MMode
Step m low;
o d e isis TR: SOl isis 'don't
low; SDI 'don't cae'; clock isis DCLK
care': clock DCLK
Program: Shift
Progrcrn: Shift state
state
yields of of 100% in ac and dc parameters are guaranteed,
guaranteed, as as (Read address;
(Read address; execution
execution of of verify; shft
shift regster
register latch
latch
isis loaded)
loaded)
is aa programming timetime of less than I second. The
ofless The 5-V5-V pro-
gramming circuitry generates the necessarynecessary higherhigher'volt- Step 8 MMode
Step o d e isis m
TIL low;
low; SDI next 88-bit word;
SOIlsis next clock IsisDC\.K,
word; clock DCLK.
volt- Program. Shift
Progrcrn: Shift state
state
ages
ages internally and also shapes waveforms
waveforms so so that the de-
the de- (Shift out 82
(Shift 82 data bits a1d
data bits and 6 address
address bits; observe SDO)
bits:observe SDO)
vice can be programmed through the four-pin interface Step 9 RRepeat
Step steps 4-6
e p e a t steps for each
4-6 for each row
row address
addressof of verification
without high-cost, high-voltage external hardware. hardware.
The four-pin interface con-
trolling programming and and diag-
nostics is compatible w with
ith
Monolithic Memories' JEDEC-
, >OCLK program
standard "diagnostics on chip." SDI c o n t r o l logic M o d e
0
By eliminating multiplexed Internal
Internal connection
from SOl ppin
from SDI in Program
data paths, the interface opti- control signals CK
mizes data propagation. It has
four basic functions: diagnostic Output 0
preload, program shift, pro- logic 22
22
macrocell
gram read, and and program write.
The chip's state machine con- E'CMOS
CCMOS
64
64 by
by 32
32 programmable
programmable : cKJ. J,OE
troIs sequence with infor-
trols the sequence ANOarray
AND array
(ispGAL 16ZS)
tispGAL16Z8)
mation from three of the four • V
signal pins: Serial Data In Os p u t
(SOl)
(SDI) for programming; Mode • E l l o g i c 15
15
macrocell
for loading; and Diagnostic
Clock (DCLK)
(DCLK) for diagnostics.
The fourth
fourth pin, Serial Data Out
Out
(SOO),
(SDO), for data shifting, comes
comes SDI
Shift
into play whenwhen the serial scan Internal
Internal connection register latch S D O
from DCLK input pin
from
data has to be expanded into aa • DCL,K
loop (Fig. 2).
When,the
When the chip receives a 1,
1. The 24-pln ispGA11628
The 24-pin IspGAL16Z8 starts starts with
with an an E 2 CMOS programmable AND array
E2CMOS programmable AND array
Power on Reset signal, the state at Its ccore
at its o r e and
and eight
eight output
output macrocells,
macrocells. Then Then It it adds
adds aa serial
serial diagnostic
diagnostic
machine resets to the normal and programming port
and programming port and
a n d 5-V5-V programming
programming circuitry, circuitry.
6-10
6-10
erate, needing only the output ports of aa standard single-
chip microprocessor and a little support software. A typi-
cal serial scan programming-and-diagnostic
programming-and-diagnostic control loop loop
can take
take on
on a system
system with several
several devices
devices (Fig. 3). In its
normal state,
state, the I16Z8
6Z8 works like a standard PLD, re-
membering the last last update
update to the E'CMOS
E"CMOS logic and
functioning in the system asas programmed. In the diagnos
diagnos and ends
and on the
ends on the next;
next; the
the user
user must
must maintain
maintain the
the correct
correct
tic preload
preload state, the chip latches the macrocells' presen 10-ms programming timing (see
IO-ms programming se-
(see the programming se-
condition and,
and, with DCLK, lets diagnostic test
test informa quence, p.
quence, p. 95).
95).
tion move from SDI to SDO.
tion SDO. SDI is loaded
loaded into the least The chip's
The chip's in-circuit reprogrammability
reprogrammability makes possi-
makes possi-
significant output register
register on
on DCLK's rising edge.
edge. Most ble the design
ble design andand programming
programming of of generic
generic hardware
hardware forfor
significant register
register data is shifted out through SDO. specific applications. Small-volume system
specific system manufactur-
manufactur-
When the chip returns to normal, its outputs resume
resume their ers
ers can
can blend
blend several
several lines
lines of
of hardware
hardware into
intoone,
one, simply
simply by
by
preload state. updating
updating thethe firmware.
firmware. TheThe fast system upgrades
fast system upgrades cancan
even be predesigned
even be predesigned into
into aa system
system and
and enabled
enabled later
later by
by re-
re-
SHIFT, READ, AND WRITE
programming.
programming.
In the program shift state, one row of data data in the
the array
array
ACHIEVING
ACHIEVING flEXIBILITY
FLEXIBILITY
is shifted into SDI, with the appropriate array data data mov-
mov-
ing first, followed by the row address field. To configure a
address field. a On-the-spot reprogramming
On-the-spot reprogramming maintains
maintains the
the integrity
integrity of
of
device completely, each array location must be be filled with 'a'a system's
system's hardware,
hardware, eliminating
eliminating the
the need
need for
for field
field service
service
the appropriate data. Any data already in the serial shift or
or for
for returning
returning thethe chip
chip to
to the
the maker
maker for
for upgrading
upgrading or or re-
re-
register is shifted out through SDO for cascading or for placement. Upgrading can
placement. Upgrading can be done in the
be done the field
field by
by soft-
soft-
verifying aa device. ware
ware delivered electronically or by by mail, whichever
whichever is is
In the program read state, one
one row ofof the
the array
array is
is trans-
trans- more
more convenient.
convenient. Furthermore, the chip chip is
is programmed
programmed
ferred in parallel into the
the serial shift register, whose
whose con- through
through the serial
serial scan
scan path, so that
path, so that system
system diagnostics
diagnostics
tents are transferred out of the selected row, row, in the array.
array. are
are easy
easy toto do,
do, either
either locally
locally ororfrom
from aa remote
remote host
host system.
system.
Returning the chip to the program shift state loads the Repair time
time and costs can
and costs can bebe cut
cut without significant
significant im-
im-
shift register and lets the user verify the device.
device. However, pact on the
pact on the system's
system's cost
cost or complexity.
complexity. Since
Since thethe chip's
chip's
if
if the chip goes to the program write state, the register's serial
serial scan path is
scan path is compatible
compatible with with the
the ports
ports in
in other
other com-
com-
data is programmed to the selected row in the array and and mercial ICs, aa complete
mercial ICs, system, including
complete system, including logic,
logic, can
can use
use
its contents remain unchanged. these
these powerful
powerful andand flexible
flexible diagnostic
diagnostic techniques.
techniques.
In the program write state, one row of the the array isis pro- Two design examples—a
Two design examples-a programmable
programmable two-output,
two-output,
grammed with data from the serial shift register. Pro- 16-bit selection decoder
I 6-bit input selection decoder and and aa programmable
programmable out- Out-
gramming begins on one leading edge edge ofofthe
the DCLK
DCLK signal put port-show
port-show off off the
the 16Z8
I 6Z8 chip's
chip's best
best points.
points. Normally
Normally
Mode
Mode 'l:itiJ \ rr-l k L i 15-1—
SOl
SDI
'tl&l
K : X t Valid
Valid data
::J Valid data __
_______
Va_lid_d_at_a
soo
SDO
st&J SOl SOl
SDI V a \XXXX"-",,-,,-,,,,->--v_a_lid_d_a_ta
l i d data_ _S D I
OCLK
DOM<
H—pulsePgirZ
N
Al
2 +3
--1-+2+ 3a
a ....
·I +
I I·-
3 ---
b --3b-----
I 144
t -4 – 5 6 + 7a +
. 4 4r < -7 - - -
b -7b----j
4 1 0 ms
1 N oNormal
rmal 55 P rProgram:
o g r a m : Write
Write (time-out
(time-out write
write pulse)
pulse)
2 D iDiagnostic:
a g n o s t i c : Preload
Preload 66 P rProgram:
o g r a m : Read
Read
3a
3a P r o g r a m : Shift
Program: Shift 78
7a PProgram:
r o g r a m : Shift
Shift (parallel
(parallel shift
shift register
register loads
loads on
on
3b
3b SShift
h i f t In
in 82
82 data
data and
and 6
6 row
row address
address bits
bits read-ta-shift
read-to-shift transition)
transition)
44 P rProgram:
o g r a m : Read
Read 7b
7b SShift
h i f t in
in 88
88 bits;
bits; verify
verify BB
88 bits
bits
2. During cchip
2. During hip p programming, just four
r o g r a m m i n g , just four lines
lines transfer
transfer all
all data
d a t a and
a n d perform
p e r f o r m diagnostiCS,
d i a g n o s t i c s , ensuring
ensuring that
t h a t bit
bit
patterns
patterns are p r o p e r l y loaded.
a r e properly loaded.
6-11
6-11
aa decoder's circuitry includes such standard
standard logic
logic as ad-
as ad-
Diagnostic
Diagnostic
dress comparators, DIP switches, and pull-up resistors.
dress resistors. controller
controller
The pull-up resistors guarantee noise immunity at the
resistors guarantee Serial Data
Serial Data In
In
comparator when a switch is off.off.

The decoder compares a 16-bit address
address from aa micro-
micro- Single-chip
Mode
Mode 1
SDI
Single-chip 501
microcarnputer
microcd'1nputer
processor with a preset address held in the set of DIP Mode
Mode
switches. Decoding
Decoding the two outputs
oUlputs requires four
four com-
com- ispGal 16Z8
ispGal16ZB
I-- DCLK
DCLK
parators, four octal
octal DIP switches, and octal resistor
and four octal resistor SDO
500
packs. In addition, the circuit needs
needs 104 solder connec-
104 solder connec-
tions and 32 switch contacts, all subject to mechanical
mechanical
SDI
I
501
wear and tear. Mode
Mode
A single
single 16Z8
16Z8 can implement the same decoder. 0 ispGal 16Z8
ispGal16ZB
Switches controlling the address selection functions are
functions are DCLK
DCLK
SDO
500
internal and,
and, in fact, are the product terms
terms in the
the AND
array. A All
l l programming occurs through the four-pin r
serial interface, and
and address
address selection updates
updates are
are handled
handled 501
SDI
through reliable interactive software, rather than

than through '--- Mode
Mode
aa production-line assembler
assembler that uses
uses aa factory-standard
factory-standard Diagnostic Clock
Diagnostic Clock - - -
/ DCLK
DCLK
ispGAL 16ZB
ispGAL 16Z8
DIP-switch programming pencil. Moreover, there are 500

SDO
only 24 solder connections andand no switch contacts, which
substantially improves reliability and calls for a
which
much
a much
Serial control
Serial control loop
loop Serial Data
Serial Out (500)
Data Out (SOO)
1
smaller board area.
area.
3. Through the
3. t h e four-line serial port, several several logic logic
WORKING TOGETHER
WORKING TOGETHER chips can
chips c a n tie t i e into
i n t o one
o n e diagnostic
d i a g n o s t i c controller
c o n t r o l l e r for
for
board-level
b o a r d - l e v e l troubleshooting.
t r o u b l e s h o o t i n g . Preloading
Prel o a d i n g the t h e out-
out-
The
The second application, a reconfigurable output port, put
put registers affords r a p i d tesllng
a ff o r d s rapid testing of o f program-
program-
gives
gives systems wide flexibility andand can
can be
be put together
together eas-
eas- mable
m a b l e devices,
d e v i c e s , since
s i n c e the
the logic-based c i r c u i t can
l o g i c - b a s e d circuit can
ily. In this
this setup, two chips work together,
together, one
one for
for the
the out-
out- be
be made
m a d e to t o start at a t any
a n y desired
desired state.
put data path
path and the other for the,
the. microprocessor
microprocessor bus bus
SOl
SDI 0
and output-port control paths (Fig.(Fig. 4). The data path can can Mode
Mode 0
be configured for registered, combinatorial, or latched
outputs, and
and each
each output bit can be be either
either active
active high or
DCLK
DCLK 0
1
DCLK S501
DCLK D I MMode
ode
1
active low. Other Boolean logic manipulations are are possi-
possi- Data
Data busO
bus 0 Output 0
ble with the logic inin the chip's AND

AND array.
array. , Data bus 77
Data.bus Output
Output 77
ispGAL 16ZB
ispGAL 16Z8
The
The control-path
control-path device handles
handles the other chip's Clock
and Output Enable signals, and its
and its inherent logic
logic can
can im-
plement virtually
virtually any microprocessor or or output
output port
port inter-
inter- OE I--
DE tt.—
A SSDO
A DO
face Interfaces may be synchronous or asyn-
face protocol. Interfaces asyn-
chronous, and each signal set up individually as as a
registered or combinatorial
combinatorial output,
output, active high or active
low. The interface can be programmed through
scan
through the
scan programming interface ICs. Thus aa single interface
the serial
interface
1
DCLK S501
DCLK Mode
DI M ode
1-
•
Ao0 Bus
Bus control
control outputs
outputs
is
is all that is necessary to tie into many different kinds of
22/
peripherals. 0 A,
A,
2
- ispGAL
ispGAL 16ZB
16Z8 / 0
WR
WR • Bus
Bus control
control inputs
inputs
Interrupt •
Interrupt
-
Acknowledge
Acknowledge SDO
SDO
Interrupt
Interrupt 0
State
State Control
Control
Clock
Clock
I S SOo
D O
4. A
4. A programmable
p r o g r a m m a b l e outputo u t p u t port
p o r t can
c a n be
b e readily
readily
formed
f o r m e d using
using two i5pGAL16Z85. The
t w o ispGAl16Z8s. The top
t o p one
o n e sets
sets
up
up the
t h e data
d a t a path,
p a t h , the
t h e bottom
b o t t o m one
o n e handles
h a n d l e s inter-
inter-
face
f a c e control
c o n t r o l and
a n d external
e x t e r n a l handshaking.
handshaking. The The out-
out-
put situation is
put situation is very
very flexible;
flexible; datad a t a can
c a n beb e config-
config-
ured in several
ured in several ways. ways.
6-12
6-12
INTEGRATEDCIRCUITS
INTEGRATED CIRCUfI'S
Multiple factors define

true cost of PLDs
By DEAN SUHR
MIMI,
D
D e s i esigners
Thanks to
g n e r s using
vices) ffor
consideration iin
using PLDs
o r system
traditionally tthink
recent advances
to recent
PLDs (programmable
system design
n tthe
advances iin
(programmable logic
design aand
h e PPLD
logic de-
manufacturing
n d manufacturing
h i n k ooff piece price price as as the
selection process.
L D selection
technology, however,
n technology,
de-
the key
key
process.
however,
Hidden
Hidden cast
To
PLD
also
cost factors
To calculate the system cost of
type, vendor
PLD type, vendor aand
o f using a particular
technology, managers
n d technology,
also take into consideration the additional costs
purchasing overhead, inventory management, proto-
managers mustmust
costs of
of
the system
system cost cost ooff using PLDs is influenced bbyy fac- fac- type
type inventory and quality assurance
assurance (QA).(QA). Purchas-
tors such
such as as fabrication
fabrication technology,technology, device device quality,
quality, ing overhead can add 2 percent to the actual device device
reliability and yield. cost. As tthe
cost. number ooff inventory lline
h e number items rises,
i n e items rises,
System cost is quite different from the sum ooff the the overhead
overhead neededneeded tto purchase those
o purchase those items
items iin-
n-
component costs. costs. TThe h e ppricer i c e ppaid
a i d ffor
o r aa device
device oorr creases. PLDs with generic architectures can mini-
creases. PLDs
component representsrepresents only only one one pparta r t ooff the system
system mize tthe
h e nnumber
u m b e r ooff different devices
devices a companycompany
cost of a PLD; the systems team also has to consider must purchase,
purchase, aand' therefore rreduce
n d therefore purchasing
e d u c e purchasing
the costs
costs hhiddeni d d e n iin n tthe programming, handling,
h e programming, handling, costs.
costs.
quality ccontrol,
o n t r o l , tthroughput
h r o u g h p u t aand overhead tthat's
n d overhead hat's As
As much as as 10 10 percent .of
o f a device's cost can be
necessary to get get aa ""raw"r a w " PLD PLD tto o aa functional
functional statestate attributed tto inventory management
o inventory management overhead,
overhead, iin-n-
on a board. cluding
cluding sshelf space, depreciation,
h e l f space, depreciation, ccO\lnt manage-
o u n t manage-
Because the true system system cost of a PLD is the sum ment, obsolete
obsolete write-offs, and safety stock.
write-offs, and stock. Reduc-
Reduc-
of the piece
piece price and all of o f these hidden costs, and ing inventory line items simplifies the management management
is spread
spread over over several
several functions
functions aand departments,
n d departments, overhead, in turn
overhead, turn cutting costs.
it's often
often ddifficult
i ff i c u l t tto
o define aand measure. In
n d measure. most
I n most
companies, ffor example, purchasing
o r example, purchasing and and engineer-
engineer-
ing ddefine
e f i n e ttheh e ppartsa r t s llist
i s t aand
n d aacquire
c q u i r e tthe parts.
h e parts, BY
BY ELIMINATING YIELD
YIELD AND HANDLING
HANDLING LOSS,
LOSS,
These departments
departments are are often
often under pressure to re- IMPROVING
IMPROVING qlJAI.ITY,
QUALITY, AND
AND SlMPLlF'lJNG
SIMPLIFYING INVENTORY
INVENTORY
absolute uunit
duce absolute cost and tto
n i t cost purchase the least-
o purchase least- MANAGEMENT,
MANAGEMENT, DESIGNERS .CAN THE 1'AUE
CAN CUT THE TRUE
expensive part available. COST
COST OF USING PlDS
PLDS
profitability of
But the profitability o f both the product line and
the company
company is based not on device acquisition cost
but on total system system cost. cost. Buying the least-expensive PLDs
PLDs aarer e pparticularly adaptable tto
a r t i c u l a r l y adaptable just-in-time
o just-in-time
part may not provide the lowest t.otal total system cost. (JIT) inventory
inventory management
management systems, systems, w which
hich m mini-
ini-
mize inventory bpyy increasing
mize inventory increasing throughput. UUsing sing a
JIT system
system constrains
constrains aa company's company's fflexibility
l e x i b i l i t y bbe-
e-
COST A N A LY S I S cause tthe company m
h e company must
u s t ccarrY
a r r y ffewer items. BBut
e w e r items. ut
PA L V S
GAL DEVICES
adding PLDs
PLDs tto o tthe inventory w
h e inventory will
i l l llet
e t tthe
h e same same
narrow range of o f products provide a wide variety of of
functions.
functions.
Macrocell-based PPLDs
Macrocell-based L D s aalso l s o hhave increased tthe
a v e increased he
flexibility
flexibility ofo f c.ompanies
companies that that use
use them
them and and reduced
reduced
stocking
stocking requirements. IIn n the past, designers using
fixed-architecture
fixed-architecture PLDs PLDs had had to keep keep in i n stock
stock every every
lao PLD
PLD architecture required ffor o r a design. Macrocell-
Macrocell-
l 150 based devices; on the other hand,
based devices, hand, can be configured configured
i
i
140
130
to emulate
emulate dozens
The m
logic
dozens ooff oold
new configurati.ons.
The
configurations.
macr.ocell
a c r o c e l l uuS.ed
(GAL) devices
devices goes
s e d iin
goes oone
architectures aand
l d architectures
E'CMOS ggeneric
n E2CMOS
n d many
e n e r i c aarray
step ffurther.
many
rray
These
§
--
120
casr
logic (GAL) n e step u r t h e r. These
110 USING devices also .offer 100 percent socket
devices also o ff e r 100 percent socket compatibility cOl'l):patibility
with oolder programmable aarray
l d e r programmable r r a y llogic
o g i c ((PAL)
PA L ) aar- r-
100
chitectures,
chitectures, so so designers
designers can can simply
simply substitute
substitute the
Programmability can
can play
playaa significant role
roe in the
the otal
total cost
cost of
of PLDs.
PlDs. The
The GAL device ffer
GAL device o r tthe h e ooldld P PLD architecture. N
L D architecture. No o rre-
e-
exampte above was
example above was taken from a system that used 100,000
hat used 100,000 bipolar
bipotar PLOs
PlDs per
per design
design isis necessary.
necessary. Existing Existing JEUEC JEDEC files files andand mas- mas-
Moving to E'
year. Moving E'CMDS GAls can
CMOSGALs cim reduce
reduce total cost by
by up
up to
to 34
34 percent.
percent. ter
ter devices can be be used,
used, reducing system cost.
DECEMBER 1989
DECEMBER 11, 1989 Reprinted
Reprinted with permission from
with permission from PennWell
PennWell Publications.
Publications, COMPUTER QESIGNS/NEWS EDITION
COMPUTER DESIGNS/NEWS EDITION
6-13
6-13
INTEGRATEDCIRCUITS
INTEGRATED CIRCUITS
No longer a simple calculation, the system cost ofof using
using
programmable logic devices
devices is affected by their fabrication
fabrication
technology, testability 'and
and impact on inventory management.
management.
The cost cost ooff the the prototype

prototype inventory inventory also also iinflu-
nflu- vices. These devices
vices. These devices can
can bbee tested
tested w with
i t h one com-com-
ences total system system cost. cost. Although
Although engineering
engineering labs mon test program and then configure in
mon i n many
many waysways
are stocked
stocked wwith devices ffor
i t h devices o r bbuilding
u i l d i n g andand debug-debug- during the programming operation. This step elimi-
during
ging prototypes,
prototypes, many many companies meet meet engineering
engineering nates maintenance of
nates the generation and maintenance o f multiple
lab shortages
shortages bby y bborrowing
o r r o w i n g ffrom manufacturing
r o m manufacturing test programs aand
test programs n d ffixtures,
i x t u r e s , oone
n e for
f o r each
e a c h ffixed
ixed
stock. This
This policy
policy can can shrinkshrink manufacturing inven- architecture.
architecture.
tories and, by doing so, can increase the system cost
.of the remaining
remaining manufacturing units by as much as Analyzing the
Analyzing the system
system cost
cost
percent when
1 percent when uunits n i t s aare ordered tto
r e ordered restock tthe
o restock he Managers can reduce
Managers can reduce these
these overhead
overhead costs costs ttoo a
shelves. formula based on a simple approach that
formula that assumes
assumes aa
All PLDs have
A l l PLDs have aa programmable
programmable element element that de- percentage
percentage ccost
o s t aadder
d d e r aand
n d yyield
i e l d ffactor
a c t o r ffor each
o r each
termines their functionality and ac/dc performance.
These programmable
programmable elements elements ccan a n bbe fabricated
e fabricated
from mmetal-link fuses, pprogrammable
e t a l - l i n k fuses, r o g r a m m a b l e ddiodes i o d e s oorr The
The Factor
transistors, volatilevolatile static static RRAM cells, U
A M cells, UV EPROM
V EPROM of
of Ten
Ten rule
cells oorr EEPROM
EEPROM cells. cells. Each Each ooff these technologiestechnologies
,varies
•varies iin programmability and
n programmability and has has aa diff different
er ent im- It's
It's crucial thatthat managers
managers keep keep in mind the
in mind the cost
cost of of
pact on device performance and reliability. detecting
detecting and repairing defective
and repairing PLDs during
defective PLDs during manufac-
manufac-
Each programmable
programmable element element also also offers
offers a differ- turing
turing — - and
and the the importance
importance of of early
early detection.
detection. A com- com-
ent erase
erase capability.
capability. Metal-link Metal-link aand one-time-pro-
n d one-time-pro- mon guideline for
mon guideline for determining
determining this this cost
cost isis the
the Factor
Factor of of
grammable devices, devices, ffor instance, can't
o r instance, can't bbe erased.
e erased. Ten rule.
Ten rule.
EPROM devices can be erased, but this process
UV EPROM This rule states
This rule states thatthat the
the cost
cost of
of detecting
detecting and and repairing
repairing
requires an expensive windowed package and takes aa defective
defective PLD PLD growsgrows by by aa factor
factor ofof ten
ten atat each
each subse-
subse-
20 tto
o 30 minutes. EEPROM
30 minutes. EEPROM devices devices ooffer f f e r iinstant
nstant quent stage in
quent stage in the
the manufacturing
manufacturing process.
process. This This dramatic
dramatic
erasability iin n as as llittle
i t t l e as as 5050 ms.ms. Technologies
Technologies that growth
growth raterate isis possible
possible because
because other
other symptoms
symptoms mask mask
aren't erasable oorr tthat
aren't erasable have lengthy
h a t have lengthy erase erase times times the PLD's faulty
the PLD's faulty functionality
functionality as as the
the device
device is is buried
buried
constrain test test fflexibility
l e x i b i l i t y aandn d may add tto o the
t h e total
deeper
deeper in in the
the system.
system.
system cost. The Factor of
The Factor of Ten
Ten rule
rule implies
implies that
that thethe earlier
earlier defective
defective
Finally, PPLDs L D s aare usually subjected
r e usually subjected tto o aa com-
com- devioes
devices are are caught,
caught, the
the lower
lower the
the repair
repair cost.
cost. IfIf defects
defects
electrical Q
plete, electrical QA A test test uponupon receipt,
receipt, w which
h i c h typi- aren't found
aren't found early,
early, a very
very small
small yield
yield loss
loss can
can bebe greatly
greatly
cally adds
adds 77 percentpercent.to to the device device cost. cost. TThis addi-
h i s addi-
magnified
magnified by the quantity quantity of devices
devices on on aa board
board or in in a
tional cost
cost is is based
based on on test engineering and manu- system.
system. EvenEven aa yieldyield loss
loss asas small
small as as 0.5
0.5 percent
percent can can
facturing resources,
resources, yyield i e l d aand equipment utiliza-
n d equipment utiliza- result
result inin a 5 percent
percent system
system failure
failure rate
rate with
with only
only five
five
tion. Manufacturers
Manufacturers ccan avoid tthis PLDs
PLDs per system.
system. A loss loss of of 0.5
0.5 percent
percent translates
translates to to aa
a n avoid h i s aadditional
d d i t i o n a l eex-
x- defect
pense wwithout degrading device
i t h o u t degrading device qquality,
u a l i t y, bby using
y using defect rate
rate of
of 5,000
5,000 ppm,
ppm, aa high
high defect
defect rate.
rate.
E'CMOS
E2CMOS devices. These devices are 100 percent pre-
tested by the manufacturer,
manufacturer, and require no incom- operation: Costn=Cost n-1+(Costn_1IYield n). TThis
operation: Costn=Costn_11-(Costn_1/Yieldn). h i s ffor-
or-
ing test. A And n d ttheir
h e i r instant erasability lets IC manu- mula
mula isis· generic, so managers
managers can tailor
t a i l o r the factors
factors
facturers perform extensive tests at the manufactur- to ttheir
to h e i r specific environment and and then
then analyze
analyze the the
ing stage, prior to shipment to end-users. actual
actual system cost of of using
using aa particular
particular PLD. PLD.
Some companies,
companies, however, however, have have extensive
extensive incom- incom- E'CMOS
EzeMOS PLDs offer performance, quality, reliabil-
ing QAQA operations
operations tthat can't be
h a t can't be eliminated.
eliminated. Reus- Reus- ity
able E2CMOS
E'CMOS devices devices are are ideal
ideal for these these operations
operations ity and, most
most important, cost advantages over alter-
cost advantages
native solutions. By
native solutions. By eliminating yield and handling
because they they can be be returned
returned to manufacturing
manufacturing in- loss, improving quality,
loss, improving quality, aand simplifYing inventory
n d simplifying inventory
ventory aafter fter Q QA testing,: instantly
A testing, instantly reprogrammed,
reprogrammed, management, designers can significantly reduce
management, designers reduce the the
and reused
reused iin production boards.
n production boards. TThis h i s fflexibility
lexibility true
also lets
lets QA QA engineers
engineers perform perform ttheir inspection aatt true cost of of using
using PLDs.
h e i r inspection
any step in
any step in the process.
the process. Dean is product
Dean Suhr is product marketing
marketing manager at Lattice
a t Lattice
QA engineers
engineers can can also also ssimplifY
i m p l i f y ttheir testing bbyy
h e i r testing Semiconductor, Hillsboro, OR.
OR.
using generic-architecture, macrocell-based macrocell-based dde- Semiconductor, Hillsboro,
using generic-architecture, e-
COMPUTER DESIGNS/NEWS EDITION

COMPUTER DESIGNS/NEWS EDITION R e p r i nReprinted
t e d with
with permission
permission from
from PennWell
PennWell Publications.
publications. DECEMBER
DECEMBER11,
11, 1989
1989
6-14
6-14
I'
1-1

2-ii
GAL16V8NB
GAL16V8A1B 2-1
2-1
GAL20V8NB
GAL20V8A1B 2-25
2-25
GAL18V10 2-47
2-47
GAL22V10/B 2-61
2-61
GAL26CV12 2-81
2-81
GAL2ORA10
GAL20RA10 2-95
2-95
GAL6001 2-109
2-109
ispGAL16Z8 2-121
2-121

3-1
MIL-STD-883C Flow 3-2
3-2
3-3
GAL16V8A/B
GAL 16V8A1B Military Datasheet 3-5
3-5
GAL20V8A Military Datasheet 3-13
3-13
3-19
GAL2ORA10
3-27

4-1
4
4-3
PCMOS 4-5
4-5
5,: Technical Notes

Section 5:
5-1
55
Latch-up Protection 5-17
5-17

Avoid the Pitfalls of High-Speed Logic Design 6-1
6-1 6
22V100 EPLD
Extending the 22V1 6-7
6-7
In-Circuit Logic Device Can be Reprogrammed onon the Fly 6-9
6-9
6-13
7-1
7-3
7-5
Package Thermal Resistance 7-8
7-8
7-9
7-16
Sales Offices 7-17
7-17
7-i
7-i
7-ii
DeveloplfJent
Development
Tools
Lattice Semiconductor recommends that customers use Lattice's stringent
Lattice's stringent qualification
qualification program
program includes
includes an
only Lattice
Lattice qualified
qualified programming
programming equipment.
equipment. Lattice
Lattice evaluation of
evaluation ofalgorithms,
algorithms, verification
verificationof
oftiming
timing and
andvoltage
voltage
guarantees 100% programming yield to customers
customers using levels, and a complete
levels, complete yield
yield analysis.
analysis.
qualified programming
programming tools.
tools. B Below
e l o w is
is aa matrix
matrix that
that
provides the third-party programmers whichwhich are
are qualified
qualified Foraacurrent
For currentlisting
listingof
ofLattice
Latticequalified
qualifiedGAL
GALprogrammers,
programmers,
to program Lattice GAL devices. please call Lattice's Literature Distribution
please Distribution Department
Department
(Tel: 503-693-0287; FAX:
(Tel: FAX: 503-681-3037)
503-681-3037) and
and request
request aa
Lattice works
works closely
closely with
with third-party
third-party programming
programming GAL Qualified
GAL Qualified Programming
programming Hardware
Hardware List.
List. TThis
his
equipment manufacturers
manufacturers toto ensure
ensure that
that customers
customers document contains
document contains information regarding
regarding programmer
programmer
programming yields
achieve the highest programming yields and
andquality
quality levels.
levels. revision levels,
revision levels, adapters,
adapters, and
and features.
features.
LATTICE QUALIFED PROGRAMMERS (as of May 1991)
Lattice
Lattice GAL
GAL Device
Device Type
Type
Vendor Programmer
16V8A
16V8A 16V8B
16V8B 2OV8A
20V8A 2OV8B
20V8B 18V10
18 V10 22V10
22V10 22V10B
22V1 OB 26CV12
26CV12 20RA10
20RA10 6001
6001
Unisite
•
•
••
•
•
•
III
••
•
•
•
II
•
•
•
III
•IIII
DatalJO
Data I/O
2900
•
•
••
•
IN
•
II
•III
•
III
•
•
•
•
•
III
•II
29B
•
II
•NI
•
•
•
•
••
•
111
•
III
•
III
•
II
•II
60AIH
60NH
•
•
••
•
•
•
•
••
•
•
•
II 01:1
•
•
•II
Logical Devices
Davlces
A1lpro
Alipro 40
•
•
••
•
III
•
•
•n •• •• •• •• ••
PALPR02X
PALPRO 2X
•
•
••
•
•
•
• 00
•
• 00 00 00 00
Stag
System
System 3000
•
•
••
•
•
•
•
•
III
•
•
•
•
•
•
•
•
••
ZL30/A
•
•
••
•
•
•
•
•
•
•
•
•
•
•
•
•
In
•II
TURPR0-1
TURPRO-1
•
II
••
•
III
•
II
•
III
•
•
•
II
•
•
•
III
•II
System Genaral
General SGUP-85A
•
II
••
•
•
•
•
•
•
•
•
•
•
•
•
•
11
••
SGUP-85
•
•
••
•
•
•
•
•
III
•
•
•
•
•
•
•
•
•II
SMS
Mlcrocomputar
Sprint Expert
•
•
••
•
•
•
•
•
III
•
•
•
•
•
II
•
II
•In
Microcomputer
Sprint Plus
•
III
•III
•
III
•
II
•
II
•
•
•
I
•
III
•
In
••
Digelec Model 860

•
•
••
•
•
•
II
•
•
•
•
•
• 00
•
III
•III
BP-Microsystems PLD-1100
BP-Mlcrosystems
•
•
••
•
•
•
•
•
•
•
•
•
• 00
•
III
•II
Prog. Logic Tech. Logic Lab

•
• ••
•
• •
•
•• •• •• •• •• ••
Advln
Advin Pilot-GL
•
III
•III
•
•
•
•
•
a
•
IIII
•
•
•
•
•
•
•In
...
• -- Programmer is qualified, refe
refertto
o the GAL Qualified
Quail led Programming Hardware list
list for
for additional
additional information.
information.
= Programmer was not qualified as of 5191.
LI ..
Q Contact Lattice or programmer vendor
5/91. Contact vendor forfor latest
latest information.
information.
0=
0 = Programmer does not support 28-pin devices.
7-1
7-1
Development Tools
LOGIC COMPILER SUPPORT (as of May 1991)
Lattice GAL Device Type
Vendor Programmer
16VSAlB 2OV8A1B 18V10 22V101B 26CV12 20RA10 6001
AccelTech. TangoPLD
• • • • • • •
Data 110 ABEL
• • • • • • •
ISDATA LOGliC
• • • • • • •
Logical Devices CUPL
• • • • • • •
Mine PLDesigner
• • • • • • •
OreAD OrCADPLD
• • • • • • 0
Omalion Schema-PLD
• • • • • • •
• =Compiler supports GAL device type. Contact vendor or Lattice for the current revision level.
o = Contact vendor for support date.
PROGRAMMER/COMPILER VENDORS
Accel Technologies Dlgltronlcs Israel Ltd. Mlnc Incorporated Stag Mlcrosystems
6825 Flanders Dr. 25 Galgaley Haplada St. 1575 York Rd. Martinfield
San Diego, CA 92121 Herzliya B 46722 Colorado Springs, CO 80918 Welwyn Garden City
Phone: (619) 554-1000 Israel Phone: (719) 590-1155 Hertz. AL715T
FAX: (619) 554-1019 Tel: 052-559615 FAX: (719) 594-4708 United Kingdom
fax: 052-555240 Phone: 011-44-707-332148
Advln Systems Omatlon
In the U.S. contact FAX: 011-44-707-371503
1050-L Duane Ave 801 Presidential
Digelec In the U.S. contact:
Sunnyvale, CA 94086 Richardson, TX 75081
20144 Plummer st. Phone: (214) 231-5167 Stag Microsystems
Phone: (408) 243-7000
Chatsworth, CA 91311 FAX: (214) 783-9072 1600 Wyatt Dr.
Fax: (408) 736-2503
Tel: (818) 701-96n Santa Clara, CA 95054
Fax: (818) 701-5040 DrCAD Systems Corp. Phone: (408) 988-1118
BP Microsystems
3175 N.W. Aloclek Dr. FAX: (408) 988-1232
10681 Haddington
ISDATAGmbH Hillsboro, OR 97124
Suite #190
Haid-und-Neu-StraBe 7 Phone: (503) 690-9881 System General
Houston, TX 77043 FAX: (503) 690-9891
7500 Karlsruhe 1 3FI., No.6, Lane 4
Tel: (713) 461-9430 West Germany Tun Hwa N. Rd.
Fax: (713) 461-7431 Phone: 0721-693092 Programmable Logic Tech P.O. Box: 53-591
SSS: (713) 461-4958 FAX: 0721-174263 P.O. Box 1567
Taipei, Taiwan R.O.C.
In the U.S. contact Longmont, CO 80501
Phone: 886-2-7212613
Data 110 Corp. Tel: (303) 772-9059
ISDATA Inc. FAX: 886-2-7212615
10525 Willows Road N.E. Phone: (408) 373-7359 Fax: (303) 772-5617
In the U.S. contact:
P.O. Box 97046 FAX: (408) 373-3622 System General
Redmond, WA 98073-9746 SMS Micro Systems
244 S. Hillview Dr.
Phone: (206) 881-6444 Logical Devices 1M Morgenthal
Milpitas, CA 95035
FAX: (206) 882-1043 1321 N.W. 65th Place. 0-8994 Hergatz
Phone: (408) 263-6667
In Europe contact: Fort Lauderdale, FL 33309 Scwarzenberg
FAX: (408) 262-9220
Data va Corp. Phone: (305) 974-0967 W.Germany
Phone: +31 (0)20-6622866 FAX: (305) 974-8531 In the U.S. contact:
In Japan contact: Encore Technology Corp.
Data va Corp. 13720 Midway Suite 105
Phone: (03) 432-6991 Dallas, TX 75244
Tel: (214) 233-2614
Fax: (214) 233-3122
7-2
Copying PAL, EPLD & PEEL
Patterns Into GAL Devices
PaffelTJs
INTRODUCTION device can then
device then be programmed
programmed from from thethe programmer
programmer
generic/universal architectures of
The generic/universal of Lattice
Lattice GAL devices memory.
devices memory.
are able
able to
to emulate
emulate a wide
wide variety
variety of PAL,
PAL, EPLD
EPLD and
PEEL devices. GAL GAL devices
devices are direct functional
functional and CROSSCROSS PROGRAMMING:
PROGRAMMING: GAL22V10/GAL20RA10 GAL22V10/GAL2ORA10
parametric replacements
replacements ffor o r most
most PLD PLD device The GAL22V1
device The GAL22V10 andGAL20RA
0 and GAL2ORA10 aredirect
10 are directreplacements
replacements
architectures. ToTo use GAL devices in place of other other PLD for for bipolar
bipolar PAL PAL devices,
devices, and and are are JEDECJEDEC fuse fuse map map
types, some conversion of the original devicedevice pattern
pattern may compatible
compatible with with these
these industry
industry standard
standard devices.devices. TTo o
be needed.
needed. This
This conversion
conversion is notnot difficult, and can be programprogram a GAL22V10GAL22V10 or GAL2ORA10 GAL20RA10 device device from from an an
eitherthe
accomplished at either manufacturing level. existing
the design or manufacturing existing PAL JEDEC JEDEC file, file, simply select the
simply select the appropriate
appropriate
The following
following sections
sections describe
describe several
several techniques
techniques GAL GAL device
device code,code, then then download
download the the PAL
PAL JEDEC
JEDEC file file to
to
convert PAL, EPLD and PEEL device
available to convert patterns the programmer.
device patterns programmer. TThe h e resulting
resulting GAL device is 100%
to Lattice GAL device patterns. The compatible with
The following table lists compatible with the
the original
original PAL.PAL.
PLD devices that can be replaced by by Lattice
Lattice GAL devices.
devices.
GAL devices also
GAL also may may be be programmed
programmed from from Master
Master PAL PAL
CROSS PROGRAMMING: GAL-I6V8 GAL16V8 AND GAL20V8 devices by
devices by reading
reading the the pattern
pattern of of the
the Master
Master PAL PAL into
intothe
the
The GAL16V8
GAL 16V8 and and GAL20V8
GAL20V8 devices
devices replace
replace most programmermemory,
most programmer memory,then thenselecting
selectingthe theappropriate
appropriate GAL GAL
standard 20-pin and 24-pin PAL devices. To To simplify the the device
device code.
code. The The GAL GAL devicedevice can can then
then be be programmed
programmed
conversion process, Lattice has workedworked with
with programmer
programmer from from the programmer memory. memory.
hardware manufacturers to provide the ability to to program
GAL devices directly fromfrom existing PAL JEDEC files, or The The GAL22V10 and and GAL20RA10
GAL2ORA10 also also can
can store
store a User
User
master PAL devices. Lattice Electronic Signature (seethe
Lattice qualified programmers can ElectronicSignature (see thedatasheets
datasheetsonthese on thesedevicesdevices
automatically configure the architecture of a GAL device for for more
more information).
information). To To useuse this
this feature,
feature, thethe JEDEC
JEDEC file file
to emulate the source PAL device. must contain
must contain this this information.
information. To add add thethe signature
signature data data
to the JEDEC map, map, use use the the PALtoGAL
PALtoGAL conversionconversion utility utility
To provide
provide aa conceptual
conceptual framework for the conversion (see (see next section)
section) or recompile
recompile the the source
source equations
equations for for
from PAL
PAL devices
devices to GALGAL devices,
devices, a mythical
mythical device aa Lattice GAL GAL device instead instead of a generic generic 22V10 22 V10 type.
type.
known as a RAL RAL device was created. AA RAL device is Many Many programmers list list two
two device
device types types to to differentiate
differentiate
simply a GAL device configured to emulate a PAL. There between between the two types types of JEDEC JEDEC files, files, and
and list both a
is a one-to-one correspondence between the name of GAL22V10 and
of a GAL22V10 and a name name such such as as GAL22V1OUES
GAL22V10UES or
PAL device
device and
and that .of
of a RAL device. For For example, a GAL22V10ES.
GAL22V1 OES. Other Other programmers
programmers allow allow both
both types
types of of
RAL 16L8 is simply a GAL
RAL16L8 16L8 configured as a PAL
GAL16L8 JEDEC files
16L8. JEDEC
PAL16L8. filestoto be
be accepted, and and simply
simplydon't don'tprogram
programthe the
Some programmers list the RAL device types as choices Signature Signature fuses fuses ifif they
they are are not
not present
present in in the
the file.
file.
for cross-programming,
cross-programming, while while others
others specifically
specifically statestate
that a cross-programming operation is to be performed PAL PALTOGAL CONVERSION UTILITY
TOGAL CONVERSION UTILITY SOFTWARESOFTWARE
using a PAL device type as the architecture type. Lattice
Lattice has
has created
created a softwaresoftware utility
utility that
that will
will convert
convert an an
existing PAL device JEDEC JEDEC file file to
to the
the appropriate
appropriate GAL GAL
To program
program aa GAL16V8
GAL16V8 or GAL20V8
GAL20V8 devicedevice fromfrom an an device JEDEC format. format. Called Called PALtoGAL,
PALtoGAL, this this software
software
existing PAL
PAL JEDEC simply select the appropriate utility
JEDEC file, simply utility can be used to convert PAL device device files files to GAL
to GAL
device code
code (either
(either RAL
RAL type,
type, or PAL
PAL type
type to to cross-
cross- device files,
files, add or orchange
change the the User
User Electronic
Electronic Signature
Signature
program from), then
then download the PAL JEDEC file file to
to the without
withoutchanging
changingdevice devicefunctionality,
functionality, and andreformat
reformatexisting
existing
programmer. Insert
Insert the appropriate GAL device that that can GAL
GAL JEDEC
J EDEC filesfiles forfor readability.
readability.
directly emulate the
the PAL device (according to the the chart
chart on
on
the following page). The The programmer will automatically Since Since a few few programmable
programmable logiC logic devices
devices have have features
features
configure the
the GAL
GAL device
device toto emulate
emulate thethe PAL
PAL device
device that
that a GAL device device cannot
cannot exactly
exactly emulate,
emulate, the the PALtoGAL
PALtoGAL
during programming. The The resulting GAL device is is 100% utility
utility will
will clearly
clearly describe the the incompatibility
incompatibility but but will
will not
not
compatible with the original PAL device. create
create an output file. file. GAL GAL devices
devices programmed
programmed using using
files converted by PALtoGAL will be 100% compatible compatible
A GAL device may also be programmed from from a master with the the original
original logic
logic device. PALtoGAL is
device. PALtoGAL is just
just another
another
PAL device by reading the pattem
pattern of the
the master PAL PAL into method
method of cross-programming,
cross-programming, and and shoulcJ
should produce
produce the the
the programmer memory, then selecting the appropriate same same results as as using a programmer.
programmer. The The advantage
advantage is is
RAL device or or PAL
PAL type to cross-program from. from. The GAL GAL that
that a full GAL device device JEDEC JEDEC map map is is created,
created, meaning
meaning
7-3
copying PAL
COpying PAL. Patterns
Into GAL Devices
then be
that the appropriate GAL device may then be selected on
on SOFTWARE COMPILER
SOFTWARE COMPILER CONVERSION
CONVERSION
the programmer, which
which may simplify the
the manufacturing IfIf the
the equation
equation source
source file
file is
is available
available for
forthe
the PAL
PAL device,
device,
flow. itit can
can be
be converted
converted by by re-compiling
re-compiling using
using aa suitable
suitable logic
logic
compiler that supports
compiler supports GAL devices.
devices. IIff there
there are
are any
of the P
A copy ofthe PALtoGAL conversion utility
ALtoGAL conversion utility software
software can
canbe
be deviceincompatibilities
device incompatibilities(there
(thereshouldn't
shouldn'tbe beininmost
mostcases),
cases),
obtained through youryour local Lattice representative, or by by the compiler
the compiler will
will describe
describe thethe errors.
errors. The output of
The output of the
the
contacting the
the GAL
GAL Applications
Applications Hotline
Hotline at at 1-800-
1-800- compiler will
compiler will be
be a GAL
GAL JEDEC
JEDEC file file that
that can
can bebe used
used to to
FASTGAL (327-8425) or (503) 693-0201. The The software
software program aa GAL
program GAL device
device directly.
directly. The
The resulting
resulting GAL
GALdevice
device
also may be downloaded from Lattice's Electronic Bulletin
alsomaybedownloadedfromLattice'sElectronicBulletin will be 100%
will 100% functionally compatible with
functionally compatible with the
the original
original
Board aat t ( 5(503)
0 3 ) 693-0215;
693-0215; t theh e f file
i l e nname
a m e iis
s device.
device.
"PALTOGALEXE".
·PAL TOGAL.EXE".
Suitable logic compilers
Suitable compilers areare listed in the
the Development
Development
Tools section.
Tools section. If additional
additional questions
questions arise,
arise, contact
contact your
your
compiler manufacturer
compiler manufactureror or aaLattice
Lattice Applications
Applications Engineer
Engineer
bycalling
by callingthe
theGAL
GALApplications
ApplicationsHotline
Hotlineat
at1-800-FASTGAL
1-800-FASTGAL
or (503)
or (503) 693-0201.
693-0201.
COPYING PAL,
PAL, EPLD AND PEEL PATTERNS INTO GAL DEVICES
GAL1&Y8AIB GAl1&V8AIB
GALA6V8A/8
GAl.2GV8AIB
GA1.20,188./8 GAL2OV8AIB
GAL20V8A/B
GAll8Vl0
GA118%110 GAl18Vl0
GAL:18t/10
GAL22Y10IB
GAL221/10/13 GAL22V101B
GAL.22V10/8
GAL26CV12
GA1.280/12 GAL26CVI2
GAL26CV12
/ A / GAL2ORA10
GAL2ORA10 / / GAL20RA10
GAL2ORAIO
PAll0H8
PAL10H8
•• • i ED
a PAlI8P8
PA1.18P8 00 e
•••••
PAllOl8
PALI 01.8 ED PAL18U8
PAL181_18 0 e
PAll0P8
PALIOP8
PAlI2H6
PA1.12H6
CD
CD
PAl.2OH2
PAL20H2
PAl2OH8
PA1.20H8
••• e
e
PAl12L6
PA1.121..6
PAlI2P6
PALI2P6
•••
• Ci)
0
G
0
PAL2Ol2
PAL212
PAL2OL8
PAL201.8
•••••
• e
e
PAl14H4
PAU 4H4
•• • CD PAL20P8
PAL20P8 e
•• ••• ••••
PAlI4H8
PALI 4H8 Ell PAl2OR4
PAI.20R4 e
PAl14L4
PALICA CD PAl2OR6
PAL20R6 e
PAlI4L6
PAL141.8
PAlI4P4
PAL14P4
•• • 00
Ell PAl2OR8
PAL20R8
PAl2ORP4
PAL2ORP4
••• 0
e
PAL14P8
PAL14P8
PALI6H2
PALI 6H2
•• •••CD
0 PAl2ORP6
PAL2ORP6
PAL2ORP8
PAL2ORP8
•••• e
0
PALI6H6
PAL16H6 Ell PAL20RA10
PAL2ORAIO
••
PALI6H8
PAL16H8
•• 0 PAL22Vl0
PAL2211i0
••
PAlI6L2
PAU 6L2
PALI616
PAL161.6
• •• 0
Ell
PALCE16V8
PALCEI6V8
PALCE20V8
PALCE201/8
•• •• e
0
PAlI6L8
PALI 61.8
••• CD PALCE22Vl0
PALCE22V10
••
PAlI6P2
PA1.16P2
PAlI6P6
PAL16P6
• •• ED
Ell
PAlCE2&V12
PALCE26V12
PEELI8CV8
PEEL18CV8 0 0
0
PAlI6P8
PAL16P8
••• e
CD EP320
EP320 0 e
, PAlI6R4
PALI6R4
•• (9 85C220
85C220 0 e
••••
PALI6R6
PALI6R6 t9 85C224
135C224 0 e
PAlI6R8
PAL16R8 t9 GALI6V8AIB
GA1.16V8A/B e
PAl16RP4
PALISRP4
PAlI6RP6
PALI6RP6
••• t9
CD
GAL20V8AIB
GA1.20V8NE e
PAlI6RP8
PAII6RP8
•• •
G •• Direct
Direct Replacement.
Replacement,with
withCross
CrossProgralMing
ProgrammingAvailable.
Availlable.
•••• ••
PAllSH4
PAL.18114 Q) (!) Direct Replacemem.
0 Direct no Cross
Replacement, no Cross ProgralMing
ProgramningAvailiable.
PAlI8L4
PALMA o0 Direct Replacement,wtth
Direct Replacement. withsame
someFunction
FunctionRestrictions.
Restrictions.
PAl18P4
PALI8P4
7-4
7-4
GAL Product Line
GAL Line
Reference
Cross Reference
MANUFACTURER PART # LATTICE PART ## MANUFACTURER PART ##
MANUFACTURER PART PART##
LATTICE PART
LATTICE
ALTERA EP310 GAL16V8A/B1

GAl16V8A1B' AMD
AMD AmPAL2ORP10
AmPAl20RP10 GAL22V10/B
GAL22V10/8
EP320 or...
or... GAL18V10
GAl18V1 0
EP330 PAL20S10
PAl20S10 GAL22V10/B
GAl22V10/8
PAL2ORS4
PAl20RS4
AMD PALI OH8
PAl10H8 GALI 6V8A/B
GAl16V8A1B PAL2ORS8
PAl20RS8
PALI OL8
PAl10l8 PAL2ORS10
PAl20RS10
PALI 2H6
PAl12H6
PALI 2L6
PAl12l6 AmPAL201_10
AmPAl20L10 GAL22V10/131
GAl22V10/B'
PAULO-14
PAl14H4 PAL20L10
PAL20L10
PAL141_4
PAl14l4 PAL20X4
PA!-20X4
PAL16H2
PAl16H2 PAL20X8
PAl20X8
PAl16l2
PAL16L2 PAL20X10
PAL20X10
PALI 6L8
PAl16l8 GAL16V8A/B
GAl16V8AIB AmPAL22V10
AmPAL22V10 GAL22V10/13
GAl22V10/8
PALI 61=14
PAl16R4 PAl22V10
PAL22V10
PALI 6R6
PAl16R6 PAlC22V10
PALC22V10
PALI 61:38
PAl16R8 PAlCE22V10
PALCE22V10
PAlC16l8
PALC16L8
PALM 6R4
PAlC16R4 PAlCE24V10
PALCE24V10 GAL26CV121
GAl26CV12'
PAlC16R6
PALC16R6 PALCE26V12
PAlCE26V12
PAlC16R8
PALC16R8
AmPAl16L8
AmPAL16L8 ATMEL
ATMEL AT22V10
AT22V10 GAl22V10/8
GAL22V10/B
AmPAl16R4
AmPAL16R4
AmPAl16R6
AmPAL16R6 CYPRESS
CYPRESS PALC16L8
PALM 6L8 GAL16V8AIB
GAL.16V8A/B
AmPAl16R8
AmPAL16R8 PALC16R4
PALCI 6E14
PAl16P8
PAL16P8 PALC16R6
PALM 6R6
PAl16RP4
PAL161RP4 PALC16R8
PALC16R8
PAl16RP6
PAL16RP6
PAl16RP8
PALI 6RP8 PLDC18G8
PLDC18G8 GAL 16V8A1B'
GAL16V8A/B1
or... GAl18V1
or... GAL18V100
PAlCE16V8
PALCE16V8 GAl16V8AIB
GAL16V8NB
PALC20CG10
PALC2OCG10 GAl20V8A1B'
GAL20V8A/B1
AmPAl18P8
AmPAL18P8 GAl16V8A1B'
GAL16V8NBI PALC22V10
PALC22V10 or... GAL22V10/13
or... GAL22V10/8
PAlC18U8
PALC18U8 or... GAL18V10
or... GAl18V1 0 PAl22V10
PAL22V10
PAl14l8
PALI 41_8 GAL20V8AIB
GAL20V8A/B PlD20RA10
PLD2ORA10 GAl20RA10
GAL2ORA10
PAl16l6
PAL16L6
PAl18l4
PAL18L4 HARRIS
HARRIS HPl16LC8
HPLI 6LC8 GAl16V8AIB
GAL16V8A/B
PAl20l2
PAL20L2 HPl16RC4
HPL16RC4
HPl16RC6
HPL16RC6
PAl20L8
PAL20L8 GAl20V8AIB
GAL20V8A/B HPL16RC8
HPL16RC8
PAL20R4
PAl20R6
PAL20R6 ICT
Id T PEEL18CV8
PEEL18CV8 GAL
GALI16V8A1B'
6V8A/Bt
PAL20R8 or... GAl18V1
or... GAL18V10 0
AmPAL20RP4
AmPAL2ORP4
AmPAL20RP6
AmPAL2ORP6 PEEl153
PEEL153 GAl16V8A18'
GAL16V8A/B'
AmPAL20RP8
AmPAL2ORP8 PEEL253
PEEL253 or... GAl18V1
or... 0'
GAL18V10'
PALCE20V8 GAL20V8A1B
GAL20V8A/B PEEL20CG10
PEEL200G10 GAl20V8A18'
GAL20V8A/BI
PEEL22CV10A
PEEL22CV1 OA or... GAl22V10/8
or... GAL22V10/B
PAl20RA10
PAL2ORA10 GAL20RA10
GAL2ORA10
1) Possible
Possible conversion but not 100% compatible to this device.
device.
7-5
GAL Product Une
GAL Line
Cross Reference
Cmss
MANUFACTURER PART ## LATTICE PART
LArnCE PART ## MANUFACTURER PART
MANUFACTURER PART ## LArnCE PART##
LATTICE PART
INTEL 5CO31
5C031 GAD 6V8A/B1
GAL16VSAIB' RICOH
RICOH ERA 0P8
EPL10PS GAL16V8A/B
GAL16VSAIB
5CO32
5C032 or...
or... GAL18V10
GAL 1SV1 0 EPL.12P6
EPL12P6
850220
S5C220 ERA L1P4
EPL14P4
EPL16P2
EPL16P2
850224
S5C224 GAL20V8A/B1
GAL20VSAlB'
or...
or... GAL22V10/B
GAL22V101B EPL16P8
EPL16PS GAL16V8A/B
GAL16VSAlB
EPL16RP4
EPL16RP4
NATIONAL PAL
PALI10HS
OH8 GAL16VSAIB
GAL16V8A/B ERA 6RP6
EPL16RP6
EPL16RPS
El:1_1611PB
PAL10LS
PAD 01.8 GAL16VSAIB
GAL16V8A/B
PAL12H6
PALI 2H6 SAMSUNG
SAMSUNG CPL16LS
CP1_161I3 GAL16VSAlB
GAD 6V8A/B
PAL12L6
PAD 21_6 CPL16R4
CPL161R4
PAL14H4
PAD ithizt CPL16R6
CPL16R6
PAL14L4
PALI 41.J1 CPL16RS
CPL16R8
PAL16H2
PALI 6H2
PAL16L2
PAU 61.2 CPL20LS
CPL20L8 GAL20VSAIB
GAL.20V8A/B
CPL20R4
CPL.201:14
PAL16LS
PAL16L8 GAL16VSAIB
GAL16V8A/B CPL20R6
CPL.20R6
PAL16R4
PAL.161:14 CPL20RS
CPL20IR8
PAL16R6
PALI 6R6
PAL16RS
PAL16R8 CPL22V10
CPL22V10 GAL22V10/B
GAL22V10/B
GAL16VS
GAL16V8 GAL16VSAlB
GALA 6V8A/B SG5- THOMSON GAL16VS
SGS-THOMSON GAL16V8 GAL16VSAIB
GAO 6V8A/B
GAL16VSA
GAL16V8A
GAL20VS
GAL20V8 GAL20VSAlB
GAL20V8NB
GAL1SV10
GAL.18V10 GAL1SV10
GAL18V10
GAL39V1S
GAL39V18 GAL6001
GAL6001
PAL14LS
PALA 4_8 GAL20VSAIB
GAL20V8A/B
PAL16L6
PAU 61.6 GAL16ZS
GAO 6Z8 ispGAL16ZS
ispGAL16Z8
PAL1SL4
PALI 81_4
PAL20L2
PAL20L2 SIGNETICS
SIGNETICS PLHS16LS
PLFIS16L8 GAL16VSAIB
GAL.16V8A/B
PLUS16Ls
PLUS16L8
PAL20LS
PAL201.13 GAL20VSAIB
GAL.20V8A/B PLUS16R4
PLUS161R4
PAL20PS
PAL20P8 PLUS16R6
PLUS161R6
pAL20R4
PAL201=14 PLUS16RS
PLUS16R8
PAL20RP4
PAL2ORP4
PAL20R6
PAL.20R6 PLHS1SPS
PLHS18P8 GAL 16VSAlB'
GAL16V8A/131
PAL20RP6
PAL2ORP6 or... GAL1SV1
or... GAL18V100
PAL20RS
PAL.20R8
PAL20RPS
PAL2ORP8 PLS153
PLS153 GAL 16VSAlB'
GAL.16V8A/B1
PHD16NS
PHD16N8 or... GALlSV10'
or... GALI8V101
PAL20RA10
PAL2ORA10 GAL20RA10
GAL2ORA10
PLUS20LS
PLUS20L8 GAL20VSAIB
GAL20V8A/B
PAL20L10
PAL201_10 GAL22V101B'
GAL22V10/131 PLUS20R4
PLUS20R4
PAL20X4·
PAL20X4 PLUS20R6
PLUS201R6
PAL20XS
PAL20X8 PLUS20RS
PLUS201R8
PAL20X10
SPRAGUE
SPRAGUE SPL14LCS
SPL141...C8 GAL16VSAlB
GAL16V8A/B
GAL22V10 GAL22V101B
GAL22V10/B SPL16LCS
SPL16LC8
SPL16RC4
SPL16FIC4
GAL26CV12 GAL26CV12 SPL16RC6
SRA 6IRC6
SPL16RCS
SRA 6RC8
GAL6001 GAL6001
GAL6001
1) Possible
7-6
7-6
GAL Product
GAL Product Une
Line
Cross Reference
Cross Reference
MANUFACTURER PART ## LATTICE PART ##
SPRAGUE SRA 81_C4

SPL18LC4 GAL20V8AIB
GAL20V8A/B
SPL2OLC2
SPL20LC2
SPL2OLC8
SPL20LC8 GAL20V8A/B
GAL20V8A1B
SPL20RC4
SPL2ORC4
SPL20RC6
SPL2ORC6
SPL20RC8
SPL2ORC8
n
TI TIBPAL16L8 GAL16V8A/B
GAL16V8A1B
TIBPAL16R4
TIBPAL16R6
-IMPALA 6R6
TIBPAL16R8
TICPAL16L8
TICPAL161_8 GAL16V8A1B
GAL16V8A/B
TICPAL1.6R4
TICPAL.16114 GAL16V8A1B
GAL16V8A/B
TICPAL16R6
TICPAL16R8
TICPALI 6R8
EP330 GAL16V8A1B'
GAL16V8A/B1
TIBPAD16N8 or... GAL18V101
or... GAL18V1 0'
TIBPAL20L8 GAL20V8A1B
GAL.20V8A/B
TIBPAL20R4
TIBPAL2OR4
TIBPAL20R6
TIBPAL20R8
TIBPAL22V10 GAL22V10!B
GAL22V10/6
TICPAL22V10
1) Possible
7-7
Thermal
Package Thel,nal
Resistance
on the
The following table provides information on the package mounted on a thermal
mounted thermal test board conforming to SEMI
conforming to SEMI
thermal resistance of Lattice commercial and industrial SPECIFICATION G42-88:
SPECIFICATION G42-88: "Thermal
"Thermal Te s t Board
Test Board
grade devices. For the package
For information on the package thermal Standardization for Measuring
Standardization Measuring Junction-to-Ambient
Junction-to-Ambient
resistance of Lattice military please refer
military grade devices, please refer Thermal Resistance
Thermal Resistance of
of Semiconductor
Semiconductor Packages".
Packages".
to "MIL-M-38510, Appendix C". Co.
Test Conditions
Test Conditions
was performed
Testing was performed per SEMI TEST METHOD
METHOD G38- Power Dissipation
Power Dissipation == 0.5watts (IC
(IC chip
chip reverse
reverse biased)
biased)
87: "Still
"Still and
and Forced-Air
Forced-Air Junction-to-Ambient
Junction-to-Ambient Thermal
Thermal Velocity =
Ambient Air Velocity
Ambient = Zero
Zero (still
(still air)
air)
Packages" with
Resistance Measurements of IC Packages· with devices Temperature =65°C
Ambient Temperature
Ambient 65°C
Measuring Current =
Measuring Current = 3mA
3mA
PACKAGE THERMAL RESISTANCE
Commercial/Industrial Grade Devices

Package Type: Device Type: eJA
°JA ex
°JC
20-Pin Plastic DIP GAL16V8NB

GAL16V8A1B 59cO/W
59°C/W 39°C/W
39°C/W
GAL18V10
24-Pin Plastic DIP GAL20V8NB

GAL20V8A1B 57°C/W
57°C/W 36°C/W
36°CIW
GAL22V10/13
GAL22V10/B
GAL2ORA10
GAL20RA10
GAL6001
ispGAL16Z8
28-Pin Plastic DIP GAL26CV12 55°C/W

55°CIW 33°C/W
33°CIW
20-Pin Plastic LCC GAL16V8NB

GAL16V8A1B 46°CIW
46°C/W 32°CIW
32°C/W
GAL18V10
GAL18V10
28-Pin Plastic LCC GAL20V8NB

GAL20V8A1B 45°CIW
45°C/W 29°CIW
29°C/W
GAL22V10/B
GAL22V101B
GAL2ORA10
GAL20RA10
GAL26CV12
GAL26CV12
GAL6001
7-8
7-8
Package Diagrams
Diagrams
20-Pin Plastic
plastic DIP
in Inches MIN.
Dimensions In MIN. I/ MAX.
(:::::::: :I=r .309/325
E
.2A0 / 165
1.040 MAX
I' .-- -I
0091.015
.000 .010
\-
0-11"
200 MAX . 0 1 5 HIM
I:
r- --i r- :::
.120 PAN t
ii
1 .055 I/ .0lI0
.055
•••••••••110
.000 . 0 9 0 / .0lI0
. 1 I1.110
0
•••••••••••.- • - • • • 41,-- .055 /.065
4 o - - .015 /.022
24-pin plastic DIP

24-Pin Plastic
Dimensions
Dimensions In
in Inches MIN.
MIN. I/ MAX.
• 11111 M I N I •
.300 1.325
.240 / .290
MI U M 11 0
1.270 MAX
1.270 MAX
.009 / .015
.0081.016
2 0 0 MAX
r-
.120 MIN . 0 1 5 MIN
• • • • • • • ••••••.••••
1 . . 0 :51.022
5/
.oSS
A N /I A
.090
N 2 9 0 / ..090
1 1I .110
0
7-9
7-9
Package Diagrams
28-Pin Plastic
plastic DIP
Dimensions In Inches MIN.
Dimensions MIN. I/ MAX.
MAX.
270 /.290 .300 I .325
1.355 MAX
1.355 MAX
a
-II- \-
.009 1.015
.009/.015 0 - 1 5 0·15"
*
.200 MAX .015 MIN
.015 MIN
.120 MIN
.01111-••••• * * * - - .045 /.055

•.•-••••••••, .015 /.022
/ .030
.020 1.030 . 0 9 .090/.110
0 1.110
7-10
7-10
Package Diagrams
Package Diagrams
20-Pin PLCC Package

20-Pio Package
Dimensions In
Dimensions in Inches
Inches MIN.
MIN. I/ MAX.
MAX.
- • • • • • - o - - .042 / .048 X
.Il42 /.048 X 445°
5' .042 / .056 X 4 5 "
l o o - - .048 / .052
.042
.042 /.048 X 45"
/ .048 X 45°
.G13 / .1121
.385/ .385 Top View

.280 /.330
til
·-n
•••••• -*1— .025 M N
I r=
.090 / .120
....
.165 . 1 8 0 ••••-••••
28-Pio
28-Pin PLCC package
Package
Dimensions In
in Inches MIN. I/ MAX
inches MIN. MAX..
••••••••• - 0 - - .042 / .048 X 4 5 ' .042 / .056 X 4 5 "
.048 / .052
•.042
042 // .048 X 445°
.048 X 5" .013/.021
.390/ A30
I - - - - - - _,_ I - 4 - - .025 M N
.0— .090/.120
.090 / .120
ASS/ADS
.165/.180
.165 /.180 —••••• -4--
7-11
7-11
Package Diagrams
20-Pin (300 MIL) CERDIP

Dimensions in
Dimensions in Inches
Inches MIN.
MIN. I/ MAX.
MAX.
1-..--.005 MIN
250 /.310
w .203 / .320
fl
1.080 MAX
.0OB/.015 0.15"
.015 / .010
1.150 MIN
.080
.080 MAX .080/.110
.090 / .110
7-12
7-12
Package Diagrams
Package
24-Pin (300 MIL) CEBDIP

24-pin CERDIP
Dimension.
Dimensions In
in Inche.
inches MIN.
MIN. I/ MAX.
MAX.
.220 / .310
1.*--.005 MIN
1.280 MAX 3"
/ F 2 1 \ 1
.008 / .016
'-/.1115 ..." •
.015 / .070
I 1111 M O E l _ r • • •
150 MN
•••••••••• .038 / .066

• • , , , § 1 • • - .014 1.0Z3
.098 MAX
.GIll '-1.110
_000 / .110
7-13
7-13
Package Diagrams
20-Pin LCC
20-Pin
Dimensions
Dimensions in
In Inches MlN.t/ MAX
inches MIN. MAX.•
..030
030 I/ .050 X
X 45* 4101
45· (t, 0")
.005 / .030 X
.00sl.030 X 45* (510)
4S· (t,O")
Pin / I
.020 / .030
.0SOlYP.
.050 TYP.
.345 / .360
•••••••-••••• .0671 .063
1
1
.345 I .360
1
1
1
f..-..I.0581.072
058/ .072
7-14
Package Diagrams
Package Diagrams
28-Pin LCC
Dimensions In
Dimensions In Inches
Inches MIN.
MIN. I/ MAX
MAX.•
•.035
l
0351/ .045 X
X 45*
45° ((±
.•••••••••
± 0.5°) P i n #1
.077 / .093 .015 / .025 X 45* ( ± 0.5°)

.........
1 X 45° (± 0.5°)
TYP.
.050 TYP.
BoltomVI_
.075 TYP. .025 TYP.
.050TYP.
.050 TYP.
H .063 / .077
.0631.077
Top View
.44
.44 1.458
/ .458
1--/.0541
1-•—•1 .054/ .066
.066
7-15
Reel
Tape and Reel
Specifications
A tape-and-reel packing container is available for for plastic
plastic the pockets. AA full reel
the reel holds
holds a maximum quantity of
maximum quantity of
leaded chip carriers
carriersto
toprotect
protectthe
theproduct
productfrom
frommechanicaV
mechanical/ devices depending
devices dependingon onthe
the package
package size.
size. Lattice requires
Lattice requires
electrical damage and to provide an an efficient method for ordering in full
ordering full reel
reel quantities.
quantities. Once
Once loaded, the tape
loaded, the tape is
is
handling. Lattice's
Lattice's tape-and-reel containers are
are shipped wound onto
wound onto a plastic
plastic reel
reel for
for labeling
labeling and
and packing.
packing.
in full
full compliance
compliance to Electronics
Electronics Industry
Industry Association
Association
Standard EIA-RS481. Devices packaged
Devices packaged in tape-and-reel
tape-and-reel containers
containers must
must bebe
factory programmed
factory programmed (pre-pattemed).
(pre-patterned). Custom markingof
Custom marking of
tape-and-reel packing system consists
The tape-and-reel consists of
of a pocketed devices prior to
pocketed devices to mounting
mounting on on tape-and-reel
tape-and-reel is available
available
carrier tape loaded with
carriertape with one
onedevice
device per
perpocket.
pocket. Aprotective upon request.
A protective upon request. Contact your local
Contact your local Lattice
Lattice sales
sales office
office for
for
tape and holds the
cover tape seals the carrier tape the devices
devices in
in more
more details
details on
on Lattice's
Lattice's tape-and
tape-and reel
reel packing
packing system.
system.
TAPE-AND-REEL QUANTITIES
TAPE·AND-REEL QUANTITIES AND DIMENSIONS
AND DIMENSIONS
Package Pin Count Carrier Tape

Carrier Tape Dimensions
Dimensions Quantity Per
Quantity Per
Width P i t cPitch
Width h 13 Inch
13 inch Reel
Reel
PLCC 20-pin 16mm 1 2 m12mm
16mm m 1000
1000
28-pin 24mm 1 6 m16mm
24mm m 750
750
7-16
7-16
Sales Offices
DIRECT SALES OFFICES
FRANCE NORTH AMERICA
tlQBltf MASSACHUSETTS OP-WI!
QBEGQtI
Lattice Semiconductor Lattice Semiconductor
Les Bureaux de Sevres QALLE2BNIA
QLlFOBNIA 67 S.
67 S. Bedford St.
Bedford St. 5555 N.E.
5555 N.E. Moore
Moore Ct.
Ct.
72-78, Grand
Grand Rue Lattice Semiconductor Suite 400 West
Suite West Hillsboro, OR
Hillsboro, OR 97124
97124
92310 Sevres 1731 Technology Dr.
1731 Dr. Burlington, MA 01803
Burlington, 01803 TEL: ( 5(503)
TEL: 0 3 ) 780-6771
780-6771
France Suite 590 TEL: ( 6(617)
TEL: 1 7 ) 229-5819
229-5819 FAX: (503)
FAX: 681-3037
(503) 681-3037
TEL: 1 -1-45
4 5 34 10 10
341010 San Jose, CA 95110 FAX: (617)
FAX: 272-3213
(617) 272-3213
FAX: 1 1-462671
- 4 6 26 71 36
36 TEL: ( 4(408)
0 8 ) 441-0196 mA!Z
TEXAS
FAX: (408)
(408) 441-0739 MINNESOTA
MltltlEIZCITA Lattice Semiconductor
GERMANY Lattice Semiconductor
Lattice Semiconductor 100 Decker
100 Decker Ct.Ct. Ste.
Ste. 280
280
Lattice 13664 Hannibal Circle
13664 Circle Irving, TX
Irving, TX 75062
75062
Stahlgruberring 1212 Carlsbad Pacific Ctr. One Apple Valley,
Apple Valley, MN
MN 55124
55124 TEL: ( 2(214)
TEL: 1 4 ) 650-1236
650-1236
8000 Munich 82 701 Palomar
701 Rd.
Palomar Airport Rd. TEL: ( 6(612)
TEL: 1 2 ) 891-5200
891-5200 FAX: (214)
FAX: 650-1237
(214) 650-1237
West Germany 3rd Floor FAX: (612)
FAX: 891-5205
(612) 891-5205
TEL: ( 0(089)
8 9 ) 42 01 107
107 Carlsbad, CA 92009
FAX: (089)
(089) 422 731 TEL: ( 6(619)
1 9 ) 931-4751
931-4751 NEW JERIZEX
tlEW JERSEY
FAX: (619)
(619) 431-1821
431-1821 Lattice Semiconductor
JAPAN 175-3C Fairfield Rd.
175-3C Rd.
Lattice Semiconductor gagiglA
GEQBGlA West Caldwell, NJ
West Caldwell, NJ 07006
07006
Peony Kikuchi 201 Lattice Semiconductor TEL: ( 2(201)
TEL: 0 1 ) 744-5908
744-5908
1-8-4, Botan 3105 Medlock Bridge Rd.
Rd. (201) 509-9309
FAX: (201)
FAX: 509-9309
Koto-ku, Tokyo Norcross, GA 30071
Japan 135 TEL: ( 4(404)
0 4 ) 446-2930
03-642-0621
TEL: 03-642-0621 (404) 416-7404
FAX: (404)
FAX: 03-642-0629
03-642-0629
NORTH AMERICAN SALES REPRESENTATIVES

ALABAMA Earle Associates USBOA
GEQBGlA MA..S3A2100131
The Novus Group 7585 Ronson Rd.
Rd. #200 The
The Novus Group Comp
Comp Rep
Rep Associates
Associates
2905 Westcorp Blvd. #120 San Diego, CA 92111
92111 6115A
6115A Oakbrook Pkwy.
Pkwy. 100
100 Everett
Everett Street
Street
Huntsville, AL 35805 (619) 278-5441 Norcross,
Norcross, GA 30093
GA 30093 Westwood,
Westwood, MA MA 02090
02090
(205) 534-0044 (404)
(404) 263-0320 (617)
(617) 329-3454
329-3454
c()LQBADQ
COLORADO
ARIZQNA
ARIZONA Waugaman
Waugaman Associates iLLINOIS
IlLltlQl1Z MICHIGAN
MICl::IlGAti
Summit Sales 4800 Van
Van Gordon Omni
Omni Electronics
Electronics Greiner
Greiner && Associates
Associates
7802 E. Gray Rd. #600 Wheat Ridge, CO 80033 328
328 E. Main 15324
15324 E.
E. Jefferson
Jefferson Ave.
Ave.
Scottsdale, AZ 85260 (303) 423-1020 Barrington, 60010
Barrington, IL 60010 Grosse
Grosse Pointe
Pointe Park,
Park, MI
MI
(602) 998-4850 (708)
(708) 381-9087 48230
48230
CONNECTICUT (313)
(313) 499-0188
499-0188
QLlEQBNIA
CALIFORNIA Comp Rep
Rep Associates KANSAS
KAtllZAlZ
Bager
Gager Electronics 117
117 Church
Church St. Stan
Stan Clothier Company
Company MINNESOTA
MltltlElZQIA.
17220 Newhope St. #209
#209 Yalesville, CT 06492 805
805 Clairborne
Clairborne Stan
Stan Clothier
Clothier Company
Company
Fountain Valley, CA 92708 (203)
(203) 269-1145 Olathe,
Olathe, Kansas 66062
66062 10000
10000 W.
W. 76th
76th St
St #0
#D
(714) 957-3367 (913)
(913) 829-0073
829-0073 Eden
Eden Prairie,
Prairie, MN
MN 55344
55344
FLORIDA
ElQRIDA (612)
(612) 944-3456
944-3456
Bager Electronics Sales Engineering Concepts
Concepts MARYLAND
MABXLAtiD
6324 Variel Ave. #314 776
776 S. Military Trail Deltatronics
Deltatronics MISSOURI
MIIZIZQ!.!BI
Woodland
Woodland Hills, CA 91367 Deerfield
Deerfield Beach, FL 33442 24048
24048 Sugar
Sugar Cane
Cane Ln.
Ln. Stan
Stan Clothier
Clothier Company
Company
(818) 712-0011
(818) 712-0011 (305) 426-4601
(305) 426-4601 Gaithersburg,
Gaithersburg, MD
MD 20882
20882 3910
3910 Old
Old Highway
Highway 94
94 South
South
(301)
(301) 253-0615
253-0615 St.
St. Charles,
Charles, MO
MO 63303
63303
Criterion Sales Sales Engineering Concepts (314)
(314) 928-8078
928-8078
3350 Scott Blvd,
3350 Bldg.44
Blvd, Bidg.44 600 S. Norhtlake
600 S. Norhtlake Blvd.
Blvd. #230
#230
Santa Clara, CA
Santa Clara, CA 95054
95054 Altamonte Spgs, FL 32701
(408) 988-6300
(408) 988-6300 (407) 830-8444
(407) 830-8444
7-17
7-1 7 Effective:
Effective: April
April 1991
1991
North American
Sales Representatives
NEW JERSEY OHIO
QI:IlQ TEXAS
I.EXM CANADA
CANAPA
Technical Marketing Group Makin & Associates West Associates
West Associates
175-3C Fairfield Rd. 3165 Lynwood Rd.
3165 Rd. 4615 Southwest
4615 Southwest Fwy
Fwy #720
#720 ALBERTA
ALBERTA
West Caldwell, NJ 07006 Cincinnati, OH 45208
Cincinnati, Houston, TX
Houston, TX 77027
77027 Dynasty Components
Dynasty Components
(201) 226-3300 (513) 871-2424
(513) (713) 621-5983
(713) 621-5983 Calgary, Alberta
Calgary, Alberta
(403) 560-1212
(403) 560-1212
NEW MEXICO Makin & Associates
Makin Associates West Associates
West Associates
Summit Sales 6400 Riverside Dr.
6400 Dr. Bldg.
Bldg, A 9171 Capital
9171 of Texas
Capital of Texas BRITISH COLUMBIA
BRITISH COLUMBIA
2651 KK Pan American N.E. OH 43017
Dublin, OH North Houston
North Houston Bldg.
Bldg. #120
#120 Dynasty Components
Dynasty Components
Albuquerque, NM 87107 (614) 793-9545
(614) Austin, TX
Austin, TX 78759
78759 Vancouver, British
Vancouver, British Columbia
Columbia
(505) 345-5003 (512) 343-1199
(512) 343-1199 (604) 597-0068
(604) 597-0068
Makin & Associates
NEW YORK 32915 Aurora
32915 Ave. #270
Aurora Ave. #270 West Associates
West Associates ONTARIO
ONTARIO
Technical Marketing Group Solon, OH 44139 801 E. Campbell
801 Rd. #350
Campbell Rd. #350 Dynasty Components
Dynasty Components
20 Broad Hollow Rd.
20 (216) 248-7370 Richardson, TX
Richardson, TX 75081
75081 174 Colonade
174 Colonade Rd.
Rd. S.
S.
Melville, NY 11747 (214) 680-2800
(214) 680-2800 Unit 21
Unit 21
(516) 351-8833 OKLAHOMA
OKLAHOMA Nepean, Ontario
Nepean, Ontario
West Associates
West Associates MIAEI
YIAI:t Canada, K2E
Canada, K2E 7J5
7J5
Tr-Tech Electronics
Tri-Tech 9717 E. 42nd St. #125
9717 Waugaman Associates
Waugaman Associates (613) 723-0671
(613) 723-0671
300 Main St.
S!. Tulsa, OK 74146
Tulsa, 74146 876 East
876 East Vine
Vine St.
St.
E. Rochester, NY 14445
E. (918) 665-3465
(918) Murray, UT 84107
Murray, 84107 Dynasty Components
Dynasty Components
(716) 385-6500 (801) 261-0802
(801) 261-0802 Toronto, Ontario
Toronto, Ontario
OREGON
OREGON (416) 672-5977
(416) 672-5977
Tr-Tech Electronics
Tri-Tech Northwest Marketing
Northwest VIRGINIA
VIRGINIA
14 Westview Dr. 6975 SW
6975 SW Sandburg Rd. Deltatronics
Deltatronics QUEBEC
QUEBEC
Fishkill, NY 12524 #330
#330 1439
1439 Gills
Gills Rd.
Rd. Dynasty Components
Dynasty Components
(914) 897-5611 Portland,
Portland, OR 97223
97223 Powhatan, VA 23139
Powhatan, 23139 Montreal, Quebec
Montreal, Quebec
(503)
(503) 620-0441 (804)
(804) 492-9027
492-9027 (514)
(514) 694-0275
694-0275
Tr-Tech Electronics
Tri-Tech
6836 E. Genesee St.
S!. PENNSYLVANIA
PENNSYLVANIA WASHINGTON
WASHINGTON
Fayetteville, NY 13066 Deltatronics
Deltatronics Northwest Marketing
Northwest Marketing
(315) 446-2881 921 Penllyn Pike
921 Penllyn 12835
12835 Bel-Red Rd. #330N
Bel-Red Rd. #330N
Blue 19422
Blue Bell, PA 19422 Bellevue,
Bellevue, WA
WA 98005
98005
NORTH CAROLINA (215)
(215) 641-9930 (206)
(206) 455-5846
455-5846
The Novus Group
1102L
02L Commonwealth Ct.
Cary, NC 27511
(919) 460-7771
INTERNATIONAL SALES REPRESENTATIVES AND

AND DISTRIBUTORS
AUSTRALIA BELGIUM
BELGIUM FINLANP
FINLAND Franelee
Franelec
Zatek Components A.leom
Alcorn Electronics B. V.BA
B.V.B.A. TelercasOY
Telercas OY ZI
ZI Les
Les Glaises
Glaises
Level 2, 96
96 Phillip St.
S!. Singel3
Singel 3 Luomannotko
Luomannotko 66 6·8 Rue A.
6-8 Rue A. Ctoizat
Croizat
Paramatta 2150 2550
2550 Kontich 02200
02200 Espoo
Espoo 91124
91124 Palaiseau
Palaiseau Cedex
Cedex
Australia Belgium
Belgium Finland
Finland France
France
TEL: (02)
(02) 895-5534 TEL: 03-458 30
TEL: 03-458 30 33
33 TEL: (358) 0-452·1622
TEL: (358) 0-452-1622 TEL: (33) 16
TEL: (33) 16 9202002
9202002
FAX: (02)
(02) 895-5535 FAX: 03-458
03-458 31
31 26 FAX: (358) 0-452-3337
FAX: (358) 0-452-3337 FAX: (33) 169207469
FAX: (33) 16 9207469
TLX: 857123212
TLX: 857123212 TLX: 842250067
TLX: 842250067
AUSTRIA
AUSTR A PENMARK
DENMARK
Ing. E.
E. Steiner GmbH. Ditz
Ditz Schweitzer FRANCE
FRANCE DataDis
DataDis
Hummelgasse 14 Vallensbaekvej 41
Vallensbaekvej 41 Aquitech
Aquitech 33 Bis
Bis Rue
Rue Rene
Rene Cassin
Cassin
A-1130 Wien Postboks
Postboks 5, 22 Rue
Rue Alexis
Alexis De
De Tocqueville
Tocqueville B.P84
B.P 84
Austria DK-2605
DK-2605 Brendby 92138 Antony Cedex
92138 Antony Cedex 91303
91303 Massey
Massey Cedex
Cedex
TEL: (43) 222-827-4740
TEL: (43) Denmark
Denmark France
France France
France
FAX: (43) 222-828-5617
FAX: (43) 222·828-5617 TEL: (45) 42
TEL: (45) 42 45
45 30
30 44
44 TEL: (33) 140969494
TEL: (33) 140969494 TEL: (33) 69-20
TEL: (33) 69-20 4141
4141
FAX: (45) 42 45
FAX: (45) 45 92
92 06
06 FAX: (33) 140969300
FAX: (33) 140969300 FAX: (33) 69-204900
FAX: (33) 69-20 4900
TLX: 85533257
TLX: 85533257
7-18 Effective:
Effective: April
April 1991
1991
International Sales
Sales Representatives
Representatives
and Distributors
and Distributors
W. GERMANY
W.GERMANY JAPAN
IlAfAH N ORWAY
NORWAY Lite-On Inc.
Lite-On Inc.
Alfatron GmbH. Ado Electronic Indust. Co. Henaco A/S
Henaco AIS 9F NO
9F NO 33 Tunghua
Tunghua South
South Rd.
Rd.
Stahlgruberring 12
12 4th Floor,
Floor, Fukui Building Trondheimsveien 436
Trondheimsveien 436 Taipei, Taiwan
Taipei, Taiwan
8000 Munich 82 No. 2-12 Sotokanda Ammerud
Ammerud Republic of
Republic of China
China
West Germany 2-Chome, Chiyoda-ku Oslo 9 Norway
Oslo TEL: (886)
TEL: 2-7769-950
(886) 2-7769-950
TEL: (49)
(49) 89 4204 910
894204 Tokyo 101
Tokyo 101 TEL: ( 4
TEL: 7 ) 2162110
(47) 2162110 FAX: (886)
FAX: 2-7712-344
(886) 2-7712-344
FAX: (49)
(49) 89 4204 9159
8942049159 Japan FAX: (47)
FAX: 2257780
(47) 2257780 TLX: 785-15283
TLX: 785-15283
TLX: 5216935
5216935 TEL: (81)
(81) 3-3257-2600 TLX: 76716
TLX: 76716
FAX: (81)
FAX: (81) 3-3251-6796 UNITED KINGDOM
UNITED KINGDOM
HONG KONG TLX: 7812224754
7812224754 SINGAPORE
SINGApORE Macro Marketing
Macro Marketing
RTI Industries Co. Ltd. Technology Distribution
Technology Burnham Lane
Burnham Lane
A19, 10th
10th Floor Japan Macnics Corp. 14 Sungei
14 Sungei Kadut
Kadut Ave.
Ave. Slough SL
Slough SL1 6LN
1 6LN
Proficient Ind. Centre
Centre Hakusan High-Tech Park #03-00
#03-00 England
England
6, Wang Kwan Rd. 1-22-2 Hakusan-cho,
1-22-2 Singapore 2572
Singapore TEL: (44)
TEL: 628 604383
(44) 628 604383
Kowloon, Hong Kong Midori-ku
Midori-ku TEL: (65)
TEL: 368 6065
(65) 368 6065 FAX: (44)
FAX: 628 666873
(44) 628 666873
TEL: (852)
(852) 795 7421 Yokohama, 226 FAX: (65)
FAX: 368 0182
(65) 368 0182 TLX: 851E347945
TLX: 851847945
FAX: (852)
(852) 795 7839 Japan
TEL: (81)
(81) 45-939-6140 SOUTH
SOUTH AFRICA
AFRICA Micro Call
Micro Call
IHI21A
INDIA FAX: (81)
FAX: (81) 45-939-6141 Multikomponent
Multikomponent 17 Thame
17 Thame Park
Park Rd.
Rd.
Hindetron TLX: 78128988
78128988 Cnr. Vanacht
Cnr. Gewel St.
Vanacht & Gewel St. Thame, Oxon
Thame, Oxon 0X9 3XD
OX9 3XD
33/44A, 8th Main Road Isando 1600, P.O Box
lsando 1600,13.0 Box 695
695 England
England
Rajmahal Vilas Ext.
Ext. Hakuto Company, Ltd.
Hakuto Ltd. Republic
Republic of
of South Africa
South Africa TEL: (44) 84426-1939
TEL: (44) 84 426-1939
Bangaore, India 560-080 2-29, Toranomon,
Toranomon, 1 chome
chome TEL: (27) 11 974 1525
TEL: (27) FAX: (44) 84
FAX: (44) 84 426-1678
426-1678
TEL: (91)
(91) 812 348 266 105
Minato-Ku, Tokyo 105 FAX: (27) 11
FAX: (27) 11 392
3922463
2463
FAX: (91)
(91) 812 345 022
812345 Japan TLX: 960426905
TLX: 960426905 Silicon
Silicon Concepts
Concepts
TEL: (81)
(81) 3-3597-8910 PEC
PEC LynchOOrough
Lynchborough Rd.
Rd.
IRELAND FAX: (81)
(81) 3-3597-8975 SWEDEN
SWEDEN Passfield,
Passfield, Liphook
Liphook
Silicon Concepts TLX: J22912BRAPAN
J22912BRAPAN Pelcon
Pelcon Electronics Hampshire GU30
Hampshire GU30 7SB
7SB
3 Mills View Close Fagerstagatan
Fagerstagatan 6-8 6-8 England
England
Dukesmeadow, Kilkenny Hoei
Hoei Denki S-163
S-163 08
08 Spanga TEL: (44) 428
TEL: (44) 428 77617
77617
Kilkenny County 6-60, 2-Chome, Niitaka
Niitaka Sweden
Sweden FAX: (44) 428
FAX: (44) 428 77603
77603
Ireland Chiyoda-Ku,
Chiyoda-Ku, TEL: (46)
TEL: ( 4 795 9870
6 ) 88 795 9870
TEL: (353)
(353) 566 4002 Osaka 532, Japan
Japan FAX: (46) 8 760
FAX: (46) 760 7685
7685 Silicon
Silicon Concepts
Concepts
TEL: (81)
(81)63941113
6 394 1113 The
The Green
Green
ISRAEL FAX: (81) 6
FAX: (81) 63965647
396 5647 SWITZERLAND
SWITZERLAND Painshawfield
Painshawfield Road
Road
Unitec TLX: 5233694H0EIDK
5233694HOEIDK J Ascom
Ascom Primotec
Primotec AG
AG Stocksfield
Stocksfield
Rechov Maskit 11 Tafernstrasse
Tafernstrasse 37
37 Northumberland
Northumberland NE43
NE43 7PX
7PX
Herzlia B, PO Box 2123 KOREA CH-5405
CH-5405 Baden-Dattwil
Baden-Dattwil Scotland
Scotland
Israel 46120 Ellen
Ellen & Company Switzerland
Switzerland TEL: (44) 661-843955
TEL: (44) 661-843955
TEL: (972)
(972) 52 576006 Suite #302 Ilbok
IlOOk Bldg. TEL: (41) 5684-0171
TEL: (41) 5684-0171 FAX: (44) 661-843955
FAX: (44) 661-843955
FAX: (972)
(972) 52 576790
576790 1602-4
1602-4 Seocho-Dong FAX: (41) 5683-3454
FAX: (41) 5683-3454
TLX: 922341990
922341990 Seocho-ku, Seoul TLX: 2 8 221
TLX: 8828 221 apri ch
ch
Republic of South Korea
lIALY.
ITALY (82) 02 587 5724
TEL: (82) TAIWAN
TAIWAN
Comprel Rep (82) 02 5851519
FAX: (82) 585 1519 Master
Master Electronics Corp.
Corp.
Viale F. Testi, 115
115 16F
16F
20092 Cinosello B. Milano NETHERLANDS #810
#810 Tunghua South
South Rd.
Rd.
Italy Alcom
Alcorn Electronics B.V. Taipei,
Taipei, Taiwan
•
TEL: (39) 2-61206415
TEL: (39) Essebaan
Essebaan 11 Republic
Republic ofof China
China
FAX: (39)
(39) 2-61280526 2908 LJ
W Capelle Aan
Aan TEL: (886) 02-735-7316
TEL: (886) 02-735-7316
Den Ijssel FAX: (886) 02-735-0902
FAX: (886) 02-735-0902
The Netherlands
TEL: (31)
(31) 10
104519533
4519533
FAX: (31)
(31) 10
104586482
4586482
TLX: 26160
26160
7-19 Effective: April 1991

Effective: April 1991
North American Distributors
NORTH AMERICAN DISTRIBUTORS
ALABAMA
ALABAMA Marshall Industries
Marshall Marshall Industries
Marshall Marshall Industries
Marshall Industries
Arrow Electronics
Arrow Electronics 3039 Kilgore Ave. #140 26637 Agoura
26637 Agoura Rd.
Rd. 20 Sterling
20 Sterling Dr.
Dr.
1015 Henderson Rd. Rancho Cordova, CA 95670
Rancho Calabasas, CA 91302-1959
Calabasas, 91302-1959 PO Box
PO Box 200
200
Huntsville, AL 35816 (916) 635-9700
(916j (818) 878-7000
(818) 878-7000 Wallingford, CT
Wallingford, CT 06492-0200
06492-0200
(205) 837-6955 (203)
(203) 265-3822
265-3822
Merit Electronics
Merit Marshall Industries
Marshall
Marshall Industries 2070
2070 Ringwood Ave.
Ringwood Ave. 9320
9320 T elstar Ave.
Teistar Ave. FLORIDA
FLORIDA
3313 Memorial Pkwy S. San
San Jose, CA 95131 EI
El Monte, CA
CA 91731-3004
91731-3004 Arrow
Arrow Electronics
Electronics
Huntsville, AL 35801 (408)
(408) 434-0800 (818)
(818) 307-6000
307-6000 400
400 Fairway
Fairway Dr.
Dr.
(205) 881-9235 Deerfield Beach,
Deerfield Beach, FL
FL 33441
33441
SOUTHERN
SOUTHERN Marshall Industries
Marshall Industries (305) 429-8200
(305) 429-8200
ABIZPIIA
ARIZONA CALIFORNIA
CALIFORNIA One
One Morgan
Morgan
Arrow Electronics
Arrow Electronics Arrow Electronics Irvine, CA
Irvine, CA 92718
92718 Arrow
Arrow Electronics
Electronics
4134 E. Wood St. 19748
19748 Dearborn St.
St. (714)
(714) 458-5301
458-5301 37 Skyline
37 Skyline Dr.
Dr.
/liZ. 85040
Phoenix, AZ 85040 Chatsworth, CA 91311
91311 Bldg.
Bldg. 0,
D, Suite
Suite 3101
3101
(602) 437-0750 (818)
(818) 701-7500 Marshall
Marshall Industries Lake
Lake Mary,
Mary, FL32746
FL 32746
10105
10105 Carroll
Carroll Canyon
Canyon Rd.
Rd. (407)
(407) 333-9300
333-9300
Bell Industries Arrow Electronics San
San Diego, CACA 92131
92131
140 S. Lindon
Lindon Ln. #102
#102 2961 Dow Ave.
2961 Dow (619)
(619) 578-9600
578-9600 Bell
Bell Industries
Industries
Tempe, AZ/liZ. 85281 Tustin,
Tustin, CA 92680 600
600 S.S. Norhtlake
Norhtlake Blvd.
Blvd. #100
#100
(602) 267-7774 (714) 838-5422 Sterling
Sterling Electronics
Electronics Altamonte
Altamonte Springs,
Springs, FL
FL 32701
32701
9340
9340 Hazard
Hazard Way
Way #3A
#3A (407)
(407) 339-0078
339-0078
Insight Electronics Arrow Electronics San
San Diego,
Diego, CA
CA 92123
92123
1525 W. University Dr. 9511 Ct.
Ridgehaven Ct.
9511 Ridgehaven (619)
(619) 560-8097
560-8097 Marshall
Marshall Industries
Industries
Suite #105 San
San Diego, CA 92123 380
380 S.
S. Northlake
Northlake Rd.
Rd. #1024
#1024
Tempe, AZ/liZ. 85281 (619) 565-4800 Sterling
Electronics Altamonte
Altamonte Springs,
Springs, FL
FL 32701
32701
(602) 829-1800 1342
1342 Bell Ave.
Ave. (407)
(407) 767-8585
767-8585
Bell
Bell Industries Tustin,
Tustin, CA
CA 92680
92680
Marshall Industries 30101 Agoura Ct. #118
30101 Agoura (714)
(714) 259-0900
259-0900 Marshall
Marshall Industries
Industries
9830 S. 51st St. #B121 Agoura
Agoura Hills, CA 91301 2700
2700 Cypress
Cypress Ck.
Ck. Rd.
Rd. #0114
#D114
/liZ. 85044
Phoenix, AZ (818) 706-2608 Sterling
Electronics Ft.
Ft. Lauderdale,
Lauderdale, FL
FL 33309
33309
(602) 496-0290 9410
9410 Topanga
Topanga Canyon
Canyon #103
#103 (305)
(305) 977-4880
977-4880
Bell
Bell Industries Chatsworth,
Chatsworth, CA
CA 91311
91311
NORTHERN 11812
11812 San Vicente
Vicente #300 (818)
(818) 407-8850
407-8850 Marshall
Marshall Industries
Industries
CALIFORNIA Los Angeles, CA 90049
Los Angeles, 2840
2840 Scherer
SchererDr.
Dr. #410
#410
Arrow Electronics (213)
(213) 826-6778 COLOBAOO
COLORADO St.
St. Petersburg,
Petersburg, FL
FL 33716
33716
Kitting Services Division Arrow
Arrow Electronics
Electronics (813)
(813) 573-1399
573-1399
1180 Murphy Ave. Bell
Bell Industries 3254C
3254C Fraser
Fraser St.
St.
San Jose, CA 95131 11095 Knott Ave.
Ave. #E
#E Aurora,
Aurora, CO
CO 80011
80011 Vantage
Vantage Components
Components
(408) 452-3550 Cypress, CA 90630 (303)
(303) 373-5616
373-5616 1110
1110 Douglas
Douglas Ave.
Ave. #2050
#2050
(714) 895-7801 Altamonte
Altamonte Springs,
Springs, FL
FL32714
32714
Bell Industries AVED
AVED (407)
(407) 682-1199
682-1199
4311 Anthony
Anthony Ct. #100 Bell Industries 4090
4090 Youngfield
You ngfield St.
Rocklin, CA 95677 7827 Convoy Ct. #403
#403 Wheat
Wheat Ridge,
Ridge, CO
CO 80033
80033 Vantage
Vantage Components
Components
(916) 367-2095 San
San Diego, CA 92111 (303)
(303) 422-1701
422-1701 1761
1761 W.
W. Hillsboro
Hillsboro #318
#318
(619)
(619) 268-1277 Deerfield
Deerfield Beach,
Beach, FL
FL 33441
33441
Bell Industries Bell
Bell Industries
Industries (305)
(305) 429-1001
429-1001
1161 N.N. Fairoaks Ave. Insight
Insight Electronics 12421
12421 W. 49th
49th Ave.
Ave.
Sunnyvale, CA 94089 28038 Dorothy Dr. #2#2 Wheat
Wheat Ridge,
Ridge, CO 80033
CO 80033 GEORGIA
GEORGIA
(408) 734-8570 Aquora, CA 91301
91301 (303)
(303) 424-1985
424-1985 Arrow
Arrow Electronics
Electronics
(818) 707- 2100 4205E
4205E River
RiverGreen
Green Pkwy.
Pkwy.
Insight Electronics Marshall
Marshall Industries Duluth,
Duluth, GA
GA 30136
30136
1295 Oakmead Pkwy. Insight Electronics 12351
12351 N. Grant
Grant (404)
(404) 497-1300
497-1300
Sunnyvale, CA 94086
94086 6885 Flanders Dr. #C#C Thornton,
Thornton, CO
CO 80241
80241
(408)720-9222
(408)720-9222 San Diego, CA 92121 (303) 451-8383
(303) 451-8383 JACO
JACO
(619)
(619) 587-0471 6035
6035 Atlantic
Atlantic Blvd. #J
Blvd. its1
Marshall Industries !:;QHHECTIC!.II
CONNECTICUT Norcross,
Norcross, GA
GA 30071
30071
336 Los Coches
Cocbes St.
St. Insight
Insight Electronics Arrow
Arrow Electronics
Electronics (404)
(404) 449-9508
449-9508
Milpitas, CA 95035
95035 15635
15635 Alton Pkwy. #120
#120 12
12 Beaumont
Beaumont Rd.
Rd.
(408) 942-4600 Irvine, CA 92718 Wallingford,
Wallingford, CT
CT 06492
06492
(714)
(714) 727-3291 (203)
(203) 265-7741
265-7741
7-20
7-20 Effective:
Effective: April
April 1991
1991
American Distributors
North American Distributors I:
Marshall Industries
Marshallindustries MARYLAND MISSOURI
MISSOURI JACO
JACO
5300 Oakbrook Pkwy #140 Arrow Electronics Arrow Electronics
Arrow Electronics 145 Oser
145 Oser Ave.
Ave.
Norcross, GA 30093 8300 Guilford Dr. 2380 Schuetz Rd.
2380 Rd. Hauppauge, NY
Hauppauge, NY 11788
11788
(404) 923-5750 Columbia, MD 21046 St. Louis,
St. MO 63146
Louis, MO 63146 (516)273-5500
(516)273-5500
(301) 995-6002 (314) 567-6888
(314) 567-6888
LQIYA
IQWA Marshall Industries
Marshall Industries
Arrow Electronics Marshall Industries Marshall
Marshall Industries
Industries 275
275 Oser
Oser Ave.
Ave.
375 Collins Rd. NE 2221 Broadbirch Dr.
Broadbirch Dr. 3377
3377 Hollenberg Dr. Hauppauge, NY
Hauppauge, NY 11788
Cedar Rapids, IA 52402 Silver Springs, MD 20904 Bridgeton, MO
Bridgeton, MO 63044
63044 (516)
(516) 273-2424
273-2424
(319) 395-7230 (301) 622-1118
622-1118 (314)
(314) 291-4650
291-4650
Marshall
Marshall Industries
Industries
ILUNOIS
ILLINOIS Vantage Components NEW JERSEY 1250
1250 Scottsville
Scottsville Rd.
Rd.
Arrow Electronics 6925 Oakland Mills Rd.
Rd. Arrow Electronics
Arrow Rochester,
Rochester, NY 14624
14624
1140 W. Thorndale Ave. Columbia, MD 21045 44 East Stow
Stow Rd.
Rd. Unit 11 (716)
(716) 235-7620
235-7620
ltasca,lL 60143
Itasca, IL 60143 (301) 720-5100 Marlton,NJ
Marlton,NJ 08053
(312) 250-0500 (609)
(609) 596-8000 Marshall
Marshall Industries
Industries
MA§§ACt:l!.!§ETTS
MASSACHUSETTS 100
100 Marshall
Marshall Drive
Drive
Bellindustries
Bell Industries Arrow Electronics Arrow
Arrow Electronics
Electronics Endicott,
Endicott, NY
NY 13790
13790
870 Cambridge Dr. 25
25 Upton Dr. 66 Century Dr.
Dr. (607)
(607) 785-2345
785-2345
Elk Grove Village, IL 60007 Wilmington, MA 01887 Parsippany-Trow
Parsippany-Trow Hills, NJ
(312) 640-1910 (508) 658-0900 07054
07054 Vantage
Vantage Components
Components
(201)
(201) 538-0900 1056
1056 Jericho
Jericho Turnpike
Turnpike
Marshallindustries
Marshall Industries Interface Electronic Corp.
Interface Corp. Smithtown,
Smithtown, NY 11787
NY 11787
50 E. Commerce Dr. Unit 11 228 South Street Marshall
Marshall Industries
Industries (516)
(516) 543-2000
543-2000
Schaumberg,lL
Schaumberg, IL 60173 Hopkinton, 01748
Hopkinton, MA 01748 101
101 Fairfield Rd.
Rd.
(708) 490-0155 (508) 435-9521 Fairfield,
Fairfield, NJ 07006 NOW
NORTH CAROLINA
CAROLINA
(201)
(201) 882-0320 Arrow
Arrow Electronics
Electronics
IINPIANA
MAM Marshall Industries 5240
5240 Greens
Greens Dairy
Dairy Rd.
Rd.
Arrow Electronics 33 Upton Dr. Marshall
Marshall Industries Raleigh,
Raleigh, NC
NC 27604
27604
7108 Lakeview Pkwy. W. Dr. Wilmington, MA 01887 158
158 Gaither Dr. (919)
(919) 876-3132
876-3132
Indianapolis, IN 46268 (508) 658-0810 Mt. Laurel, NJ
Mt. Laurel, NJ 08054
08054
(317) 299-2071 (609)
(609) 234-9100
234-9100 Marshall
Marshall Industries
Industries
MICt:llGAN
NacjilaAti 5224
5224 Greens
Greens Dairy
Dairy Rd.
Rd.
Bellindustries
Bell Industries Arrow Electronics Vantage
Vantage Components
Components Raleigh,
Raleigh, NC
NC 27604
27604
5230 W. 79th St. 3510 Roger Chaffee Mem. 23
23 Sebago St. (919)
(919) 878-9882
878-9882
Indianapolis, IN 46268 Blvd.
Blvd. SE Clifton,
Clifton, NJ
NJ 07013
07013
(317) 875-8200 Grand Rapids, MI (201)
(201) m-4100
777-4100 JACO
JACO
(616) 243-0914 3029·105
3029-105 Stonybrook
Stonybrook Dr.
Dr.
Custom Service Electronics NEW
NEW MEXICO
MEXICO Raleigh,
Raleigh, NC
NC 27604
27604
8730 Commerce Park Pl. PI. #A Arrow Electronics Bell
Bell Industries
Industries (919)
(919) 876·7767
876-7767
Indianapolis, IN 46268 19880
19880 Haggerty Rd. 11728
11728 Unn
Linn NE
NE
(317) 879-9119 Uvonia. MI48152
Livonia, MI 48152 Albuquerque,
Albuquerque, NM NM 87123
87123 QJ:II.Q
OHIO
(313) 462-2290
462·2290 (505)
(505) 292·2700
292-2700 Arrow
Arrow Electronics
Electronics
Marshallindustries
Marshall Industries 6573E
6573E Cochran
Cochran Rd.
Rd.
6990 Corporate Dr. Bell
Bell Industries NEW
NEW YORK
YORK Solon,
Solon, OH
OH 44139
44139
Indianapolis, IN 46278 Ct. #81
28003 Center Oaks Ct. #B1 Arrow
Arrow Electronics
Electronics (216)
(216) 248-3990
248-3990
(317) 297-0483
297·0483 Wixon, MI 48393 25
25 Hub
Hub Drive
Drive
(313) 347-6633 Melville,
Melville, NY 11747 Arrow
Arrow Electronics
Electronics
KAN§A§
KAN.aoll (516)
(516) 391-1300
391-1300 8200
8200 Washington
Washington Village
Village Dr.
Dr.
Arrow Electronics Marshall
Marshall Industries #A
#A
8208 Melrose Dr. #210 31067 Schoolcraft Arrow
Arrow Electronics Centerville,
Centerville, OH
OH 45458
45458
Lenexa, KS 66214 Uvonia, MI48150
Livonia, MI 48150 200serAve.
20 Oser Ave. (513)
(513) 435-5563
435-5563
(913) 541-9542 (313) 525-5850 Hauppauge,
Hauppauge, NY 11788
11788
(516) 231-1000
(516)231- 1000 Bell
Bell Industries
Industries
Marshallindustries
Marshall Industries MINNE§OTA
MINNESOTA 444
444 Windsor
Windsor Park
Park Dr.
Dr.
10413 W. 84th Terr.
Tem Arrow Electronics Arrow
Arrow Electronics
Electronics Dayton,
Dayton, OH
OH 45459
45459
Pine Ridge Business Park 10120A
10120A West 76th Street 3375
3375 Brighton-Henrietta (513)
(513) 435-8660
435-8660
Lenexa, KS 66214 Eden
Eden Prairie, MN 55344
55344 Townline
Townline Rd.
Rd.
(913) 492-3121 (612) 829-5588 Rochester,
Rochester, NY 14623 Marshall
Marshall Industries
Industries
(716) 427-0300
(716) 427-0300 3520
3520 Park
Park Center
Center Dr.
Dr.
Marshall Industries Dayton,
Dayton, OH
OH 45414
45414
3955 Annapolis Lane (513)
(513) 898-4480
898-4480
Plymouth,
Plymouth, MN 55447
(612) 559·2211
559-2211
7-21
7-21 Effective:
Effective: April
April 1991
1991
North American DistributolS
Nolth Distributors
Marshall Industries Insight Electronics Insight Electronics
Insight Electronics ONTARIO
ONTARIO
30700 Bainbridge Rd. Unit A 15437 McKaslde
15437 McKaskle 12002 115th Ave.
12002115th Ave. NE
NE Arrow Electronics
Arrow Electronics
Solon, OH 44139 Sugarland, TX n478-1311
77478-1311 Kirkland, WA 98034
Kirkland, 98034 36 Antares
36 Antares Dr.
Or. Unit
Unit 100
100
(216) 248-1788 (713) 448-0800 (206) 820-8100
(206) 820-8100 Nepean, Ontario
Nepean, Ontario
Canada, K2E
Canada, K2E 7W5
7W5
OKLAHOMA
OKLAHOMA JACO Marshall Industries
Marshall Industries (613) 226-6903
(613) 226-6903
Arrow Electronics Kellway Circle
4251-A Kellway Circle 11715 N.
11715 N. Creek
Creek Pkwy.
Pkwy. S.
S.
12111 East
East 51st St.
St. #101
#101 Addison, TX 75244
Addison, 75244 Suite 112
Suite Arrow
ArrowElectronics
Electronics
Tulsa, OK 74146 (512)
(512) 835-0220 Bothell,
Bothell, WA 98011
98011 11093 Meyerside Dr.
093. Meyerside Dr.
(918) 252-7537 (206)
(206) 486-5747
486-5747 Mississauga,
Mississauga, Ontario
Ontario
JACO Canada,
Canada, 15P
L5P 11M4
M4
OREGON
OREGON 2120 M.
2120 M. Bracker Lane WISCONSIN
WISCONSIN (416) 670-n69
(416) 670-7769
Arrow Electronics Austin,
Austin, TX 78758
78758 Arrow
Arrow Electronics
Electronics
9275 S.W. Nimbus Ave.
Ave. (512) 835-0220 200 North
200 North Patrick
Patrick Blvd.
Blvd. Future
Future Electronics
Electronics
Beaverton, OR 97005 Brookfield, WI 53005
Brookfield, 53005 1050
1050 Baxter
Baxter Road
Road
(503) 627-7667 JACO (414)
(414) 792-0150
792-0150 Ottawa,
Ottawa, Ontario
Ontario
1005
1005 Industrial Blvd.
Blvd. Canada,
Canada, K2C
K2C 3P2
3P2
Bell Industries Sugarland,
Sugarland, TX 77478
n478 Bell
Bell Industries (613)
(613) 820-8313
820-8313
6024 S.W. Jean Rd. (713)
(713) 240-2255 W226
W226 N.N. 900 Eastmound
Eastmound Dr.
Dr.
Lake Oswego, OR 97035 Waukesha,
Waukesha, WI 53186
WI 53186 Future
Future Electronics
Electronics
(503) 635-6500 Marshall
Marshall Industries (414)
(414) 547-8879
547-8879 5935
5935 Airport
Airport Rd.,
Rd., #200
#200
8504 Cross Park Dr. Mississauga,
Mississauga, Ontario
Ontario
Insight Electronics Austin,
Austin, TX 78754 Marshall
Marshall Industries
Industries Canada,
Canada, L4 V 11W5
L4V W5
8705 SW Nimbus #200 (512) 837-1991
(512) 837-1991 20900
20900 Swenson
Swenson Dr.
Dr. #150
#150 (416)
(416) 612-9200
612-9200
Tigard, OR 97005 Waukesha,
Waukesha, WIWI 53186
53186
(503) 644-3300 Marshall Industries (414)
(414) 797-8400
797-8400 Marshall
Marshall Industries
Industries
7250
7250 Langtry 44 Paget
Paget Rd.
Rd.
Marshall Industries Houston,
Houston, TX n040
77040 Bldg.
Bldg. 1112, Unit 10
10
9705 SW Gemini Dr. (713)
(713) 895-9200 MUM
CANADA Brampton,
Brampton, Ontario
Ontario
Beaverton, OR 97005 Canada,
Canada, L6T
L6T 5G3
5G3
(503) 644-5050 Marshall
Marshall Industries ALBERTA
ALBERTA (416)
(416) 458-8046
458-8046
2045
2045 Chenault Street
Street Future
Future Electron·ics
Electronics
PENNSYVANIA
E!EHH§XllAHIA Carrollton,
Carrollton, TX 75006
75006 3833-29th
3833-29th Street
Street QUEBEC
QUEBEC
Marshall Industries (214)
(214) 233-5200 Calgary,
Calgary, Alberta
Alberta Arrow
Arrow Electronics
Electronics
401 Parkway View Dr.
401 Parkway Canada,
Canada, T2A
T2A 5Nl
5N1 1100
1100 St.
St. Regis
Regis Blvd.
Blvd.
Pittsburgh, PA 15205 .I.lIAI:l
UTAH (403)
(403) 250-5550
250-5550 Dorval,
Dorval, Quebec
Quebec
(412) 788-0441 Arrow
Arrow Electronics Canada,
Canada, H4P
H4P 2T5
2T5
1946 West Parkway Blvd. Future
Future Electronics
Electronics (514)
(514) 421-7411
421-7411
mM
TEXAS Salt
Salt Lake City,
City, UT 84119 4606-97th
4606-97th Street
Arrow Electronics (801) 973-6913 Edmonton,
Edmonton, Alberta
Alberta Future
Future Electronics
Electronics
2227 West Braker Lane Canada,
Canada, T6E
T6E 5N9
5N9 237
237 Hymus
Hymus Blvd.
Blvd.
Austin, TX 78758 Bell
Bell Industries (403)
(403) 438-2858
438-2858 Pointe
Pointe Claire,
Claire, Quebec
Quebec
(512) 835-4180 6912 S. 185th West #B
#B Canada,
Canada, H9R
H9R 5C7
5C7
Midvale,
Midvale, UT 84047 ElBID§1:I
BRITISH COLUMBIA (514)
(514) 694-n10
694-7710
Arrow Electronics (801)
(801) 255-9611 Arrow
Arrow Electronics
Electronics
3220 Commander Dr. 8544
8544 Baxter
Baxter Place
Place Future
Future Electronics
Electronics
Carrollton, TX 75006 Marshall Industries Burnaby,
Burnaby, British Columbia
Columbia 1000
1000 St.Jean
St-Jean Babtiste
Babtiste #100
#100
(214) 380-6464 2355 South 1070
1070 West Canada,
Canada, V5A
V5A 4T8
4T8 Quebec
Quebec City,
City, Quebec
Quebec
Salt
Salt Lake City, UT 84119
84119 Canada,
Canada, G2E
G2E 5G5
5G5
Arrow Electronics (801) 973-2288 Future
Future Electronics
Electronics (418)
(418) 8n-6666
877-6666
10899 Kingfiurst
Kingflurst Dr. #100 1695
1695 Boundary
Boundary Road
Road
Houston, TX 77099
n099 !tlA§I:IIHgIQH
WASHINGTON Vancouver,
Vancouver, British
British Columbia
Columbia Marshall
Marshall Industries
Industries
(713) 530-4700 Arrow Electronics Canada,
Canada, V5K
V5K 4X7
4X7 148
148 Brunswick
Brunswick Blvd.
Blvd.
14320 NENE 21st
21st St.
St. (604)
(604) 294-1166 Pointe
Pointe Claire,
Claire, Quebec
Quebec
Insight Electronics Bellevue,
Bellevue, WA 98007 Canada,
Canada, H9R
H9R 5B9
5B9
12703-A Research Blvd. #1 (206) 643-4800 MAHIIQ&A
MANITOBA (514)
(514) 694-8142
694-8142
Austin, TX 78759 Future
Future Electronics
Electronics
(512) 467-0800 Bell Industries 100 King Edward
lOOKing Edward
16650
16650 NE 79th,
79th, Suite
Suite 103 Winnipeg,
Winnipeg, Manitoba
Manitoba
Insight Electronics Redmond,
Redmond, WA 98052
98052 Canada,
Canada, R3H
R3H ON8
0N8
1n8 Plano Rd. #320
1778 (206)
(206) 867-5410 (204) 786-n11
(204) 786-7711
Richardson, TX 75081
(214) 783-0800
7-22
7-22 Effective:
Effective: April
April 1991
1991
Lattice
Semiconductor
Corporation
5555 Northeast Moore Ct.
Hillsboro, OR 97124
Telephone: (503) 681-0118
FAX: (503) 681-3037
Literature & *pplications Hotline
1-800-FASTGAL
(503) 693-0201
Electronic Bulletin Board

(503) 693-0215
1200/2400 Baud • N, 8, 1
Printed on recycled paper. O r d e r #: B0005

GAL Databook 1991 PDF

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

GAL Databook 1991 PDF

Uploaded by

Copyright:

Available Formats

DATA BOOK

Commercial Grade Devices

Industrial Grade Devices

MIL-STD-883C Grade Devices

In our new 1991 Data

We look forward to satisfying all of your programmable logic requirements.

Generic Array Logic, Latch-Lock, and RFT are

PAL is a registered trademark of Advanced Micro Devices, Inc.

Products discussed in this literature are

Section 3: GAL Military Products

Section 4: Quality and Reliability

Section 5: Technical Notes

INTRODUCTION THE GAL

Section 2: GAL Datasheets

Section 3: GAL Military Products

Section 4: Quality and Reliability

Section 5: Technical Notes

Section 6: Article Reprints

Section 7: General Information

Datasheet Identification Product Status

No Identification Full Production This

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

Hillsboro, Oregon 97124, U.S.A.

Industrial Grade Specifications

PART NUMBER DESCRIPTION

The following discussion pertains to configuring the output logic

COMPILER SUPPORT FOR OLMC

When using compiler software to configure the device, the user

Registered Complex Simple

..... -- .. - .. _- ...... -- ........ -- ...... - ..... .

Note: The development software configures all

REGISTERED MODE LOGIC DIAGRAM

Architecture configurations available in

Note: The development software configures all

IIIII IIIIIIIIIIII 111111111ln

All outputs in the simple mode have a maximum

SIMPLE MODE LOGIC DIAGRAM

.---. "'" 111 . 111 . 111 . 1 1 . 1 1 1 0 1 1 1 . 1 1 1 . 1 1 1 . .

SYMBOL PARAMETER CONDITION

tco 11 Clock to Output Delay 22 55 22 77 ns

tsu -— Setup Time, Input or Feedback before

th -— Hold Time, Input or Feedback after Clock"

SWITCHING TEST CONDITIONS

SYMBOL PARAMETER CONDITION

VIH Input High Voltage 2.0

VOH Output High Voltage loH = MAX.

tsu -— Setup Time, Input or Feedback before

11 Maximum Clock Frequency with 62.5 ..:: 62.5

ten 2 Input or I/O

1SWITCHING TEST CONDITIONS

SYMBOL PARAMETER CONDITION

tcf2 -— Clock to Feedback Delay -— 66 -— 88 ns

tsu -— Setup Time, Input before Clocki

twh4 -— Clock Pulse Duration, High 88 -— 88 -— ns

SWITCHING TEST CONDITIONS

SYMBOL PARAMETER CONDITION

VIL Input Low Voltage Vss -0.5

VIH Input High Voltage 2.0

1) One output at a time for a maximum duration

tco 11 Clock to Output Delay ?

tsu -— Setup Time, Input or

th -— Hold Time, Input or Feedback alter

1 Maximum Clock Frequency with 62.5 r:p!,i\!•—