Wafer Level Packaging 5.
Wafer is singulated into individually packaged die
WLP involves packaging the chip on the wafer, rather than slicing the wafer
first into individual chips and then packaging them.
Wafer level packaging (WLP) is a packaging technology where most or all of
the IC packaging process steps are carried out at the wafer level.
Wafer Level Packaging (WLP) is essentially a true chip- scale packaging (CSP)
technology, since the resulting package is practically of the same size as the
die.
Wafer-level packaging basically consists of extending the wafer fab processes
to include device interconnection and device protection processes.
WLP is consists of a first dielectric layer, conductive metal redistribution
layer(RDL) to redistribute signal path from the die peripheral to a solder ball
pad and a second dielectric layer to cover the RDL metal layer.
Wafer-level packaging (WLP), as its name implies, involves packaging the die
while it is still on the wafer: protective layers may be bonded to the top
and/or bottom of the wafer, then electrical connections are prepared and the
wafer is diced into individual chips.
BACK THINNING. The purpose of back thinning is to ensure a minimum of
mechanical stability and to avoid warping during high temperature
processing steps.
CARRIER WAFERS are carrier substrate for the processing of thin
semiconductor wafers. These carriers are used to permit the safe handling of
delicate semiconductor wafers (e.g. those made of silicon and gallium
arsenide).
Wafer level packaging process flow
1. Wafer is encapsulated with a cover glass at the initial stage of processing.
2. Silicon via creation and dielectric application
3. Electrical contact routing
4. Solder bumps formed on the wafer backside
Advantage of WLP
1. Shortened manufacture cycle time
2. Ease of cooling through the fully exposed back of the die.
1. Space saving or smaller area - wafer-level packaging encapsulates only the
same size of the chip having smaller area used compared to the conventional
packaging.
2. Lower cost - electrical testing, burn-in of the device is done more efficiently
on water level and some traditional package assembly have been replaced by
wafer-level interconnection process.
3. Enhanced electrical performance - because of its minimum-length
interconnection
4. Elimination of need for underfilling of solder joints with organic material
5. Easier inventory management - since fab, assembly, test, and burn-in can
essentially be housed under one production floor
The underfill process consists of dispensing a void-free fluid to encapsulate
the bottom side of a silicon die or BGA device
Fan-out WLPs. As opposed to a conventional fan-in WLP, fan-out WLPs start
with the reconstitution or reconfiguration of single dies to an artificial molded
wafer. The fan-out WLP has received increased attention because of the
demand for thinner features and increasing I/O count devices.
Advantage of FOWLP
1. A wider range of different designs due to thinner package.
2. Expands application space
3. In fan-out, the RDL traces can be routed inward and outward, enabling
thinner packages with more I/Os and expanded available area of the package.
4. It provides a smaller package footprint with higher input/output (I/O) along
with improved thermal and electrical performance.
5. Only confirmed known good dice are packaged
 Failure Analysis 7. Hot Spot Detection and Light Emission Microscopy

Device failure is defined as any non-conformance of the device to its electrical 8. Microprobing
and/or visual/mechanical specifications.
9. Die Deprocessing
Device failure is when some system or part of a system fails to perform up to
10. FA Report/Conclusion
the expectations for which it was created.
Curve tracing is used to identify electrical failures that exhibit abnormal
Reasons for FA:
voltage-current relationships between pins. Equipment used is called curve
1. Determining corrective actions for product failures tracer.

2. Obtain a better understanding of failure events and causative factors Why Bench Testing? To verify the electrical test results by bench testing to
ensure that all failures are not due to contact issues only.
3. Meeting regulatory standards required for product sales or exports.
Bench testing is the process of characterizing the failure mode of the sample
4. To reduce financial costs associated with product failure
using various bench equipment for exciting the device and measuring its
5. To provide feedback to the product designers for improving design or even responses.
correcting minor design faults that might have been overlooked in the initial
The purpose of X-RAY INSPECTION is to look for internal package anomalies
design.
such as broken wires, incorrect or missing die, excessive die attach voids, etc.
6. To determine how a particular event or failure occurred, because knowing
Confocal Scanning Acoustic Microscopy (CSAM) can give clearer images by
this, one will be able to determine corrective measures, andover time, the
varying the frequencies of the acoustic signal penetrating the device.
root causes identified can be used to target major opportunities for
improvement. Why use CSAM over XRAY?

7. To validate the failure of the sample. In traditional x-ray inspection, this type of analysis would only be possible
with very thick layers, and with voids of a reasonable thickness. Acoustic
8. Used to evaluate the reliability of a product under actual operation
microscopy can be used with thin layers of device and can give this
FA Process Flow information nondestructively.

1. Failure Information Review and Verification Delamination is the separation of the epoxy resin glass fiber bond in the basic
board material. Possible causes are not properly cured epoxy resin, an
2. External Visual Inspection insufficient (too low) temperature in the press cycle when manufacturing the
3. Bench Testing and Curve Tracing board or absorbed moisture. Delamination can be recognized as bubbles or
discoloration of the PCB surface.
4. X-ray Inspection and CSAM
Decapsulation Techniques
5. Decapsulation
1. Manual chemical etching consists of manually dispensing some acid on the
6. Internal Visual Inspection surface of a package to remove the plastic material covering the die.
2. Jet etching is the automated version of chemical decapsulation, using a
piece of equipment known as a jet etcher. The jet etcher automatically squirts
heated acid on the area of the package that needs to be removed.
3. Thermomechanical decapsulation is a technique involves heating the
package followed by grinding, breaking, and cutting to separate the top part
of the package from its bottom part.
4. Plasma etching removes plastic by making it react with a gas which can
easily be vented out.
Internal visual inspection is done by the use of magnification, borescopes,
cameras, or other optical arrangements for direct or remote viewing. The
internal structure of a sample can be examined for a volumetric inspection
with penetrating radiation (RT), such as X-rays, neutrons, or gamma radiation.
Internal Visual Inspection: Internal Analysis of the device examines the die
markings, internal package characteristics, topography and compares against
a known good device if possible.
Microthermography or Hot Spot Detection is a semiconductor failure
analysis technique used to locate areas on the die surface that exhibit
excessive heating. Excessive heating indicates a high current flow, which may
be due to die defects or abnormalities like dielectric ruptures, metallization
shorts, and leaky junctions.
Hot spot Detection methods
•Infrared Thermography -IR cameras used for thermography
•Thermoreflectance -Test materials or devices are illuminated by an external
light source, and the reflected light is imaged onto a camera
•Emission Microscopy - Works by counting electrons emitted
• Liquid crystal - consists of dropping liquid crystal on the die surface of a
biased device.
Light Emission Microscopy (LEM), is a relatively new failure analysis
technique for detecting photonic radiation from a defect site, primarily due
to carrier recombination mechanisms.
Photoemission Microscopy (LEM) can detect: 1)previously unknown or
undetectable electroluminescence; 2)avalanche luminescence from junction
breakdowns, junction defects, currents due to saturated MOS transistors, and
transistor hot electron effects; 3)dielectric electroluminescence from current
flow through SiO2 and SiN.
Microprobing means probing individual conductors and devices that lets
analysts selectively inject, and measure the effects of, real-time currents and
voltages on individual semiconductor devices under varying conditions.
Microprobing, or simply probing, is a failure analysis technique used to
achieve electrical contact with or access to a point in the active circuitry of
the die.
Decapsulation is a failure analysis step performed to open a plastic package
to facilitate the inspection, chemical analysis, or electrical examination of the
die and the internal features of the package.
Deprocessing (also called delayering), as the name implies, is the systematic
process of removing the thin film layers of the die after it has been exposed
or removed from the package. The purpose is to provide the analyst more
visibility and accessibility to areas below the surface of the die where much
of the electrical activity takes place.
Deprocessing is the semiconductor failure analysis technique of stripping off
the upper layers of the die to expose a defect site that is buried underneath
these layers.
Die Processing Methods
1. Plasma etching is a dry and anisotropic (in one direction only) etching
process that consists of a glow discharge produces chemically reactive species
from a relatively inert gas.
2. Reactive ion etching is similar to plasma etching, except that it involves
bombardment of the surface being etched with accelerated reactive ions.
3. Wet etching involves the application of liquid solutions to the die surface
to remove one or more layers of materials or to highlight defects.
FA report tools

Ishikawa/fishbone diagram – Causes and effects are listed in categories such

as measurement, material, machine, mother nature, man power, and
method.

Fault or logic tree analysis – A failure is identified and the failure modes are
described and tested until the roots are identified.

Pareto chart – Shows the relative frequency of problems or failures in rank-

order so that process improvement activities can be focused on the
significant few.