EE303A Digital System Verilog Simulator Tutorial

ModelSim-Altera Tutorial

EE303A Digital System

1
EE303A Digital System Verilog Simulator Tutorial

Installation Guide

 We will use ModelSim-Altera as a Verilog simulator

throughout this course.
 Get the installation file of ModelSim-Altera from
Altera’s website.
 http://dl.altera.com/?edition=subscription&product=model
sim_ae#tabs-2
 Download and install ModelSim-Altera Edition.

2
EE303A Digital System Verilog Simulator Tutorial

 Follow the link in the previous page and you will see
this webpage.

Click here first!

And click here

3
EE303A Digital System Verilog Simulator Tutorial

 User Name: KAIST-EE303A

Password: digital303ee
 Or you can create your own account for free.

4
EE303A Digital System Verilog Simulator Tutorial

 You will see this after downloading and starting the

installation file.

Click Next

5
EE303A Digital System Verilog Simulator Tutorial

Select ModelSim-Altera Starter Edition

Click Next

6
EE303A Digital System Verilog Simulator Tutorial

Accept

Click Next

7
EE303A Digital System Verilog Simulator Tutorial

Specify the directory

as you want

Click Next

8
EE303A Digital System Verilog Simulator Tutorial

Click Next

9
EE303A Digital System Verilog Simulator Tutorial

 The actual installation is in progress.

10
EE303A Digital System Verilog Simulator Tutorial

 Now we’re all set!

Click Finish

11
EE303A Digital System Verilog Simulator Tutorial

Simulation

 We will simulate Verilog modules from the textbook

as an example.
 Section 3.6 Boolean Expressions in Verilog,
Figure 3.7 and Figure 3.8

 Figure 3.7
module Majority(a, b, c, out);
input a, b, c;
output out;

assign out = (a & b) | (a & c) | (b & c);

endmodule

12
EE303A Digital System Verilog Simulator Tutorial

 Figure 3.8
module test;
reg [2:0] count; //input-three bit counter
wire out; // output of majority

// instantiate the gate

Majority m(count[0],count[1],count[2],out);

// generate all eight input patterns

initial begin
count = 3’ b000;
repeat (8) begin
#100
count = count + 3’ b001;
end
end
endmodule

13
EE303A Digital System Verilog Simulator Tutorial

 Run ModelSim-Altera.

14
EE303A Digital System Verilog Simulator Tutorial

 Create a new project.

Click Project

15
EE303A Digital System Verilog Simulator Tutorial

 Put the name of your new project.

16
EE303A Digital System Verilog Simulator Tutorial

 Now, we need to create a Verilog file for Majority

module.

Click here

17
EE303A Digital System Verilog Simulator Tutorial

 Set the file name for Majority module and make sure
the file type is Verilog.

Type is Verilog

18
EE303A Digital System Verilog Simulator Tutorial

 Open “majority.v”.

Double-click

19
EE303A Digital System Verilog Simulator Tutorial

 Write Verilog code for Majority module.

20
EE303A Digital System Verilog Simulator Tutorial

 After that, we need an another Verilog file for testing

Majority module.

Add a new file

21
EE303A Digital System Verilog Simulator Tutorial

22
EE303A Digital System Verilog Simulator Tutorial

 Write Verilog code for test module.

23
EE303A Digital System Verilog Simulator Tutorial

 Compile the design.

24
EE303A Digital System Verilog Simulator Tutorial

Make sure there are no errors

25
EE303A Digital System Verilog Simulator Tutorial

 In case you have syntax errors in your code,

compile will fail.

Double-click to see this error report

26
EE303A Digital System Verilog Simulator Tutorial

 After successful compile, we start simulation.

Click Start Simulation

27
EE303A Digital System Verilog Simulator Tutorial

 Select the test module.

Select this

28
EE303A Digital System Verilog Simulator Tutorial

 You will see the layout has been changed.

29
 EE303A Digital System Verilog Simulator Tutorial

 We want to see waveforms of “count” and “out”

variable to verify the functionality of designed circuit.

Select
both
variables

Click Add Wave

30
EE303A Digital System Verilog Simulator Tutorial

 Wave window will show up. However, you will not be

able to see any waveforms.

31
EE303A Digital System Verilog Simulator Tutorial

 You have to run simulation to see waveforms.

Click Run -All

32
EE303A Digital System Verilog Simulator Tutorial

 Waveforms are generated now. Check if outputs are

correct for each input.

33
EE303A Digital System Verilog Simulator Tutorial

 A simple tutorial is provided to help you get used to

ModelSim-Altera.
 Refer “Using ModelSim to Simulate Logic Circuits in
Verilog Designs” if you want to get more details.
 It is also uploaded on the course webpage.

 Feel free to contact TAs if you have any trouble

using the simulator.

34