MC74HC4051A,

MC74HC4052A,
MC74HC4053A

Analog Multiplexers /
Demultiplexers
High–Performance Silicon–Gate CMOS http://onsemi.com

MARKING
The MC74HC4051A, MC74HC4052A and MC74HC4053A utilize DIAGRAMS
silicon–gate CMOS technology to achieve fast propagation delays,
16
low ON resistances, and low OFF leakage currents. These analog
PDIP–16
multiplexers/demultiplexers control analog voltages that may vary N SUFFIX HC405xAN
across the complete power supply range (from VCC to VEE). 16 AWLYYWW
CASE 648
The HC4051A, HC4052A and HC4053A are identical in pinout to 1
1
the metal–gate MC14051AB, MC14052AB and MC14053AB. The 16
Channel–Select inputs determine which one of the Analog SO–16
Inputs/Outputs is to be connected, by means of an analog switch, to the HC405xAD
D SUFFIX
16 AWLYYWW
Common Output/Input. When the Enable pin is HIGH, all analog CASE 751B
1
switches are turned off. 1
The Channel–Select and Enable inputs are compatible with standard 16
CMOS outputs; with pullup resistors they are compatible with LSTTL SO–16 WIDE
outputs. HC405xA
16 DW SUFFIX
AWLYWW
These devices have been designed so that the ON resistance (Ron) is CASE 751G
more linear over input voltage than Ron of metal–gate CMOS analog 1 1
switches. 16
For a multiplexer/demultiplexer with injection current protection,
see HC4851A and HC4852A. TSSOP–16 HC40
5xA
• Fast Switching and Propagation Speeds 16 DT SUFFIX
CASE 948F ALYW
• Low Crosstalk Between Switches 1
1
• Diode Protection on All Inputs/Outputs 16
• Analog Power Supply Range (VCC – VEE) = 2.0 to 12.0 V SOEIAJ–16
• Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V 16
F SUFFIX 74HC405xA
ALYW
• Improved Linearity and Lower ON Resistance Than Metal–Gate 1
CASE 966

Counterparts 1
• Low Noise A = Assembly Location
• In Compliance With the Requirements of JEDEC Standard No. 7A WL = Wafer Lot
YY = Year
• Chip Complexity: HC4051A — 184 FETs or 46 Equivalent Gates WW = Work Week
HC4052A — 168 FETs or 42 Equivalent Gates
HC4053A — 156 FETs or 39 Equivalent Gates
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.

 Semiconductor Components Industries, LLC, 2000 1 Publication Order Number:

March, 2000 – Rev. 1 MC74HC4051A/D
 MC74HC4051A, MC74HC4052A, MC74HC4053A

FUNCTION TABLE – MC74HC4051A

LOGIC DIAGRAM Control Inputs
MC74HC4051A Select
Single–Pole, 8–Position Plus Common Off Enable C B A ON Channels

13
L L L L X0
X0 L L L H X1
14
X1 L L H L X2
15 3 COMMON L L H H X3
X2 X
ANALOG 12 OUTPUT/ L H L L X4
INPUTS/ X3 MULTIPLEXER/ INPUT L H L H X5
OUTPUTS X4 1 DEMULTIPLEXER
L H H L X6
5
X5 L H H H X7
2 H X X X NONE
X6
4
X7 X = Don’t Care
11
A
CHANNEL 10
SELECT B Pinout: MC74HC4051A (Top View)
INPUTS 9 VCC X2 X1 X0 X3 A B C
C
6
ENABLE 16 15 14 13 12 11 10 9
PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND

1 2 3 4 5 6 7 8
X4 X6 X X7 X5 Enable VEE GND

FUNCTION TABLE – MC74HC4052A

LOGIC DIAGRAM Control Inputs
MC74HC4052A
Select
Double–Pole, 4–Position Plus Common Off
Enable B A ON Channels
12
X0 L L L Y0 X0
14
X1 13 L L H Y1 X1
15 X SWITCH X
X2 L H L Y2 X2
11 L H H Y3 X3
X3
ANALOG COMMON H X X NONE
INPUTS/OUTPUTS 1 OUTPUTS/INPUTS
Y0 X = Don’t Care
5 3
Y1 Y SWITCH Y
2
Y2
4
Y3 Pinout: MC74HC4052A (Top View)
10
CHANNEL-SELECT A VCC X2 X1 X X0 X3 A B
9 PIN 16 = VCC
INPUTS B
PIN 7 = VEE 16 15 14 13 12 11 10 9
PIN 8 = GND
6
ENABLE

1 2 3 4 5 6 7 8
Y0 Y2 Y Y3 Y1 Enable VEE GND

http://onsemi.com
2
 MC74HC4051A, MC74HC4052A, MC74HC4053A

FUNCTION TABLE – MC74HC4053A

Control Inputs
LOGIC DIAGRAM
MC74HC4053A Select
Triple Single–Pole, Double–Position Plus Common Off Enable C B A ON Channels
L L L L Z0 Y0 X0
12 L L L H Z0 Y0 X1
X0 14
13 X SWITCH X L L H L Z0 Y1 X0
X1 L L H H Z0 Y1 X1
L H L L Z1 Y0 X0
2 L H L H Z1 Y0 X1
Y0 15 COMMON
ANALOG 1 Y SWITCH Y L H H L Z1 Y1 X0
INPUTS/OUTPUTS Y1 OUTPUTS/INPUTS
L H H H Z1 Y1 X1
H X X X NONE
5
Z0 4
3 Z SWITCH Z X = Don’t Care
Z1
11
A
CHANNEL-SELECT 10 PIN 16 = VCC
INPUTS B
9 PIN 7 = VEE Pinout: MC74HC4053A (Top View)
C PIN 8 = GND
6 VCC Y X X1 X0 A B C
ENABLE
16 15 14 13 12 11 10 9
NOTE: This device allows independent control of each switch.
Channel–Select Input A controls the X–Switch, Input B controls
the Y–Switch and Input C controls the Z–Switch

1 2 3 4 5 6 7 8
Y1 Y0 Z1 Z Z0 Enable VEE GND

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit This device contains protection
circuitry to guard against damage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC Positive DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V
(Referenced to VEE) – 0.5 to + 14.0 due to high static voltages or electric

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
fields. However, precautions must
VEE Negative DC Supply Voltage (Referenced to GND) – 7.0 to + 5.0 V be taken to avoid applications of any

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
voltage higher than maximum rated
VIS Analog Input Voltage VEE – 0.5 to V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
voltages to this high–impedance cir-
VCC + 0.5
cuit. For proper operation, Vin and

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vout should be constrained to the
v v
Vin Digital Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
range GND (Vin or Vout) VCC.
I DC Current, Into or Out of Any Pin ± 25 mA Unused inputs must always be

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
EIAJ/SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450 Unused outputs must be left open.

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Tstg
ÎÎÎÎÎ
ÎÎÎ
Storage Temperature Range – 65 to + 150 _C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL

ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ
ÎÎÎ
Plastic DIP, SOIC or TSSOP Package
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
EIAJ/SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

http://onsemi.com
3
 MC74HC4051A, MC74HC4052A, MC74HC4053A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Symbol ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎ
ÎÎÎ
Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC Positive DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
(Referenced to VEE) 2.0 12.0

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VEE Negative DC Supply Voltage, Output (Referenced to – 6.0 GND V
GND)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VIS
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin
ÎÎÎÎÎ
ÎÎÎ
Analog Input Voltage

ÎÎ
ÎÎÎ
Digital Input Voltage (Referenced to GND)
VEE
GND
VCC
VCC
V
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VIO*

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA
ÎÎÎÎÎ
ÎÎÎ
Static or Dynamic Voltage Across Switch

ÎÎ
ÎÎÎ
Operating Temperature Range, All Package Types – 55
1.2
+ 125
V
_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
tr, tf
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Input Rise/Fall Time

ÎÎÎ
ÎÎ
(Channel Select or Enable Inputs)
VCC = 2.0 V
VCC = 3.0 V
0
0
1000
600
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC = 4.5 V 0 500
VCC = 6.0 V 0 400
*For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be
drawn; i.e., the current out of the switch may contain both VCC and switch input components.
The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted
Guaranteed Limit
VCC
Symbol Parameter Condition V –55 to 25°C ≤85°C ≤125°C Unit
VIH Minimum High–Level Input Ron = Per Spec 2.0 1.50 1.50 1.50 V
Voltage, Channel–Select or 3.0 2.10 2.10 2.10
Enable Inputs 4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
VIL Maximum Low–Level Input Ron = Per Spec 2.0 0.5 0.5 0.5 V
Voltage, Channel–Select or 3.0 0.9 0.9 0.9
Enable Inputs 4.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8
Iin Maximum Input Leakage Current, Vin = VCC or GND, 6.0 ± 0.1 ± 1.0 ± 1.0 µA
Channel–Select or Enable Inputs VEE = – 6.0 V
ICC Maximum Quiescent Supply Channel Select, Enable and µA
Current (per Package) VIS = VCC or GND; VEE = GND 6.0 1 10 20
VIO = 0 V VEE = – 6.0 6.0 4 40 80
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

http://onsemi.com
4
 MC74HC4051A, MC74HC4052A, MC74HC4053A

DC CHARACTERISTICS — Analog Section

Guaranteed Limit
Symbol Parameter Condition VCC VEE –55 to 25°C ≤85°C ≤125°C Unit
Ron Maximum “ON” Resistance Vin = VIL or VIH; VIS = VCC to 4.5 0.0 190 240 280 Ω
VEE; IS ≤ 2.0 mA 4.5 – 4.5 120 150 170
(Figures 1, 2) 6.0 – 6.0 100 125 140
Vin = VIL or VIH; VIS = VCC or 4.5 0.0 150 190 230
VEE (Endpoints); IS ≤ 2.0 mA 4.5 – 4.5 100 125 140
(Figures 1, 2) 6.0 – 6.0 80 100 115
∆Ron Maximum Difference in “ON” Vin = VIL or VIH; 4.5 0.0 30 35 40 Ω
Resistance Between Any Two VIS = 1/2 (VCC – VEE); 4.5 – 4.5 12 15 18
Channels in the Same Package IS ≤ 2.0 mA 6.0 – 6.0 10 12 14
Ioff Maximum Off–Channel Leakage Vin = VIL or VIH; µA
Current, Any One Channel VIO = VCC – VEE; 6.0 – 6.0 0.1 0.5 1.0
Switch Off (Figure 3)
Maximum Off–Channel HC4051A Vin = VIL or VIH; 6.0 – 6.0 0.2 2.0 4.0
Leakage Current, HC4052A VIO = VCC – VEE; 6.0 – 6.0 0.1 1.0 2.0
Common Channel HC4053A Switch Off (Figure 4) 6.0 – 6.0 0.1 1.0 2.0
Ion Maximum On–Channel HC4051A Vin = VIL or VIH; 6.0 – 6.0 0.2 2.0 4.0 µA
Leakage Current, HC4052A Switch–to–Switch = 6.0 – 6.0 0.1 1.0 2.0
Channel–to–Channel HC4053A VCC – VEE; (Figure 5) 6.0 – 6.0 0.1 1.0 2.0

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit
VCC
Symbol Parameter V –55 to 25°C ≤85°C ≤125°C Unit
tPLH, Maximum Propagation Delay, Channel–Select to Analog Output 2.0 270 320 350 ns
tPHL (Figure 9) 3.0 90 110 125
4.5 59 79 85
6.0 45 65 75
tPLH, Maximum Propagation Delay, Analog Input to Analog Output 2.0 40 60 70 ns
tPHL (Figure 10) 3.0 25 30 32
4.5 12 15 18
6.0 10 13 15
tPLZ, Maximum Propagation Delay, Enable to Analog Output 2.0 160 200 220 ns
tPHZ (Figure 11) 3.0 70 95 110
4.5 48 63 76
6.0 39 55 63
tPZL, Maximum Propagation Delay, Enable to Analog Output 2.0 245 315 345 ns
tPZH (Figure 11) 3.0 115 145 155
4.5 49 69 83
6.0 39 58 67
Cin Maximum Input Capacitance, Channel–Select or Enable Inputs 10 10 10 pF
CI/O Maximum Capacitance Analog I/O 35 35 35 pF
(All Switches Off) Common O/I: HC4051A 130 130 130
HC4052A 80 80 80
HC4053A 50 50 50
Feedthrough 1.0 1.0 1.0
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D)
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD Power Dissipation Capacitance (Figure 13)* HC4051A 45 pF
HC4052A 80
HC4053A 45
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).

http://onsemi.com
5
 MC74HC4051A, MC74HC4052A, MC74HC4053A

ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)

Limit*
VCC VEE
Symbol Parameter Condition V V 25°C Unit
BW Maximum On–Channel Bandwidth fin = 1MHz Sine Wave; Adjust fin Voltage to ‘51 ‘52 ‘53 MHz
or Minimum
Mi i Frequency
F Response
R Obt i 0dBm
Obtain 0dB att VOS; Increase
I fin
2.25 –2.25 80 95 120
(Figure 6) Frequency Until dB Meter Reads –3dB;
4.50 –4.50 80 95 120
RL = 50Ω, CL = 10pF
6.00 –6.00 80 95 120
— Off–Channel Feedthrough Isolation fin = Sine Wave; Adjust fin Voltage to 2.25 –2.25 –50 dB
(Figure 7) Obtain 0dBm at VIS 4.50 –4.50 –50
fin = 10kHz, RL = 600Ω, CL = 50pF 6.00 –6.00 –50
2.25 –2.25 –40
4.50 –4.50 –40
fin = 1.0MHz, RL = 50Ω, CL = 10pF 6.00 –6.00 –40
— Feedthrough Noise. Vin ≤ 1MHz Square Wave (tr = tf = 6ns); 2.25 –2.25 25 mVPP
Channel–Select Input to Common Adjust RL at Setup so that IS = 0A; 4.50 –4.50 105
I/O (Figure 8) Enable = GND RL = 600Ω, CL = 50pF 6.00 –6.00 135
2.25 –2.25 35
4.50 –4.50 145
RL = 10kΩ, CL = 10pF 6.00 –6.00 190
— Crosstalk Between Any Two fin = Sine Wave; Adjust fin Voltage to 2.25 –2.25 –50 dB
Switches (Figure 12) Obtain 0dBm at VIS 4.50 –4.50 –50
(Test does not apply to HC4051A) fin = 10kHz, RL = 600Ω, CL = 50pF 6.00 –6.00 –50
2.25 –2.25 –60
4.50 –4.50 –60
fin = 1.0MHz, RL = 50Ω, CL = 10pF 6.00 –6.00 –60
THD Total Harmonic Distortion fin = 1kHz, RL = 10kΩ, CL = 50pF %
(Figure 14) THD = THDmeasured – THDsource
VIS = 4.0VPP sine wave 2.25 –2.25 0.10
VIS = 8.0VPP sine wave 4.50 –4.50 0.08
VIS = 11.0VPP sine wave 6.00 –6.00 0.05
*Limits not tested. Determined by design and verified by qualification.

300 180
160
250
Ron , ON RESISTANCE (OHMS)

Ron , ON RESISTANCE (OHMS)

140
200 120
125°C 125°C
100
150
25°C 80
25°C
– 55°C
100 60
40 – 55°C
50
20
0 0
0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 2.5 2.75 3.0
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

Figure 1a. Typical On Resistance, VCC – VEE = 2.0 V Figure 1b. Typical On Resistance, VCC – VEE = 3.0 V

http://onsemi.com
6
 MC74HC4051A, MC74HC4052A, MC74HC4053A

120 105

100 90
Ron , ON RESISTANCE (OHMS)

Ron , ON RESISTANCE (OHMS)

75 125°C
80
125°C
60
60 25°C
25°C 45
– 55°C
40
– 55°C 30

20 15

0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

Figure 1c. Typical On Resistance, VCC – VEE = 4.5 V Figure 1d. Typical On Resistance, VCC – VEE = 6.0 V

80 60

70
50
Ron , ON RESISTANCE (OHMS)

60 Ron , ON RESISTANCE (OHMS) 125°C

40
50 25°C
125°C
40 30
– 55°C
30 25°C
20
20 – 55°C
10
10
0 0
–4.5 –3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5 –6.0 –5.0 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 5.0 6.0
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

Figure 1e. Typical On Resistance, VCC – VEE = 9.0 V Figure 1f. Typical On Resistance, VCC – VEE = 12.0 V

PLOTTER

PROGRAMMABLE
POWER MINI COMPUTER DC ANALYZER
SUPPLY
– + VCC
DEVICE
UNDER TEST

ANALOG IN COMMON OUT

GND VEE

Figure 2. On Resistance Test Set–Up

http://onsemi.com
7
 MC74HC4051A, MC74HC4052A, MC74HC4053A

VCC VCC

VCC VCC
VEE 16 VEE 16
ANALOG I/O
OFF OFF
VCC A VCC
NC OFF COMMON O/I OFF COMMON O/I

VIH 6 VIH 6
7 7
8 8
VEE VEE

Figure 3. Maximum Off Channel Leakage Current, Figure 4. Maximum Off Channel Leakage Current,
Any One Channel, Test Set–Up Common Channel, Test Set–Up

VCC VOS
VCC VCC
A 16 0.1µF 16 dB
ON fin ON METER
VEE N/C CL* RL
OFF COMMON O/I
VCC ANALOG I/O

VIL 6 6
7 7
8 8
VEE VEE
*Includes all probe and jig capacitance

Figure 5. Maximum On Channel Leakage Current, Figure 6. Maximum On Channel Bandwidth,

Channel to Channel, Test Set–Up Test Set–Up

VIS VCC VOS VCC

0.1µF 16 dB 16
RL
fin OFF METER ON/OFF COMMON O/I
TEST
RL CL* RL ANALOG I/O
POINT
OFF/ON RL CL*
RL

6 6
7 7 VCC
8 Vin ≤ 1 MHz 8 11
tr = tf = 6 ns
VEE VCC VEE
CHANNEL SELECT CHANNEL SELECT
VIL or VIH GND
*Includes all probe and jig capacitance *Includes all probe and jig capacitance

Figure 7. Off Channel Feedthrough Isolation, Figure 8. Feedthrough Noise, Channel Select to
Test Set–Up Common Out, Test Set–Up

http://onsemi.com
8
 MC74HC4051A, MC74HC4052A, MC74HC4053A

VCC
VCC
16
VCC
CHANNEL ON/OFF COMMON O/I
50% TEST
SELECT ANALOG I/O
POINT
OFF/ON CL*
GND
tPLH tPHL

6
ANALOG 7
OUT 50%
8

CHANNEL SELECT

*Includes all probe and jig capacitance

Figure 9a. Propagation Delays, Channel Select Figure 9b. Propagation Delay, Test Set–Up Channel
to Analog Out Select to Analog Out

VCC
16
ANALOG I/O COMMON O/I
VCC TEST
ON
ANALOG POINT
IN 50% CL*
GND
tPLH tPHL
6
7
ANALOG 8
OUT 50%

*Includes all probe and jig capacitance

Figure 10a. Propagation Delays, Analog In Figure 10b. Propagation Delay, Test Set–Up
to Analog Out Analog In to Analog Out

tf tr POSITION 1 WHEN TESTING tPHZ AND tPZH

VCC 1 POSITION 2 WHEN TESTING tPLZ AND tPZL
90%
ENABLE 50% 2
VCC
10%
GND VCC 1kΩ
tPZL tPLZ 16
HIGH 1 ANALOG I/O
IMPEDANCE TEST
ANALOG 2 ON/OFF
50% POINT
OUT 10% CL*
VOL
tPZH tPHZ
ENABLE
VOH 6
90%
ANALOG 7
OUT 50% 8
HIGH
IMPEDANCE

Figure 11a. Propagation Delays, Enable to Figure 11b. Propagation Delay, Test Set–Up
Analog Out Enable to Analog Out

http://onsemi.com
9
 MC74HC4051A, MC74HC4052A, MC74HC4053A

VCC
VIS A
VCC
16 16
RL VOS
fin ON ON/OFF COMMON O/I
ANALOG I/O NC
0.1µF OFF/ON

OFF
VEE RL CL* RL CL* VCC
RL 6
7
6 VEE 8 11
7
8 CHANNEL SELECT

*Includes all probe and jig capacitance

Figure 12. Crosstalk Between Any Two Figure 13. Power Dissipation Capacitance,
Switches, Test Set–Up Test Set–Up

0
VIS
VCC VOS – 10 FUNDAMENTAL FREQUENCY
0.1µF 16 – 20
TO
fin ON DISTORTION – 30
RL METER
CL* – 40
dB

– 50
DEVICE
– 60
6 SOURCE
– 70
7
8 – 80
VEE – 90
*Includes all probe and jig capacitance
– 100
1.0 2.0 3.125
FREQUENCY (kHz)

Figure 14a. Total Harmonic Distortion, Test Set–Up Figure 14b. Plot, Harmonic Distortion

APPLICATIONS INFORMATION

The Channel Select and Enable control pins should be at outputs to VCC or GND through a low value resistor helps
VCC or GND logic levels. VCC being recognized as a logic minimize crosstalk and feedthrough noise that may be
high and GND being recognized as a logic low. In this picked up by an unused switch.
example: Although used here, balanced supplies are not a
VCC = +5V = logic high requirement. The only constraints on the power supplies are
GND = 0V = logic low that:
The maximum analog voltage swings are determined by VCC – GND = 2 to 6 volts
the supply voltages VCC and VEE. The positive peak analog VEE – GND = 0 to –6 volts
voltage should not exceed VCC. Similarly, the negative peak VCC – VEE = 2 to 12 volts
analog voltage should not go below VEE. In this example, and VEE ≤ GND
the difference between VCC and VEE is ten volts. Therefore, When voltage transients above VCC and/or below VEE are
using the configuration of Figure 15, a maximum analog anticipated on the analog channels, external Germanium or
signal of ten volts peak–to–peak can be controlled. Unused Schottky diodes (Dx) are recommended as shown in Figure
analog inputs/outputs may be left floating (i.e., not 16. These diodes should be able to absorb the maximum
connected). However, tying unused analog inputs and anticipated current surges during clipping.

http://onsemi.com
10
 MC74HC4051A, MC74HC4052A, MC74HC4053A

VCC VCC
+5V VCC
16 Dx 16 Dx
+5V +5V
ANALOG ANALOG
ON ON/OFF
–5V SIGNAL SIGNAL –5V
Dx Dx

VEE VEE

6 11 TO EXTERNAL CMOS
7 10 CIRCUITRY 0 to 5V 7
8 9 DIGITAL SIGNALS 8
–5V VEE

Figure 15. Application Example Figure 16. External Germanium or

Schottky Clipping Diodes

+5V +5V

+5V 16 +5V +5V 16 +5V

ANALOG ANALOG ANALOG ANALOG
ON/OFF ON/OFF
VEE SIGNAL SIGNAL VEE VEE SIGNAL SIGNAL VEE
+5V
*
R R R +5V
6 11 6 11
LSTTL/NMOS LSTTL/NMOS
7 10 7 10
CIRCUITRY CIRCUITRY
8 9 8 9
VEE VEE
* 2K ≤ R ≤ 10K HCT
BUFFER
a. Using Pull–Up Resistors b. Using HCT Interface
Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs

11 LEVEL 13
A X0
SHIFTER

14
X1

10 LEVEL 15
B X2
SHIFTER

12
X3

9 LEVEL 1
C X4
SHIFTER

5
X5

6 LEVEL 2
ENABLE X6
SHIFTER

4
X7

3
X
Figure 18. Function Diagram, HC4051A

http://onsemi.com
11
 MC74HC4051A, MC74HC4052A, MC74HC4053A

10 LEVEL 12
A X0
SHIFTER

14
X1

9 LEVEL 15
B X2
SHIFTER

11
X3
13
X
6 LEVEL 1
ENABLE Y0
SHIFTER

5
Y1

2
Y2

4
Y3

3
Y

Figure 19. Function Diagram, HC4052A

11 LEVEL 13
A X1
SHIFTER

12
X0
14
X
10 LEVEL 1
B Y1
SHIFTER

2
Y0
15
Y
9 LEVEL 3
C Z1
SHIFTER

5
Z0
4
Z
6 LEVEL
ENABLE
SHIFTER

Figure 20. Function Diagram, HC4053A

http://onsemi.com
12
 MC74HC4051A, MC74HC4052A, MC74HC4053A

ORDERING & SHIPPING INFORMATION

Device Package Shipping
MC74HC4051AN PDIP–16 500 Units / Unit Pak
MC74HC4051AD SOIC–16 48 Units / Rail
MC74HC4051ADR2 SOIC–16 2500 Units / Tape & Reel
MC74HC4051ADT TSSOP–16 96 Units / Rail
MC74HC4051ADTR2 TSSOP–16 2500 Units / Tape & Reel
MC74HC4051ADW SOIC WIDE 48 Units / Rail
MC74HC4051ADWR2 SOIC WIDE 1000 Units / Tape & Reel
MC74HC4051AF SOEIAJ–16 See Note 1.
MC74HC4051AFEL SOEIAJ–16 See Note 1.
MC74HC4052AN PDIP–16 500 Units / Unit Pak
MC74HC4052AD SOIC–16 48 Units / Rail
MC74HC4052ADR2 SOIC–16 2500 Units / Tape & Reel
MC74HC4052ADT TSSOP–16 96 Units / Rail
MC74HC4052ADTR2 TSSOP–16 2500 Units / Tape & Reel
MC74HC4052ADW SOIC WIDE 48 Units / Rail
MC74HC4052ADWR2 SOIC WIDE 1000 Units / Tape & Reel
MC74HC4052AF SOEIAJ–16 See Note 1.
MC74HC4052AFEL SOEIAJ–16 See Note 1.
MC74HC4053AN PDIP–16 500 Units / Unit Pak
MC74HC4053AD SOIC–16 48 Units / Rail
MC74HC4053ADR2 SOIC–16 2500 Units / Tape & Reel
MC74HC4053ADT TSSOP–16 96 Units / Rail
MC74HC4053ADTR2 TSSOP–16 2500 Units / Tape & Reel
MC74HC4053ADW SOIC WIDE 48 Units / Rail
MC74HC4053ADWR2 SOIC WIDE 1000 Units / Tape & Reel
MC74HC4053AF SOEIAJ–16 See Note 1.
MC74HC4053AFEL SOEIAJ–16 See Note 1.
1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.

http://onsemi.com
13
 MC74HC4051A, MC74HC4052A, MC74HC4053A

PACKAGE DIMENSIONS

PDIP–16
N SUFFIX
CASE 648–08
ISSUE R
–A NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
– Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 8 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
F DIM MIN MAX MIN MAX
C L A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
SEATING F 0.040 0.070 1.02 1.77
–T PLANE G 0.100 BSC 2.54 BSC
– H 0.050 BSC 1.27 BSC
K M J
H J 0.008 0.015 0.21 0.38
G K 0.110 0.130 2.80 3.30
D 16 PL L 0.295 0.305 7.50 7.74
M 0° 10° 0° 10°
0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01

SOIC–16
D SUFFIX
CASE 751B–05
ISSUE J
–A
– NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16 9 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
–B MOLD PROTRUSION.
P 8 PL 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
–
1 8 0.25 (0.010) M B M PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
G MAXIMUM MATERIAL CONDITION.

MILLIMETERS INCHES
DIM MIN MAX MIN MAX
F A 9.80 10.00 0.386 0.393
K R X 45° B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
C F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
–T
–
SEATING M J J 0.19 0.25 0.008 0.009
PLANE K 0.10 0.25 0.004 0.009
D 16 PL M 0° 7° 0° 7°
0.25 (0.010) M T B S A S P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

http://onsemi.com
14
 MC74HC4051A, MC74HC4052A, MC74HC4053A

PACKAGE DIMENSIONS

SOIC–16 WIDE
DW SUFFIX
CASE 751G–03
ISSUE B
D A
q
16 9 NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
M

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.
B

3. DIMENSIONS D AND E DO NOT INLCUDE MOLD

H

h X 45 _
M

PROTRUSION.

E
8X

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

0.25

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
1 8 CONDITION.

MILLIMETERS
16X B B DIM MIN MAX
A 2.35 2.65
0.25 M T A S B S A1 0.10 0.25
B 0.35 0.49
C 0.23 0.32
D 10.15 10.45
E 7.40 7.60
A

e 1.27 BSC
H 10.05 10.55
L h 0.25 0.75
SEATING
14X e PLANE L 0.50 0.90
q 0_ 7_
A1

T C

TSSOP–16
DT SUFFIX
CASE 948F–01
ISSUE O
16X K REF

0.10 (0.004) M T U S V S
NOTES:
0.15 (0.006) T U S
K 1. DIMENSIONING AND TOLERANCING PER ANSI

ÉÉÉ
ÇÇÇ
Y14.5M, 1982.
K1 2. CONTROLLING DIMENSION: MILLIMETER.

ÇÇÇ
ÉÉÉ
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
16 9 PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
2X L/2

ÇÇÇ
J1 GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
B SECTION N–N FLASH OR PROTRUSION. INTERLEAD FLASH OR
L PROTRUSION SHALL NOT EXCEED
–U– 0.25 (0.010) PER SIDE.
J
PIN 1 5. DIMENSION K DOES NOT INCLUDE DAMBAR
IDENT. PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
1 8 DIMENSION AT MAXIMUM MATERIAL CONDITION.
N 6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
0.25 (0.010) 7. DIMENSION A AND B ARE TO BE DETERMINED AT
0.15 (0.006) T U S DATUM PLANE –W–.
A M
MILLIMETERS INCHES
–V–
DIM MIN MAX MIN MAX
N A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
F C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
DETAIL E F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
C –W– K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
0.10 (0.004) M 0_ 8_ 0_ 8_
–T– SEATING H DETAIL E
PLANE D G

http://onsemi.com
15
 MC74HC4051A, MC74HC4052A, MC74HC4053A

PACKAGE DIMENSIONS

SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01 NOTES:
ISSUE O 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
16 9 LE MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
Q1 OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
E HE M_ 4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
1 8 L DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DETAIL P DIMENSION AT MAXIMUM MATERIAL CONDITION.
Z DAMBAR CANNOT BE LOCATED ON THE LOWER
D RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
VIEW P
e A MILLIMETERS INCHES
c DIM MIN MAX MIN MAX
A ––– 2.05 ––– 0.081
A1 0.05 0.20 0.002 0.008
b 0.35 0.50 0.014 0.020
c 0.18 0.27 0.007 0.011
A1 D 9.90 10.50 0.390 0.413
b E 5.10 5.45 0.201 0.215
e 1.27 BSC 0.050 BSC
0.13 (0.005) M 0.10 (0.004) HE 7.40 8.20 0.291 0.323
L 0.50 0.85 0.020 0.033
LE 1.10 1.50 0.043 0.059
M 0_ 10 _ 0_ 10 _
Q1 0.70 0.90 0.028 0.035
Z ––– 0.78 ––– 0.031

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

NORTH AMERICA Literature Fulfillment: CENTRAL/SOUTH AMERICA:
Literature Distribution Center for ON Semiconductor Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)
P.O. Box 5163, Denver, Colorado 80217 USA Email: ONlit–spanish@hibbertco.com
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support
Email: ONlit@hibbertco.com Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)
Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada Toll Free from Hong Kong & Singapore:
001–800–4422–3781
N. American Technical Support: 800–282–9855 Toll Free USA/Canada Email: ONlit–asia@hibbertco.com

EUROPE: LDC for ON Semiconductor – European Support
German Phone: (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich Time)
Email: ONlit–german@hibbertco.com
French Phone: (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse Time)
Email: ONlit–french@hibbertco.com
English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time)
Email: ONlit@hibbertco.com
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549
Phone: 81–3–5740–2745
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com

EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781 For additional information, please contact your local
*Available from Germany, France, Italy, England, Ireland Sales Representative.

http://onsemi.com MC74HC4051A/D
16