Digital electronics

 Synchronous circuits:

In synchronous circuits the input are pulses (or levels and pulses) with certain restrictions on pulse width
and circuit propagation delay. Therefore synchronous circuits can be divided into clocked sequential circuits
and uncklocked or pulsed sequential circuits.

In a clocked sequential circuit which has flip-flops or, in some instances, gated latches, for its memory elements
there is a (synchronizing) periodic clock connected to the clock inputs of all the memory elements of the circuit, to
synchronize all internal changes of state.

Hence the operation of the entire circuit is controlled and synchronized by the periodic pulses of the clock.

 Asynchronous circuits:

The circuit is considered to be asynchronous if it does not employ a periodic clock signal C to synchronize
its internal changes of state. Therefore the state changes occur in direct response to signal changes on primary
(data) input lines, and different memory elements can change state at different times.

In asynchronous sequential circuits the inputs are levels and there are no clock pulses; the inputs events drive
the circuit.

In general, an asynchronous circuit does not need the precise timing control supported by flip-flops. It may
therefore contain latches rather than flip-flops. In many cases, an asynchronous circuit simply relies on the
propagation delays of its component gates and connections, combined with the circuit’s feedback structure, to
implement its memory functions

Up-Down Counter

Counters are used in many different applications. Some count up from zero and provide a change in state of
output upon reaching a predetermined value; others count down from a preset value to zero to provide an output
state change.

However, some counters can operate in both up and down count mode, depending on the state of an up/down
count mode input pin. They can be reversed at any point within their count sequence. Dual purpose ICs such as
the TTL 74LS190 and 75LS191 are available which implement both Up and Down count functions.

The TTL 74LS190 is a 4-bit device that can be switched between Up and Down modes, and provides a BCD
decade output; the 74LS191 is a binary counter. The counters are synchronous, but they are asynchronously
presettable. Four data inputs (A – D) allow the preset target to be loaded. The counter is decremented or
incremented synchronously with the low to high transition of the clock. The counters can be cascaded in high-
speed mode.

A simple three-bit Up/Down synchronous counter can be built using JK flip-flops configured to operate as toggle
or T-type flip-flops giving a maximum count of zero (000), advancing through 001, 010 to seven (111) and back to
zero again.

This sequential device loads the data present on its inputs and then moves or “shifts” it to its output once every
clock cycle, hence the name Shift Register.
A shift register basically consists of several single bit “D-Type Data Latches”, one for each data bit, either a logic
“0” or a “1”, connected together in a serial type daisy-chain arrangement so that the output from one data latch
becomes the input of the next latch and so on.
 Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit at a time, with the stored
data being available at the output in parallel form.
 Serial-in to Serial-out (SISO) - the data is shifted serially “IN” and “OUT” of the register, one bit at a time
in either a left or right direction under clock control.
 Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register simultaneously and is shifted
out of the register serially one bit at a time under clock control.
 Parallel-in to Parallel-out (PIPO) - the parallel data is loaded simultaneously into the register, and
transferred together to their respective outputs by the same clock pulse.

 Error detection codes − are used to detect the error(s) present in the received data (bit stream).
These codes contain some bit(s), which are included (appended) to the original bit stream. These
codes detect the error, if it is occurred during transmission of the original data (bit stream).Example −
Parity code, Hamming code.

 Error correction codes − are used to correct the error(s) present in the received data (bit stream) so
that, we will get the original data. Error correction codes also use the similar strategy of error detection
codes.Example − Hamming code
Error Correcting Codes

The codes which are used for both error detecting and error correction are called as “Error Correction Codes”.
The error correction techniques are of two types. They are,

 Single bit error correction

 Burst error correction

The process or method of correcting single bit errors is called “single bit error correction”. The method of
detecting and correcting burst errors in the data sequence is called “Burst error correction”.

Error detection is the process of detecting the errors that are present in the data transmitted from transmitter to
receiver, in a communication system. We use some redundancy codes to detect these errors, by adding to the
data while it is transmitted from source (transmitter). These codes are called “Error detecting codes”.

Types of Error detection

1. Parity Checking
2. Cyclic Redundancy Check (CRC)
3. Longitudinal Redundancy Check (LRC)
4. Check Sum

Flip flops are actually an application of logic gates. With the help of Boolean logic you can create memory with
them. Flip flops can also be considered as the most basic idea of a Random Access Memory [RAM]. When a
certain input value is given to them, they will be remembered and executed, if the logic gates are designed
correctly. A higher application of flip flops is helpful in designing better electronic circuits.
SR Flip Flopt

There are majorly 4 types of flip flops, with the most common one being SR flip flop. As shown above, it

is the simplest and the easiest to understand. The two outputs as shown above are the inverse of each

other. The outputs of an SR flip flop are highlighted in the table below.

JK Flip-flop

Due to the undefined state in the SR flip flop, another is required in electronics. The JK flip flop is an

improvement on the SR flip flop where S=R=1 is not a problem.he input condition of J=K=1, gives an

output inverting the output state. However, the outputs are the same when one tests the circuit

practically.

D Flip Flop

D flip flop is a better alternative that is very popular with digital electronics. They are commonly used for counters

and shift-registers and input synchronisation.

In a D flip flop, the output can be only changed at the clock edge, and if the input changes at other times, the

output will be unaffected.

T Flip Flop

A T flip flop is like JK flip-flop. These are basically a single input version of JK flip flop. This modified form of JK

flip-flop is obtained by connecting both inputs J and K together. This flip-flop has only one input along with the

clock input.

T Flip-Flop

These flip-flops are called T flip-flops because of their ability to complement its state (i.e.) Toggle, hence the

name Toggle flip-flop.

The serial binary adder or bit-serial adder is a digital circuit that performs binary addition bit by bit. The
serial full adder has three single-bit inputs for the numbers to be added and the carry in. There are two single-bit
outputs for the sum and carry out. The carry-in signal is the previously calculated carry-out signal. The addition is
performed by adding each bit, lowest to highest, one per clock cycle.
Serial binary addition

Serial binary addition is done by a flip-flop and a full adder. The flip-flop takes the carry-out signal on each clock
cycle and provides its value as the carry-in signal on the next clock cycle. After all of the bits of the input
operands have arrived, all of the bits of the sum have come out of the sum output.

Half Adder

Half adder is a combinational logic circuit with two inputs and two outputs. The half adder circuit is designed to
add two single bit binary number A and B. It is the basic building block for addition of two single bit numbers.
This circuit has two outputs carry and sum

Full Adder

Full adder is developed to overcome the drawback of Half Adder circuit. It can add two one-bit numbers A and
B, and carry c. The full adder is a three input and two output combinational circuit.
Carry Look-ahead Adder :
A carry look-ahead adder reduces the propagation delay by introducing more complex hardware. In this design,
the ripple carry design is suitably transformed such that the carry logic over fixed groups of bits of the adder is
reduced to two-level logic. Let us discuss the design in detail.
Half Subtractors

Half subtractor is a combination circuit with two inputs and two outputs (difference and borrow). It produces the
difference between the two binary bits at the input and also produces an output (Borrow) to indicate if a 1 has
been borrowed. In the subtraction (A-B), A is called as Minuend bit and B is called as Subtrahend bit.

Full Subtractors

The disadvantage of a half subtractor is overcome by full subtractor. The full subtractor is a combinational circuit
with three inputs A,B,C and two output D and C'. A is the 'minuend', B is 'subtrahend', C is the 'borrow' produced
by the previous stage, D is the difference output and C' is the borrow output.
Code Converters
Numbers are usually coded in one form or another so as to represent or use it as required. For instance,
a number ‘nine’ is coded indecimal using symbol (9)d. Same is coded in natural-binary as (1001)b. While
digital computers all deal with binary numbers, there are situations wherein natural-binary representation
of numbers in in-convenient or in-efficient and some other (binary) code must be used to process the
numbers.

One of these other code is gray-code, in which any two numbers in sequence differ only by one bit
change. This code is used in K-map reduction technique. The advantage is that when numbers are
changing frequently, the logic gates are turning ON and OFF frequentlyand so are the transistors
switching which characterizes power consumption of the circuit; since only one bit is changing from
number to number, switching is reduced and hence is the power consumption.

Binary-to-Gray

The table that follows shows natural-binary numbers (upto 4-bit) and corresponding gray codes.

Looking at gray-code (G3G2G1G0), we find that any two subsequent numbers differ in only one bit-
change.

The same table is used as truth-table for designing a logic circuitry that converts a given 4-bit
natural binary number into gray number. For this circuit, B3 B2 B1 B0 are inputs while G3 G2 G1 G0 are
outputs.

Gray-to-Binary
Once the converted code (now in Gray form) is processed, we want the processed data back
in binary representation. So we need aconverter that would perform reverse operation to that of
earlier converter. This we call a Gray-to-Binary converter.

The design again starts from truth-table:

Decoders -
The decoders are used to decode binary information in a digital system. The input lines to a decoder are used to
feed binary data while based on the binary data, one of the output lines is selected which represents the
respective minterm. If a decoder has n input lines then, it can have maximum 2 n output lines. With n number of
input lines, the decoder can decode n-bit digital data. Like with 3 input lines, a decoder can decode 3-bit binary
data and so maximum 23 or 8 binary symbols. If there are some unused combinations in n-bit coded information,
the decoder can have fewer than 2n output lines. So, any decoder is n-to-m line decoder where m <= 2n.

In a decoder, each output line represents a minterm which is selected based on the input binary data. For any
input data only one output line is activated at a time. It can be noted that in a decoder, the number of output lines
is always greater than number of input lines. If the number of inputs and outputs in a decoder circuit are equal, it

is then called converter.\

De-Multiplexers -
De-Multiplexers are digital circuits that are used to transmit binary data from one line to many. The word
“demultiplexer” itself means one into many. So, Demultiplexing is the process of taking information from one input
and transmitting the same over one of several outputs. The demultiplexers have digital circuit similar to decoders
except that they have a single input line and have select lines to determine the output line for data transmission.
The data is transmitted over a single output line at a time. Like decoder, if a de-multiplexer has n select lines,
there can be 2n or less output lines controlled by them in a demultiplexer. A de-multiplexer can be represented by
the following block diagram –
Encoders -

The encoders are used for coding binary data. They are opposite to decoders. So, they perform inverse operation
of a decoder. The opposite of the decoding process is called encoding. The encoder is a combinational logic
circuit that converts an active input signal into a coded output signal.

It has n input lines, only one of which is active at any time and m output lines. It encodes one of the active inputs
to a coded binary output with m bits. In an encoder, the number of output lines is less than the number of inputs.
If an encoder has n input lines and m output lines than n<= 2 m. An encoder can be represented by the following
block diagram -
Multiplexers -

The multiplexers are used for routing digital data from many to one line. They convert parallel data into serial
data. The term multiplex itself means many to one. Multiplexing is the process of transmitting a large number of
information over a single line.

A digital multiplexer is a combinational circuit that selects single digital information from several resources and
transmits the selected information on a single output line. A multiplexer is also called a data selector, where it
selects one of many inputs and sends the information to the output. The multiplexers are similar to encoders
except that they have several data – input lines and a single output line. The selection of a particular input line is
controlled by a set of select lines. A multiplexer can be represented by the following block diagram -

Boolean Algebra
Boolean algebra, a logic algebra, allows the rules used in the algebra of numbers to be applied to logic. It
formalizes the rules of logic. Boolean algebra is used to simplify Boolean expressions which
represent combinational logic circuits. It reduces the original expression to an equivalent expression that has
fewer terms which means that less logic gates are needed to implement the combinational logic circuit.

Different Forms of Canonical Expression

There are two forms of canonical expression.

1. Sum of Products (SOP)

2. Product of Sums (POS)

Sum of Products (SOP)

A boolean expression consisting purely of Minterms (product terms) is said to be in canonical sum of products
form.

Product of Sums (POS)

A boolean expression consisting purely of Maxterms (sum terms) is said to be in canonical product of sums form