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MOSFET

Note to Professors and Students: Discussion given in the following, using three applet programs, on the metal-oxide-
semiconductor (MOS) field effect transistor (FET) is meant to supplement the traditional course materials of text books and
lectures. It is not intended to replace them. As such, this resource is best when used as part of lecture presentation, recitation,
or homework assignments.

In this exercise we use three applets to provide a visual simulation of the MOSFET physics. This text is an initial
draft.

1. MOS Electrostatics

If a bias voltage is applied to the Gate metal, relative to the silicon substrate, in excess of the Threshold
Voltage, Vt, then charge carriers are gethered in sufficient concentration under the Gate oxide. The type of
charge carriers conducting the channel current is opposite to the substrate. For example, if the substrate is p-type
silicon, then electrons are the channel charge; for n-type silicon substrate, it is the holes. This is due to the need to
separate electrically the MOSFET device from the silicon bulk.

In an n-channel MOS structure, fabricated on a p-type silicon substrate, a Gate bias Vg greater than Vt will
create an inversion n-channel under the gate oxide. The inversion layer charge, QN, is given by

QN = - Cox (Vg - Vt) for Vg >= Vt

where Cox is the capacitance of the oxide layer. In the following applet, the inversion n-channel is formed by
increasing Vg above Vt. The width of the inversion layer is on the order of 50 Angstrom. The increasing inversion
layer charge with increasing Gate bias voltage is illustrated in this applet.

For Vt = 1.0 Volts, a Gate bias Vg > 1.0 V will induce an n-channel. In the following applet, use the arrows next
to "Vg" to change the gate bias and observe when the n-channel is formed. You may change the threshold
voltage and see the effect on the necessary Gate bias voltage to induce an n-channel.

A p-channel MOS structure needs a bias voltage opposite to the n-channel MOS. Change the channel-type to
p-channel in the above applet. For Vt = -1 V, a gate bias Vg < -1 V shall induce a p-channel under the Gate.
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= -1 V, a gate bias Vg < -1 V shall induce a p-channel under the Gate.
That is, a Gate bias which is more negative than the Threshold Voltage will induce a sufficient concentration of
positive charge carriers in the channel region (inversion p-channel). Quatitatively, an inversion channel is formed if
the charge carrier concentration under the Gate is greater than or equal to the carrier concentration in the bulk.

A normally-off (or enhancement-mode) n-MOSFET has a positive Vt. At Vg = 0 V, the Vg is less positive than
Vt and thus no inversion n-channel is present. Likewise, a normally-off p-MOSFET has a negative Vt. The exact
value of Vt is important as it controls at what applied voltage the device is switched. Its value should be well
within the available battery source on the circuit.

The Threshold voltage of a MOS structure depends on the physical properties of the MOS structure such as the
kind of Gate metal, oxide thickness, and silicon doping level. It also depends on any fixed charge that may be
present between the Gate metal and the oxide. The complete theory is rather complicated and is a topic in other
applet pages.

This very simple applet is given here to acquaint you with the channel formation in MOS structure by an applied
Gate bias.

2. A MOSFET in Saturation or as a Triode.

Charge carriers in MOSFET originate in Source and flow into Drain. The total amount of charge that flows
depends on how much charge is injected into channel from Source. This is controlled by the Gate-Source bias,
Vgs. The drain current may or may not depend on the voltage drop between Source and Drain. The following
applet shows a visual simulation of the MOSFET characteristics as controlled by the Gate-Source bias, Vgs, and
the Gate-Drain bias, Vgd.

First, this applet demonstrates the facts that the inversion channel at the Source-end is controlled by Vgs, and at
the Drain-end by Vgd. For an n-channel MOSFET, the inversion channel is present at the Source-end of

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channel if Vgs > Vt, and is present at the Drain-end of channel if Vgd > Vt. Use the arrows next to these
voltages in the applet and observe that the blue n-channel is controlled at either end of the channel by these two
voltages, respectively.

n-MOSFET: (1) Triode If Vgs > Vt and Vgd > Vt, then the n-channel is continuous all the way from S to D.
The S and D are connected by a conductor (or a resistor) of a given resistance. The drain current increases if the
voltage drop between S and D increases. The channel resistance depends on how much charge is injected at the
S-end, which in turn is controlled by Vgs. The Drain current Id depends on both Vgs and Vgd (or Vds), and
thus we call thgis region of operation a Triode. (2) Saturation If Vgs > Vt and Vgd < Vt, then n-channel is
presen (or induced) at the S-end, but the channel is depleted at the D-end. That is, the n-channel is pinched off at
the Drain-end. What happens to all the electrons injected into channel from Source ? Think about it. [answer].
Once the drain-end of channel is pinched off, the current no longer depends on the voltage drop between S and
D (actually there is a small dependence of Id on Vds. Why ? What is this phenomenon called ? answer). (3)
Cutoff If Vgs < Vt (and of course, Vgd < Vt), then the no n-channel is present and no current flows.

p-MOSFET: The same discussion applies as in the NMOS case except that the inequality reverses between
Vgs (and Vgd) and Vt.

3. The Output Characteristics of MOSFET

n-MOSFET:

(1) Triode

For Vgs > Vt and Vds < Vds(sat) = Vgs - Vt (or equivalently, Vgd > Vt), the channel is continuous all the way
from S to D. Thus the n-channel acts like a conductor (or resistor) whose conductance is proportional to the
amount of electrons induced at the Source-end (and thus injected from Source into channel). The channel current
(or drain current) is given by

Id = k [ (Vgs - Vt)Vds - 1/2 Vds*Vds ]

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(2) Saturation

At Vds = Vds(sat), where Vds(sat) is defined as Vgs - Vt, the Drain-end of channel is just pinched off. Beyond
this voltage, that is, Vds > Vds(sat), the channel is no longer acts as a resistor. This is in the sense that the current
Id does not depend on the bias voltage Vds. The current is pretty much determined by how many carriers flow
into the channel at the Source-end of channel. The saturated drain current, Ids, is given by

Ids = 0.5 k (Vgs - Vt)2.

Increasing Vds while keeping Vgs constant does not increase the drain current. At the end of channel (channel
pinch-off) all carriers are swept into Drain by the electric field.

Actually, the Drain current Ids increases slightly as Vds increases. This is because the increasing Vds decreases
the channel length (try to change Vds in the applet and watch the changing channel length). This is called channel
length modulation. Mathematically, the channel length modulation introduces a Vds-dependent term in Ids:

Ids = 0.5 k (Vgs - Vt) ( 1 + L * Vds )

where L is a small number.

(3) Circuit model parameters for MOSFET

Input resistance: The electrically insulating Gate oxide layer prevents any flow of current from Gate to Source.
In a common-Source configuration with Gate as the input and Drain as the Output, the input resistance is infinity.
This is because the input current (the Gate current Ig) is zero regardless of the value of the input voltage (the
Gate-Source voltage Vgs).
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Output resistance: The small-signal circuit model parameter for output resistance in the common-Source
configuration is calculated as follows. The Drain-Source voltage Vds is such that the MOSFET is in saturation.
The ac output voltage is a small variation of Vds around the dc-bias point. As the Vds varies, the drain current
Id (or Ids, the saturated value -- "s" stands for "saturation") varies a little due to the channel length
modeulation. The variation in Ids is the ac output current, and its ratio to the ac output voltage is equal to the
output resistance. The channel length modulation effect is expressed as

Ids = 0.5k (Vgs - Vt)2 [1 + L Vds]

and the output resistance is

ro = del(Vds)/del(Ids) = 1/[Ids0 L].

Where

Ids0 = 0.5k (Vgs - Vt)2.

(4) The SPICE Model Parameters of MOSFET: Level 1 DC Model

LAMBDA
GAMMA
PHI
VT0
KP
LD
L
Leff

n-Well CMOS Level 1 SPICE Model parameters

Level 1 SPICE Parameter n-channel MOSFET p-channel MOSFET Units

Gate oxide thickness TOX 150 150 Angstrom
Transconductance Parameter KP 50 x 10-6 25 x 10-6 Amp/V2
Threshold Voltage VT0 1.0 -1.0 Volts
0.1/L 0.1/L
Channel-length modulation parameter LAMBDA
L in micron L in micron V-1

Bulk Threshold Parameter GAMMA 0.6 0.6 V1/2

Surface Potential PHI 0.8 0.8 V
Gate-drain overlap capacitance CGDO 5 x 10-10 5 x 10-10 F/m

Gate-source overlap capacitance CGSO 5 x 10-10 5 x 10-10 F/m

Zero-bias planar bulk depeletion
capacitance CJ 10-4 3 x 10-4 F/m2

Zero-bias sidewall bulk

depletion capacitance CJSW 5 x 10-10 3.5 x 10-10 F/m

Bulk junction potential PB 0.95 0.95 V

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Planar bulk junction
0.5 0.5 None
grading coefficient MJ
Sidewall bulk junction
0.33 0.33 None
grading coefficient MJSW

For visual effect, the increasing inversion layer charge with increasing Gate bias is illustrated by the increasing
blue n-channel thickness (or red p-channel thickness). This does not, however, mean that the inversion layer
thickness increases linearly with the applied Gate bias voltage. This is only for a visual effect which is to
emphasize the increasing inversion layer charge.

Carrier electrons at the pinched-off drain-end of the n-channel: Increasing Vds beyond Vds(sat), or
equivalently decreasing Vgd below Vt, creates a fully depleted region between the inversion n-channel and the
drain region. An electric field is set up in this region, pointing from the Drain region toward the inversion channel.
Carrier electrons in the n-channel that reach the depletion boundary are swept across the depletion region into
the Drain. This is similar to pn junction diode where the minority carrier electrons of the p-side are swept to the
n-side by the built-in field whenever they reach the depletion boundary. Look at this pn-junction applet.

Channel length modulation: The Drain-end of channel is pinched off at Vgd = Vt, or equivalently at Vds =
Vds(sat) = Vgs - Vt. For an n-channel MOSFET, increasing Vds further so that Vds > Vds(sat) (or decreasing
Vgd so that Vgd < Vt), the length of inversion channel (i.e., the blue inversion channel in the applet) is
'effectively' decreased. Since the channel resistance is proportional to the channel length, the channel resistance is
decreased. This results in the slight increase of the drain current beyond the saturation level.

Ids = (1/2) K'n(W/L) (Vgs - Vt)2 (1 + LAMBDA * Vds).

in which LAMBDA is called the channel-length modulation parameter and k = K'n * (W/L). Here, W is the
width and L is the length of the channel. The typical values are

0.001 V-1 < LAMBDA < 0.1 V-1.

In the saturation region, try to vary the bias voltage, Vgd or Vds, and watch the variation in the channel length
and the (slight) increase/decrease of the drain current. In the applets, the changes in the channel length with Vds
(or Vgd) is not drawn to scale.

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