2014 Annual IEEE India Conference (INDICON)
Voltage Collapse Mitigation by using SVC and
Phase-Plane Trajectory Analysis
Champa Nandi
Department of Electrical Engineering
Tripura University (A Central University)
Suryamaninagar, India
champanandi@yahoo.com
c.nandi.2014@ieee.org
Abstract—This paper deals with modeling and simulation of
SVC in IEEE 14 bus System with Induction Motor load for
avoiding voltage collapse. Voltage collapse can be simply
described by insufficient reactive power support to the load bus.
Three Phases to ground fault is applied in predominant
Induction motor load bus for voltage collapse analysis. Due to
fault, chaotic behavior is present in power system network during
fault time interval. The effect of Post Fault Clearing Time
[PFCT] of the system after facing the fault, to prevent permanent
voltage collapse has been analyzed with and without SVC. A
simple method is used for analyzing the phase-plane trajectory.
The Phase-Plane trajectory is calculated from the computer
simulation waveform data. Chaotic behavior has been observed
in computer simulations for an IEEE 14 bus power system
network including SVC.
Keywords— SVC, Voltage Collapse, Post fault clearing time,
Phase-Plane Trajectory
I. INTRODUCTION
The Voltage collapse is characterized by an initial slow
progressive decline in the voltage magnitude of the power
system buses and a final rapid decline in the voltage
magnitude. The main symptoms of voltage collapse are – low
voltage profiles, heavy reactive power flows, inadequate
reactive power support, and heavily loaded systems. Voltage
Instability and the problem of voltage collapse can cause the
major blackout in the power system. There are many
conventional controllers such as transformer tap changers,
phase shifters which are used for improving Voltage Stability.
But, these controllers are not fast in response and have so many
limitations. To avoid these drawbacks, FACTS devices are
proposed, to get fast response and also used to study the
Voltage Stability in the power system [1, 3, and 6].
There are several definitions of voltage collapse [7]. One
definition developed by CIGRE is that a power system
undergoes voltage collapse if the post-disturbance equilibrium
voltages are below acceptable limits, voltage collapse may be
total (blackout) or partial [7, 8]. Definition according to IEEE
is that Voltage Collapse is the process by which voltage
instability leads to loss of voltage in a significant part of the
system [7, 9].Chaotic phenomena are one type of oscillation
existing in unhealthy power systems. Study on chaotic
phenomena is one important part of power system stability
studies.
978-1-4799-5364-6/14/$31.00 ©2014 IEEE
Dr. Ajoy Kumar Chakraborty
Department of Electrical Engineering
NIT, Agartala
Agartala, India
akcalll@yahoo.co.in
In this paper Phase-Plane Trajectory is calculated from the
computer simulation waveform data. Vertical axis has been
chosen as amplitude just likes as time-series display and
horizontal axis is redefined so that first derivative of vertical
axis is used rather than using time.
The symbolic differentiation of functions is a topic that is
introduced in all elementary calculus courses. The first
derivative is the rate of change of Y (amplitude) with X (time)
that is dy/dx, which is interpreted as the slope of the tangent to
the amplitude at each point. Assuming that the x-interval
between adjacent points is constant, the simplest algorithm for
computing first derivative is
Yj' = Y (j+1) – Y (j) = Y (j+1) -Y (j) (1)
X (j+1)-X (j) ΔX
Xj' = X (j+1) +X (j) (2)
2
(For 1<j<n-1)
Where Xj' and Yj' are the X and Y values of the jth point of
the derivative, n=number of points in the amplitude, and △X
is the difference between the X values of adjacent data points.
A commonly used variation of this algorithm computed the
average slope between three adjacent points:
Yj' = Y (j+1) – Y (j -1) (3)
2Δ X
Xj' = Xj, (for 2<j<n-1) (4)
This is called central difference methods; its advantage is
that it does not involve a shift in the x-axis position of the
derivative.
In this paper, voltage collapse is designed by three phase to
ground fault which is electrically closed to the motor. Chaotic
phase trajectory are observed in IEEE 14 bus power system
network at bus 6. The final section of this paper concentrates
on applying phase portraits for a sample power system to the
IEEE 14 bus network including SVC. The concepts of voltage
collapse Model are firstly defined in section II. In section III
and IV, SVC control scheme and method of Phase Plane
Trajectory are described. Finally, simulation results are shown
to demonstrate the effectiveness of this simple method in
voltage stability study.
II. MODELLING OF VOLTAGE COLLAPSE
This paper makes the assumption that voltage dip is caused
by a three phase fault which is electrically closed to the
Induction motor. The worst case scenario is that of a three
phase fault which occurs electrically closed to the motor. It is
this scenario which is examined in this paper for voltage
collapse case study. A three phase to ground fault is applied at
bus 6 (Bus 6 is already a predominant Induction motor load
bus) in IEEE 14 bus system.
The following table briefly summarizes the causes of
disturbances which may cause voltage instability.
TABLE 1 SUMMERY OF VOLTAGE COLLAPSE MODELING
Disturbance Duration of Model
Disturbance
3-Phase to Ground Fault applied at
predominant Induction motor load (2-2.75 ) Sec dynamic
bus 6
III. SVC CONTROL SCHEME
.
Fig. 1. SVC Controller Scheme
The block diagram of basic SVC Controller incorporating
voltage regulator is shown in Fig. 1. [5]. This shows that both
voltage (VSVC) and current (ISVC) signals. The AC filter is
basically a notch filter to eliminate the signal component of
frequency corresponding to the parallel resonance in the
system viewed from the SVC bus. The line capacitance (in
parallel with SVC capacitance) can result in parallel resonance
with the line inductance. The SVC voltage regulator has a
tendency to destabilize this resonant mode of oscillation and
the notch filter is aimed at overcoming this problem. As a
matter of fact, any parallel resonance mode (of frequency
below second harmonic) can have adverse interaction with
SVC voltage regulator. If series capacitors are used along with
SVC, then they can cause parallel resonance with a
neighboring shunt reactor. If the second (parallel resonance)
mode has a lower frequency (say below 20 Hz), a high pass
filter in addition to the notch filter has been suggested. The
rectified signal is filtered. The DC side filters include both a
low pass filter (to remove the ripple content) and notch filters
tuned to the fundamental and second harmonic components.
The auxiliary signals mentioned in Fig. 2 are outputs from the
Susceptance (or reactive power) Regulator and Supplementary
Modulation Controller. The Susceptance Regulator is aimed at
regulating the output of SVC in steady state such that the full
dynamic range is available during transient disturbances. The
output of Susceptance Regulator modifies the voltage
reference Vref in steady state. However its operation is
deliberately made slow such that it does not affect the voltage
regulator function during transients
The block diagram of the controller in this case is shown in
Fig. 2. The proportional gain (KP) may be set zero unless a
faster response is required. The transfer function Hm(s)
represents a low pass filter as given below:
First order LP filter:
1
H m (s) = (5)
(1 + sTm )
Second order LP filter:
1
H m (s) =
1 + 2 s ζ T m + ( sT m ) 2 (6)
T is the period of the supply voltage. Td arises due to the
discrete nature of the firing pulse. Tb represents the average
delay in getting BSVC from the instant of delivering the order.
The current signal ISVC is used to provide a positive slope for
the control characteristic of SVC. However the current signal
contains harmonics and there are measurement problems
particularly when ISVC is close to zero (the normal operating
point). A solution to this problem is to take the signal from Bref
SVC instead of ISVC. Here the voltage regulator is typically a
PI controller as shown in Fig. 3. Simulations of the SVC in
IEEE 14 bus system were carried out by using Power System
Computer Aided Design (PSCAD/EMTDC) software.
Fig. 2. Block Diagram of SVC Voltage Control
 trajectory result. The flowchart of the programming for the
Trajectory design is as below.

START

Read System Data i.e. X Data, Y Data,

X=Voltage
Y=Time

Fig. 3. Voltage Regulator for SVC Read n;

Number of points in the amplitude

E 0.8

Max D Find
Vpu DX(j)=x(j)-x(j-1)
0.03 D &
N
DY(j)=(y(j+1)-y(j-1))/(2*DX(j))
- D * N/D N/D Qsvc
Isvc N
+
for j=2:n-1
F
Vpu 300.0 D

Find
DY(1)=DY(2);
DY(n)=DY(n-1)
Alpha Order

Btcr N Btcrn * AORD

N/D 0.0174533 Plot for trajectory
Bl D
BL Bl tdblk
P
BSVS BSVS BTCR CapOn + KB
D -+ TCR/TSC CSW STOP
B S V S (o rd )

I CS
F Nc QTCR(Ord) - NC

Vref Kp Ti
- Fig. 5. Flowchart for Phase Plane Trajectory design
CAPS_ON Cap Count D + CapOff CAPS_ON
F
Bl
Fig. 4. PSCAD/EMTDC software simulation representation of SVC
control scheme V. RESULTS AND OBSERVATION

A. Voltage Collapse case

IV. METHOD OF PHASE PLANE TRAJECTORY

Phase trajectory provides a powerful qualitative aid for
investigating system behavior. In this paper, Phase Plane
Trajectory has been generated by plotting voltage magnitude
as a Horizontal axis(X axis) and the first derivative as the
Vertical axis(Y axis). Fixed delay is used for taking the
Vertical axis data for each epoch. This is a very simple
method for designing the phase-plane trajectory from dynamic
wave form data. The state of the system at any moment can be
represented by a point of coordinates (x, y). Dynamic voltage
waveform data has been collected from PSCAD software
simulation result (from voltage collapse case). Matlab
software Programming is used for observing the phase plane Fig. 6. Voltage characteristics graph during voltage collapse case
B. Post Fault Clearing Time D. TSC ON/OFF time switching

Fig. 7. Critical fault clearing Time graph

Fig. 8. TSC ON /OFF Switching Time
C. Voltage level in BUS6 with and without SVC
From Figure 8 It is observed that during faulty condition
TABLE 2 Voltage Level
SL Time(sec) Voltage level Voltage level when Reactive Power requirement is extremely necessary,
NO without SVC(P.U) With SVC immediately switch on the capacitor bank (TSC
SVC(P.U) operation). After fault at 2.025 Sec one TSC has come for the
1. 0.0 0.0 0.0 operating mode but due to more capacitive reactive Power
2. .5 1.05 1.00
requirement another one TSC has switched on again for
3. 1.0 1.04 1.02
4. 1.5 1.03 1.00 compensate the system. During fault (2sec to 2.75 sec) full
5. 2.0 1.03 1.00 range support of TSC has come for the operation.
6. 2.1 0.89 1.01
7. 2.2 0.85 1.02
8. 2.3 0.82 1.02 E. Induction Motor Speed Condition
9. 2.4 0.78 1.01
10. 2.5 0.78 1.01
11. 2.6 0.76 1.01
12. 2.7 0.76 1.01
13. 2.75 0.76 1.01
14. 2.8 0.84 0.99
15. 2.9 0.83 1.00
16. 3.0 0.83 0.99
17. 3.5 0.82 1.00
18. 4.0 0.82 1.00
19 4.5 0.812 1.00
20 5 0.807 1.00

From Figure 6, Figure 7 and Table 2, it is clear that during

fault condition (2 Sec -2.75 Sec) uncompensated system
voltage levels gradually decreased and also observe that
voltage level enters in voltage instability zone even if the fault
is cleared. But due to presence of SVC voltage level remains
healthy reason even during faulty condition. But during
transient condition SVC case also shows some chaotic
behavior in system. Post fault Recovery is important to ensure
stable operating voltage for the Induction Motor predominant
load buses. The post fault clearing time for the system to
regain voltage at stable state due to Presence of SVC is
70msec.Within 4.2 cycles voltage levels again reach at stable
zone. But uncompensated system voltage level gradually
decreases even after 20 cycles of fault removal Voltage level
reaches 0.82 P.U. (stable voltage level range 0.95 P.U. – 1.05
P.U).
Computer simulation result shows voltage level gradually
decreases. Voltage level enters in voltage collapse condition as
post-disturbance equilibrium voltages are below acceptable
limits in case of uncompensated system.
Fig. 9. Induction Motor Speed Characteristics
In this incident, an unwanted voltage drop led to motor
stalling in case of uncompensated system. But due to
presence of SVC during faulty condition motor got proper
reactive power support so there is no voltage dip due to
proper reactive power compensation by SVC. So motor
can run smoothly in healthy condition.
F. Reactive Power Demand and Compensation
During voltage dip SVC instantly supplied the Reactive
Power .Induction Motor stalling condition nicely avoided by
proper reactive power compensation by SVC. Figure 10 shows
different reactive power characteristics.
 Fig. 10. Reactive Power Graphs

G. Phase-Plane trajectory for uncompensated system

Fig. 11. Phase Plane Trajectory for uncompensated system

H. Phase-Plane Trajectory for compensated (SVC) System

Fig. 12. Phase Plane Trajectory for compensated system

From Fig. 11 and Fig 12 it is clear that Phase Plane Trajectory
for uncompensated system goes voltage collapse condition as
it enters in unstable zone. Voltage should be 1 P.U. (stable
voltage level range 0.95 P.U. – 1.05 P.U).So singular point is
(1, 0). As equilibrium point for first derivative of voltage is
zero. From fig 11. It is shown that Trajectory enters in stable
zone but during fault and post fault condition trajectory enters
in unstable zone. It is also clear that the behavior of trajectory
will be remain unstable zone even after post fault condition as
direction of trajectory towards unstable Zone. But In Fig 12.
Trajectory enters in Stable Zone even fault and post fault
condition it remain in stable zone and trajectory enters in
singular point .Singular point is in stable focus.
VI. CONCLUSION
This paper presents a comparative model to describe a
voltage collapse condition with and without SVC. It has
demonstrated that the dynamic mechanism of the voltage
collapse phenomenon using an IEEE 14 bus system model
which includes an Induction motor with fault. Especially in
this paper, the mechanism of voltage collapse phenomenon
has analyzed from the physical point of view. The results of
simulations on the IEEE 14 bus test system have clearly
shown that how SVC devices increased the bus voltage level
during fault condition, improve Post fault clearing Time and
avoid unwanted motor stalling with proper reactive power
compensation. A simple method is used for deigning the Phase
Plane Trajectory analysis. It is believed that this paper may
provide a deeper insight into the dynamical mechanism of
voltage collapse phenomenon and effect of SVC on voltage
dip condition.
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