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Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Getting The Tutorial Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Manual PrimeTime Build Process . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4 Automated PrimeTime Build Process . . . . . . . . . . . . . . . . . . . . . . . . . 4
5 Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1 Introduction
In this tutorial you will gain experience generating power estimates from gate-level simulations using Syn-
opsys PrimeTime. PrimeTime takes a placed and routed design and a simulation waveform as input, then
produces several gate-level static timing analysis reports as output. Figure 1 illustrates the PrimeTime
toolflow and how it fits into the larger ECE5745 flow.
PrimeTime PX is an add-on feature to PrimeTime that analyzes power dissipation of a cell-based design.
PrimeTime PX supports two types of power analysis modes: averaged and time-based. Averaged mode
calculates average power based on toggle rates, while time-based mode provides both peak and average
power using gate-level simulation activity.
Performing power analysis gives us the opportunity to compare our designs with respect to an increasingly
important metric: energy. Combined with the area and execution time results obtained from IC Compiler
and VCS, we can now fully evaluate the tradeoffs offered by competing system architectures.
For this tutorial we will be performing power analysis on the netlist of the synthesized, placed, and routed
greatest common divisor (GCD) circuit, which you should have generated in Tutorial 3. Switching informa-
tion will be provided by the vcd file generated during gate-level simulation in Tutorial 4.
Note that this tutorial is by no means comprehensive. Synopsys documentation is located on the public
course webpage (http://www.csl.cornell.edu/courses/ece5745/syndocs) and can be accessed using
the username and password distributed in lecture.
You should follow along through the tutorial yourself by typing in the commands marked with a ’%’ symbol
at the shell prompt. To cut and paste commands from this tutorial into your bash shell (and make sure bash
ignores the ’%’ character) use an alias to ”undefine” the ’%’ character:
% alias %=""
Once you have logged into a BRG machine you will need to setup the ECE5745 toolflow with the following
commands:
% source setup-ece5745.sh
(Version 606ee8a), Spring 2013 2
Design IC
iverilog VCS
Compiler Compiler
Design IC
./a.out ./simv VCS
Vision GUI Compiler
IC
GTKWave ./simv
VCS Compiler
GUI
Test Post-P&R
Waveform
Results Simulator
(.vcd)
(.out) (simv)
For this tutorial you will be using a GCD circuit as your example design. If you don’t already have the source
files from the previous tutorials, create an ece5745 folder in your home directory and clone the tutorial files
from the git repository:
% mkdir ${HOME}/ece5745
% cd ${HOME}/ece5745
% git clone git@github.com:cornell-ece5745/ece5745-tut-asic.git
% cd ece5745-tut-asic/tutorial
% TUTROOT=$PWD
Before starting, take a look at the subdirectories in the project directory. Note that there are directories for
your RTL source (src) and for generated content (build). The build directory has subdirectories for each
major step in the ECE5745 toolflow, these subdirectories contain scripts and configuration files necessary
for running the tools. For this tutorial you will work primarily in the pt-pwr subdirectory.
Before we can generate averaged mode Primetime power reports, we need to create a switching activity file
(saif) from our gate-level vcd waveform:
% cd $TUTROOT/build/vcs-sim-gl-par
% make convert
Now that we have our switching activity file, use the following commands to launch the PrimeTime shell:
% cd $TUTROOT/build/pt-pwr
% pt_shell
You should be left at the PrimeTime shell prompt from which you can can execute various commands to load
your design, analyze the design, print reports, etc. You can get more information about a specific command
by entering man <command> at the pt shell prompt.
Execute the following commands manually in the pt shell> prompt. The first command will create an alias
to ”undefine” the pt shell> string, which will allow you to cut and paste commands from this tutorial into
PrimeTime.
# Read the post place and route gate-level netlist into PrimeTime PX.
# Averaged mode power analysis uses the saif format. Read the parasitics
# generated by IC Compiler before you run report_power.
# Time-based power analysis takes the vcd format as an input. Read the parasitics
# and run report power. You will see the estimated peak power as well as the
# average power.
You can now use various commands to perform further analysis on your design and display more reports.
Using the shell directly is useful for finding out more information about a specific command or playing with
various options, but for reproducibility and convenience reasons you will primarily use TCL scripts to control
this tool.
The final step in the Manual process is to exit the PrimeTime shell.
pt_shell> exit
There are two different power reports generated by primetime: one for averaged mode analysis and one for
time-based analysis. The time-based analysis provides additional information, such as peak power consumed,
at what time peak power was reached in the simulation, as well as glitching power (which should always be
zero when using the simple-stdcells). Both averaged and time based modes should provide a hierarchical
power breakdown that indicates how much power is consumed by each submodule in the design. Units are
provided in the report above the results table.
Keep in mind that the power reports we are generating for this tutorial are based on the waveforms generated
from the unit tests. In the labs, we will not be using the test harness as the source of our waveforms, instead
we will be using waveforms generated by the simulation harness (run.vcd). This will allow us to more
easily experiment with various input vectors and compare how different workloads influence performance
and energy consumption.
5 Acknowledgements
Many sources have contributed to the content of this tutorial. The original material for this tutorial was
developed as a lab for the CS250 VLSI Systems Design course at University of California at Berkeley by Yun-
sup Lee. Contributors include: Krste Asanović, Christopher Batten, John Lazzaro, and John Wawrzynek.
Versions of that lab have been used in the following courses:
• CS250 VLSI Systems Design (2009-2011) - University of California at Berkeley
• CSE291 Manycore System Design (2009) - University of California at San Diego