lOMoARcPSD|3589571

Assignment-3 - Detailed programming solution

Vlsi System Design (Binghamton University)

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HOMEWORK #3
-Akanksha Agrawal

Clock period: 3.8 ns

Optimized schematic

Critical path :

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 lOMoARcPSD|3589571

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 lOMoARcPSD|3589571

After timing optimization, we have a slack of 0.17ns only when the

clock period of 3.8 ns is set.

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ModelSim Simulation
Gate-level vhdl code :

library IEEE;

use IEEE.std_logic_1164.all;

package CONV_PACK_c_l_addr is

-- define attributes
attribute ENUM_ENCODING : STRING;

end CONV_PACK_c_l_addr;

library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_c_l_addr.all;

entity c_l_addr is

port( x_in, y_in : in std_logic_vector (7 downto 0); carry_in : in

std_logic; sum : out std_logic_vector (7 downto 0); carry_out : out
std_logic);

end c_l_addr;

architecture SYN_behavioral of c_l_addr is

component OR2X1
port( IN1, IN2 : in std_logic; Q : out std_logic);
end component;

component AO22X1
port( IN1, IN2, IN3, IN4 : in std_logic; Q : out std_logic);
end component;

component XOR3X1
port( IN1, IN2, IN3 : in std_logic; Q : out std_logic);
end component;

signal n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29,
n30 : std_logic;

begin

U25 : XOR3X1 port map( IN1 => y_in(7), by

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sarath IN3 => n16, Q =>
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sum(7));
U26 : XOR3X1 port map( IN1 => y_in(6), IN2 => x_in(6), IN3 => n17, Q =>
sum(6));
U27 : XOR3X1 port map( IN1 => y_in(5), IN2 => x_in(5), IN3 => n18, Q =>
sum(5));
U28 : XOR3X1 port map( IN1 => y_in(4), IN2 => x_in(4), IN3 => n19, Q =>
sum(4));
U29 : XOR3X1 port map( IN1 => y_in(3), IN2 => x_in(3), IN3 => n20, Q =>
sum(3));
U30 : XOR3X1 port map( IN1 => y_in(2), IN2 => x_in(2), IN3 => n21, Q =>
sum(2));
U31 : XOR3X1 port map( IN1 => y_in(1), IN2 => x_in(1), IN3 => n22, Q =>
sum(1));
U32 : XOR3X1 port map( IN1 => y_in(0), IN2 => x_in(0), IN3 => carry_in, Q =>
sum(0));
U33 : AO22X1 port map( IN1 => x_in(7), IN2 => n16, IN3 => y_in(7), IN4 =>
n23, Q => carry_out);
U34 : OR2X1 port map( IN1 => n16, IN2 => x_in(7), Q => n23);
U35 : AO22X1 port map( IN1 => x_in(6), IN2 => n17, IN3 => y_in(6), IN4 =>
n24, Q => n16);
U36 : OR2X1 port map( IN1 => n17, IN2 => x_in(6), Q => n24);
U37 : AO22X1 port map( IN1 => x_in(5), IN2 => n18, IN3 => y_in(5), IN4 =>
n25, Q => n17);
U38 : OR2X1 port map( IN1 => n18, IN2 => x_in(5), Q => n25);
U39 : AO22X1 port map( IN1 => x_in(4), IN2 => n19, IN3 => y_in(4), IN4 =>
n26, Q => n18);
U40 : OR2X1 port map( IN1 => n19, IN2 => x_in(4), Q => n26);
U41 : AO22X1 port map( IN1 => x_in(3), IN2 => n20, IN3 => y_in(3), IN4 =>
n27, Q => n19);
U42 : OR2X1 port map( IN1 => n20, IN2 => x_in(3), Q => n27);
U43 : AO22X1 port map( IN1 => x_in(2), IN2 => n21, IN3 => y_in(2), IN4 =>
n28, Q => n20);
U44 : OR2X1 port map( IN1 => n21, IN2 => x_in(2), Q => n28);
U45 : AO22X1 port map( IN1 => x_in(1), IN2 => n22, IN3 => y_in(1), IN4 =>
n29, Q => n21);
U46 : OR2X1 port map( IN1 => n22, IN2 => x_in(1), Q => n29);
U47 : AO22X1 port map( IN1 => x_in(0), IN2 => carry_in, IN3 => y_in(0), IN4
=> n30, Q => n22);
U48 : OR2X1 port map( IN1 => x_in(0), IN2 => carry_in, Q => n30);

end SYN_behavioral;

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TESTBENCH :
library ieee;
use ieee.std_logic_1164.all;

entity c_l_adder_tb is
end c_l_adder_tb;

architecture behave of c_l_adder_tb is

signal r_ADD_1 : std_logic_vector(7 downto 0) := (others => '0');

signal r_ADD_2 : std_logic_vector(7 downto 0) := (others => '0');
signal w_RESULT : std_logic_vector(7 downto 0);
signal w_cout : std_logic;

component c_l_adder is
PORT
(
x_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
y_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
carry_in : IN STD_LOGIC;
sum : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
carry_out : OUT STD_LOGIC );
end component c_l_adder;

begin
-- Instantiate the Unit Under Test (UUT)
UUT : c_l_adder
port map (
x_in => r_ADD_1,
y_in => r_ADD_2,
carry_in => '0',
sum => w_RESULT,
carry_out => w_cout );

process is
begin
r_ADD_1 <= "00000000";
r_ADD_2 <= "00000001";
wait for 10 ns;
r_ADD_1 <= "00000100";
r_ADD_2 <= "00000010";
wait for 10 ns;
r_ADD_1 <= "00000010";
r_ADD_2 <= "00000110";
wait for 10 ns;
r_ADD_1 <= "00000111";
r_ADD_2 <= "00000111";
wait for 10 ns;
end process;

end behave;
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OUTPUTS :

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Optimizing for Area – (set_max_area 360)

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 lOMoARcPSD|3589571

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