CS 258F Class Project

Winter 2006

Density Aware Global Placement Refinement

Prof. Jason Cong

I. Project Description
The objective of this project is to let you gain better understanding of standard cell based circuit
placement, especially for simultaneous wirelength and density optimization. You are given a global
placement solution optimized for wirelength, and you are asked to make refinement to the solution
so that it minimizes the cell density overflow. In particular, you are asked to develop a C++
program based on the Linux/Unix platform and solve the following problem: Given a netlist
(specified in BookShelf format [5]) and a global placement result produced by mPL [9], improve
the Scaled HPWL (defined below) which penalize the density overflow.
Through this project, you will also get some concrete experience about developing VLSI layout
programs in general, representing and manipulating the netlists, and applying combinatorial
optimization techniques to VLSI layout.

II. Input Circuits, Netlist Parser, Data Structure, Utility Tools and Objective
Definition

The project testcases, parser source code and utility tool can be downloaded at:
http://ballade.cs.ucla.edu/~nksze/cs258f_w06.tar.gz
For each circuit we have the following files:
.aux A list of the component files for a problem instance
.nodes Library file describing the cell library for the problem
.pl Describe the location and orientation of each node (in this case, describing global placemet)
.nets Describe each net and the pins it connects
.scl Describe the standard cell row, i.e., its location, height, starting position of each row
.wts Describe the weight associated with each net
The circuit statistics are shown below:

movable fixed cells target density

#pad #cells #nets cells area area whitespace utilization ratio
ibm01 246 12506 14111 37% 43% 20% 65% 70%
ibm02 259 19342 19584 25% 55% 20% 55% 60%
ibm03 283 22853 27401 30% 50% 20% 60% 65%
ibm04 287 27220 31970 38% 42% 20% 66% 70%
ibm05 1201 28146 28446 80% 0% 20% 80% 85%
ibm06 166 32332 34826 35% 45% 20% 63% 70%
ibm07 287 45639 48117 44% 36% 20% 69% 75%
ibm08 286 51023 50513 39% 41% 20% 66% 70%
adaptec1 480 210967 221142 33% 43% 24% 57% 60%
bigblue1 528 277636 284479 37% 17% 46% 45% 60%
A netlist parser is provided for the convenience of your code development. It takes an .aux
filename as input, and allocates the data structure of netlist in memory. A small sample circuit with
9 cells is included for easy testing.

Netlist data structure is put in “netlist/netlist.h”. It has the class for cell, pin, net, and hypergraph:
– Vertex (represents cell, has (x(), y()) as the cell center location; wth(),
hgt() and area() as the cell’s width, height and area respectively.
Pin_list() is a list of pins on the cells that provides the connections with
other cells; has degree() the number of pins on the cell; cell has types:
is_pad() (terminal), is_fixed() (fixed cell))
– Hedge (represents net, has pin_list() containing a list of pins, where each
pin belong to a cell, an hence describing the connection between the cells;
has degree() the number of pins connected by the net)
– Pin (located on cell; has the (loc_cx(), loc_cy()) as the relative location
with respect to cell center; cells are connected through pins; has vtx() as
the cell it belongs to and has net() as the net it belongs to)
– Hgraph (A hypergraph represents the netlist; it has a vertex_list()
containing a list of cells and a hedge_list() containing a list of nets)

A class called parser_main (“local-main/parser_main.h”) is used to read in the netlist and necessary
information for the circuit. It has the member values:
– ip_graph (the netlist Hgraph)
– lx, ly, rx, ry ( (lx, ly) is the lower left corner of the placement region,
and (rx, ry) is upper right corner the placement region)
– nrows (# of rows)
– rows_ury (contains center location each row height)
– std_cell_hgt (=row_hgt)

A binary (both Unix and Linux version) is provided for placement plot and reporting circuit
statistics, HPWL, and Scaled HPWL of a given circuit. Your program performance will be
measured by this binary. Please read the readme.txt for more detailed information and suggestions
regarding the source code and the binary usage for the project.

Scaled Bin Overflow (SBO)

• Superimpose a bin grid on the placement region, each bin is a square of
length 10 x standard cell height (boundary bins may have smaller size)
• #bin rows = ceil(chip height / (10 x std_cell_hgt))
• #bin cols = ceil(chip width / (10 x std_cell_hgt))
• Bin->density = sum of all movable cells area overlapping with the bin
• Bin->fixed density = sum of all fixed cells area overlapping with the bin
• Bin capacity = target density ratio * (Bin area – bin->fixed density)
• Bin overflow = max(bin->density – bin capacity, 0)
• SBO = (total bin overflow / (total movable area / bin area / target
density ratio) / 400)2

Scaled HPWL
• HPWL of a net = rightmost pin x-loc – leftmost pin x-loc + rightmost pin
y-loc – leftmost pin y-loc
• HPWL = sum of HPWL of each net
• Scaled HPWL = HPWL * (1 + SBO/100)
QoR (quality ratio)
• QoR of your solution = scaled HPWL / HPWL of the given global placement

Objective: Move the cells to minimize the scaled HPWL of the circuit. The one who can produce
the smallest average scaled HPWL or QoR over all the testcases in the table above will be the
winner. Your program needs to be scalable and the runtime for the largest testcase should not
exceed 24 hours.

III. Example (ibm01)

The above figure is plotted by the utility tool. The fixed cells are drawn in yellow color; the
terminals (pads) are the tiny rectangles lying just right next to the placement region; the movable
cells are in blue colors.
The following are the statistics and scaled HPWL reported by the utility tool:
Circuit Statistics

circuit name = ibm01

# pad = 246
# cell = 12506
# net = 14111
# row = 144
chip width = 2295
chip height = 2304
chip area = 5.28768e+06
cell height = 16
tot cell area = 4.23141e+06
% of WS = 19.9761
min cell deg = 1
max cell deg = 39
min net size = 2
max net size = 42
 # macros = 246
# fixed cells = 246
HPWL of the read in placement = 2.21016e+06

Density congestion profile :

Target bin density ratio = 0.7
lx = 0, ly = 0, rx = 2295, ry = 2304
bin width = 160, bin height = 160
# rows = 15, # of cols = 15
# of bins = 225
# of overflow bins = 68
Total movable area = 1879456
Total fixed density = 2181888
Total bin capacity = 5287680
Total amount of overflow = 303647.3
Scaled bin overflow = 52.387847
HPWL = 2210156.3
Scaled HPWL = 3368009.6

IV. Requirements

1. You need to complete the project by yourself.

2. You need to email me a one-page proposal by Feb. 20th describing an outline of your approach.

3. You need to turn in a class project report by Friday, March 17, 5pm PST. A typical report has 8-
10 pages, including:
• A brief summary of related work on this topic,
• Detailed description of your approach,
• Justification of your approach,
• A table of about test circuits, including the numbers of cells, nets, and pins for each test
circuit,
• A table summarizing your solutions, including scaled HPWL, QoR and runtime for each
solution and machine configuration.
• Some implementation details, such as the computer and compiler used for implementation
and experiment.
Please use figures and tables effectively to improve the quality of your presentation.

4. You need to inform me and Kenton Sze <nksze@cs.ucla.edu> (via e.mail) where your program
(executable and source codes) and output files are located on the departmental servers, so that
Kenton and I can verify your results if necessary. Please make sure that I have the proper access
right to these data for 3 weeks from the date you turn in the report.

5. Each person will give a 20-min presentation of their work on Monday, March 20th, 8-11am PST.
V. Grading

The grading includes two parts:

Basic: You'll receive 75% credit if your program works correctly for all test cases, and produces
reasonably optimized solutions (QoR <= 1.5).

Competitive: The remaining 25% credit will be assigned based on how good your solution
compared to others.

VI. References

[1]. K. Doll, F. Johannes, K. Antreich, “Iterative placement improvement by network flow

methods,” IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems,
vol.13, no.10, Oct. 1994, pp. 1189-1200.
[2]. J. Vygen, “Algorithms for detailed placement of standard cells,” Proc. Design, Automation and
Test in Europe, pp.321-324.
[3]. A. Kahng, P. Tucker, A. Zelikovsky, “Optimization of linear placements for wirelength
minimization with free sites,” Proc. of the ASP-DAC '99 Asia and South Pacific Design
Automation Conference, pp. 241-244.
[4]. H. Sung-Woo, J. Lillis, “Mongrel: hybrid techniques for standard cell placement,” Proc. of
IEEE/ACM International Conference on Computer Aided Design. pp. 165-170.
[5]. Bookshelf file format description:
http://vlsicad.ucsd.edu/GSRC/bookshelf/Slots/Placement/plFormats.html
[6]. Bo-Kyung Choi, Huaiyu Xu, Maogang Wang, Majid Sarrafzadeh: Flow-Based Cell Moving
Algorithm for Desired Cell Distribution. ICCD 2003.
[7]. U. Brenner and A. Rohe. An Effective Congestion Driven Placement Framework. In Proc. Int.
Symp. on Physical Design, pages 6–11, 2002.
[8]. C. Li, M. Xie, C.K. Koh, J. Cong, and P. Madden," Routability-Driven Placement and White
Space Allocation," Proceedings of the International Conference on Computer-Aided Design,
November 2004, pp. 394-401.
[9]. T.Chan, J. Cong, and K. Sze " Multilevel Generalized Force-directed Method for Circuit
Placement, " Proceedings of the International Symposium on Physical Design, San
Francisco, CA, April 2005, pp. 185-192.