Assembler TPF

IBM ESA/390 ASSEMBLER COURSE
2nd Edition
Shrimanikandan A
Sanil M Joseph
Revision History
The following changes are amended in the second edition of the material.
 The string instructions are included.
 The treatment given to the instruction descriptions are changed.
 The layout is more reader friendly.
Thanks!
We thank Joshua.J and Karthik.I for their unfathomable efforts in getting the second edition ready in time.
IBM ESA/390 Assembler Handbook page 2 of 178

© Aviation Software Development Consultancy India Ltd.
Course Objectives
The course aims to give the participants the knowledge and skills needed to construct programs in IBM ESA/390
assembler.
The course is designed to run for 4 man weeks, out of which 2.5 weeks are dedicated to cover the course material and
the rest for programming exercises.
The course does not deal in detail on the operating system dependent system calls/macros. The prerequisites for the
course are:
 An understanding of the VM/CMS development environment, and
 Working knowledge of JCLs.

Copyright Statement
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any
form or by any means, without the prior written permission of the company, ASDC.
Address for Communication:
The Chief Executive Officer,

Aviation Software Development Consultancy India Ltd,
Unit 21/22, 2nd Floor, Elnet Software City,
TS 140 Block 2&9, CPT Road,
Taramani,
Chennai-600 113.
INDIA.
 +91-44-2541015, 2541097, 2541598

Fax: +91-44-2541016
Website: www.asdc.co.in
Email: ceo@asdc.co.in

Legend
The following are the legends / conventions used throughout this handbook and their meaning.
 Warning! / Caution! / Don't do this!
 Do this! / Tip / Information.
 Footnote.
 Even-odd register pair required.

TABLE OF CONTENTS
Revision History _______________________________________________________________________2
Thanks!______________________________________________________________________________2
Course Objectives _____________________________________________________________________3
Copyright Statement ___________________________________________________________________4
Legend_____________________________________________________________________________5
INTRODUCTION_____________________________________________________________________11
SYSTEM ARCHITECTURE / 390__________________________________________________________12
CPU_______________________________________________________________________________13
CPU_______________________________________________________________________________14
REGISTERS_________________________________________________________________________15
REGISTERS_________________________________________________________________________16
PSW AND INTERRUPT PROCESSING_____________________________________________________17
PSW AND INTERRUPT PROCESSING_____________________________________________________18
ADDRESSING SCHEMES_______________________________________________________________19
ADDRESSING SCHEMES_______________________________________________________________20
Why 31 bits? ________________________________________________________________________20
VIRTUAL MEMORY AND DYNAMIC ADDRESS TRANSLATION____________________________________21
VIRTUAL MEMORY / DYNAMIC ADDRESS TRANSLATION______________________________________22
EFFECTIVE ADDRESS COMPUTATION_____________________________________________________23
KEY PROTECTION____________________________________________________________________24
INTEGRAL BOUNDARIES_______________________________________________________________25
CONDITION CODES___________________________________________________________________26
INSTRUCTION FORMATS_______________________________________________________________27
NUMBER SYSTEMS__________________________________________________________________31
BINARY NUMBERS____________________________________________________________________32
Decimal to Binary conversion______________________________________________________________32
BINARY NUMBERS____________________________________________________________________33
Binary to Decimal Conversion ___________________________________________________________33
SIGNED AND UNSIGNED BINARY INTEGERS________________________________________________34
HEXADECIMAL NUMBERS______________________________________________________________35
Hex to Decimal Conversion ____________________________________________________________35
HEXADECIMAL NUMBERS______________________________________________________________36
LOAD AND STORE INSTRUCTIONS___________________________________________________37
LOAD ADDRESS - LA__________________________________________________________________38
LOAD REGISTER - LR_________________________________________________________________39
LOAD - L____________________________________________________________________________40
STORE - ST_________________________________________________________________________41
LOAD HALFWORD - LH________________________________________________________________42
STORE HALFWORD - STH_____________________________________________________________43
INSERT CHARACTER - IC______________________________________________________________44
STORE CHARACTER - STC_____________________________________________________________45
INSERT CHARACTERS UNDER MASK - ICM________________________________________________46
STORE CHARACTERS UNDER MASK - STCM______________________________________________47
LOAD MULTIPLE - LM_________________________________________________________________48
STORE MULTIPLE - STM_______________________________________________________________49
ARITHMETIC INSTRUCTIONS________________________________________________________50
ADD REGISTER - AR__________________________________________________________________51
SUBTRACT REGISTER - SR_____________________________________________________________52
MULTIPLY REGISTER - MR_____________________________________________________________53
DIVIDE REGISTER - DR________________________________________________________________54
ADD - A____________________________________________________________________________55
SUBTRACT - S_______________________________________________________________________56
MULTIPLY - M________________________________________________________________________57
DIVIDE - D__________________________________________________________________________58
ADD HALFWORD - AH_________________________________________________________________59
SUBTRACT HALFWORD - SH____________________________________________________________60
MULTIPLY HALFWORD - MH____________________________________________________________61
LOAD AND TEST REGISTER - LTR_______________________________________________________62
CSECTS & ASSEMBLER DIRECTIVES_________________________________________________63
OPERAND DESIGNATION_______________________________________________________________64
TERMS AND EXPRESSIONS_____________________________________________________________65
Self-Defining Terms: __________________________________________________________________65
CONTROL SECTIONS__________________________________________________________________69
Executable Control section _____________________________________________________________69
Reference Control Section _____________________________________________________________69
LITERALS___________________________________________________________________________70
ASSEMBLER DIRECTIVES - 1____________________________________________________________71
Line Format _________________________________________________________________________71
ASSEMBLER DIRECTIVES - 1_________________________________________________________73
USING Directive: _____________________________________________________________________74
CSECT Directive _____________________________________________________________________74
ASSEMBLER DIRECTIVES – 1___________________________________________________________75
DROP Directive: ______________________________________________________________________75
TITLE Directive: ______________________________________________________________________75
SPACE Directive: _____________________________________________________________________76
PRINT Directive: _____________________________________________________________________76
EJECT Directive: _____________________________________________________________________77
END Directive: _______________________________________________________________________77
LTORG Directive: _____________________________________________________________________77
EQU Directive: _______________________________________________________________________77
ORG Directive: _______________________________________________________________________78
Example:_________________________________________________________________________78
DATA DEFINITIONS__________________________________________________________________79
STORAGE EXPRESSIONS_______________________________________________________________80
Introduction: _________________________________________________________________________80
Storage Expression Format: ____________________________________________________________80
Example:_________________________________________________________________________80
Attributes of Storage Types: ____________________________________________________________81
Character Data Type: __________________________________________________________________82
Format: _____________________________________________________________________________82
Examples:________________________________________________________________________82
Hexadecimal Data Type: _______________________________________________________________83
Format: _____________________________________________________________________________83
Examples:________________________________________________________________________83
Fullword Data Type: ___________________________________________________________________84
Format:_____________________________________________________________________________84
Examples:________________________________________________________________________84
Halfword Data Type: __________________________________________________________________85
Format: _____________________________________________________________________________85
Examples:________________________________________________________________________85
Doubleword Data Type: ________________________________________________________________86
Format:_____________________________________________________________________________86
Examples:________________________________________________________________________86
Address Data Type: ___________________________________________________________________87
Format:_____________________________________________________________________________87
Examples:________________________________________________________________________87
ASSEMBLER DIRECTIVES - 2_________________________________________________________88
DS Directive: ________________________________________________________________________89
Format: _____________________________________________________________________________89
Example:_________________________________________________________________________89
DC Directive: ________________________________________________________________________90
Format: _____________________________________________________________________________90
Example:_________________________________________________________________________90
CONTROL TRANSFER, EXTENDED MNEMONICS & COMPARISONS_____________________91
COMPARE REGISTER - CR_____________________________________________________________92
COMPARE - C________________________________________________________________________93
COMPARE HALFWORD - CH____________________________________________________________94
BRANCHING_________________________________________________________________________95
BRANCH ON CONDITION REGISTER - BCR________________________________________________96
BRANCH ON CONDITION - BC___________________________________________________________97
BRANCH ON COUNT REGISTER - BCTR__________________________________________________98
BRANCH ON COUNT - BCT_____________________________________________________________99
BRANCH ON INDEX LOW OR EQUAL - BXLE______________________________________________100
BRANCH ON INDEX HIGH - BXH________________________________________________________101
EXTENDED BRANCH MNEMONICS_______________________________________________________102
Name of extended mnemonic____________________________________________________________102
Extended form_______________________________________________________________________102
Mask______________________________________________________________________________102
DECIMAL INSTRUCTIONS___________________________________________________________103
ZONED DECIMAL NUMBERS___________________________________________________________104
Zoned Decimal Numbers: _____________________________________________________________104
PACKED DECIMAL NUMBERS__________________________________________________________105
Packed Decimal Numbers: ____________________________________________________________105
CONVERT TO BINARY - CVB___________________________________________________________106
CONVERT TO DECIMAL - CVD_________________________________________________________107
ADD PACKED - AP___________________________________________________________________108
SUBTRACT PACKED - SP_____________________________________________________________109
MULTIPLY PACKED - MP______________________________________________________________110
DIVIDE PACKED - DP_________________________________________________________________111
COMPARE PACKED - CP______________________________________________________________112
ZERO AND ADD PACKED - ZAP________________________________________________________113
SHIFT AND ROUND PACKED - SRP_____________________________________________________114
SHIFTS, CHARACTER MANIPULATION & SUBROUTINES_____________________________115
SHIFT INSTRUCTIONS : OVERVIEW______________________________________________________116
Introduction: ________________________________________________________________________116
Logical Shift:_________________________________________________________________________116
SHIFT INSTRUCTIONS : OVERVIEW______________________________________________________117
Arithmetic Shift: _____________________________________________________________________117
SHIFT LEFT LOGICAL - SLL___________________________________________________________118
SHIFT RIGHT LOGICAL - SRL__________________________________________________________119
SHIFT LEFT ARITHMETIC - SLA________________________________________________________120
SHIFT RIGHT ARITHMETIC - SRA_______________________________________________________121
SHIFT LEFT DOUBLE LOGICAL - SLDL___________________________________________________122
SHIFT RIGHT DOUBLE LOGICAL - SRDL_________________________________________________123
SHIFT LEFT DOUBLE ARITHMETIC - SLDA________________________________________________124
SHIFT RIGHT DOUBLE ARITHMETIC - SRDA______________________________________________125
MOVE CHARACTERS – MVC__________________________________________________________126
MOVE CHARACTERS – MVC__________________________________________________________127
MOVE IMMEDIATE – MVI______________________________________________________________128
MOVE CHARACTER LONG – MVCL_____________________________________________________129
MOVE CHARACTER LONG – MVCL_____________________________________________________130
COMPARE LOGICAL CHARACTERS – CLC________________________________________________131
COMPARE LOGICAL IMMEDIATE – CLI___________________________________________________132
COMPARE LOGICAL CHARACTER LONG – CLCL___________________________________________133
BRANCH AND SAVE REGISTER – BASR_________________________________________________134
BRANCH AND SAVE – BAS____________________________________________________________135
EXECUTE - EX______________________________________________________________________136
LOGICAL INSTRUCTIONS___________________________________________________________137
BOOLEAN OPERATIONS - AND_________________________________________________________138
AND Operation: _____________________________________________________________________138
BOOLEAN OPERATIONS - OR__________________________________________________________139
OR Operation: ______________________________________________________________________139
BOOLEAN OPERATIONS - XOR_________________________________________________________140
XOR Operation: _____________________________________________________________________140
AND REGISTER – NR________________________________________________________________141
AND – N___________________________________________________________________________142
AND CHARACTER – NC______________________________________________________________143
AND IMMEDIATE – NI_________________________________________________________________144
OR REGISTER – OR_________________________________________________________________145
OR – O____________________________________________________________________________146
OR CHARACTER – OC_______________________________________________________________147
OR IMMEDIATE – OI__________________________________________________________________148
XOR REGISTER – XR________________________________________________________________149
XOR – X__________________________________________________________________________150
XOR CHARACTER – XC______________________________________________________________151
XOR IMMEDIATE – XI________________________________________________________________152
TEST UNDER MASK – TM_____________________________________________________________153

CONVERSION INSTRUCTIONS_______________________________________________________154
PACK - PACK______________________________________________________________________155
UNPACK - UNPK____________________________________________________________________156
MOVE WITH OFFSET - MVO___________________________________________________________157
MOVE NUMERICS - MVN_____________________________________________________________158
MOVE ZONES - MVZ_________________________________________________________________159
TRANSLATE - TR____________________________________________________________________160
TRANSLATE AND TEST - TRT__________________________________________________________161
EDIT - ED__________________________________________________________________________162
EDIT – ED_________________________________________________________________________163
EDIT - ED__________________________________________________________________________164
Fill Byte: ___________________________________________________________________________164
Source Digits: ______________________________________________________________________164
Significance Indicator: ________________________________________________________________164
Digit Selector: ______________________________________________________________________164
Significance Starter:_________________________________________________________________164
Field Separator: _____________________________________________________________________164
Message Bytes: _____________________________________________________________________164
EDIT – ED_________________________________________________________________________165
Conversion mechanism _______________________________________________________________165
EDIT - ED__________________________________________________________________________166
EDIT – ED_________________________________________________________________________167
EDIT AND MARK - EDMK_____________________________________________________________168
STRING INSTRUCTIONS____________________________________________________________169
MOVE STRING – MVST______________________________________________________________170
MOVE STRING – MVST______________________________________________________________171
SEARCH STRING – SRST_____________________________________________________________172
SEARCH STRING – SRST_____________________________________________________________173
COMPARE LOGICAL STRING – CLST____________________________________________________174
COMPARE LOGICAL STRING – CLST____________________________________________________175
DSECTS____________________________________________________________________________176
DSECTS – DUMMY SECTIONS________________________________________________________177
DSECTS – DUMMY SECTIONS________________________________________________________178
Example:________________________________________________________________________178

Introduction

System Architecture / 390
CPU
MAIN STORAGE
CPU
CHANNEL SUB SYSTEM
Serial Channel Paths Parallel Channel Paths

CPU
Overview:
 Central controlling point of operations.

 Performs execution of instructions, interrupt processing etc.
 390 architecture supports more than one processor in a physical machine.
 The 390 architecture defines the instruction set.
 Instruction sets are micro-coded; i.e. another CPU is simulating the instruction set of 390 machine.
 Permits wide range of processors to be used. The processors must follow the same instruction set.
 Makes change to instruction set easy.
Instruction Types:
 General : Binary arithmetic, Comparison, Logical, Branching, Load and Store, Move instructions.
 Packed Decimal : Arithmetic, Comparison and Conversions.
 Floating Point : Arithmetic, Comparison, Load and store.
 Control : Load PSW, Set program mask.
 I/O : Instructions to drive the I/O sub system.
 Vector : Instructions used for vector processing.
 CPU

CPU
System States:
There are two system states used by the 390 architecture.

 Problem State : General, Packed Decimal, Floating Point, Control 
 Supervisor State : Control, I/O.
Registers

Some semi-privileged instructions may be executed in problem state

The 390 architecture provides the following registers.
General Registers:
 16 General Registers in the system numbered 0 through 15.

 Each register is of size 32 bits.
 General Registers are used to hold both data and address.
 Registers are paired together for some instructions, called even-odd register pair.
 The register specified, in such instructions are even numbered registers. The pair register (odd) will be the next
highest register.
EG: R2 is the even register and the registers in the pair are R2, R3.
Control Registers:
 16 control Registers in the system, numbered 0 through 15.

 Each control register is of size 32 bits.
 Control Registers are used by the operating system.
 Not for application use.
Floating Point Registers:
 4 Floating Point Registers in the system, numbered 0, 2, 4 and 6.

 Each floating point register is 64 bits long.
 Each register can either hold a 64 bit (long) or 32 bit (short) data.
 In case of a short data, the operand occupies the leftmost 32 bits and the rest are ignored.
 Two adjacent registers can be used as a pair for extended operations. For extended operations (eg.128 bytes),
two adjacent register are used as a pair.
Registers

Access Registers:
 16 access Registers in the system, numbered 0 through 15.

 Each register is of size 32 bits.
 Used for address translation by the address translation mechanism 
 Not for application use.
PSW and Interrupt Processing

Will be introduced under the section, Dynamic Address Translation

 PSW is used to reflect the current status of the system.
 Contains in it, the instruction to be executed next along with other control information.
 One register with PSW value.
 Each interrupt type has a storage location designated as old-PSW and a new-PSW.
 The PSW that is active is called Current PSW.
 PSW is of size 64 bits.
PSW key P CC
0 8 12 15 18 20 31
1 Instruction Address
32 33 63
P Problem State/Supervisor State Indicator

CC Condition Code
PSW and Interrupt Processing

Interrupt Processing:
 Six types of interrupts are supported by 390 architecture:

1. External
2. I/O
3. Machine check
4. Program
5. Restart
6. SVC.
 On occurrence of an interrupt, the current PSW is saved into the old-PSW.
 The execution is continued from the instruction specified at the new-PSW.
 On completion of the interrupt processing, old-PSW is reloaded and marked as the current PSW.
Addressing Schemes

 Addresses are unsigned binary numbers used to designate main storage.
 The types of address supported by system 390 are:
1. 24 bit address
2. 31 bit address
24 bit addressing:
 Originally, 370 series of machines used 24 bit addressing.

 Low order 3 bytes of a register specified, were used to hold the address.
 The top order byte had control information in them set up, when special instructions were executed.
Ctrl Byte0 Byte1 Byte2
31 bit addressing:
 IBM came up with a 370 series of machines called XA (Extended Architecture) which used 31 bit addressing.
System 390 also supports this scheme.
 Top order bit had the value '1' to designate that the address is a 31bit address.
1 Byte0 Byte1 Byte2 Byte3
Addressing Schemes

Why 31 bits?
Registers are of size 32 bits; hence 32 bit addressing is possible. But, the reason for not supporting 32 bit addressing
and just supporting 31 bit addressing is:
 To provide compatibility for older application, which use the control information in the top order byte or use that
byte as storage location or as flag bits.
Virtual Memory and Dynamic Address Translation

 An address space is the view of main storage.
 System 390 divides the main memory into 4K pages.
 These pages are logically grouped into segments, each segment is of size 1MB.
 The address of an instruction or data is its virtual address (while the real address where the instruction/data
resides in the memory may be different)
 When a required data or instruction is not in the memory, the operating system swaps in or swaps out pages and
brings in the needed information.
 The operating system just before using an address, converts the virtual address to real address.
 This process is known as Dynamic Address Translation (DAT).
 A Virtual Address is made up of the following components:
1. Bit 0 Unused
2. Bits 1-11 Segment Index(SX)
3. Bits 12-19 Page Index(PX)
4. Bits 20-31 Byte Index (BX)
SX PX BX
0 1 11 19 31
 Segment Table Origin is in a Control Register.
 DAT multiplies SX by 4 and adds the control register contents, locates the segment table item.
 PX is then multiplied by 4 and is added to the address in the segment table.
 The page table item thus computed has the real base address of the page.
 Adding BX to this provides the real address of the item referenced.
Virtual Memory / Dynamic Address Translation

Page Table Origin Real Address of Page 0 Page 0
IBM ESA/390 Assembler Handbook


Invalid Real Address of Page 3 Page 3
Page Table Origin Invalid Page 5
page 22 of 178
Effective Address Computation
Address Computation:
Effective address is the address that is not yet transformed to any other forms, viz., absolute or real address. There is
no dynamic address translation or prefixing. An effective address can be specified directly in a register or can result
from an address arithmetic operation.
The 390 architecture's addressing scheme, as introduced before is based on 4K pages. To access data or instruction,
the effective address is used. The effective address is a combination of a base register, index register and an offset,
which is otherwise called as displacement.
Any instruction which access memory, for operands or to point to other instruction use the effective address. Not all
the instruction formats use index register, they simply use the base register and the displacement. The following is the
mechanism used to compute the effective address.
EFA = contents of base register [+index register]+offset
The following are the rules which apply.
 All general purpose registers 1-15 can be used as base and index registers.
 The offset should be an unsigned number within the range 0 through FFF (which is 4K)
Example,
Base register R2 - 00 00 10 00
Index register R3 - 00 00 30 00
Displacement - 00 00 04 00
Effective address is (R2)+(X2)+Disp = 1000+3000+400

= 00 00 44 00

Beware! Using R0 as base or index register is disastrous! R0 is used to
indicate the absence of a register & the contents of R0 will not be added to
form the effective address. No assembly error will be displayed and the
results are unpredictable.

Key Protection
 System 390 uses this mechanism for restricting access to memory regions.
 Each 4K block is associated with a storage key.
 The storage key is of the size 7 bytes and is of the following format:
ACC F R C
0 4 5 6
 The ACC field is a 4-byte field, which has the key value for the 4K block. Any process trying to write into the block
should have a PSW storage key, which matches the value.
 If the keys don't match an access exception occurs.
 The F field has a flag indicating if this block is fetch protected. If a block is fetch protected, then any fetch is
should undergo the key matching process.
 The R and C bits are set whenever a block is referenced / changed respectively. The swapper for its
management uses them.
 The PSW with storage key can access any block irrespective of the storage key value and is unique. This is used
mostly by the operating system.

Integral Boundaries
 Groups of 2, 4 and 8 bytes consecutive bytes are given special names when they begin on a specific address.
 These addresses are called Integral Boundaries.
 Any group of address, which is a multiple of 2, is said to be on a halfword boundary.
 Any group of address, which is a multiple of 4, is said to be on a fullword boundary.
 Any group of address, which is a multiple of 8, is said to be on a doubleword boundary.
 Instructions, CCWs should be on a halfword boundary.
 There are certain instructions that expect the operands to be on a particular integral boundary.

Condition Codes
 Condition Codes are used to reflect the result of the previously executed instruction.
 The condition code is a 2-bit field in the PSW, with possible values 0, 1, 2 or 3 depending upon the result.
 Most arithmetic and logical operation set condition codes.
 Also, a few other instructions set the condition code.
 Other instructions, which don't set, will leave the condition code field unaltered.

Instruction Formats
 A System 390 instruction is one, two or three halfwords in length.

 It's mandatory that all instructions should start on a halfword boundary.
 Any instruction will be of one of these eleven basic formats.
E Format:
Opcode
0 15
RR Format:
Opcode R1 R2
0 8 12 15
RRE Format:
Opcode R1 R2
0 16 24 28 31

Instruction Formats
RX Format:
Opcode R1 X2 B2 D2
0 8 12 16 20 31
RS Format:
Opcode R1 R3 B2 D2
0 8 12 16 20 31
RSI Format:
Opcode R1 R3 I2
0 8 12 16 31
 RS format by definition specifies the 2 nd operand to be an effective address.

But, for the Shift family of instruction, it behaves differently. In this
case, the second operand will be the 'Shift Amount'. More explanation in
the chapter "Shift instructions".

Instruction Formats
RI Format:
Opcode R1 OpCd I2
0 8 12 16 31
SI Format:
Opcode I2 B2 D2
0 8 16 20 31
S Format:
Opcode B2 D2
0 8 16 20 31
SS Format: Variant 1:
Opcode L B1 D1 B2 D2
0 8 16 20 32 36 47

Instruction Formats
Opcode L1 L2 B1 D1 B2 D2
0 8 12 16 20 32 36 47
Opcode R1 R3 B1 D1 B2 D2
0 8 12 16 20 32 36 47
SSE Format:
Opcode B1 D1 B2 D2
0 16 20 32 36 47

Number Systems

Binary Numbers
A base B number system uses B symbols and the largest has a decimal value B - 1. Binary or base 2 numbers use the
symbols 0 and 1. Each digit position in the representation of a binary number, is a power of 2. To emphasize the base,
the text uses a subscript notation. 1012 represents the binary integer 101.
Decimal to Binary conversion
To convert Decimal integer I to Binary,
Divide I by 2 and let the quotient be Q1 and the remainder is bn, the right most bit.
Divide Q1 by 2 and let the quotient be Q2 and the remainder is bn-1.
Continue this until Qn = 0. The remainder b1 will be the left most bit.
Binary equivalent will be b1b2...bn.
Example:
To convert 1410 into binary.
14 / 2 = 7 with remainder 0 (Q1 = 7 , bn = 0)

7 / 2 = 3 with remainder 1 (Q2 = 3 , bn-1 = 1)
1410 = 11102

Binary Numbers
Binary to Decimal Conversion
To convert b1b2...bn to decimal
b1b2...bn = b1 * 2n-1 + b2 * 2n-2 + ... + bn * 20
Example:
11102 = 1 * 23 + 1 * 22 + 1 * 21 + 0 * 20
= 8 + 4 + 2 + 0
= 1410
Signed and Unsigned binary integers

The most significant bit of a signed binary integer represents the sign. For a positive integer, this bit will be zero. A
negative number is expressed as two's complement of the magnitude. The biggest signed integer is limited to 31 bits.
The range of an n bit signed number will be, -2 n-1 .. 2n-1-1.
The range of an unsigned n bit binary number, will be 0 .. 2n-1.
The two's complement of a d-bit binary integer N is equal to 2 d-N, where the subtraction is performed in binary. Another
method of finding the two's complement of one number is by adding 1 to the one's complement of the number ( invert
the bit values to get one's complement ).
Hexadecimal Numbers

Hexadecimal ( Hex ) or base 16 numbers use the symbols 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E and F. Each digit
position in the representation of a hex number, is a power of 16.
Decimal to Hex conversion
To convert Decimal integer I to Hex,
Divide I by 16 and let the quotient be Q1 and the remainder is hn, the right most nibble.
Divide Q1 by 16 and let the quotient be Q2 and the remainder is hn-1.
Continue this until Qn = 0. The remainder h1 will be the left most nibble.
Hex equivalent will be h1h2...hn.
Hex to Decimal Conversion
To convert h1h2...hn to decimal
h1h2...hn = h1 * 16n-1 + h2 * 16n-2 + ... + hn * 160
Hex is used as a short hand way of representing binary. For example,
1010 01102 = A616 = 16610

Hexadecimal Numbers
Binary to hex conversion
Splitting the binary digits into groups of four from the right performs this and each group is then converted into the
corresponding hex digit.
1101001102 = 0001 1010 01102 = 1A616
Hex to binary conversion
Replace each hex digit by the corresponding four bit binary equivalent.
1230A16 = 0001 0010 0011 0000 10102
= 000100100011000010102

Load and Store Instructions
Load Address - LA

Instruction LA
Function  Loads the effective address computed with the second operand into the general-
purpose register specified as the first operand.
Addressing Schemes
31 – Bit Addressing  The Most Significant Bit (bit 0) is set with a value 1.
 The address computed is placed in positions 1-31.
24 – Bit Addressing  The Most Significant Byte (0-7) is set with control information, which are not
significant.
 The address computed is placed in positions 8-31.
Syntax LA R1 , D2 (X2,B2)
Opcode
41 R1 X2 B2 D2
Instruction Format RX
Condition Code Remains unchanged.
Program Exceptions None
Programming  Storage is not referred for operands & addresses are not checked for access
Considerations exceptions.
 Usage of R0 as base or index register will result in zero being used instead of the
contents of R0.
 This instruction can be used to load a constant within the range 0 – 4095 into a
register.
 Increment operation can be achieved using this instruction.
 Two registers and a constant can be added with this instruction.
 This instruction supports only integer arithmetic operations.
Example Assume TABLE is X ’400’ bytes from location pointed to
by R5.
LA R1 , TABLE
Opcode – 41 10 51 90
Register / Location Initial Value Final Value
R1 00 F0 20 33 00 80 34 00
R5 00 80 30 00 Unchanged

Load Register - LR
Instruction LR
Function  Copies the contents of the second operand (general-purpose register) into the first
operand (general-purpose register).
Addressing Schemes Insignificant.
Syntax LR R1 , R2
Opcode
18 R1 R2
Instruction Format RR
Example The following instruction copies the contents of general-purpose register R14 into register
R1.
LR R1 , R14
Opcode – 18 1E
R1 Insignificant 00 80 30 00

Load - L
Instruction L
Function  It takes the contents of 4 bytes starting at the storage location represented by the
second operand and places it into the first operand (general-purpose register).
Addressing Schemes Insignificant
Syntax L R1 , D2 (X2,B2)
Opcode
58 R1 X2 B2 D2
Program Exceptions Access – Fetch 2nd operand
Example Assume that the 4 bytes starting from location 21003 are to be loaded into general-purpose
register 3.
L R3 , 0(R5,R6)
Opcode – 58 35 60 00
R3 Insignificant 00 00 AB CD
( 21003 ) 00 00 AB CD Unchanged

Store - ST
Instruction ST
Function  It places the contents of the first operand (general-purpose register) into the 4 bytes
starting at the address computed with the second operand.
Syntax ST R1 , D2 (X2,B2)
Opcode
50 R1 X2 B2 D2
Program Exceptions Access – Store 2nd operand
Example Assume that the contents of register 3 are to be saved into the 4 bytes starting with location
21003.
ST R3 , 0(R5,R6)
Opcode – 50 35 60 00
R3 00 AB CD EF Unchanged
( 21003 ) Insignificant 00 AB CD EF

Load Halfword - LH
Instruction LH
Function  It places unchanged, a halfword (2 bytes) from storage represented by the second
operand into the two lower order bytes (rightmost 2 bytes) of the general-purpose
register specified as the first operand.
 The halfword is then sign-extended to a 32-bit signed number. (The two
higher order bytes of the register are loaded with zeroes or ones according to
the sign of the halfword).
Syntax LH R1 , D2 (X2,B2)
Opcode
48 R1 X2 B2 D2
Examples Assume that the 2 bytes in storage locations 1803-1804 are to be loaded into R1.
LH R1 , 0(0,R5)
Opcode – 48 10 50 00
R1 00 00 FF FF 00 00 00 20
( 1803 ) 00 20 30 40 Unchanged

R1 00 00 FF FF FF FF A7 B6
( 1803 ) A7 B6 00 10 Unchanged

Store Halfword - STH
Instruction STH
Function  It places unchanged, the two lower order bytes of the first operand (general-purpose
register), into the two bytes starting from the address computed with the second
operand.
Syntax STH R1 , D2 (X2,B2)
Opcode
40 R1 X2 B2 D2
Example Assume that the two lower order bytes of register R1 are to be stored at storage locations
1803-1804.
STH R1, 0(0,R5)
Opcode – 40 10 50 00
R1 12 34 AB CD Unchanged
( 1803 ) Insignificant AB CD

Insert Character - IC
Instruction IC
Function  This instruction, places into the right-most byte of the first operand (general-purpose
register), the byte pointed to by the second operand.
Syntax IC R1 , D2 (X2,B2)
Opcode
43 R1 X2 B2 D2
Example Assume that the byte in storage location 1515 is to be loaded into the right-most byte of R2.
IC R2 , 5(R5)
Opcode – 43 25 00 05
R2 12 34 56 00 12 34 56 78
( 1515 ) 78 AB AB 98 Unchanged

Store Character - STC
Instruction STC
Function  This instruction places the right-most byte of the first operand (general-purpose
register), into the byte pointed to by the second operand.
Syntax STC R1 , D2 (X2,B2)
Opcode
42 R1 X2 B2 D2
Example Assume that the right-most byte of R2 has to be placed at storage location 1515.
STC R2 , 5(R5)
Opcode – 42 25 00 05
( 1515 ) 78 AB AB 98 00 AB AB 98

Insert Characters Under Mask - ICM
Instruction ICM
Function  Bytes from contiguous locations beginning at the second-operand address are
inserted into general register R1 under control of a mask.
 The contents of the M3 field are used as a mask. These four bits, left to right,
correspond one for one with the four bytes, left to right, of general register R1.
 ICM with a mask of 1111 or 0001 performs a function similar to that of an L or an IC
instruction respectively, with the exception of the condition-code setting.
Syntax ICM R1 , M3, D2(B2)
Opcode
BF R1 M3 B2 D2
Instruction Format RS
Condition Code 0 - All inserted bytes are zero or M3=0.
1 - If the left-most bit of the inserted bytes is 1.
2 - If the inserted bytes are not zero, but the leftmost bit is zero.
Example Assume that the two bytes at 1803-1804 are to be inserted into bytes 2 and 4 of register 2.
ICM R2 , B’0101’, 3(R5)
Opcode – BF 25 50 03
R2 12 34 56 78 12 C1 56 C2
( 1803 ) C1 C2 C3 C4 Unchanged

Store Characters Under Mask - STCM
Instruction STCM
Function  This instruction stores the selected bytes of the register specified as the first operand,
into consecutive bytes starting from the address location computed by the third
operand.
 The second operand serves as a mask for selecting the bytes to be replaced in the
register.
 STCM with a mask of 1111, 0011, or 0001 performs the same function as ST, STH, or
STC, respectively.
Syntax STCM R1 , M2, D3(B3)
Opcode
BE R1 M2 B3 D3
Example The following instruction stores the first, third and fourth bytes of register R2 into the 3
consecutive bytes starting from location X’1803’.
STCM R2 , B’1011’, 3(R5)
Opcode – BE 2B 50 03
R2 12 C1 56 C2 Unchanged
( 1803 ) Insignificant 12 56 C2

Load Multiple - LM
Instruction LM
Function  This instruction loads several consecutive registers stating from R1 and ending with
R3, with data from consecutive fullwords (4 bytes) of storage.
Syntax LM R1, R3, D2(B2)
Opcode
98 R1 R3 B2 D2
Example Load registers 2,3 and 4 from memory location X’1803’.
LM R2, R4, 3(R5)
Opcode – 98 24 50 03
R2 Insignificant C1 C2 C3 C4
R3 Insignificant C5 C6 C7 C8
R4 Insignificant C9 CA CB CC
C1 C2 C3 C4 C5 C6
( 1803 ) C7 C8 C9 CA CB CC Unchanged
CD CE CF AB DC EF

Store Multiple - STM
Instruction STM
Function  The contents of the set of general registers starting with general register R1 and
ending with general register R3 are placed in the storage area beginning at the
location designated by the second-operand address.
Syntax STM R1, R3, D2(B2)
Opcode
90 R1 R3 B2 D2
Example Save registers 2,3 and 4 into memory locations starting from X’1515’.
STM R2, R4, 5(R5)
Opcode – 90 24 50 05
R2 0A 0B 0C 0D Unchanged
R4 A1 B2 C3 D4 Unchanged
0A 0B 0C 0D 11 22
( 1515 ) Insignificant
33 44 A1 B2 C3 D4

Arithmetic Instructions
Add Register - AR

Instruction AR
Function  Adds the binary integers contained in general registers, assuming the two’s
complement binary number system.
 The sum replaces the contents of the first operand location, leaving the second
operand unchanged.
Syntax AR R1 , R2
Opcode
1A R1 R2
Condition Code 0 Zero
1 Negative
2 Positive
3 Overflow
Program Exceptions Fixed Point Overflow

Example AR R1 ,R14
Opcode – 1A 1E
R1 00 00 03 21 00 80 33 21
Condition Code – 2
Subtract Register - SR

Instruction SR
Function  Subtracts the binary integers contained in general registers, assuming the
two’s complement binary number system.
 The result replaces the contents of the first operand location, leaving the
second operand unchanged.
Syntax SR R1 , R2
Opcode
1B R1 R2
1 Negative
2 Positive
3 Overflow
Program Exceptions Fixed point overflow
Example SR R1 ,R14
Opcode – 1B 1E
R1 00 23 03 21 00 23 00 21
Multiply Register - MR
Instruction MR

Function  Computes a 64-bit product from two 32-bit integers called the multiplicand and
the multiplier.
 The multiplicand is in the odd-numbered register of the even-odd pair R1,
R1+1.The multiplier is in register R2.
 The product is stored in an even-odd register pair R1, R1+1 destroying their
prior contents.
Syntax MR R1 , R2 
Opcode
1C R1 R2
Condition Code  Condition code unchanged
 Since it is impossible to generate a product that is longer than 64 bits from
two 32-bit operands, overflow cannot occur.
Program Exceptions Specification.
Examples 1. MR R2 ,R14
Opcode – 1C 2E
R3 00 00 12 34 01 47 A8 00
2. MR R4,R5 squares the contents of register R5
Divide Register - DR
Instruction DR

Function  Divides a 64-bit integer called the dividend by a 32-bit integer called the
divisor to produce a 32-bit quotient and a 32-bit remainder.
 An even-odd register pair initially contains the dividend and the divisor is in a
register.
 The division results in an integer quotient in the odd register and an integer
remainder in the even register. The dividend is destroyed.
Syntax DR R1 , R2 
Opcode
1D R1 R2
Condition Code Condition code unchanged
Program Exceptions 1. Fixed point divide
2. Specification exception
Example DR R2 ,R14
Opcode – 1D 2E
R2 00 00 00 00 00 00 00 01
R3 00 00 00 09 00 00 00 02
Add - A
Instruction A
Function  Adds the binary integer contained in the second operand (4 bytes of storage)
to the first operand (general purpose register), to the first operand (general
purpose register), assuming the two’s complement binary number system.
 The sum replaces the contents of the first operand location, leaving the
Syntax A R1,D2(X2,B2)
Opcode
5A R1 X2 B2 D2
1 Negative
2 Positive
3 Overflow
Program Exceptions 1. Access – Fetch 2nd operand

2. Fixed point overflow
Example This instruction adds the content of 4 bytes from the
location pointed by 8(R2) to the contents of R1.
A R1,8(R2)
Opcode – 5A 12 00 08
R1 00 00 03 21 00 00 03 32
(803008) 00 00 00 11 Unchanged
Subtract - S
Instruction S
Function  The S instruction subtracts the binary integer contained in the second operand
(4 bytes of storage) from the first operand (general-purpose register),

assuming the two’s complement binary number system.
 The difference replaces the contents of the first operand location, leaving the
Syntax S R1,D2(X2,B2)
Opcode
5B R1 X2 B2 D2
1 Negative
2 Positive
3 Overflow
Example This instruction subtracts the content of 4 bytes from
the location pointed by 8(R2)
From the contents of R4
S R1,8(R2)
Opcode – 5B 12 00 08
R1 00 00 03 21 00 00 03 10
(803008) 00 00 00 11 Unchanged
Multiply - M
Instruction M
Function  The M instruction computes a 64-bit product from two 32-bit integers called
the multiplicand and the multiplier.
 The multiplicand is in the odd-numbered register of the even-odd pair R1,

R1+1. The multiplier is in a memory location.
 The product is stored in the even-odd register R1,R1+1 destroying their prior
contents.
Syntax M R1,D2(X2,B2) 
Opcode
5C R1 X2 B2 D2
Condition Code  The Condition code is unchanged.
 Since it is impossible to generate a product that is longer than 64 bits from 2
32-bit operands, overflow cannot occur.
Program Exceptions 1. Specification.
2. Access – Fetch 2nd operand.
Example M R2,8(R4)
Opcode – 5C 24 00 08
R3 00 00 12 34 01 47 A8 00
(803008) 00 00 12 00 Unchanged
Divide - D
Instruction D
Function  The D instruction divides a 64-bit integer called the dividend by a 32-bit
integer called the divisor to produce a 32-bit quotient and a 32-bit remainder.
 An even-odd register pair initially contains the dividend and the divisor is at a
memory location pointed by the second operand.
 The division results in an integer quotient in the odd register and an integer
remainder in the even register. The dividend is destroyed.
Syntax D R1,D2(X2,B2) 
Opcode
5D R1 X2 B2 D2
Condition Code The condition code is unchanged.
2. Fixed point divide
3. Specification
Example D R2,8(R4)
Opcode – 5D 24 00 08
R2 00 00 00 00 00 00 00 01
R3 00 00 00 09 00 00 00 02
(803008) 00 00 00 04 Unchanged
Add Halfword - AH
Instruction AH
Function  The AH instruction adds the binary integer contained in the second operand (2
bytes of storage) to the first operand (general purpose register), assuming the
two’s complement binary number system.
 The sum replaces the contents of the first operand location, leaving the

Syntax AH R1,D2(X2,B2)
Opcode
4A R1 X2 B2 D2
1 Negative
2 Positive
3 Overflow

Example This instruction adds the content of 2 bytes from the location pointed by 8(R2) to
the contents of R1
AH R1,8(R2)
Opcode – 4A 12 00 08
R1 00 00 03 21 00 00 03 32
(803008) 00 11 00 00 Unchanged
Subtract Halfword - SH
Instruction SH
Function  The SH instruction subtracts the binary integer contained in the second
operand (2 bytes of storage) from the first operand (general-purpose register),
assuming the two’s complement binary number system.

 The difference replaces the contents of the first operand location, leaving the
Syntax SH R1,D2(X2,B2)
Opcode
4B R1 X2 B2 D2
1 Negative
2 Positive
3 Overflow

Example This instruction subtracts the content of 2 bytes at the location pointed by 8(R2)
from the contents of R4.
SH R1,8(R2)
Opcode – 4B 12 00 08
R1 00 00 03 21 00 00 03 10
(803008) 00 11 00 00 Unchanged
Multiply Halfword - MH
Instruction MH
Function  The MH instruction computes a 32-bit product from a 32-bit integer called the
multiplicand (general purpose register) and a 16-bit integer(2 bytes of storage)
called the multiplier and the product is placed in the register
Syntax MH R1,D2(X2,B2)
Opcode
4C R1 X2 B2 D2
Condition Code  The condition code is unchanged.
 Even though the result can be 48 bits long, only the rightmost 32 bits are
retained and no indication for this is given.
Example MH R2,8(R4)
Opcode – 4C 24 00 08
R2 00 00 01 23 00 14 76 00
(803008) 12 00 00 00 Unchanged
Load and Test Register - LTR
Instruction LTR
Function  The LTR instruction loads a register as if it was an LR instruction and
compares the new value of the first register operand with zero and sets the
condition code accordingly.

Syntax LTR R1,R2

Opcode
12 R1 R2
1 Negative
2 Positive
Program Exceptions None.
Example LTR R2,R4
Opcode – 12 24
R2 Insignificant 90 AB CD EF
R4 90 AB CD EF Unchanged

CSECTs & Assembler Directives
Operand Designation
Overview

 Instructions require operands to operate upon and the discussion following is about the rules, that govern
designating operands.
 The operands can be designated / mentioned in either of these two ways.
 Explicit
 Implicit
 If an operand is specified directly in terms of base & index registers, along with displacements, it is called explicit
designation.
For example
LA R1,20(R2,R3)
 If an operand is specified indirectly, entrusting the responsibility of register specification and displacement
computation to the assembler it is called implicit designation.
For example
LA R1,DATA
Where data is at displacement 50 from the address pointed
by R12. This will in turn be changed to:
LA R1,50(0,R12)
by the assembler
Terms and Expressions

It’s a good programming practice to designate operands in the implicit form,
as this will allow a greater deal of flexibility
 Not all instruction formats follow implicit designation of data. RR format
for example, requires both the operands to be in the registers and they have
to be specified explicitly.
 The implicit designation of operands applies only to those instruction
formats that use memory operands

Self-Defining Terms:
 Constants written in hexadecimal, decimal, binary or character form that designate instruction components like
registers, masks and displacements within the operand entry are called self-defining term.
 Their values are inherent in their definitions. For example, 1 is a self-defining term which can be used to designate
register 1 or a displacement 1 or a mask.
Symbols:
 A symbol is a sequence of characters limited to a maximum of 8 and should begin with an alphabet. Both self-
defining terms & symbols are called terms.
Expressions
 An expression can be a term or a combination of terms and arithmetic operators +,-,*,/.

 The expressions can be embedded within parenthesis.
 The expressions are evaluated at assembly time and not during execution time.
 Parenthesis is used to force change in the order of evaluation.
 There are two types of expressions.
 Absolute
 Relocatable

 An absolute expression is an expression whose value is independent of its location in the memory.
 A relocatable expression is an expression whose value is dependent on, where the program is loaded in the
memory.
 Any expression which is of the form rel-rel or abs#abs, where # (can be +, -, * or / ) is absolute.
 Any expression of the form rel-abs or rel+abs will be relocatable.
Rules for constructing expressions:

 A term should not be followed by another term; an operator should not be next to another operator.
 An expression should not contain embedded blanks with one exception. Blanks can be part of a character string
within apostrophes.
 Parenthesized subexpressions are evaluated first. Multiplication and division next and addition, subtraction at the
last. The operations are performed from left to right.
 A maximum of 19 operators and 5 levels of parentheses may be used in an expression.
 The value of an expression must be an integer in the range –2 31 to 231 –1.
 The result of a division is always truncated to an integer.
 Division by zero produces a zero result.
 Relocatable terms cannot be used with multiplication or division

Examples
Assume the following definition. X, Y & Z are relocatable symbols and A is an absolute symbol.
The following are relocatable expressions:

X+Y-Z+4
X+A-8
X/4
The following are absolute expressions:

4*A-8
X-Y
2*(X-Y)/A+1
A+4
X+Y-Z-Z-A
Control Sections
 A control section is the smallest subdivision of a program, which can be relocated as a unit.
 A control unit can contain in itself, code, constants, data areas and a combination of any of these.

 Control sections are divided generally into two types.
1. Executable Control Section.
2. Reference Control Section
Executable Control section
 An executable control section has in it code and data.

 The CSECT or START directive initiates an executable control section.
 The executable control section is generally referred as CSECT.
 A CSECT should begin on a double word boundary.
Reference Control Section
 A reference control section in contrast to its executable cousin does not contain code and data.
 They instead, map storage locations or reserve them.
 DSECT or COM directive initiates a reference control section.
 The reference control sections are further classified into, dummy control sections and common control section.
 Though they sound to be the same, dummy control section, which is initiated by DSECT directive just, describes
the storage map.
 The common control section, which is initiated by COM directive, can describe the storage map and also reserve
memory.
 The reference control section in general is referred as DSECT.
Literals
 Literals are used for defining a constant.

 They are used instead of implicit constant.
 The assembler will define the storage needed, unlike the DC # expression where the programmer has to define the
storage.
 Apart from allocating storage, literals will also initialize the location with the value the way DC does.
 The literal looks exactly the way the operand of a DC entry works, but precedes with an equal sign(=).
 When the same literal is coded in two places in the program, the assembler recognizes it and uses the same
location for both the instructions.
Example
S R4,=F’4’
Subtracts from the contents of R4, the value ‘4’ that is a literal constant coded.
Assembler Directives - 1
Line Format
#
Do not try to store into a literal. Literals are constants.
 Do not combine with a literal to form an expression. A literal is not a term.
 Do not specify an index register. A literal pool is referred with just the base register.
 Do not use a zero duplication factor. The literal pool organization is quite different!
 Literal pool is the place where storage is allocated for all the literals within a CSECT
#
Discussion on this topic is deferred to maintain sequence in the discussion.

 Traditionally, punched cards were used as secondary storage media; hence the assembler program source lines
are of 80 characters.
 Each line in the assembler source statement should adhere to the following format:
 Columns 1-71 Instruction/Comments
 Column 72 Continuation mark
 Columns 73-80 Sequence number
 A further breakdown of instruction area should be as follows:
 Columns 1-8 Label
 Column 9 Space (separator)
 Column 10 Opcode start point
 Column 15 Space (separator)
 Column 16 or after Operands start point
 Comments should start after the operands separated by at least one space. A ‘*’ in the first column indicates that
the whole line is a comment.
 In case that, the operands go beyond one line, there should be an indication in the continuation column(72) and
the operands in the next line onwards should exactly start at column 16.
Hence an instruction occupying one line will be of the format:

[label] Opcode Operands [comments]
While a multiple line instruction will be of the format:

[label] Opcode Operands [comments] X
Operand Continuation X
Operand Continuation

Labels and comments which are encased in [] are optional
 Operand continuation not exactly on column 16 or making the continuation column for a single line instruction
will result in assembly errors.

USING Directive:
 This directive declares a base register, which is to be used by the assembler. The assembler will use the register
to address the locations, which fall under the designated area(name).
USING name, register or
USING name, registers

 If more than one register is specified, the first 4K of locations are addressed by the 1 st register and the next 4k by
the 2nd and so on.
Example:
USING *,R12
LR R12,R5
Assume that the address of the first instruction in a program is in the register R5. The example above will direct the
assembler to use R12 as the base registers for all the labels in the program.
CSECT Directive
 This directive initiates a control section.
[label] CSECT
Assembler Directives – 1
DROP Directive:
 This directive directs the assembler to stop using the register(s) specified as base register.
DROP register or
DROP registers
Example:
DROP R12

TITLE Directive:
 This directive causes a skip to the next page in the printout.
 Skip will occur only if the listing is not already at head-of-form.
 All pages until another TITLE directive will have the string printed on the first line of the page.
TITLE string
SPACE Directive:
 This directive will result in a blank line being inserted in the assembly.
 The parameter n is optional & if presents specifies the number of blank lines.
 If not mentioned, the default is 1.
SPACE [n]

Be cautious while you drop registers. Missing out the operand may result in a lot of assembly errors. This is
because, DROP without operand will result in all base registers being dropped.
 If * is used as the name parameter in the USING directive, the next 4K location will be addressed by the base
register specified. Note that, * is used to indicate the current address to the assembler. * is called the location
counter reference.

PRINT Directive:
 Use this directive to control the amount of details in the assembly listing.
PRINT [on/off] [‘gen/nogen] [,nodata/data]
 Up to a maximum of 3 options can be specified. The list says what each option means.
 ON/OFF – Print the assembler statements in the listing / Don’t print them in the listing.
 GEN/NOGEN – Print the assembler statements generated by macros in the listing / Don’t print them in the listing.
 NODATA/DATA – Print the whole of all data constants in the assembler statements in the listing / Don’t print them
in the listing.

EJECT Directive:
 This directive causes a skip to the new page in the printout.
EJECT
END Directive:
 The END instruction marks the last source statement in the module.
 Any further statements will be ignored.
 The optional parameter, i.e., the relocatable expression, specifies the entry point #
END [relocatable expression]
LTORG Directive:
 Positions the literal pool, which was created since the beginning of the program or since the last LTORG at the
next doubleword boundary in the program.
LTORG
EQU Directive:
 The EQU directive informs the assembler to assign to the label name, the value of the expression.
 The expression may be either absolute or relocatable.
 The assembler will substitute the value of the expression wherever the name is used.
Name EQU expression

Example:
R9 EQU 9
This makes the assembler substitute the value 9 wherever R9 is used.
#
Entry point of a program is the address of the first instruction to be
executed.
 LTORG in a CSECT will result in storage being allocated at the end of the
CSECT Omitting.
ORG Directive:
 This directive changes the current value of the location counter.
 By resetting the current value, it redefines the contents or layout of the storage.
 The relocatable expression supplied as the operand will be evaluated and the location counter will be loaded with
that value.
ORG relocatable expression
Example:
WORKAREA DC 100X’00’
ORG WORKAREA+50
DC X’50’
ORG
The first statement above would define a storage area of size 100 bytes all initialized to zeros. The ORG with the
expression will reset the pointer to the 51st byte of WORKAREA which will then be initialized to X’50’. 

Omitting the operand (blank) in the ORG directive will result in the location counter being set to the next available
value in the current CSECT. Here, in the example, the ORG with no operand sets the location counter to next byte
after the 100 bytes defined as WORKAREA.
 A more complex form of the ORG directive where one can specify the length and type is available. The book
excludes this, as the discussion will go beyond its scope.

Data Definitions

Storage Expressions
Introduction:
 Storage expressions are used to instruct the assembler about the storage requirements.
 The assembler, with the help of storage expressions allocates storage and initializes them .
Storage Expression Format:

The assembler requires the storage expressions to be of the following format for processing.
DDDDTLL’VVVVVV’
where,
DDDD is the duplication factor which specifies the number of times the same definition should be repeated.
T is the type of the data.
LL is the length modifier. This is used to override the length of the type for the definition.
VVVVVV is the nominal value to which the storage has to be initialized.
Example:
The following definition will allocate 100 consecutive 4-byte character storage, initialized to ‘S’
100CL4’S’

Initializing will be done only with the DC directive, which will be introduced in the section
Assembler Directives – 2.

Storage Expressions
Attributes of Storage Types:

 The type parameter of the storage expression (T), unlike in high level languages, is not used for type checking.
 It is used to specify the attributes of the definition.
 The following are the attributes associated with the data types.
 Implicit length
 Alignment
 Padding
 Truncation
 The implicit length is the attribute that represents the size of the storage required.
 The alignment factor specifies the boundary on which the storage is to be allocated.
 Padding factor specifies what that has to be done if the initial value specified was smaller than the storage
allocated.
 The truncation factor, inverse of the padding factor, specifies what that has to be done if the initial value specified
was greater than the storage allocated.

Out of the 4 attributes, the length attribute can be overridden by specifying it explicitly.
 The other attribute that can be modified is the alignment factor. Though there is no explicit field in the storage
expression that specifies about alignment, specifying length explicitly results in the alignment being byte aligned
irrespective of it’s implicit style. Beware of this tricky one!

Storage Expressions
Character Data Type:

 The character data type defines a field holding EBCDIC characters.
 Special characters like “ ’ ” and “&” should be doubled. Hence, mentioning special characters should be done as “
’’ ” and “&&”.
Format:
C’character string’
Implicit Length Alignment Padding Truncation

Length of the initial value or 1 byte Byte aligned. With spaces. Right.
if no value specified.
Examples:
C’ASDC’
C1 E2 C4 C3
CL6’ASDC’
C1 E2 C4 C3 40 40
CL2’ASDC’
C1 E2

Storage Expressions
Hexadecimal Data Type:

 The hexadecimal type defines a field of bytes, holding hexadecimal data if initialized.
 Zeros are prefixed to bring the number of digits to an even value.
Format:
X’hexstring,hexstring,hexstring,......’

Length of the initial value or 1 byte Byte aligned. With hex-zeros. Left.
if no value specified.
Examples:
X’E’
0E
XL4’FACE’
00 00 FA CE
XL1’4323’
23

Storage Expressions
Fullword Data Type:

 The fullword data type defines one or more 4 byte words.
 The values are decimal numbers rounded to the nearest integer.
Format:
F’decimal number,decimal number,........’

4 bytes. Word aligned. With zeros. Left.
Examples:
F’2000’
00 00 07 D0
FL2’100.7’ (will be rounded to 101)

00 65
4FL1’1,2,3,4’
01 02 03 04

Storage Expressions
Halfword Data Type:

 The halfword data type defines one or more 2 byte words.
Format:
H’decimal number,decimal number,........’

2 bytes. Halfword aligned. With zeros. Left.
Examples:
H’2000’
07 D0
H’-2’
FF FE
FL1’1000’
E8

Storage Expressions
Doubleword Data Type:

 The doubleword data type defines one or more 8 byte words.
Format:
D’decimal number,decimal number,........’

8 bytes. Doubleword aligned. With zeros. Left.
Examples:
DL2’2000’
07 D0
D’2’
00 00 00 00 00 00 00 02
2DL4’1000,2000’
00 00 00 E8 00 00 07 D0

Storage Expressions
Address Data Type:

 This data type defines a fullword field, which can hold an address.
 Out of the value specified, only the offset will be setup at assembly time. It is the linkage editor that modifies and
loads the correct value at load time.
Format:
A(expression)

4 bytes. Word aligned. With zeros. Left.
Examples:
A(MYDATA)
00 0C 07 D0
A’*+8’
00 0C 07 D8
AL1(16)
0F


DS Directive:
 The DS directive reserves storage and provides a symbolic label to the area that can be implicitly mentioned.
 The data type determines the attributes of the area.
 This directive accomplishes no storage initialization.
 The initial value is used here to sort out the size of the storage  to be allocated.
Format:
Label DS storage expression
Example:
The following statement defines an array of 200 strings, each of size 4 bytes.
ARRAY DS 200CL4

Remember that, in case of character and hex data types, the initial value can determine the length.

DC Directive:
 The DC directive reserves storage area and provides a symbolic label to the area that can be implicitly mentioned.
 The data type determines the attributes of the area.
 The initial value is padded/truncated if needed, and the storage is initialized with it.
Format:
Label DC storage expression
Example:
The following statement defines a storage area of size 10 bytes and initializes it to the value 4.
MYAREA DC XL10’04’

Control Transfer, Extended Mnemonics & Comparisons

Compare Register - CR
Instruction CR
Function  Compares the two 32-bit signed binary integers held in registers R1 and R2 and sets
the condition code accordingly.
Syntax CR R1, R2
Opcode
19 R1 R2
Condition Code 0 - R1 = R2
1 - R1 < R2
2 - R1 > R2
Example The following instruction compares contents of registers R1 and R2 and sets the condition
code accordingly.
CR R1 , R2
Opcode – 19 12
Register R1 Register R2 Condition Code
12 34 56 78 12 34 56 78 0
00 12 34 56 12 34 56 78 1
52 34 56 78 12 34 56 78 2

Compare - C
Instruction C
Function  Compares a 32-bit signed binary integer held in register R1 with a 32-bit signed binary
integer at the address indicated by the second operand and then sets the condition
code accordingly.
Syntax C R1, D2(X2,B2)
Opcode
59 R1 X2 B2 D2
Condition Code 1 - Operands equal
2 - Operand 1 < Operand 2
3 - Operand 1 > Operand 2
Program Exceptions Access – Fetch 2nd operand.
Example The following instruction compares contents of register R1 and the fullword at location
pointed to by 8(R2) and sets the condition code accordingly.
C R1, 8(R2)
Opcode – 59 12 00 08
Register R1 Value at 8(R2) Condition Code
12 34 56 78 12 34 56 78 0
00 12 34 56 12 34 56 78 1
52 34 56 78 12 34 56 78 2

Compare Halfword - CH
Instruction CH
Function  Compares a 32-bit signed binary integer held in register R1 with the fullword
expansion of a 16-bit binary integer at the address indicated by the second operand
and then sets the condition code accordingly.
Syntax CH R1 , D2(X2,B2)
Opcode
49 R1 X2 B2 D2
Condition Code 0 - Operands equal
1 - Operand 1 < Operand 2
2 - Operand 1 > Operand 2
Example
CH R1 , 8(R2)
Opcode – 49 12 00 08
Register R1 Value at 8(R2) Condition Code
00 00 00 12 00 12 34 56 0
00 00 00 08 00 12 34 56 1
00 12 34 56 00 00 12 34 2

Branching
 A branch on condition instruction tests the condition code and determines the instruction to be executed next.
 If the condition code is as specified by the instruction, a branch takes place and the instruction sequence is
altered.
 If the condition code does not match with the specification, the next sequential instruction is executed.
 In either case, the condition code remains unaltered.
 Branches on condition instructions are in RR and RX formats.
 However, the first operand designation, which is in bits 8-11 of the instruction does not name a register. These bits
constitute a MASK and are used to specify the condition code values.
 The second operand specifies the address of the next instruction to be executed when the condition code is as
specified by the mask. This address is called the branch address.
 Register R0 cannot be used to specify the branch address. In this case, no branch is made regardless of the
mask value.

Branch on Condition Register - BCR
Instruction BCR
Function  This instruction branches the control to the address specified in register R2, if the
condition code is as specified by the mask M1.
 The four condition codes (0, 1,2, and 3) correspond, left to right, with the four bits of
the mask.
 It does not branch if either the condition code does not match or R2 is the register R0.
Syntax BCR M1, R2
Opcode
07 M1 R2
Examples 1. The following instruction branches to the address in register R1 if the condition code is
2 or 3.
BCR B’0011’, R1
Opcode - 07 31
2. This instruction would branch to the address in R1 for all condition codes.
(Unconditional branch).
BCR B’1111’, R1
Opcode - 07 F1
3. The instruction below can never cause a branch.
BCR B’1111’ , R0
Opcode - 07 F0

Branch on Condition - BC
Instruction BC
Function  This instruction branches the control to the effective address computed by the second
operand, if the condition code is as specified by the mask M1.
 The four condition codes (0, 1,2, and 3) correspond, left to right, with the four bits of
the mask.
 It does nothing if the condition code does not match.
Syntax BC M1 , D2(X2,B2)
Opcode
47 M1 X2 B2 D2
Examples 1. The following instruction branches to the address 8(R2) if the condition code is 2 or 3.
BC B’0011’, 8(R2)
Opcode - 47 32 00 08
2. Assume LOOP is X’08’ displaced from R8.
This instruction will branch to the label LOOP if the condition code is 0 or 2.
BC B’1010’, LOOP
Opcode - 47 A0 80 08

Branch on Count Register - BCTR
Instruction BCTR
Function  This instruction first decrements the value in register R1. It then branches the control
to the address specified in register R2 if the result in R1 is non-zero.
 If R1 is zero, then no branch occurs.
 If R2=R0, then no branch occurs, but the value in R1 gets decremented.
Syntax BCTR R1 , R2
Opcode
06 R1 R2
Examples 1. The following instruction branches to the address in register R1 if the result in R2 after
decrementing, is non-zero.
BCTR R2, R1
Opcode - 06 21
2. This instruction just decrements R1.
BCTR R1, 0
Opcode - 06 10

Branch on Count - BCT
Instruction BCT
Function  This instruction first decrements the value in register R1. It then branches the control
to the effective address computed with the second operand if the result in R1 is non-
zero.
 If R1 is zero, then no branch occurs.
Syntax BCT R1, D2(X2,B2)
Opcode
46 R1 X2 B2 D2
Example The following instruction will decrement R1 and branch to the address 8(R2) if the result in
R1 is non-zero.
BCT R1, 8(R2)
Opcode - 46 12 00 08

Branch on Index Low or Equal - BXLE
Instruction BXLE
Function  This instruction increments the first operand with a value from the second operand and
the incremented first operand is then compared against a limit from the second
operand.
 If the first operand is less than or equal to the compared value, then the control
branches to the address represented by the third operand.
 If the second operand is an even register, then it contains the increment and the odd
register will contain the limit.
 If the second operand is an odd register, then the increment and limit are the same.
 This instruction and the following BXH instruction are peculiar in the sense that they
can take the second operand from an even-odd register pair or just a single register.
Syntax BXLE R1 , R3, D2(B2) 
Opcode
87 R1 R3 B2 D2
Example BXLE R1, R2, 8(R4)
Opcode - 87 12 40 08
After adding the contents of R2 to R1, this instruction branches to 8(R4) if the result in R1 is
less than or equal to the value in register R3.

BXH and BXLE is peculiar in the sense that it can take the second operand from an even-odd register or just a
single register. The legend for even-odd register pair here is optional

Branch on Index High - BXH
Instruction BXH
Function  This instruction increments the first operand with a value from the second operand and
the incremented first operand is then compared against a limit from the second
operand.
 If the first operand is higher than the compared limit, then the control branches to the
address represented by the third operand.
 If the second operand is an even register, then it contains the increment and the odd
register will contain the limit.
 If the second operand is an odd register, then the increment and limit are the same.
 This instruction and the following BXH instruction are peculiar in the sense that they
can take the second operand from an even-odd register pair or just a single register.
Syntax BXH R1, R3, D2(B2) 
Opcode
86 R1 R3 B2 D2
Example After adding the contents of R3 to R1 the following instruction branches to 8(R4) if the value
in R1 is greater than that of R3.
BXH R1, R3, 8(R4)
86 13 40 08

Extended Branch Mnemonics
Name of extended mnemonic Extended form Mask

Branch unconditionally B / BR X’F’
No operation NOP / NOPR X’0’
Branch on equal BE / BER X’8’
Branch on high BH / BHR X’2’
Branch on low BL / BLR X’4’
Branch on not equal BNE / BNER X’7’
Branch on not high BNH / BNHR X’D’
Branch on not low BNL / BNLR X’B
Branch on zero BZ / BZR X’8’
Branch on plus BP / BPR X’2’
Branch on minus BM / BMR X’4’
Branch on overflow BO / BOR X’1’
Branch on not zero BNZ / BNZR X’7’
Branch on not plus BNP / BNPR X’D’
Branch on not minus BNM / BNMR X’B’
Branch on no overflow BNO / BNOR X’E’

Decimal Instructions

Zoned Decimal Numbers
Zoned Decimal Numbers:

Each byte in a zoned-decimal number consists of two portions. The leftmost 4 bits are called zone bits (usually with
value X’F’) and the rightmost 4 bits are the numeric bits (0-9). The rightmost zone bits in the number represents the
sign code.
Zone Digit Zone Digit Sign Digit

Code Code Code Code Code Code
Since a zoned-decimal number is a maximum of 16 bytes long, the decimal integer that it represents can be a
maximum of 16 digits long.
The sign code can be X’A’, X’C’, X’E’ or X’F” for positive and X’B’ or X’D’ for negative.

Packed Decimal Numbers
Packed Decimal Numbers:

Each byte in a packed-decimal number consists of two decimal digits. The rightmost 4 bits of the last byte represents
the sign code (same as that for zoned – decimal numbers).
Digit Digit Digit Digit Digit Sign

Code Code Code Code Code Code
Since a packed-decimal number is a maximum of 16 bytes long, the decimal integer that it represents can be a
maximum of 31 digits long.
Implicit length of packed type data is one, byte aligned and the padding/truncation is from left and the decimal points
are ignored.

Convert to Binary - CVB
Instruction CVB
Function  The CVB instruction converts the packed-decimal number in the 8-byte field(second
operand) to an integer in the two’s complement binary number system.
 The binary integer then replaces the contents of R1 (the first operand).
 The instruction checks both the sign code and the digit code of the packed decimal
number for validity. Any invalid code will result in a data exception.
Syntax CVB R1,D2(X2,B2)

Opcode
4F R1 X2 B2 D2
Condition Code The condition code remains unchanged.
Program Exceptions 1. Data exception
2. Fixed point divide exception
3. Access – Fetch 2nd operand
4. Specification
Example CVB R1,8(R2)
Opcode – 4F 12 00 08
R1 Insignificant 07 5B CD 15
0(803008) 0 00 00 12 Unchanged
34 56 78 9C

Convert to Decimal - CVD
Instruction CVD
Function  The CVD instruction converts a 32-bit signed integer in the register R1(first operand)
to an 8 byte packed-decimal number at the second operand location.
 The instruction pads the left of the result with zeros.
Syntax CVD R1,D2(X2,B2)

Opcode
4E R1 X2 B2 D2
Program Exceptions 1. Access – Store 2nd operand
2. Specification
Example CVD R1,8(R2)
Opcode – 4E 12 00 08
R1 07 5B CD 15 Unchanged
0(803008) Insignificant 00 00 00 12
34 56 78 9C

Add Packed - AP
Instruction AP
Function  The AP instruction adds two packed-decimal numbers, the sum of which replaces the
first operand in packed-decimal form.
 The lengths of the operands (L1 and L2) are to be explicitly specified.
 The lengths in the instruction code are less by 1 than the actual length.
Syntax AP D1(L1,B1),D2(L2,B2)
Opcode
FA L1 L2 B1 D1 B2 D2
Instruction Format SS
Condition Code 0 Sum Zero
1 Sum negative
2 Sum positive
3 Overflow
Program Exceptions 1. Access – Fetch 2nd operand, Store 1st operand
2. Decimal overflow
3. Data
Example AP 0(4,R1),0(2,R2)
Opcode – FA 31 10 00 20 00
0(R1) 00 01 23 4C 00 01 32 0C
0(R2) 08 6C 08 6C

Subtract Packed - SP
Instruction SP
Function  The SP instruction subtracts a packed-decimal number(second operand) from another
packed decimal number (first operand), the result of which replaces the first operand in
packed-decimal form.
 The instruction computes the difference by changing the sign of a copy of the second
operand and adding it to the first operand.
 The lengths of the operands (L1 and L2) are to be explicitly specified. The lengths in
the instruction code are less by 1 than the actual length.
Syntax SP D1(L1,B1),D2(L2,B2)
Opcode
FB L1 L2 B1 D1 B2 D2
Condition Code 1 Difference Zero
2 Difference negative
3 Difference positive
4 Overflow
Program Exceptions 1. Access – Fetch 2nd operand, Store 1st operand
2. Decimal overflow.
3. Data.
Example SP 0(4,R1),0(2,R2)
Opcode – FB 31 10 00 20 00
0(R1) 00 01 23 4C 00 01 14 8C
0(R2) 08 6C 08 6C

Multiply Packed - MP
Instruction MP
Function  The MP instruction computes the product of two packed-decimal numbers, the first
operand being the multiplicand and second, the multiplier.
 The product replaces the multiplicand.
 If the leading zeros are ignored, the number of digits in a decimal integer product
cannot exceed the sum of the number of digits in the operands.
 To ensure that the product will fit into the L1 bytes of the first operand field, the MP
instruction restricts the operands as follows:
 L2 <= 8 and L2 <L1 (Violation results in specification exception).
 L1 must contain at least L2 bytes of leading zeros (Violation results in data exception).
Syntax MP D1(L1,B1),D2(L2,B2)
Opcode
FC L1 L2 B1 D1 B2 D2
Condition Code Condition code remains unchanged.
Program Exceptions 1. Access – Fetch 2nd operand, Store 1st operand.
2. Specification.
3. Data exception.
Example MP 0(4,R1),0(2,R2)
Opcode – FC 31 10 00 20 00
0(R1) 00 01 23 4C 01 06 12 4C
0(R2) 08 6C 08 6C

Divide Packed - DP
Instruction DP
Function  The DP instruction divides two packed-decimal numbers, that are specified as the first
and second operands. The quotient and the remainder replaces the dividend.
 There is always a remainder, even if it is zero.
 The largest possible absolute value of a remainder in an integer division is 1 less than
the divisor, which means the remainder can occupy as many bytes as the divisor. So,
the instruction always uses L2 bytes for the remainder and L1 – L2 bytes for the
quotient.
 The sign of the quotient is determined from those of the operands. The sign of the
remainder is that of the dividend. The rule applies for zero results.
 The DP instruction restricts the operands as follows.
 L2 <= 8 and L2 <L1 (Violation results in specification exception).
 The leftmost digit of the first operand must be zero. (Violation results in decimal divide
exception. The same will occur if the divisor is zero).
Syntax DP D1(L1,B1),D2(L2,B2)
Opcode
FD L1 L2 B1 D1 B2 D2
Condition Code Condition code remains unchanged.
2. Specification.
3. Decimal divide exception.
4. Data.
Example DP 0(4,R1),0(2,R2)
Opcode – FD 31 10 00 20 00
0(R1) 00 01 23 4C 01 4C 03 0C
0(R2) 08 6C 08 6C

Compare Packed - CP
Instruction CP
Function  The CP instruction algebraically compares the values of two packed-decimal numbers
and sets the condition code accordingly.
Syntax CP D1(L1,B1),D2(L2,B2)
Opcode
F9 L1 L2 B1 D1 B2 D2
Condition Code 0 Operands equal
1 First operand low
2 First operand high
Program Exceptions 1. Access – (fetch, operands 1 and 2).
2. Data.
Example CP 0(4,R1),0(2,R2)
Opcode – F9 31 10 00 20 00
0(R1) 00 01 23 4C 00 01 23 4C
0(R2) 08 6C 00 00 08 6C 00 00

Zero and Add Packed - ZAP
Instruction ZAP
Function  The ZAP instruction replaces the contents of the first operand field with a copy of the
packed-decimal number in the second operand field, which is adjusted appropriately to
match the length L1 of the first field, after necessary truncation or left padding with
zeros.
Syntax ZAP D1(L1,B1),D2(L2,B2)

Opcode
F8 L1 L2 B1 D1 B2 D2
Condition Code 0 Result is zero
1 Result is negative
2 Result is positive
3 Overflow

2. Decimal overflow.
3. Data.
Example ZAP 0(4,R1),0(2,R2)
Opcode – F8 31 10 00 20 00
0(R1) Insignificant 00 00 08 6C
0(R2) 08 6C 00 00 08 6C 00 00

Shift and Round Packed - SRP
Instruction SRP
Function  The SRP instruction shifts the packed-decimal at the first operand location by the
value specified at the rightmost 6 bits of the second operand which is in two’s
complement binary number system.
 A positive value represents a left shift whereas a negative value represents a right
shift. To round before a shift, the third operand is added to the leftmost of the digits
which are shifted out and the carry is propagated.
 The value is then shifted right(rounding occurs only for right shifts). The length in the
instruction code is less by 1 than the actual length.
Syntax SRP D1(L1,B1),D2(B2),I3

Opcode
F0 L1 I3 B1 D1 B2 D2
Condition Code 0 Result is zero
1 Result is negative
2 Result is positive
3 Overflow
Program Exceptions 1. Access (fetch and store, operand 1).
2. Data.
3. Decimal Overflow.
Example SRP 0(4,R1),B’111110’,6
Opcode – F0 36 10 00 00 3E
0(R1) 01 23 45 6C 00 01 23 5C

Shifts, Character Manipulation & Subroutines

Shift Instructions : Overview
Introduction:
 Shift instructions change the position of bits of the operand in a uniform pattern, depending on the type of shift
used.
 Shift instructions operate only on general-purpose registers.
 Shifts can be classifies in two ways.
 The first is based on the direction of shift, which can be either a left shift or a right shift.
 In the other classification, which is based on the type of the operand, a shift can either be logical or arithmetic.
Logical Shift:
 A logical shift instruction treats data as a string of discrete bit patterns.
 It assumes that the bits collectively don’t own any meaning though in reality, it’s not true.
 When a register undergoes a logical shift, all 32 bits are involved in the shift.
 The bits shifted beyond the edge of the register are lost.
 Zeros are introduced in the other end.
 The following figure depicts a logical shift left.
Register
Bits shifted out here are lost. Zeros are inserted here.
 The following figure depicts a logical shift right.
Register
Zeros are inserted here. Bits shifted out here are lost.

Shift Instructions : Overview
Arithmetic Shift:
 An arithmetic shift instruction treats data as integers in two’s complement form.
 When contents of a register undergo an arithmetic shift, not all 32 bits are involved in the shift. The sign bit is not
involved in the shift.
 This ensures that the sign of the number remains unchanged.
 If a bit being shifted out of the sign bit differs from the sign bit, an overflow occurs.
 The bits that are shifted beyond the edge of the register are lost.
 Zeros are introduced into the other end.
 The following figure depicts what an arithmetic shift left achieves.
Register
S
Zeros are inserted here.
Bits shifted out here are lost.

 The following figure shows what an arithmetic shift right achieves.
Register
S
Bits shifted out here are lost.
Sign bit is inserted here
The System 390 also provides instructions to shift 64 bits held in an even-odd register pair. These are called, double
shifts. The following discussion will focus on the instructions provided to achieve shifting.

An arithmetic shift to left is equivalent to multiplication by powers of 2and shifting right is equivalent to division
by powers of 2!
 It is a common programming practice to use arithmetic shifts instead of multiplication or division if the multiplier or
divisor is a number that is a power of 2.
Shift Left Logical - SLL
Instruction SLL
Function  This instruction shifts the 32-bit first operand left, the number of bits specified by the
second-operand address.
 The second-operand address is not used to address data; its rightmost six bits indicate
the number of bit positions to be shifted. The remainder of the address is ignored.
 Bits 12-15 of the instruction are ignored.
Syntax SLL R1, D2(B2)
Opcode
89 R1 B2 D2
Example The instruction below shifts contents of R1 left by 2 bits.
SLL R1, 2
89 10 00 02
R1 FF FF FF FF FF FF FF FC

Shift Right Logical - SRL
Instruction SRL
Function  This instruction shifts the 32-bit content of the register specified as the first operand,
the number of bits specified by the second-operand address.
 The second-operand address is not used to address data; it’s rightmost six bits
indicate the number of bit positions to be shifted. The remainder of the address is
ignored.
 Bits 12-15 of the instruction are ignored.
Syntax SRL R1, D2(B2)
Opcode
88 R1 B2 D2
Example The instruction below shifts contents of register R5 right by 2 bits.
SLL R5, 2
88 50 00 02
R5 FF FF FF FF 3F FF FF FF

Shift Left Arithmetic - SLA
Instruction SLA
Function  The 31-bit numeric part of the signed first operand (general-purpose register) is shifted
left the number of bits specified by the second-operand.
 The sign bit is not involved in the shifting.
 Zeroes are inserted to the right.
Syntax SLA R1, D2(B2)
Opcode
8B R1 B2 D2
Condition Code 0 – Result zero
1 – Result negative
2 – Result positive
3 – Overflow
Program Exceptions Floating point overflow.
Example The instruction below shifts contents of R1 left by 2 bits.
SLA R1, 2(R0)
8B 10 00 02

Shift Right Arithmetic - SRA
Instruction SRA
Function  This instruction shifts the 31-bit numeric part of the signed first operand (general-
purpose register) right, the number of bits specified by the second-operand.
 The sign bit is not involved in the shifting.
 The content of the sign bit is inserted in place of the bits being shifted right .
Syntax SRA R1, D2(B2)
Opcode
8A R1 B2 D2
Example The instruction below shifts contents of R1 right by 2 bits.
SRA R1, 2(R0)
8A 10 00 02
R1 FF FF FF FF FF FF FF FF

Shift Left Double Logical - SLDL
Instruction SLDL
Function  This instruction shifts left, the contents of an even-odd register pair specified as the
first operand.
 The content of the registers is treated as a 64 bit unsigned binary number.
 The number of bits to be shifted is specified by the second operand and is restricted to
a maximum of 63.
Syntax SLDL R1, D2(B2) 
Opcode
8D R1 B2 D2
Program Exceptions Specification exception.
Example The following instruction shifts contents of the even-odd register pair R4-R5 left by 2 bits.
SLDL R4, 2
8D 40 00 02

Shift Right Double Logical - SRDL
Instruction SRDL
Function  This instruction shifts right, the contents of an even-odd register pair specified as the
first operand.
 The content of the registers is treated as a 64 bit unsigned binary number.
 Zeroes are inserted to the left.
a maximum of 63.
Syntax SRDL R1, D2(B2) 
Opcode
8C R1 B2 D2
Example The following instruction shifts contents of the even-odd register pair R4-R5 right by 2 bits.
SRDL R4, 2
8C 40 00 02
R4 FF FF FF FF 3F FF FF FF

Shift Left Double Arithmetic - SLDA
Instruction SLDA
Function  Shifts left, the 63-bit numeric part of the even-odd register pair specified as the first
operand.
 The content of the registers is treated as a 64 bit signed binary number.
 The sign bit remains unchanged and does not participate in the shift.
a maximum of 63.
 If one or more bits unlike the sign bit are shifted out of bit position 1 of the even-
numbered register, an overflow occurs, and condition code 3 is set.
Syntax SLDA R1, D2(B2) 
Opcode
8F R1 B2 D2
Condition Code 0 – Result is zero
3 – Overflow
Program Exceptions 1. Specification exception.
2. Fixed point overflow.
Example The following instruction shifts contents of the even-odd register pair R4-R5 left by 2 bits.
SLDA R4, 2
8F 40 00 02

Shift Right Double Arithmetic - SRDA
Instruction SRDA
Function  Shifts right, the 63-bit numeric part of the even-odd register pair specified as the first
operand.
 The content of the registers is treated as a 64 bit signed binary number.
 The sign bit remains unchanged and does not participate in the shift.
 The sign bit is inserted to the left.
a maximum of 63.
Syntax SRDA R1, D2(B2) 
Opcode
8E R1 B2 D2
Condition Code 0 – Result is zero
Example The following instruction shifts right, the contents of the even-odd register pair R4-R5 by 2
bits.
SRDA R4, 2
8E 40 00 02
Move Characters – MVC

Instruction MVC
Function  Copies the consecutive bytes starting from the effective address specified by the
second operand into the area pointed to by the first operand.
 The number of bytes to be copied is specified as the length parameter.
 In the mnemonic the length is stored as one less than the specified value.
 The bytes are copied one at a time, left to right.
 The maximum length of the data that can be copied is 256.
Syntax MVC D1(L,B1), D2(B2)
Opcode
D2 L B1 D1 B2 D2
Program Exceptions Access – Fetch 2nd operand, Store 1st operand.
Examples The following instruction moves 5 bytes of data starting from 20(R4), to the area in memory
starting from 50(R5).
MVC 50(5,R5), 20(R4)
Opcode - D2 04 50 32 40 14
20(R4) C1 C2 C3 C4 C5 C1 C2 C3 C4 C5
50(R5) D1 D2 D3 D4 D5 C1 C2 C3 C4 C5
This instruction moves a single byte of data from location 0(R4) to location 0(R5).
MVC 0(1,R5), 0(R4)
Opcode - D2 00 50 00 40 00
0(R4) C1 C2 C3 C4 C1 C2 C3 C4
0(R5) FF FF FF FF C1 FF FF FF
This example illustrates the way an MVC instruction can be used to clear an area in
storage.
MVC 1(4,R4), 0(R4)
Opcode – D2 03 40 01 40 00
0(R4) 40 FF FF FF 40 40 40 40

Move Characters – MVC
Additional Info  The restriction on the number of bytes that can be copied (256) is imposed by the
instruction format. As there is only one byte that can be used for length, the maximum
value it can hold is 255.
 The possible range of values a byte can hold is 00 – FF. As an operation with zero
length makes no sense, the mnemonic treats the length supplied as length+1, so that
256 is the maximum value and not 255.

Move Immediate – MVI
Instruction MVI
Function  It replaces the contents of the single byte of storage specified by the first operand with
the immediate data that is specified as the second operand in the instruction.
Syntax MVI D1(B1), I2
Opcode
92 I2 B1 D1
Instruction Format SI
Program Exceptions Access – Store 1st operand.
Example The following instruction moves the immediate data C‘S’ to location 20(R4).
MVI 20(R4), C’S’
Opcode - 92 E2 40 14
20(R4) C1 C2 C3 C4 C5 E2 C2 C3 C4 C5
Additional Info  The immediate data specified should be a self-defining term. Not essentially a
character, but can also be the EBCDIC equivalent of the character. For example one
can either use C’S’ or X’E2’ to represent the character S.
 These self-defining terms are part of the instruction and are not allocated storage.
 C’S’ should never be confused with =C’S’. While the former is a self-defining term, the
latter is a literal. They cannot be used interchangeably.

Move Character Long – MVCL
Instruction MVCL
Function  This instruction overcomes the length limitation imposed by the MVC instruction. It’s
similar to MVC in the sense that both are used to copy data across storage.
 The MVCL instruction copies the bytes starting from the address location specified
with the second operand, into the address location pointed to by the first operand.
 Both the operands are even-odd register pairs.
 The R1 even register contains the destination address.
 The R2 even address contains the source address.
 Bits 8-31 of the R1 odd register indicate the number of characters to be copied. I.e. the
destination length.
 Bits 8-31 of the R2 odd register specify the length of the source.
 If the source length is less than the destination length, then the value in bits 0-7 of the
R2 odd register is used to pad the destination.
 In case of destructive overlap, the move is not performed. A condition code is set.
 This instruction changes the contents of the registers specified.
Syntax MVCL R1, R2 
Opcode
0E R1 R2
Condition Code 0 – Operands are of equal length; data copied.
1 – Destination length shorter; data copied and truncated.
2 – Destination length longer; data copied and padded.
3 – Destructive overlap; no characters copied.
2. Specification exception.

Move Character Long – MVCL
Example MVCL R2, R4

Opcode – 0E 24
0(R2) FF FF FF FF FF FF FF E1 E2 E3 E4 E5 E6 E7
FF FF FF FF FF FF FF E8 40 40 40 40 40 40
R3 00 00 00 0E Unknown
0(R4) E1 E2 E3 E4 E5 E6 E7 Unchanged
E8 FF FF FF FF FF FF
R5 40 00 00 08 Unknown
Condition code – 2
Additional Info  The maximum size of data that can be copied in one shot with this instruction is 16 MB
= 224.
 This is one of the few interruptible instructions. This is because of the maximum size
permitted. If interrupted, the execution will be resumed.
 The number of characters to be moved with MVC should be known at assemble time.
But, with MVCL, the length can be dynamically used, as the registers are set with
length values at run-time.

Compare Logical Characters – CLC
Instruction CLC
Function  Compares the consecutive bytes starting from the address specified with the second
operand, with bytes starting from the address specified with the first operand.
 The number of bytes to be compared is mentioned as the length parameter.
 In the mnemonic, the length is stored one less than the specified value.
 The characters are compared one at a time, left to right.
 The maximum length of the data that can be compared is 256.
Syntax CLC D1(L,B1), D2(B2)
Opcode
D5 L B1 D1 B2 D2
Condition Code 0 – Operands equal
1 - First operand low
2 - First operand high
Program Exceptions Access – Fetch 2nd operand, 1st operand.
Example The following instruction compares the 5 bytes of data starting from 20(R4), with the bytes
in memory starting from 50(R5) and sets the condition code accordingly.
CLC 50(5,R5), 20(R4)
Opcode – D5 04 50 32 40 14
20(R4) C1 C2 C3 C4 C5 Unchanged
50(R5) D1 D2 D3 D4 D5 Unchanged

Compare Logical Immediate – CLI
Instruction CLI
Function  This instruction sets up the condition code after comparing the single byte of storage
specified with the first operand with the immediate data contained in the instruction as
the second operand.
Syntax CLI D1(B1), I2
Opcode
95 I2 B1 D1
Condition Code 0 – Operands equal
1 - 1st operand low
2 - 2nd operand low
Program Exceptions Access – Fetch 1st operand.
Example The following instruction compares the immediate data X’C1’ with the data at 0(R15).
CLI 0(R15), X’C1’
Opcode - 95 C1 F0 00
0(R15) C1 C2 C3 C4 Unchanged
Compare Logical Character Long – CLCL

Instruction CLCL
Function  The MVCL instruction compares the bytes starting from the address specified with the
second operand, with the bytes from address location pointed to by the first operand.
 Both the operands are even-odd register pairs.
 The R1 even register contains the destination address.
 The R2 even address contains the source address.
 Bits 8-31 of the R1 odd register indicate the number of characters to be copied. I.e. the
destination length.
 Bits 8-31 of the R2 odd register specify the length of the source.
 If the source length is less than the destination length, then the value in bits 0-7 of the
R2 odd register is used to pad the source.
 This instruction changes the contents of the registers specified.
 The maximum size of the data that can be compared is 16MB.
Syntax CLCL R1, R2 
Opcode
0F R1 R2
Condition Code 0 – Operands are equal.
1 - First operand low.
2 - First operand high.
Program Exceptions 1. Access – Fetch 1st operand, 2nd operand.
Example CLCL R4, R6
Opcode – 0F 46
0(R4) E1 E2 E3 E4 E5 Unchanged
E6 E7 E8 FF
R5 00 00 00 09 Unknown
0(R6) E1 E2 E3 E4 Unchanged
E5 E6 E7 E8
R7 FF 00 00 08 Unknown

Branch And Save Register – BASR
Instruction BASR
Function  The BASR instruction places the address of the next instruction to be executed, which
is pointed by the PSW, into the register indicated by R1.
 Then a branch occurs to the location indicated by R2.
 If register R2 is R0, then no branch occurs.
Syntax BASR R1, R2
Opcode
0D R1 R2
Example Assume that R8 is the base register of the CSECT and PSW address field has the value
80 FE 02 04
BASR R1, R2
Opcode - 0D 12
R1 12 34 43 21 80 FE 02 04
R2 80 FE 03 00 Unchanged
R8 80 FE 02 00 80 FE 03 00

Branch And Save – BAS
Instruction BAS
Function  The BAS instruction places the address of the next instruction to be executed, which is
pointed by the PSW, into the register indicated by R1.
 Then a branch occurs to the location computed by the second operand.
 This instruction sets the base register of the CSECT, as like all branch instructions.
Syntax BAS R1, D2(X2,B2)
Opcode
4D R1 X2 B2 D2
Example Assume that R8 is the base register of the CSECT and PSW address field has the value
80 FE 02 04
BAS R1, 100(R8)
Opcode - 4D 18 00 64
R1 12 34 43 21 80 FE 02 04
R8 80 FE 02 00 80 FE 02 64

Execute - EX
Instruction EX
Function  The EX instruction executes a single instruction specified at the effective address
computed by the second operand.
 But, before that instruction is executed, the low order byte of the register indicated by
R1 is ORed with the second byte of the instruction. This is done by hardware, and the
actual instruction specified remains unchanged.
 This instruction helps in overcoming the limitation imposed by the MVC instruction. In
the MVC instruction, the length should be specified at assembly time and cannot be
dynamic.
Syntax EX R1, D2(X2,B2)
Opcode
44 R1 X2 B2 D2
Condition Code  The EX instruction itself does not set any condition code.
 The condition code depends on the target instruction.
Program Exceptions 1. Access – Fetch target instruction.
2. Execute exception when the target instruction is in turn an EXECUTE.
Example Assume that R8 is the base register of the CSECT and an MVC instruction is at location 40
from the base register.
EX R1, 40(R8)
44 18 00 28
R1 00 00 00 01 Unknown
40(R8) D2 00 20 00 20 01 Unchanged
[The target instruction]
0(R2) 40 C1 C2 C1 C1 C2
The instruction at 40(R8) : MVC 0(1,R2), 1(R2)
It moved the byte at 1(R1) to 0(R1)

Logical Instructions

Boolean Operations - AND
AND Operation:
 The table below depicts the impact of the AND operation.
 The AND operation is usually used to set the switches OFF.
 The operations are done on individual bits.
A B A AND B
0 0 0
0 1 0
1 0 0
1 1 1

Boolean Operations - OR
OR Operation:
 The table below depicts the impact of the OR operation.
 The OR operation is usually used to set the switches ON.
A B A OR B
0 0 0
0 1 1
1 0 1
1 1 1

Boolean Operations - XOR
XOR Operation:
 The table below depicts the impact of the XOR operation.
 The XOR operation is usually used to flip bits of the switches.
A B A XOR B
0 0 0
0 1 1
1 0 1
1 1 0

And Register – NR
Instruction NR
Function  The NR instruction ANDs the operand indicated by the register R1 with the second
operand, the general-purpose register R2, and moves the result into the register
indicated by R1.
Syntax NR R1, R2
Opcode
14 R1 R2
1 – Result non-zero
Example NR R1, R2
Opcode - 14 12
R1 FF E2 F1 80 00 00 00 80
R2 00 00 00 F0 Unchanged

And – N
Instruction N
Function  This instruction ANDs the operand indicated by register R1 with the full word, which is
pointed by the effective address computed with the second operand and stores the
result in the first operand indicated by R1.
Syntax N R1, D2(X2,B2)
Opcode
54 R1 X2 B2 D2
Example N R1, 200(R2)
Opcode - 54 12 00 C8
R1 FF E2 F1 80 00 00 00 80
200(R2) 00 00 00 F0 Unchanged

And Character – NC
Instruction NC
Function  The NC instruction ANDs the character string pointed to by the first operand with the
character string pointed to by the second operand.
 The result is stored in the first operand.
 The number of bits to be involved in the operation is decided by the length parameter
specified in the first operand.
Syntax NC D1(L,B1), D2(B2)
Opcode
D4 L B1 D1 B2 D2
Example NC 0(4,R1), 0(R2)
Opcode – D4 03 10 00 20 00
0(R1) FF E2 F1 88 00 00 00 88
0(R2) 00 00 00 FF Unchanged

And Immediate – NI
Instruction NI
Function  The NI instruction ANDs the single byte pointed to by the first operand with the
immediate data, which is the second operand.
 The result is stored in the location pointed to by the first operand.
Syntax NI D1(B1), I2
Opcode
94 I2 B1 D1
Example NI 0(R4), X’FA’
Opcode - 94 FA 40 00
0(R4) 87 82

Or Register – OR
Instruction OR
Function  The OR instruction ORs the operand indicated by the register R1 with the second
indicated by R1.
Syntax OR R1, R2
Opcode
16 R1 R2
Example OR R1, R2
Opcode – 16 12
R1 FF E2 F1 98 FF E2 F1 F8

Or – O
Instruction O
Function  This instruction ORs the operand indicated by register R1 with the full word, which is
pointed by the effective address computed with the second operand and stores the
result in the first operand indicated by R1.
Syntax O R1, D2(X2,B2)
Opcode
56 R1 X2 B2 D2
Example O R1, 200(R2)
Opcode - 56 12 00 C8
R1 00 00 00 80 00 00 00 F0
200(R2) 00 00 00 70 Unchanged

Or Character – OC
Instruction OC
Function  The OC instruction ORs the character string pointed to by the first operand with the
Syntax OC D1(L,B1), D2(B2)
Opcode
D6 L B1 D1 B2 D2
Example OC 0(4,R1), 0(R2)
Opcode – D6 03 10 00 20 00
0(R1) FF E2 F1 88 FF FF FF FF
0(R2) FF FF FF FF Unchanged

Or Immediate – OI
Instruction OI
Function  The OI instruction ORs the single byte pointed to by the first operand with the
Syntax OI D1(B1), I2
Opcode
96 I2 B1 D1
Example OI 0(R4), X’00’
Opcode - 96 00 40 00
0(R4) 00 00

XOR Register – XR
Instruction XR
Function  The XR instruction XORs the operand indicated by the register R1 with the second
indicated by R1.
Syntax XR R1, R2
Opcode
17 R1 R2
Example XR R1, R2
Opcode – 17 12
R1 FF E2 F1 98 FF E2 F1 68

XOR – X
Instruction X
Function  This instruction XORs the operand indicated by register R1 with the full word, pointed
by the effective address computed with the second operand and stores the result in
the first operand indicated by R1.
Syntax X R1, D2(X2,B2)
Opcode
57 R1 X2 B2 D2
Example X R1, 200(R2)
Opcode - 57 12 00 C8
R1 00 00 00 80 00 00 00 F0
200(R2) 00 00 00 70 Unchanged

XOR Character – XC
Instruction XC
Function  The XC instruction XORs the character string pointed to by the first operand with the
Syntax XC D1(L,B1), D2(B2)
Opcode
D7 L B1 D1 B2 D2
Example XC 0(4,R1), 0(R2)
Opcode – D7 03 10 00 20 00
0(R1) FF E2 F1 88 FF 1D 0E 77
0(R2) FF FF FF FF Unchanged

XOR Immediate – XI
Instruction XI
Function  The XI instruction XORs the single byte pointed to by the first operand with the
Syntax OI D1(B1), I2
Opcode
97 I2 B1 D1
Example XI 0(R4), X’FF’
Opcode - 97 FF 40 00
0(R4) FF 00

Test under Mask – TM
Instruction TM
Function  The TM instruction tests the bits pointed to by the first operand.
 The bits are tested by ANDing them according to the selection provided by the
 The contents of the operands are not modified.
 The condition code is set to reflect the values of the bits.
Syntax TM D1(B1), I2
Opcode
91 I2 B1 D1
Condition Code 0 - All tested bits are zeroes.
1 – Result mixed.
2 ––
3 - All tested bits are ones.
Program Exceptions Access – Fetch 1st operand.
Example TM 0(R4), X’40’
Opcode - 91 40 40 00
0(R4) C0 Unchanged

Conversion Instructions

Pack - PACK
Instruction PACK
Function  The pack instruction converts decimal numbers from a zoned (second operand) form
into a packed (first operand) form.
 L2 bytes of the second operand are converted to a packed-decimal format without
validating it. The right justified result replaces the L1 bytes of the first operand.
 It L1 is larger than necessary, the result is padded on the left with binary zeros. If
smaller, truncation takes place at the left.
Syntax PACK D1(L1,B1),D2(B2),I3

Opcode
F2 L1 L2 B1 D1 B2 D2
Examples 1. PACK 0(4,R1),10(3,R1)
Opcode – F2 32 10 00 10 0A
0(R1) Irrelevant 00 00 12 3F
10(R2) F1 F2 F3 Unchanged
2. PACK 0(4,R1),0(4,R1)
Opcode – F2 33 10 00 10 00
0(R1) F1 F2 F3 F4 00 01 23 4F

Unpack - UNPK
Instruction UNPK
Function  The UNPK instruction converts decimal numbers from a packed (second operand)
form into a zoned (first operand) form.
 L2 bytes of the second operand are converted to a zoned-decimal format without
validating it. The right justified result replaces the L1 bytes of the first operand.
 If L1 is larger than necessary, the result is padded on the left with EBCDIC zeros. If
smaller, truncation takes place at the left.
Syntax UNPK D1(L1,B1),D2(B2),I3

Opcode
F3 L1 L2 B1 D1 B2 D2
Examples 1. UNPK 0(4,R1),10(2,R1)
Opcode – F3 31 10 00 10 0A
0(R1) Irrelevant F0 F1 F2 C3
10(R1) 123C Unchanged
2. UNPK 0(3,R1),0(3,R1)
Opcode – F3 22 10 00 10 00
0(R1) 12345C F3 F4 C5

Move with Offset - MVO
Instruction MVO
Function  The rightmost 4 bits of the first operand remain unchanged and the rest of the first
operand is replaced by the second operand.
 If the first field is longer the instruction pads the result on the left with zeros and if it is
short, the result is truncated on the left without warning.
Syntax MVO D1(L1,B1),D2(L2,B2)

Opcode
F1 L1 L2 B1 D1 B2 D2
Examples 1. MVO 0(4,R1),10(3,R1)
Opcode – F1 32 10 00 10 0A
0(R1) 12 34 56 7C 02 34 56 7C
10(R1) 23 45 67 Unchanged
2. MVO 0(4,R1),1(3,R1)
Opcode – F1 32 10 00 10 01
0(R1) 12 34 56 7C 03 45 67 CC

Move Numerics - MVN
Instruction MVN
Function  The MVN instruction moves the rightmost 4 bits of each byte in the second operand
field to the corresponding bits of the first operand field.
Syntax MVN D1(L,B1),D2(B2)

Opcode
D1 L B1 D1 B2 D2
Examples 1. MVN 0(3,R1),10(R1)
Opcode – D1 02 10 00 10 0A
0(R1) F1 F2 F3 F4 F5 F6
10(R1) F4 F5 C6 Unchanged
2. MVN 2(1,R1),10(R1)
Opcode – D1 00 10 02 10 0A
0(R1) 12 34 5C 12 34 5D
10(R1) 1D Unchanged
The MVN instruction in this example changes the sign of the packed-decimal number.

Move Zones - MVZ
Instruction MVZ
Function  The MVZ instruction moves the leftmost 4 bits of each byte in the second operand field
to the corresponding bits of the first operand field.
Syntax MVZ D1(L,B1),D2(B2)

Opcode
D3 L B1 D1 B2 D2
Examples 1. MVZ 0(3,R1),10(R1)
Opcode – D3 02 10 00 10 0A
0(R1) 12 34 56 F2 F4 F6
10(R1) FF FF FF Unchanged
2. MVZ 2(1,R1),10(R1)
Opcode – D3 00 10 02 10 0A
0(R1) F1 F2 D3 F1 F2 F3
10(R1) F6 Unchanged

Translate - TR
Instruction TR
Function  The TR instruction replaces 8-bit quantities with other 8-bit quantities that are
determined according to a translation table.
 Each byte in the first operand is used as an 8-bit index into the translation table
addressed by the second operand and is replaced by the corresponding value from
the table.
Syntax TR D1(L,B1),D2(B2)
Opcode
DC L B1 D1 B2 D2
Example 1. TR 0(5,R1),10(R1)
Opcode – DC 04 10 00 10 0A
0(R1) 02 00 01 03 01 C3 C1 C2 C4 C2
10(R1) C1 C2 C3 C4 C6 Unchanged

Translate and Test - TRT
Instruction TRT
Function  The TRT instruction uses each byte in the first operand as an 8-bit index into a
translation table (at second operand). If the corresponding byte in the table is zero the
next byte in the first operand is processed similarly.
 If all the corresponding bytes in the table are zeros, the condition code is set to zero
and the instruction is complete.
 If the byte in the table is non-zero, the instruction loads R1 with the address of the byte
in the first operand which is mapped to the non-zero value, and the non zero value
from the table will be inserted in the low order byte of R2.
Syntax TRT D1(L,B1),D2(B2)

Opcode
DD L B1 D1 B2 D2
Condition Code 0 All the corresponding bytes in the table were zeros.
1 Corresponding byte non-zero not for the last byte in the first operand.
2 Corresponding byte non-zero for the last byte in the first operand.
Example The following example validates the 8 bytes from R4 to be numeric
TRT 0(8,R4),NUMTABLE
BNZ WPOGONE
.
.
.
NUMTABLE DC 256X’FF’
ORG NUMTABLE+C’0’
DC 10X’00’
ORG

Edit - ED
Instruction ED
Function  The ED instruction converts one or more packed decimal numbers pointed by the
second operand (to be called source) into zoned decimal format and store it at the
location pointed by the first operand.
 The location specified by the first operand not only acts as the destination address but
also, has in it a pattern to guide the conversion.
 The pattern, of length L, after execution of this instruction will be replaced by the
result.
Syntax ED D1(L,B1),D2(B2)
Opcode
DE L B1 D1 B2 D2
Condition Code 0 Zero length of last field is zero
1 Last field is negative
2 Last field is positive
2. Data.

Edit – ED
For clarity, the discussion is divided into 2 parts.

 Construction of the pattern mask.
 Conversion mechanism.
Description:
The mask is formed by 2 components, viz., fill byte and the pattern byte. The pattern can be made up of any
combination of the following 4 items.
Pattern Byte Value

Digit Selection X’20’
Significance Starter X’21’
Field Separator X’22’
Message Byte Any other EBCIDIC
The mask is of format

ffpppp….
Where,
ff is the fill byte.
and pppp is the pattern

Edit - ED
Fill Byte:
First byte of the pattern is used as the fill byte. A fill byte is used to fill up the pattern where ever necessary.
Source Digits:
These are the bytes in packed decimal format, which will be converted. The starting byte is pointed by the second
operand.
Significance Indicator:
This is a toggle bit which is used to indicate whether the subsequent pattern byte should be replaced with the zoned
format of the corresponding source nibble or to be substituted by the fill character or to be left unaltered.
Digit Selector:
Encountering this in the pattern will result in the pattern byte being substituted by the zoned equivalent of the source
nibble or being replaced by the fill character. This zoned equivalent is replaced, if the significance indicator is turned on
or if the source nibble is a non-zero numeric digit. In case that the significance indicator is off and a non-zero numeric
digit is encountered, the significance indicator is turned on. If the significance indicator is off and if the source nibble is
zero, the digit selector is replaced by the fill character.
Significance Starter :
This is functionally the same as the digit selector. But the difference being that encountering this will turn on the
significance indicator irrespective of the source nibble.
Field Separator:
The field separator as the name suggests is used to indicate the beginning of the next destination field, it also turns off
the significance indicator.
Message Bytes:
The Message bytes in the pattern are either replaced by the fill character or will remain unchanged in the result
depending upon the state of the significance indicator. They are used for punctuation, padding or in text parts of the
significant portion of the field or used to insert the sign symbols.

Edit – ED
Conversion mechanism
The following are the three possible transformations a pattern byte can undergo.
 Left unchanged.
 Replaced by a source digit expanded to its zoned format.
 Replaced by the 1st byte of the pattern, which is the fill byte.
The following are the two conditions when the significance indicator will be turned on.
 On encountering a significance starter.
 On encountering a digit selector and the current source digit is non-zero.
The following are the three conditions when the significance indicator will be turned off.
 At the start of the pattern or in other words, beginning of the instruction execution.
 On encountering a PLUS sign in the right nibble of the current source byte.
 On encountering a field separator.

Edit - ED
Significance
Pattern byte Source digit Result
Indicator
 Change pattern to source digit’s zoned

X’20’ Non-zero 0 format.
 Turn on Significance indicator.
X’20’ Zero 0  Change pattern to fill character.

X’20’ Non-zero 1
format.

X’20’ Zero 1
format.

X’21’ Non-zero 0 format.
 Turn on significance indicator.
 Change pattern to fill character.

X’21’ Zero 0
 Turn on significance indicator.

X’21’ Non-zero 1
format.

X’21’ Zero 0
format.
No-
X’22’ 0/1  Turns off the significance indicator.
Significance
No-
Message byte 0  Change message byte to fill character.
Significance
No-
Message byte 1  Retain the same message byte.
Significance

Edit – ED
ED 0(13,R12),512(R12)
Example Opcode – DE 00 C0 00 C2 00
SOURCE AT LOCATION 512(R12)
02 57 42 6C
PATTERN AT LOCATION 0(R12) BEFORE EXECUTION
40 20 20 6B 20 21 20 4B 20 20 40 C3 D9
PATTERN AT LOCATION 0(R12) AFTER EXECUTION
40 40 F2 6B F5 F7 F4 4B F2 F6 40 40 40

Edit and Mark - EDMK
Instruction EDMK
Function  The EDMK instruction operates the same way ED works with just one difference.
EDMK will return the address of the first zoned number converted in the pattern.
 The address will be in R1. If no conversion to zoned format takes place to the pattern
after execution, R1 remains unchanged.
Syntax EDMK D1(L,B1),D2(B2)

Opcode
DF L B1 D1 B2 D2
Condition Code 0 Zero length of last field is zero
1 Last field is negative
2 Last field is positive
Program Exceptions 1. Access – Fetch 2nd operand, Store & fetch 1st operand.
2. Data.
Example EDMK 0(13,R12),512(R12)
Opcode – DF 0C C0 00 C2 00
R12 – 00 00 10 00
SOURCE AT LOCATION 512(R12) / 1200 :
02 57 42 6C
PATTERN AT LOCATION 0(R12) / 1000 BEFORE EXECUTION :

40 20 20 6B 20 21 20 4B 20 20 40 C3 D9
PATTERN AT LOCATION 0(R12) / 1000 AFTER EXECUTION :

40 40 F2 6B F5 F7 F4 4B F2 F6 40 40 40

String Instructions

Move String – MVST
Instruction MVST
Function  All or part of the second operand is placed in the first-operand location.
 The operation proceeds until the end of the second operand is reached or a CPU-
determined number of bytes have been moved, whichever occurs first.
 The CPU-determined number is at least one.
 The result is indicated in the condition code.
 The location of the leftmost byte of the first operand and second operand is designated
by the contents of general registers R1 and R2, respectively.
 The end of the second operand is indicated by an ending character in the last byte
position of the operand. The ending character to be used to determine the end of the
second operand is specified in bit positions 24-31 of general register 0.
 Bit positions 0-23 of general register 0 are reserved for possible future extensions and
must contain all zeros; otherwise, a specification exception is recognized.
Addressing Schemes
31 – bit addressing The contents of bit positions 1-31 of general registers R1 and R2 constitute the address,
and the contents of bit position 0 are ignored.
and the contents of bit positions 0-7 are ignored.
Syntax MVST R1,R2
Opcode
B255 R1 R2
Instruction Format RRE

Condition Code 0 -
1 Entire second operand moved; general register R1 updated with address of ending
character in first operand; general register R2 unchanged
2 -
2 CPU-determined number of bytes moved; general registers R1 and R2 updated with
addresses of next bytes
Program Exceptions 1. Access (fetch, operand 2; store, operand 1)

2. Operation (if the string-instruction facility is not installed)
3. Specification

Move String – MVST
Example Assume location STR1 contains the first string and STR2 the second string. LASTCHAR
contains the character X’FF’.
LA R4, STR1
LA R5, STR2
XR R0, R0
IC R0,LASTCHAR
MVST R4, R5
Opcode : B255 00 45
R4 00 00 12 00 00 00 12 03
LASTCHAR FF Unchanged
(00 00 12 00)
A1 A2 A3 A4 A5 A6 AB CD EF FF A5 A6
Address of STR1
(0 00 32 00)
AB CD EF FF B1 B2 Unchanged
Address of STR2
Condition code : 1

Search String – SRST
Instruction SRST
Function  The second operand is searched until a specified character is found, or the end of the
second operand is reached, or a CPU-determined number of bytes have been
searched, whichever occurs first. The CPU-determined number is at least 256.
 The result is indicated in the condition code.
 The location of the leftmost byte of the second operand is designated by the contents
of general register R2. The location of the first byte after the second operand is
designated by the contents of general register R1.
 The character for which the search occurs is specified in bit positions 24-31 of general
register 0.
Addressing Schemes
31 – bit addressing The contents of bit positions 1-31 of general register R1 and R2 constitute the address, and
the contents of bit position 0 is ignored.
and the contents of bit positions 0-7 are ignored.
Syntax SRST R1,R2
Opcode
B25E R1 R2

Condition Code 0 ---
1 Specified character found; general register R1 updated with address of character;
general register R2 unchanged.
2 Specified character not found in entire second operand; general registers R1 and R2
unchanged
3 CPU-determined number of bytes searched; general register R1 unchanged; general
register R2 updated with address of next byte.
Program Exceptions 1. Access (fetch, operand 2).
2. Operation (if the string-instruction facility is not installed).
3. Specification.

Search String – SRST
Example Assume location STRSTART is the starting location of the string to be searched and
STREND the location just after the ending character of the string. SRCHCHAR contains the
character to be searched, X’69’.
LA R4, STREND
LA R5, STRSTART
XR R0, R0
IC R0,SRCHCHAR
SRST R4, R5
Opcode : B25E 00 12
R4 00 00 12 0A 00 00 12 07
SRCHCHAR 69 Unchanged
(00 00 12 00) 12 23 34 45 56
Unchanged
Address of STRSTART 67 78 69 89 90
(1 00 12 0A)
Insignificant Insignificant
Address of STREND
Condition code : 1

Compare Logical String – CLST
Instruction CLST
Function  The first operand is compared with the second operand until unequal bytes are
compared, or the end of either operand is reached, or a CPU-determined number of
bytes have been compared, whichever occurs first.
 The CPU-determined number is at least 256. The result is indicated in the condition
code.
 The location of the leftmost byte of the first operand and second operand is designated
by the contents of general registers R1 and R2, respectively.
 The first and second operands may be of the same or different lengths. The end of an
operand is indicated by an ending character in the last byte position of the operand.
 The ending character to be used to determine the end of an operand is specified in bit
positions 24-31 of general register 0.
Addressing Schemes
31 – bit addressing In the 31-bit addressing mode, the contents of bit positions 1-31 of general registers R1 and
R2 constitute the address, and the contents of bit position 0 is ignored.
24 – bit addressing In the 24-bit addressing mode, the contents of bit positions 8-31 of general registers R1 and
R2 constitute the address, and the contents of bit positions 0-7 are ignored.
Syntax CLST R1,R2
Opcode
B25D R1 R2

Condition Code 0 - Entire operands equal; general registers R1 and R2 unchanged.
1 - First operand low; general registers R1 and R2 updated with addresses of last bytes
processed.
2 - First operand high; general registers R1 and R2 updated with addresses of last bytes
processed.
3 - CPU-determined number of bytes equal; general registers R1 and R2 updated with
addresses of next bytes.
Program Exceptions 1. Access (fetch, operands 1 and 2).
2. Operation (if the string-instruction facility is not installed).
3. Specification

Compare Logical String – CLST
Example Assume location STR1 is the starting location of string 1 and STR2 the starting location of
string 2. ENDCHAR contains the ending character, X’ED’.
LA R4, STR1
LA R5, STR2
XR R0, R0
IC R0,ENDCHAR
CLST R4, R5
Opcode : B2 5D 00 45
R4 00 00 12 00 00 00 12 02
R5 00 00 13 00 00 00 13 02
ENDCHAR ED Unchanged
(00 00 12 00)
12 34 56 78 89 ED Unchanged
Address of STR1
(00 00 13 00)
12 34 67 78 ED Unchanged
Address of STR2
Condition code : 1

DSECTS

DSECTS – Dummy Sections
 A dummy section provides a symbolic description of a data area that is defined.

 The dummy sections are used for description of the layout of the data area and cannot be used to initialize values.
 DSECT doesn’t allocate storage space.
 The DSECT uses the DS directive to describe the layout of the data area.
 Allocation of storage for the layout has to be handled independently.
 To use a symbol defined inside a dummy section, one should use the USING directive to designate a base
register.
 The base register should be subsequently loaded with the starting address of the area, there by establishing
addressiblity to the symbols inside the DSECT.

DSECTS – Dummy Sections
Example:
Assume that there is a data record of the following layout out in the memory.
Employee number 4 digits

Employee name 30 chars
Department 10 chars
Designation 3 chars
Date of birth 10 digits
Date of joining 10 digits
Gross salary 8 digits
The following will be the DSECT layout in the control section.

EMPLOYEE DSECT
EMPNUM DS F
EMPNAME DS CL30
EMPDEPT DS CL10
EMPDESG DS CL3
EMPDOBDS XL10
EMPDOJ DS XL10
EMPSAL DS PL5
The following is the method to refer any of the symbols defined in the DSECT give above. EMPDATA is the address of
the starting storage location where the record is stored.
USING EMPLOYEE,R1
LA R1,EMPDATA
MVC TEMPNAME(30),EMPNAME move the name to temp
……………………….
……………………….


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IBM ESA/390 ASSEMBLER COURSE

IBM ESA/390 Assembler Handbook page 2 of 178

IBM ESA/390 Assembler Handbook page 3 of 178

Address for Communication:

The Chief Executive Officer,

 +91-44-2541015, 2541097, 2541598

IBM ESA/390 Assembler Handbook page 4 of 178

 Warning! / Caution! / Don't do this!

 Do this! / Tip / Information.

 Even-odd register pair required.

IBM ESA/390 Assembler Handbook page 5 of 178

IBM ESA/390 Assembler Handbook page 9 of 178

IBM ESA/390 Assembler Handbook page 10 of 178

IBM ESA/390 Assembler Handbook page 11 of 178

CHANNEL SUB SYSTEM

Serial Channel Paths Parallel Channel Paths

IBM ESA/390 Assembler Handbook page 12 of 178

 Central controlling point of operations.

IBM ESA/390 Assembler Handbook page 13 of 178

There are two system states used by the 390 architecture.

IBM ESA/390 Assembler Handbook page 14 of 178

 16 General Registers in the system numbered 0 through 15.

 16 control Registers in the system, numbered 0 through 15.

Floating Point Registers:

 4 Floating Point Registers in the system, numbered 0, 2, 4 and 6.

IBM ESA/390 Assembler Handbook page 15 of 178

 16 access Registers in the system, numbered 0 through 15.

PSW and Interrupt Processing

IBM ESA/390 Assembler Handbook page 16 of 178

P Problem State/Supervisor State Indicator

PSW and Interrupt Processing

IBM ESA/390 Assembler Handbook page 17 of 178

 Six types of interrupts are supported by 390 architecture:

IBM ESA/390 Assembler Handbook page 18 of 178

 Originally, 370 series of machines used 24 bit addressing.

Ctrl Byte0 Byte1 Byte2

1 Byte0 Byte1 Byte2 Byte3

IBM ESA/390 Assembler Handbook page 19 of 178

Virtual Memory and Dynamic Address Translation

IBM ESA/390 Assembler Handbook page 20 of 178

Virtual Memory / Dynamic Address Translation

IBM ESA/390 Assembler Handbook page 21 of 178

Page Table Origin Real Address of Page 1 Page 1

IBM ESA/390 Assembler Handbook

© Aviation Software Development Consultancy India Ltd.

Page Table Origin Real Address of Page 4 Page 4

Page Table Origin Invalid Page 5

IBM ESA/390 Assembler Handbook page 23 of 178

IBM ESA/390 Assembler Handbook page 24 of 178

IBM ESA/390 Assembler Handbook page 25 of 178

IBM ESA/390 Assembler Handbook page 26 of 178

 A System 390 instruction is one, two or three halfwords in length.

IBM ESA/390 Assembler Handbook page 27 of 178

 RS format by definition specifies the 2 nd operand to be an effective address.

IBM ESA/390 Assembler Handbook page 28 of 178

IBM ESA/390 Assembler Handbook page 29 of 178

IBM ESA/390 Assembler Handbook page 30 of 178

IBM ESA/390 Assembler Handbook page 31 of 178

Decimal to Binary conversion

To convert Decimal integer I to Binary,

Binary equivalent will be b1b2...bn.

To convert 1410 into binary.

14 / 2 = 7 with remainder 0 (Q1 = 7 , bn = 0)

IBM ESA/390 Assembler Handbook page 32 of 178