Lecture06 140818

Lecture 06 – Capacitors (8/18/14) Page 06-1
LECTURE 06 - CAPACITORS
LECTURE ORGANIZATION
Outline
• Introduction
• pn junction capacitors
• MOSFET gate capacitors
• Conductor-insulator-conductor capacitors
• Deviation from ideal behavior in capacitors
• Summary
CMOS Analog Circuit Design, 3rd Edition Reference
Pages 46-52 and 654-657
CMOS Analog Circuit Design © P.E. Allen - 2016

INTRODUCTION
Types of Capacitors for CMOS Technology
1.) PN junction (depletion) d
xd
capacitors - +
- +
- +
- +
- +
- +
W1 W2 060204-01 + vD -
G D,S,B
2.) MOSFET gate capacitors Cox
n+ n+ p+
Cjunction p-well
060207-01
3.) Conductor-insulator-conductor Top Conductor

Bottom
capacitors Dielectric Conductor
Insulating layer
060206-02

Characterization of Capacitors
What characterizes a capacitor?
1.) Losses in a capacitor characterized by the quality factor of a capacitor is a measure of
the imaginary to real part of the impedance or admittance
1
Q= = CRp
CRs
where Rp is the equivalent resistance in parallel with the capacitor, C, and Rs is the
electrical series resistance (ESR) of the capacitor, C.
2.) Parasitic capacitors to ground from each node of the capacitor.
3.) The density of the capacitor in Farads/area.
4.) The absolute and relative accuracies of the capacitor.
5.) The Cmax/Cmin ratio which is the largest value of capacitance to the smallest when
the capacitor is used as a variable capacitor (varactor).
6.) The variation of a variable capacitance with the control voltage.
7.) Linearity, q = Cv.

PN JUNCTION CAPACITORS
PN Junction Capacitors in a Well
Generally made by diffusion into the well.
Anode Cathode
Substrate
rD
Cj Cj Cw C VB
VA
n+ p+ n+ p+ Anode Rwj Cathode
Rwj Rwj Rw Rs
Depletion
n-well Region
p- substrate
Fig. 2.5-011
Layout:
Minimize the distance between the p+ and n+ diffusions. n+ diffusion
Two different versions have been tested. p+ dif-

1.) Large islands – 9µm on a side fusion
n-well
2.) Small islands – 1.2µm on a side
Fig. 2.5-1A
PN-Junction Capacitors – Continued

The anode should be the floating node and the cathode must be connected to ac ground.
Experimental data (Q at 2GHz, 0.5µm CMOS)†:
Cmax Cmin Qmin Qmax
4 120
3.5
100
Small Islands
CAnode (pF)
3 C
Large Islands Anode Cathode
2.5 80
QAnode
Small Islands R-X Cathode
2 60 Bridge Voltage
C
1.5 Anode Cathode
40
Large Islands
1 R-X Cathode
Bridge Voltage 20
0.5
0 0
0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5
Cathode Voltage (V) Cathode Voltage (V) 060206-03
Terminal Small Islands (598 1.2µm x1.2µm) Large Islands (42 9µm x 9µm)
Under Test Cmax/Cmin Qmin Qmax Cmax/Cmin Qmin Qmax
Anode 1.23 94.5 109 1.32 19 22.6
Cathode 1.21 8.4 9.2 1.29 8.6 9.5
Electrons as majority carriers lead to higher Q because of their higher mobility.
The resistance, Rwj, is reduced in small islands compared with large islands  higher Q
†E. Pedersen, “RF CMOS Varactors for 2GHz Applications,” Analog Integrated Circuits and Signal Processing, vol. 26, pp. 27-36, Jan. 2001.
MOSFET GATE CAPACITORS

MOSFET Gate Capacitor Structure
The MOSFET gate capacitors have the gate as one terminal of the capacitor and some
combination of the source, drain, and bulk as the other terminal.
In the model of the MOSFET gate capacitor shown below, the gate capacitance is really
two capacitors in series depending on the condition of the channel.
1
Cgate =
1 1
+
Cox Cj
S G D B G Channel Resistance
Cox
Cox S D
n+ n+ p+
Cjunction p-well Cjunction

060207-02 B Bulk Resistance

MOSFET Gate Capacitor as a function of VGS with D=S=B

G D,S,B Capacitance
Cox Cox Cox
n+ n+ Weak
p+
Accumulation Inv. Strong
Cjunction p-well Inversion
Depletion Moderate VG-VD,S,B

Operation: Inversion 060207-03
In this configuration, the MOSFET gate capacitor has 5 regions of operation as VGS is
varied. They are:
1.) Accumulation
2.) Depletion
3.) Weak inversion
4.) Moderate inversion
5.) Strong inversion
For the first four regions, the gate capacitance is the series 1
combination of Cox and Cj given as, C gate =
1 1
+
Cox Cj

Use of a 3 Segment Model to Explain the Gate Capacitor Variation

Region Channel R Cox and Cj Cgate 3-Segment Model
Accumulation Large In series and Cgate ≈ Cox

Cj > Cox
Depletion In series and Cgate ≈ 0.5Cox

Large
Cj ≈ Cox ≈ 0.5Cj
Weak Large In series and Cgate ≈ Cj

Inversion Cj < Cox
Moderate Moderate In series and Cj < Cgate <

Inversion Cj < Cox Cox
Strong Small In parallel and Cgate ≈ Cox

Inversion Cj < Cox

MOSFET Gate Capacitor as a function of VGS with Bulk Fixed (Inversion Mode)
G D,S B Capacitance
Cox Cox B=D= S Cox
n+ n+ p+ Inversion VT shift
Mode MOS if VBS ≠ 0
Cjunction p-well
0 VG-VD,S
060207-04
Conditions:
• D = S, B = VSS
• Accumulation region removed by connecting bulk to ground
• Nonlinear
• Channel resistance:
L
Ron = 12K '(V -|V |)
P BG T
• LDD transistors will give lower Q because of the increased series resistance

Inversion Mode NMOS Capacitor

Best results are obtained G D,S
when the drain-source are Shown in inversion mode
D,S
connected to ac ground. Bulk R C
Cov Cox Cov
sj j B
p+ n+ n+
Rd Cd Csi Cd Rd G
p- substrate/bulk Rsi n- LDD
Fig. 2.5-2
Experimental Results (Q at 2GHz, 0.5µm CMOS)†:
Cmax Cmin Qmax Qmin
4.5 38
VG = 2.1V RX 36 VG = 2.1V
RX
4 Meter Meter
VG VD,S 34 VG VD,S
3.5
CGate (pF)
32
VG = 1.8V
QGate
3 30
VG = 1.8V
28
2.5 VG = 1.5V
VG = 1.5V 26
2
24
1.5 22
0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5
Drain/Source Voltage (V) Drain/Source Voltage (V) 070617-06
VG =1.8V: Cmax/Cmin ratio = 2.15 (1.91), Qmax = 34.3 (5.4), and Qmin = 25.8(4.9)
†E. Pedersen, “RF CMOS Varactors for 2GHz Applications,” Analog Integrated Circuits and Signal Processing, vol. 26, pp. 27-36, Jan. 2001.
Accumulation Mode NMOS Gate Capacitor

G B Capacitance
Cox Cox
n+ Depletion
n+
Inversion Accumulation
VG-VD,S,B
060207-05
Conditions:
• Build the NMOS in a n-well or the PMOS in a p-well – channel is present with no bias
• Implements a variable capacitor with a larger transition region between the maximum
and minimum values.
• Reasonably linear capacitor for values of VG-VD,S,B > 0

Accumulation Mode Capacitor – Continued

Best results are Shown in depletion mode. G D,S
obtained when the D,S
drain-source are on Cov Cox Cov
Bulk Cw B
ac ground. p+ + n n+
Rs Rw Rd Rd G
Cd Cd
n- well
n- LDD
p- substrate/bulk Fig. 2.5-5
Experimental Results (Q at 2GHz, 0.5µm CMOS)†:

Cmax Cmin Qmax Qmin
4 45
RX
RX VG = 0.3V Meter
Meter VG
3.6 VD,S
VG = 0.9V VG VD,S 40
VG = 0.6V
CGate (pF)
3.2
QGate
VG = 0.6V
35
VG = 0.9V
2.8
2.4 VG = 0.3V 30
2 25
0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5
Drain/Source Voltage (V) Drain/Source Voltage (V) 070617-07
VG = 0.6V: Cmax/Cmin ratio = 1.69 (1.61), Qmax = 38.3 (15.0), and Qmin = 33.2(13.6)
†
E. Pedersen, “RF CMOS Varactors for 2GHz Applications,” Analog Integrated Circuits and Signal Processing, vol. 26, pp. 27-36, Jan. 2001.
CONDUCTOR-INSULATOR-CONDUCTOR CAPACITORS
Polysilicon-Oxide-Polysilicon (Poly-Poly) Capacitors
LOCOS Technology:
A very linear capacitor
with minimum bottom
plate parasitic.
DSM Technology:
A very linear capacitor with
small bottom plate parasitic.

Metal-Insulator-Metal (MiM) Capacitors

In some processes, there is a thin dielectric between a metal layer and a special metal
layer called “capacitor top metal”. Typically the capacitance is around 1fF/µm2 and is at
the level below top metal.
Protective Insulator Layer
Metal Via
Top
Vias connecting top Metal
Capacitor plate to top metal
dielectric Capacitor Top Metal Second level
Inter-
Vias connecting bottom from top metal
mediate
Capacitor bottom plate plate to lower metal Third level
Oxide
Layers Vias connecting bottom from top metal
plate to lower metal Fourth level
from top metal
060530-01
Good matching is possible with low parasitics.

Metal-Insulator-Metal Capacitors – Lateral and Vertical Flux

Capacitance between conductors on the same level and use lateral flux.
Fringing field
Top view:
Metal Metal
Metal 3 + - + - Side view:
Metal 2 - + - +
Metal 1 + - + - Fig2.5-9
These capacitors are sometimes called fractal capacitors because the fractal patterns are
structures that enclose a finite area with a near-infinite perimeter.
The capacitor/area can be increased by a factor of 10 over vertical flux capacitors.
More Detail on Horizontal Metal Capacitors†

Some of the possible metal capacitor structures include:
1.) Horizontal parallel plate (HPP).
030909-01
2.) Parallel wires (PW):
Lateral View 030909-02

Top View
†R. Aparicio and A. Hajimiri, “Capacity Limits and Matching Properties of Integrated Capacitors, IEEE J. of Solid-State Circuits, vol. 37, no. 3,
March 2002, pp. 384-393.
Horizontal Metal Capacitors - Continued

3.) Vertical parallel plates (VPP):
Vias
030909-03
4.) Vertical bars (VB):
Vias
030909-04
Lateral View Top View

Horizontal Metal Capacitors - Continued

Experimental results for a digital CMOS process with 7 layers of metal, Lmin =0.24µm,
tox = 0.7µm and tmetal = 0.53µm for the bottom 5 layers of metal. All capacitors = 1pF.
Structure Cap. Caver. Area Cap. Std.  fres. Q @ Break-
Density 2
(1 pF) (pF) (µm ) Enhanc Dev. Caver. (GHz) 1 GHz down
(aF/µm2) ement (fF) (V)
VPP 1512.2 1.01 670 7.4 5.06 0.0050 > 40 83.2 128
VB 1281.3 1.07 839.7 6.3 14.19 0.0132 37.1 48.7 124
HPP 203.6 1.09 5378 1.0 26.11 0.0239 21 63.8 500
MIM 1100 1.05 960.9 5.4 - - 11 95 -
Histogram of the capacitance distribution:
Result: The horizontal metal capacitors

have a matching accuracy that is
equivalent of the better capacitors – poly-
poly and MIM.

DEVIATION FROM IDEAL BEHAVIOR IN CAPACITORS

Capacitor Errors
1.) Dielectric gradients
2.) Edge effects
3.) Process biases
4.) Parasitics
5.) Voltage dependence
6.) Temperature dependence

Capacitor Errors - Oxide Gradients

Error due to a variation in dielectric thickness across the wafer.
Common centroid layout - only good for one-dimensional errors:
No common centroid layout Common centroid layout
2C C 2C C
060207-07
An alternate approach is to layout numerous repetitions and connect them randomly to

achieve a statistical error balanced over the entire area of interest.
Improved matching of three components, A, B, and C:

Capacitor Errors - Edge Effects

There will always be a randomness on the definition of the edge.
However, etching can be influenced by the presence of adjacent structures.
For example,
Matching of A and B are disturbed by the presence of C.
C
A B
Improved matching achieve by matching the surroundings of A and B.
C
A B

Process Bias on Capacitors

Consider the following two capacitors:
If L1 = L2 = 2µm, W2 = 2W1 = 4µm and

x = 0.1µm, the ratio of C2 to C1 can
be written as,
C2 (2-.2)(4-.2) 3.8
C1 = (2-.2)(2-.2) = 1.8 = 2.11 → 5.6% error in matching
How can this matching error be reduced?
The capacitor ratios in general can be expressed as,
1 - 2x
C2 (L2-2x)(W2-2x) W2 W2  W2 2x 2x W2 2x 2x
C1 = (L1-2x)(W1-2x) = W1 2x  W11 - W2 1 + W1   W11 - W2 + W1 
1 - W 
 1
Therefore, if W2 = W1, the matching error should be minimized. The best matching
results between two components are achieved when their geometries are identical.
Replication Principle
Based on the previous result, a way to minimize the matching error between two or more
geometries is to insure that the matched components have the same area to periphery
ratio. Therefore, the replication principle requires that all geometries have the same
area-periphery ratio.
Correct way to match
the previous capacitors
(the two C2 capacitors
are connected
together):
If L1 = L2 = 2µm, W2 = 2W1 = 2µm and x = 0.1µm, the ratio of C2 to C1 can be written

as,
C2 2(2-.2)(2-.2) 2·1.8
= = = 2 → 0% error in matching
C1 (2-.2)(2-.2) 1.8
The replication principle works for any geometry and includes transistors, resistors as
well as capacitors.

Capacitor Errors - Relative Accuracy

Capacitor relative accuracy is proportional to the area of the capacitors and inversely
proportional to the difference in values between the two capacitors.
For example,
0.04
Unit Capacitance = 0.5pF

0.03
Relative Accuracy
Unit Capacitance = 1pF
0.02
0.01
Unit Capacitance = 4pF
0.00
1 2 4 8 16 32 64
Ratio of Capacitors

How to Keep the Relative Accuracy Constant as Ratio Increases

The following scheme will tend to keep the relative accuracy constant as a function of
the ratio of capacitors. Of course the tradeoff for this accuracy is area.
1:2 2 2 1 1 2 2
4 4 4 4 1 1 4 4 4 4
1:4
4 4 4 4 1 1 4 4 4 4
4 4 4 4 4 4 4 4 1 1 4 4 4 4 4 4 4 4
4 4 4 4 4 4 4 4 1 1 4 4 4 4 4 4 4 4
1:8
4 4 4 4 4 4 4 4 1 1 4 4 4 4 4 4 4 4
4 4 4 4 4 4 4 4 1 1 4 4 4 4 4 4 4 4
120625-01

Capacitor Errors - Parasitics

Parasitics are normally from the top and bottom plate to ac ground which is typically the
substrate.
Top Plate
Top
plate Desired
parasitic Capacitor
Bottom
Bottom Plate plate
060702-08
parasitic
Top plate parasitic is 0.01 to 0.001 of Cdesired

Bottom plate parasitic is 0.05 to 0.2 Cdesired

Layout Considerations on Capacitor Accuracy

Decreasing Sensitivity to Edge Variation:
Fringing Fringing
Field Field
? ?
Sensitive to alignment errors in the Insensitive to alignment errors and the
upper and lower plates and loss of flux reaching the bottom plate is lar ger
capacitance flux (smaller capacitance). resulting in large capacitance. 060207-09
A structure that minimizes the ratio of perimeter to area (circle is best).

Bottom Plate
Top
Plate
060207-10 Reduced bottom plate parasitic.

Accurate Matching of Capacitors†

Accurate matching of capacitors depends on the following influence:
1.) Mismatched perimeter ratios
2.) Proximity effects in unit capacitor photolithography
3.) Mismatched long-range fringe capacitance
4.) Mismatched interconnect capacitance
5.) Parasitic interconnect capacitance
Long-range fringe capacitance:
Obviously there will be a tradeoff between matching and speed.
†M.J. McNutt, S. LeMarquis and J.L.Dunkley, “Systematic Capacitance Matching Errors and Corrective Layout Procedures,” IEEE J. of Solid-State
Circuit, vo. 29, No. 5, May 1994, pp. 611-616.
Shielding
The key to shielding is to determine and control the electric fields.
Consider the following noisy conductor and its influence on the substrate:
Increased Parasitic Capacitance
Noisy Conductor Noisy Conductor Separate
Ground
Shield
Substrate Substrate
060118-10
Use of bootstrapping to reduce capacitor bottom plate parasitic:

Top Plate
2Cpar +1
Bottom Plate
Cpar
2Cpar Shield
Substrate Substrate
060316-02

Definition of Temperature and Voltage Coefficients

In general a variable y which is a function of x, y = f(x), can be expressed as a Taylor
series,
y(x)  y(x0) + a1(x- x0) + a2(x- x0)2+ a3(x- x0)3 + ···
where the coefficients, ai, are defined as,
df(x) | 1 d2f(x) |
a1 = dx x=x , a2 = 2 , ….
0 dx2 x=x0
The coefficients, ai, are called the first-order, second-order, …. temperature or voltage
coefficients depending on whether x is temperature or voltage.
Generally, only the first-order coefficients are of interest.
In the characterization of temperature dependence, it is common practice to use a term
called fractional temperature coefficient, TCF, which is defined as,
1 df(T) |
TCF(T=T0) = f(T=T ) dT T=T parts per million/°C (ppm/°C)
0 0
or more simply,
1 df(T)
TCF = f(T) dT parts per million/°C (ppm/°C)
A similar definition holds for fractional voltage coefficient.
Capacitor Errors - Temperature and Voltage Dependence

MOSFET Gate Capacitors:
Absolute accuracy  ±10%
Relative accuracy  ±0.2%
Temperature coefficient  +25 ppm/C°
Voltage coefficient  -50ppm/V
Polysilicon-Oxide-Polysilicon Capacitors:
B Silicide A
Temperature coefficient  +25 ppm/C° Silicide
Thin depletion regions
Effective dielectric
Voltage coefficient  -20ppm/V thickness
Metal-Dielectric-Metal Capacitors: Shallow Trench Isolation

140310-03

Temperature coefficient  +40 ppm/C°
Voltage coefficient  -20ppm/V, 5ppm/V2
Accuracies depend upon the size of the capacitors.
SUMMARY
• Capacitors are made from:
- pn junctions (depletion capacitors)
- MOSFET gate capacitors
- Conductor-insulator-conductor capacitors
• Capacitors are characterized by:
- Q, a measure of the loss
- Density
- Parasitics
- Absolute and relative accuracies
• Deviations from ideal capacitor behavior include;
- Dielectric gradients
- Edge effects (etching)
- Process biases
- Parasitics
- Voltage and temperature dependence

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Lecture 06 – Capacitors (8/18/14) Page 06-1

CMOS Analog Circuit Design © P.E. Allen - 2016

2.) MOSFET gate capacitors Cox

3.) Conductor-insulator-conductor Top Conductor

CMOS Analog Circuit Design © P.E. Allen - 2016

CMOS Analog Circuit Design © P.E. Allen - 2016

Two different versions have been tested. p+ dif-

PN-Junction Capacitors – Continued

MOSFET GATE CAPACITORS

Cjunction p-well Cjunction

CMOS Analog Circuit Design © P.E. Allen - 2016

MOSFET Gate Capacitor as a function of VGS with D=S=B

Cox Cox Cox

Depletion Moderate VG-VD,S,B

CMOS Analog Circuit Design © P.E. Allen - 2016

Use of a 3 Segment Model to Explain the Gate Capacitor Variation

Accumulation Large In series and Cgate ≈ Cox

Depletion In series and Cgate ≈ 0.5Cox

Weak Large In series and Cgate ≈ Cj

Moderate Moderate In series and Cj < Cgate <

Strong Small In parallel and Cgate ≈ Cox

CMOS Analog Circuit Design © P.E. Allen - 2016

Cox Cox B=D= S Cox

CMOS Analog Circuit Design © P.E. Allen - 2016

Inversion Mode NMOS Capacitor

Accumulation Mode NMOS Gate Capacitor

CMOS Analog Circuit Design © P.E. Allen - 2016

Accumulation Mode Capacitor – Continued

Experimental Results (Q at 2GHz, 0.5µm CMOS)†:

CMOS Analog Circuit Design © P.E. Allen - 2016

Metal-Insulator-Metal (MiM) Capacitors

Protective Insulator Layer

Good matching is possible with low parasitics.

CMOS Analog Circuit Design © P.E. Allen - 2016

Metal-Insulator-Metal Capacitors – Lateral and Vertical Flux

Metal 3 + - + - Side view:

More Detail on Horizontal Metal Capacitors†

2.) Parallel wires (PW):

Lateral View 030909-02

Horizontal Metal Capacitors - Continued

4.) Vertical bars (VB):

Lateral View Top View

CMOS Analog Circuit Design © P.E. Allen - 2016

Horizontal Metal Capacitors - Continued

Result: The horizontal metal capacitors

CMOS Analog Circuit Design © P.E. Allen - 2016

DEVIATION FROM IDEAL BEHAVIOR IN CAPACITORS

CMOS Analog Circuit Design © P.E. Allen - 2016

Capacitor Errors - Oxide Gradients

An alternate approach is to layout numerous repetitions and connect them randomly to

CMOS Analog Circuit Design © P.E. Allen - 2016

Capacitor Errors - Edge Effects

Improved matching achieve by matching the surroundings of A and B.

CMOS Analog Circuit Design © P.E. Allen - 2016

Process Bias on Capacitors

If L1 = L2 = 2µm, W2 = 2W1 = 4µm and

If L1 = L2 = 2µm, W2 = 2W1 = 2µm and x = 0.1µm, the ratio of C2 to C1 can be written

CMOS Analog Circuit Design © P.E. Allen - 2016

Capacitor Errors - Relative Accuracy

Unit Capacitance = 0.5pF

Unit Capacitance = 1pF

CMOS Analog Circuit Design © P.E. Allen - 2016

How to Keep the Relative Accuracy Constant as Ratio Increases