ICSETS 2019 063

Review of Three Phase Transformer-less

PV Converters
Ibhan Chand Rath Anshuman Shukla
Electrical Engineering Electrical Engineering
Indian Institute of Technology Bombay Indian Institute of Technology Bombay
Mumbai, India Mumbai, India
ibhanchandrath@gmail.com ashukla@ee.iitb.ac.in

Abstract—Research in solar photovoltaics over the past Hence the common mode voltage keeps varying, which
decade has resulted in significant improvement of the PV array produces common mode current [2]. Either only the even
efficiency. To further improve efficiency, transformerless PV vectors or only the odd vectors could be used to operate the
inverter topologies are developed and are successfully inverter to make a constant common mode voltage
employed in single phase PV systems. However, as the output (RSPWM-Remote State PWM technique) [2] but the length
power of solar PV becomes more than 15 kW it is
recommended to use three phase converters instead of single
of the maximum reference voltage vector which could have
phase owing to the size of the DC link capacitor and its been used with all the vectors gets reduced. As stated in [1]
lifetime. Due to the lack of galvanic isolation in case of if the grid neutral point is directly clamped to the mid-point
transformerless inverter, the parasitic capacitance between the of input split dc link capacitor 3-FB-SC (Full Bridge with
PV surface and grid ground faces varying common mode input Split Capacitors) then the common mode voltage
voltage across it. This results in the flow of common mode remains constant, provided the connecting wire has zero
leakage current and compromises overall safety of the inverter. inductance which is practically not possible. So using the
This paper discusses some of the prominent three phase grid three phase FB (Full Bridge) topology as shown in Fig. 1(a)
connected transformer-less Voltage source inverters (VSI) for it is not possible to eliminate the common mode current
solar photovoltaic (PV) application. Various topological without having additional switches. So the control of the
modifications and control strategies proposed in literature to
inverter is modified to keep common mode voltage constant
minimize the ground current or the common mode current are
presented. using techniques such as RSPWM, and AZSPWM as stated
in [2]. RSPWM technique uses only either active even
Keywords—Common mode, grid connected converters, vectors (V2,V4,V6) or active odd vectors (V1,V3,V5) to keep
multilevel converter, solar PV, three-phase VSI. common mode voltage constant (referring Table-1 and Fig.
1(f)). But the disadvantage is that the length of the
I. INTRODUCTION maximum reference voltage vector that can be achieved
decreases by 42.263% compared to maximum reference that
Due to the pollution emerging from the conventional could be produced by using all the vectors and the THD
power plants, it is advisable to use renewable sources such (Total Harmonic Distortion) in the output voltage and
as solar PV. Many single phase VSI that uses solar PV at its current increases and the switching frequency also increases
input have been discussed in the literature. When the power thereby increasing switching losses.
of the solar panel increases above 15kW, then use of single VAN + VBN + VCN
phase VSI may create unbalance in the grid [1]. A three VCM = (1)
3
phase VSI is a good alternative in such cases. The body of VAN + VBN + VCN + VDN
the solar panel forms a parasitic capacitance with the earth VCM = (2)
4
as shown in Fig. 1(a). When the voltage across this TABLE-I
capacitor (common mode voltage) varies (due to the PWM- CONVENTIONAL SPACE VECTOR POSSIBLE COMBINATIONS
Pulse Width Modulation operation of the inverter) then a Sa Sa Sa Vector VCM
common mode current flows through it. A few three phase 0 0 0 V0 0
VSI are proposed in literature [1-12] which discusses about 1 0 0 V1 VPN/3
minimizing the leakage current. This paper reviews such 1 1 0 V2 2VPN/3
three phase converters and highlights their key-points. The 0 1 0 V3 VPN/3
0 1 1 V4 2VPN/3
detailed working, pros and cons are depicted.
0 0 1 V5 VPN/3
1 0 1 V6 2VPN/3
II. THREE PHASE TRANSFORMER-LESS VSI CONVERTERS
1 1 1 V7 VPN

A. Conventional three phase VSI

Fig. 1(a) shows a three phase conventional VSI, its common
mode model is shown in Fig. 1(b) [1]. The common mode
voltage across the parasitic capacitance is given by (1) [1].
When the inverter is operated with SVPWM (Space Vector
PWM) technology as shown in Fig. 1(f) then the odd vectors
produce common mode voltage equal to one-third of the
input and the even vectors produce common mode voltage
equal to two-third of input voltage as shown in Table-I.
B. DCM-232 (DC Time Multiplexed Power Processor)
This topology belongs to family of DCM-xyz as shown in
Fig. 1(g). DCM-232 [3] uses SVM control technique and
two PV panels to keep the common mode voltage constant
across each panel. It uses two PV panels, [3] panel PVA
supplies all the odd vectors (V1, V3, V5) (referring to Table-1
and Fig. 1(f)) (S7a and S8a are ON) and panel PVB supplies
all the even vectors (V2, V4, V6) (S7b and S8b are ON) hence
the common mode voltage of panel A remains at VdcA/3 and

978-1-5386-6971-6/19/$31.00 ©2019 IEEE

 ICSETS 2019 064

that of panel B remains at 2VdcB/3. The zero vectors are active vector state, still the zero voltage is applied to the
provided by making the switches S7a, S8a, S7b, S8b OFF, (V0 load since the source is cut out. Also during the zero vectors
and V7 vectors need not be applied). So we can basically the load current freewheels in the all the six switches (S1-S6)
apply all the active vectors and zero voltage and still (unlike vector state of V0 and V7) thereby reducing the
maintain constant voltage across the parasitic capacitance of conduction losses. As the change of switching states takes
the respective panels. In between two active vectors a zero place in zero voltage intervals so a ZVS switching is
voltage is applied and during this zero voltage interval the obtained reducing the switching losses. The disadvantage of
switches of FB (S1-S6) changes state to the next upcoming this topology is that between the two active vectors a zero
P Sa Sb Sc UAN L UD N L
X S1
P S S3 S5 S ma
L UBN L 1 7 UCN L Y
mb S2
PV A L n
B n N UCN L L UBN L Z S3
C A mc
L P B UAN L S4
CPV V V S2 S4 S6C S8
CM C CC L CC ST 1 S5
C C CPV C CC C 1 ST 2 S6
Sa Sb Sc ICM G C4 UPV S7
N 0 T 2T 3T ST 3
(b) S8
CPV Lg N ICM (d)
(a) (c)
CPV ª S1 = ( X Y + X Z + Y Z ) ST 1 + X ST 1 S 2 = S1 º
« »
S7a S7 S « S 3 = ( XY + Y Z + X Z ) ST 2 + Y ST 2 S 4 = S3 »
V2110 X S2 S1 « »
ma « S 5 = ( X Z + YZ + X Y ) ST 3 + Z ST 3 S6 = S5 »
010 VdcA S1 S3 S5 P Y Eq S4 3
PVA S3 S5 «S = (S ⊕ S ⊕ S ) »
V3 IX II q mb . S6 S5 ¬ 7 1 3 5 ¼
III S8a Load S1 Z S
I L mc S8 7 (e)
VX V0 100 A L
V4 V7 V1 d S7b S2 S4 S6 B n
PV C
011 IV V1
L
VdcB ª S1 = X + Y Z S 2 = X + YZ º
PVB « »
V S8 S2 S4 S6
C « S3 = Y + X Z S 4 = Y + XZ »
S8b « » V14
001 101 N « S5 = Z + X Y S 6 = Z + XY » V12
V5 V6 « »
(g) Lg ¬ S7 = S8 = X Z + X Y + Y Z ¼ V6
(f) CPV
(i) V4
(h) -+- 0+- V10
++-
P S1a S1b S1c
P S1a S1b 0+0 00- V2 V8
S2a S2c La X S1a S1c -+0 +0-
S2b S2a -0- ++0
Cdc ma E Cdc S2a S2b La V0 V15
Lb Y S1b S2c 000
Cb Cc S2b 0++ +00 +--
Ca Lc mb
Z q. S1c P A B
Lb --- +++ 0-- V7 V13
mc S2c V 0 C Lc -++ -00
S2a S2b S2c
S1a S1b S1c 00+ 0-0 V11
S1a Cdc -0+ --0 +0+ +-0 V5 V9
N S1b S1c S2a S2b
ª S = X ( X ⊕ Y ) + XYZ S2 a = Y ( X ⊕ Y ) + XYZ º N S2c
« 1a » V3
« S1b = Y (Y ⊕ Z ) + XYZ S2 b = Z (Y ⊕ Z ) + XYZ » --+ 0-+ +-+
« » V1
CPV «¬ S1c = Z (Z ⊕ X ) + XYZ S2 c = X ( Z ⊕ X ) + XYZ »¼
(j) CPV
(k) (l) (m) (n)

Fig.1 (a) Three-phase conventional VSI.(3-FB) (b) Three phase common mode model for (a). (c) Three phase VSI with 4-legs. (d) Common mode model for
the 4 leg topology in (c). (e) Boolean logic for the 4 leg topology in (c). (f) 2-level space vectors. (g) DCM-232. (h) H8 topology. (i) Boolean logic for H8
topology. (j) Three-phase flying capacitor solar inverter. (k) Boolean logic for the flying capacitor in (j). (l) Three-phase NPC solar inverter. (m) 3 level
space vector diagram. (n) 3-D space vector.

vector has to be applied, this increases the THD of the TABLE-II

SWITCHING STATES FOR 4-LEG 3 PHASE CONVERTER
output and so no other switching pattern can be applied.
ST1-ST3 XYZ S1 S3 S5 S7 UCM
100 000 1 0 0 1 Vdc/2
C. Four leg three phase VSI 010 000 0 1 0 1 Vdc/2
Leakage current reduction of a three phase 4–leg PV 001 000 0 0 1 1 Vdc/2
inverter is proposed in [4]. A new modulation strategy using 001 0 0 1 1 Vdc/2
Boolean logic is proposed to achieve constant common 010 0 1 0 1 Vdc/2
mode voltage. The common mode current depends on 011 0 1 1 0 Vdc/2
100 1 0 0 1 Vdc/2
common mode voltage given by (2), and on the voltage 101 1 0 1 0 Vdc/2
across the capacitor C4 [4]. It is possible to apply all the 110 1 1 0 0 Vdc/2
even, odd and zero vectors (referring Fig. 1(f)) and still 100 111 0 1 1 0 Vdc/2
maintain constant common mode voltage. The switching of 010 111 1 0 1 0 Vdc/2
the fourth leg is done in such a manner that the total 001 111 1 1 0 0 Vdc/2
common mode voltage becomes constant. Fig. 1(c) shows
three phase 4-leg topology and Fig. 1(d) shows its common Now these variables logically combine with a set of high
mode equivalent circuit. (2) is derived from this equivalent frequency rotating parameter (ST1-ST2-ST3) to form firing
common mode model. Fig. 1(e) shows the modulation pulses to the inverter. Table II shows the various switching
strategy used to keep the common mode voltage constant. states of the switches for different values of X, Y, Z and ST1,
ma, mb, mc are the modulating signals, the signals X, Y, Z are ST2, ST3 (enable signals). The enable signals rotate at high
formed after the modulating signals are compared with high frequency with values 100,010,001. It can be found that the
frequency triangular carrier waves. fourth leg gets switched in a manner such that the common
ª S1 = ( X Y + X Z + Y Z ) ST 1 + X ST 1 S2 = S1 º
mode voltage given by (2) always stays at half of the input
« » dc link voltage. The firing pulses can be produced just by
« S3 = ( XY + Y Z + X Z ) ST 2 + Y ST 2 S4 = S3 »
the set of equations given by (3). The disadvantage is that
« » (3)
« S5 = ( X Z + Y Z + X Y ) ST 3 + Z ST 3 S6 = S5 » when the zero vector is applied to inverter then the zero
«S = (S ⊕ S ⊕ S ) » vector duration should be minimum of 3T to ensure that
¬ 7 1 3 5 ¼
either the first three rows or last three rows of Table II gets
 ICSETS 2019 065

applied within the duration. Moreover the zero vector is not increases. Those 6 vectors are as shown in group-3 of
the conventional zero vector, it is formed by set of three Table-III.
active vectors displaced by 120 degrees that are applied for E. H8-Converter
equal durations to produce a zero vector. The H8 converter topology [11-12] is shown in Fig. 1(h)
which uses all the active vectors of Fig. 1(f). Only during
D. Four leg VSI with 3D-SVPWM the zero vector time the switches S7 and S8 are made off. So
Reduction of common mode current with 3 phase 4–legs is during the zero vector interval the path for the common
presented in [5]. A 3-D (three dimensional) SVM technique mode current is cut which reduces the common mode
is proposed to keep the common mode voltage constant. 3- current. The same is applicable for the H7 topology [12] as
phase 4-Leg topology as shown in Fig. 1(c) has 16 possible shown in fig. 2(i). The Boolean logic used is given in (4).
switching combinations i.e., there are 16 possible switching ª S1 = X + Y Z S2 = X + YZ º
vectors which is represented in 3-D --0 space as shown in « »
« S3 = Y + X Z S4 = Y + XZ »
Fig. 1(n). When this topology is used with PV as a source « » (4)
then out of the 16 switching states only six switching states « S5 = Z + X Y S6 = Z + XY »
« »
that produce constant common mode voltage equal to half ¬ S 7 = S8 = X Z + X Y + Y Z ¼
of the dc link voltage (group-3) as shown in Table-III are F. Neutral point clamped transformer-less inverter
used to synthesize the reference voltage vector [5]. The Three level inverters are featured by low levels of THD in
common mode voltage is given by (2). As a result the the output voltage and the reduced rating of switching
maximum reference voltage vector length decreases then devices compared to two level inverters. In [6] two PWM
that could be generated by using all the 16 possible methods are proposed to reduce the common mode current
switching vectors. Also the THD content in the output in a three level VSI. The common mode
Icmc_P S5a La1
PV1 a1
Cpva 2Cpva
S3a S1a La1 vsa 0.5Udm a S6
a1 A P
VPV Na
a2 Ucm a La2 S1 S3 S5
La2 PVA
Cpva S4a a2 L
PV2 S2a -0.5Udm a
Icm a A
Icmc_N Na 0.5Udm b Lb1 B
C
(a) Icmc_P S5b L
L1 iL 1 D1 Icmb b1 O C
iPV S2 S4 S6
Cpvb N
S2R S1R S1T S3b S1b Lb1 vs b O Nb B Lg
O
C1 vS1 S1 Vdc1 S4R R
L f iR Grid side
vT R b1 2Cpvb Ucmb b2 CPV
CdC 1 VPV
n R vLg Lg
b2
Lb2 N Lb2 N
VPV RS
-0.5Udm b (i)
S Cpvb S4b S2b
vS2 S2 T Lg vST Icmc
C2 CdC 2 Vdc2 S4T S2T Lf iT T Icmc_N
Nb 0.5Udm c Lc1
S3R S3T c1 X
Icmc_P S5c ma S1X(X=a ,b,c)
L2 iL2 D2 Eq S2X (X=a ,b,c)
(b) C Y S3X (X=a ,b,c)
2CpvcNc U mb .
Cpvc cm c c2 S4X (X=a ,b,c)
L1 v1n vRn Lf S3c S1c Lc1 vs c mc Z S5X (X=a ,b,c)
v1n L1
1 R VPV c1 Lc2
S1 C1 c2 -0.5Udmc
C1 L1 n Lc2
1 ª S1a = X + Y º
v1n vg v2n L2 Cp + C2 L2 v2n vT n Lf Cpvc S4c S2c «
S 2 a = XY S3 a = X + Y
S 4a = X Y »
2 C1+C2 « S1b = Y + Z S 2 b = YZ S 3b = Y + Z »
S2 Cp V 2 i T Nc « S 4b = Y Z »
C2 - P.pro p p
Icmc_N « S1c = X + Z S 2c = X Z S 3c = X + Z »
S 4c = X Z »
«
¬ S5 a = XY + X Y S 5b = YZ + Y Z S5 c = X Z + X Z ¼
N (g)
(d) (e) (f)
(c) (h)

Fig. 2 (a) 3L-SNPC. (b) T-type solar inverter. (c) Single phase half bridge inverter. (d) High frequency equivalent for T-type in (b). (e) High frequency
model for T-type in (b). (f) Three phase cascaded H bridge solar inverter. (g) Common mode model for cascaded H-bridge in (f). (h) Boolean logic for
cascaded H-bridge in (f). (i) H7 topology.

TABLE-III switching vectors as shown in the --0 plane in Fig. 1(m).

SWITCHING STATES FOR 3-D SVPWM Out of the 27 vector combinations only 7 switching vectors
Group Vector Status VAN VBN VCN VDN VCM have common mode voltage equal to half of the input DC
1 V0 nnnn 0 0 0 0 0 link voltage as shown in Table-IV. So in the paper [6] it is
V1 nnnp 0 0 0 VDC recommended to use only these 7 switching vectors (6
V2 nnpn 0 0 VDC 0
2 V4 npnn 0 VDC 0 0
VDC/4 medium vectors and one zero vector, group -1) to produce
V8 pnnn VDC 0 0 0 the reference voltage. The maximum reference voltage
V3 nnpp 0 0 VDC VDC decreases than that could be produced by using all the 27
V5 npnp 0 VDC 0 VDC vectors. Also because of using only 7 vectors the THD
V6 nppn 0 VDC VDC 0 content in the output voltage increases. In the Fig. 1(m) the
VDC/2
V9 pnnp VDC 0 0 VDC
3
V10 pnpn VDC 0 VDC 0
symbol + represents switches S1a, S2a (considering phase ‘a’
V12 ppnn VDC VDC 0 0 of Fig. 1(l)) are ON and - represents switches S1a and S2a are
V7 nppp 0 VDC VDC VDC OFF and 0 represents S1a is OFF and S2a is ON.
V11 pnpp VDC 0 VDC VDC
3VDC/4
Another modulation technique using SPWM is also
4 V13 ppnp VDC VDC 0 VDC proposed in [6] that maintains constant common mode
V14 pppn VDC VDC VDC 0 voltage. 3 modulating signals are used in conventional
5 V15 pppp VDC VDC VDC VDC VDC
SPWM control to generate the switching signals for the
inverter, but the switching states thus produced do not
voltage is given by (1). The NPC topology is shown in Fig. guarantee to fall in group -1 of Table-IV hence the common
1(l). Using SVPWM current control there are 27 possible mode voltage is not constant. So a new scheme of SPWM
 ICSETS 2019 066

(Sine triangle PWM) is proposed which uses only one DC link voltage. To tally the status of Table-V with that of
carrier wave and 3 modulating signals ma, mb, mc. These group-1 of Table-IV take 2  +, 1  0, and 0  .
modulating signals are compared with the high frequency So using this sort of modulation, constant common mode
carrier wave individually to produce an inter-mediate PWM voltage can be achieved. The maximum reference voltage
signal which are represented by V1, V2, V3 respectively (not that can be obtained decreases when compared to the vector
to be confused with the voltage vectors of Table-IV). Now that can be produced using all the possible switching states.
the actual PWM signal for phase a, Va is (V1-V2)/2, for phase ª S = X ( X ⊕ Y ) + XYZ S2 a = Y ( X ⊕ Y ) + XYZ º
b, Vb is (V2-V3)/2, and for phase c, Vc is (V3-V1)/2 are used « 1a »
« S1b = Y (Y ⊕ Z ) + XYZ S2b = Z (Y ⊕ Z ) + XYZ » (5)
to switch the inverter and the common mode voltage is « S = Z ( Z ⊕ X ) + XYZ »
«¬ 1c S2 c = X ( Z ⊕ X ) + XYZ »¼
given by (1) as Vcomm=(Va+Vb+Vc)/3 which is equal to ((V1-
V2)+(V2-V3)+(V3-V1))/3=0. TABLE-V
TABLE-IV SWITCHING TABLE FOR FLYING CAPACITOR
SWITCHING STATES FOR NEUTRAL POINT CLAMPED INVERTER XYZ S1a S2a S1b S2b S1c S2c status
Group Vectors Status VAN VBN VCN VCM 111 1 0 1 0 1 0
111
V1 + 0 - VDC VDC/2 0 000 0 1 0 1 0 1
V2 0 + - VDC/2 VDC 0 011 0 0 0 1 1 1 012
V3 - + 0 0 VDC VDC/2 010 0 0 1 1 0 1 021
1 V4 - 0 + 0 VDC/2 VDC VDC/2 001 0 1 0 0 1 1 102
V5 0 - + VDC/2 0 VDC 101 1 1 0 0 0 1 201
V6 + - 0 VDC 0 VDC/2 110 0 1 1 1 0 0 120
V0(0) 0 0 0 VDC/2 VDC/2 VDC/2 100 1 1 0 1 0 0 210
V7 + - - VDC 0 0
V8 - + - 0 VDC 0 H. Transformer-less Cascaded H-bridge
V9 - - + 0 0 VDC The use of cascade H5-bridge using solar panel as a source
2 VDC/3
V10 0 - 0 VDC/2 0 VDC/2
V11 0 0 - VDC/2 VDC/2 0
to reduce the common mode current is proposed in [7]. In
V12 - 0 0 0 VDC/2 VDC/2 [7] the common mode model of the 3 phase cascade H-
V13 + + - VDC VDC 0 bridge is analyzed with an additional switch S5 and an
V14 - + + 0 VDC VDC equation for the common mode current of each phase is
V15 + - + VDC 0 VDC derived as shown in (6).
3 2VDC/3
V16 0 0 + VDC/2 VDC/2 VDC
The relationship of the common-mode current with the total
V17 + 0 0 VDC VDC/2 VDC/2
V18 0 + 0 VDC/2 VDC VDC/2 common mode voltage, the total differential mode voltage,
4 V0(+) + + + VDC VDC VDC VDC individual common mode voltage and individual differential
5 V0(-) - - - 0 0 0 0 mode voltage is presented in the equation (6). After this a
V19 + + 0 VDC VDC VDC/2 Boolean logic is presented to generate the switching pulses
6 V20 0 + + VDC/2 VDC VDC 5VDC/6 that keeps the common mode (individual and total) and
V21 + 0 + VDC VDC/2 VDC
V22 - 0 - 0 VDC/2 0
differential mode voltages (only total) constant so that the
7 V23 - - 0 0 0 VDC/2 VDC/6 common mode current can be suppressed. Fig. 2(f) shows a
V24 0 - - VDC/2 0 0 3 phase cascade H-bridge and Fig. 2(g) shows its common
mode model.
G. Flying Capacitor transformer-less inverter
I cmi =
( 0.25Z L + Z PV )U DM − 0.5Z LU CM + ( 3Z L + 6Z PV )U cmi (6)
A 3-level flying capacitor topology with solar PV as its ( 0.5Z L + 2 Z PV )(1.5Z L + 3Z PV )
source is presented in Fig. 1(j). A Boolean logic is presented Where, Icmi (i=a,b,c) is the common mode current of a single
in [8] to generate firing pulses of the switches such that the phase Ucmi is the common mode voltage of a phase and
common mode voltage remains constant at half of the input Ucm=(Ucma+Ucmb+Ucmc) is the total common mode voltage.
dc link voltage. When S1a, S2a are ON, VAN is Vdc (the Udmi is the differential mode voltage of each phase and
voltage of the input dc link capacitor Cdc), when S1a, S2a are UDM=(Udma+Udmb+Udmc) is defined as the total differential
OFF then VAN is 0, when S1a is 0 and S2a is 1 then VAN is mode voltage and ZPV is 1/(2sCPV) and ZL is (sL)/2 where
Vdc/2 (the voltage of the capacitor Ca, gets discharged in La1=Lb1=Lc1=La2=Lb2=Lc2=(L/2). Ud is the voltage of input
positive half cycle for unity power-factor load), when S1a is capacitor of each H-bridge. (Udmi=(Ua1Na –Ua2Na) and Ucmi =
1 and S2a is 0 then the output voltage is Vdc/2 (sum of the (Ua1Na +Ua2Na ) / 2 )
input dc link voltage and voltage of capacitor Ca. Thus Ca
gets charged in the positive half cycle for unity power-factor The Boolean logic is implemented by the block shown in
load). There are 27 possible switching vector combinations Fig. 2(h). ma, mb, mc are the 3 modulating signals compared
as shown in Table-IV. The common mode voltage is given with high frequency carrier wave to produce X, Y, Z signals.
by (1). So only group -1 switching vectors of Table-IV can ª S1a = X + Y S2 a = XY S 3a = X + Y º
be used to produce constant common mode voltage. To « S4 a = X Y »
« S1b = Y + Z S2b = Y Z S 3b = Y + Z »
produce only those 7 switching vectors a Boolean logic is « S4 b = Y Z » (7)
presented in the [8]. The Boolean logic block diagram and « S1c = X + Z S2 c = X Z S 3c = X + Z »
« S4 c = X Z »
its Boolean function are shown below in Fig. 1(k) and (5) ¬ S5a = XY + X Y S5b = Y Z + Y Z S5 c = X Z + X Z ¼
respectively. The Table-V below shows the 7 switching The various switching states given by (7) are generated to
combinations that are possible using (5) that maintains suppress the common mode current and are depicted below
constant common mode voltage equal to half of the input in Table-VI.
 ICSETS 2019 067

TABLE-VI and switched OFF later than their parallel IGBT. By doing
SWITCHING STATES FOR CASCADE H-BRIDGE so, the CoolMosfet dominates most of the switching process
XYZ Ph-A Ph-B Ph-C Ucmi UCM UDM and reduces the switching losses and avoids the tail current
S1a-S5a S1b-S5b S1c-S5c
000 10100 10100 10100 Ud/2 3Ud/2 0 of IGBT. To further reduce the switching loss during the
100 10011 10100 01101 Ud/2 3Ud/2 0 instantaneous zero voltage durations of positive and
110 10100 10011 01101 Ud/2 3Ud/2 0 negative cycle of the inverter output, a split phase control is
010 01101 10011 10100 Ud/2 3Ud/2 0 proposed.
011 01101 10100 10011 Ud/2 3Ud/2 0
The first stage consists of two parallel dc-dc converters
001 10100 01101 10011 Ud/2 3Ud/2 0
101 10011 01101 10100 Ud/2 3Ud/2 0 and each boost converter includes two parallel switches as
111 10100 10100 10100 Ud/2 3Ud/2 0 shown in Fig. 2(a) to reduce the conduction loss. The power
loss distribution was calculated in [10] and it was found that
I. 3L-SNPC (Three Level Stacked Neutral Point Clamped) the efficiency reaches to almost about 98%. The
A novel 3 phase 3 level stacked NPC grid–tied solar inverter disadvantage is that the split phase control becomes
is shown in Fig. 2(a) [10]. As this topology is a NPC complex. The grid neutral is directly clamped to mid-point
configuration so the common mode current is less compared of input dc-link capacitor so if the clamping path happens to
to 2 level VSI, and to eliminate the ground current the mid- be inductive then there may be possibility of common mode
point of the input dc link capacitor is directly clamped to the current.
neutral of the grid. (as stated in [1] when there is no S1-L X
inductance in the connecting path of grid neutral and mid- Dnpc1 -L X
S1c-L X Dp1-L X
point of capacitance then the common mode voltage stays Dn2-L X
S2-L X
constant). Also in [13] a single phase half bridge is Li-L X Lg-L X
considered as shown in Fig. 2(c) where the neutral (mid-
point of the input split-capacitors) is grounded, then
S2c-L X
common mode voltage is held constant. Similarly in this S3-L X Dp2-L X
Cf-L X

case of Fig. 2(a), it can be thought of three single phases Dnpc2 -L X

Dn1-L X AC

together [1] and when the neutral is grounded then the

S3c-L X
common mode voltages stays constant. This configuration
mainly focusses on decreasing the switching and conduction
Fig. 3 Single phase of 3L-SNPC
losses taking place in switches of conventional 3L-SNPC
inverter, i.e., it mainly focuses on improving the efficiency
J. T-type three phase transformer-less inverter
of the inverter in the low power range (solar power range).
A modified T-type transformer-less 2 stage 3-phase 3-level
The operation of a single phase is shown in Fig. 3. It uses
inverter that suppresses common mode voltage is presented
IGBT plus CoolMosfet hybrid parallel devices as its exterior
in [9]. It has reduced switches in the inverter side then the
switches i.e., S1-LX and S3-LX. The clamping IGBTS of
conventional NPC topology hence reducing switching and
conventional 3L-SNPC topology are replaced by S1c-LX and
conduction losses. One of the three phases out of (R, S, T) is
S3-LX as shown in Fig. 3. During the positive half of the grounded in the delta system. This ground is extended to
phase voltage switches S2-LX, S3-LX are ON. S1-LX and S1c-LX mid-points of input dc link capacitor and intermediate
are operated as high frequency complementary switches capacitor as shown in Fig. 2(b). The first stage has 2 parallel
during this period. When S1-LX is ON the load current gets operating boost converter that operates in 4 modes to
divided into the parallel paths of IGBT and CoolMosfet maintain constant average voltage across the capacitors Cdc1
there-by reducing conduction loss. (CoolMosfet has lower and Cdc2. The 4 modes are activated by switching S1 and S2
voltage drop). When S1c-LX is ON the freewheeling current ON or S1 and S2 OFF or S1 ON and S2 OFF or S1 OFF and S2
gets divided into S3-LX and S2-LX thereby reducing the ON.
conduction-loss. The same analysis can be extended to the Consider the line-line voltage VRS, when VRS is positive
negative half. switch S4R is always ON. Switches S1R and S2R operates at
The switching stress across the outer switches i.e., S1-LX high frequency to produce VRS equal to VPV/2 and 0,
and S3c-LX are high. Thus, to reduce the switching losses the respectively. In the negative half of the VRS switch S2R is
parallel CoolMosfet of S1-LX and S3c-LX are made ON earlier always ON. Switches S3R and S4R
TABLE-VII
COMARISION TABLE
Converter Voltage Level Modulation Switches Power Rating VCM ICM Standard<300mA
3FB 2 SPWM 6 5kW ±VPV 3.2A
3FB-SC 2 SPWM 6 5kW ±1%VPV 0.23mA
3 phase NPC 3 SPWM 18 5kW ±1%VPV 0.7mA
3 FB 2 RSPWM 6 10kW 0 - 0.667VPV 0
DCM-232 2 SVPWM 10 6kW 0.33VPV & 0.66VPV 30mA
4 LEG FB 2 Boolean logic 8 1kW VPV 23.1mA
4 LEG (3D) 2 RSPWM 8 1kW 0.5VPV 118mA
NPC 3 SVPWM 18 5kW 0 0
Cascade H5 bridge 3 Boolean Logic 15 2.1kW 1.5VPV 100mA
Flying Capacitor 3 Boolean Logic 12 2kW 0.5VPV 120mA
T-Type 3 SPWM 10 10kW 0.5VPV 46mA
H8-Converter 2 SVPWM 8 2kW 0.33VPV – 0.66VPV 200mA
 ICSETS 2019
operate at high frequency to produce VRS equal to –VPV/2
and 0, respectively. Switches S1T and S3T are switched in the
similar pattern by considering line-line voltage VTS into
account. The common mode model of this topology is
presented in Fig. 2(e).
The expression for the common mode voltage or the voltage
across the capacitor Cp (see Fig. 2(d)) is given by (8).
1
VP . prop = vstep − up (8)
0.5ws Lin Ctotal − 1
2
Where, ws = 2*pi*fs , fs is the high switching frequency, Lin =
L1=L2, Ctotal = C1+C2+Cp and Vstep-up = (v1n+v2n)/2. From (8)
it can be seen that even at high frequencies the common
mode voltage stays very low. To physically understand the
common mode suppression, consider the high frequency
common mode model shown in Fig. 2(d) The common
mode model has C1 and C2 in parallel with the parasitic
capacitance Cp. Since the voltage across the input
capacitances are almost constant so the common mode
voltage is almost constant and equal to half of VPV. As
stated in [9] the leakage current was limited within 100 mA.
III. CONCLUSION
This paper presents a review of few three phase transformer-
less solar inverters both two level and multilevel. It focuses
mainly on their common mode behavior when operated
under SVPWM techniques. The switching pattern for each
of them which produces constant common mode voltage is
identified and the Boolean logic to generate the switching
pulses are presented. The detailed comparison and working
of each converter, the advantages and disadvantages is
presented.
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