Assignment-2

Q.1. Assuming λn = λp, the gain of a MOS transistor at the transition level is

(a) Infinity
(b) 1
(c) 0
(d) -1
Answer-(a)

Q.2. If the threshold voltage of the pull-down device is higher as compared to the pull up device,
the switching threshold (VM) is:

(a) Decreases
(b) No effect
(c) Increases
(d) Depends on the biasing criteria
Answer-(c)

Q. 3. If β = [(W/L)P/(W/L)N] is increased, which of the followings statement is true:

(a) tpHL>tPLH
(b) tpLH>tPHL
(c) TpHL = tPLH
(d) No Relation
Answer-(a)

Q. 4. For a 4 block inverter chain if the output load capacitance = 3 times the minimum input
capacitance of the input inverter, then the electric effort is

(a) 4/3
(b) 2
(c) 5/3
(d) 3
Answer-(d)

Q. 5. For a static CMOS circuit, there are 2, zero to one transitions for every 4 clock cycles. The
value of the activity factor is

(a) 0.5
(b) 2
(c) 0.75
(d) None of above
Answer-(a)
Q. 6. Energy is define in terms of Power (P) and Delay (D) as

(a) P×D
(b) P/D
(c) PD
(d) None of the above
Answer-(a)

Q.7 For an ideal CMOS inverter operating at a supply of VDD the short circuit power dissipation
is maximum at

(a) VDD
(b) VDD/2
(c) VDD/4
(d) 2 VDD
Answer-(b)

Q. 8. For an ideal CMOS inverter, if the power supply VDD is reduced to VDD/2, then everything
else remaining the same, the dynamic power dissipation of the inverter will,

(a) Increase by two

(b) Decrease by two
(c) Decrease by four
(d) Decrease by 8
Answer-(c)

Q. 9. In SPICE non-linear analysis, Q point is termed as

(a) DC Analysis
(b) AC Analysis
(c) Transfer Analysis
(d) None of the above
Answer-(a)

Q.10. In statement '.TRAN 1ns 100ns UIC .OP 20ns', UIC is

(a) String
(b) Parameter
(c) Variable
(d) ASCI Value
Answer-(b)