Neutral Point Voltage Level Stabilization and DC

Link Capacitors Voltage Balance in Neutral Point
Clamped Multilevel Inverters
Gandla Radha Krishna K. Anuradha
M. Tech Scholar, EEE Professor, EEE
VNR VJIET VNR VJIET
Hyderabad, India Hyderabad, India
radhakrishnagandla@gmail.com eeehead@vnrvjiet.in

Abstract—The Neutral point clamped (NPC) inverter has iii. The balance of neutral point and individual capacitors
unbalancing problems of neutral point voltage and DC link voltage is assured.
capacitors voltages, generally dc link capacitor voltage unbalance The main problem with NPC inverter is neutral point
leads to neutral point voltage unbalance. In this paper neutral voltage (NPV) level balancing, this is due to DC-link
point voltage is balanced using sine PWM associated with phase capacitor voltage unbalance. In this paper SPWM scheme is
shift technique. But for NPC inverters with more than three level developed for NPC inverter, which provides neutral point
even though neutral point voltage is balanced dc link capacitor voltage control.
voltages are unbalanced and neutral point voltage varies with a In an NPC inverter with more than three level, neutral
wide range, Hence a control strategy is proposed in this paper for
point voltage is controlled by balancing upper and lower group
controlling both problems and is applied for NPC three level, five
level, seven level and nine level inverter. Simulation results are
capacitor voltages with respect to neutral point by using
presented to show effectiveness of proposed equalizing control SPWM scheme. But the individual capacitor voltage is not
circuits. Total harmonic distortion (THD) values are observed for balanced effectively. This is due to non-uniform power drawn
the developed control technique. from the capacitors resulting in fall of some and raise of other
capacitor voltages. A novel control circuit is proposed in this
Keywords— Capacitor Voltage Equalization, Diode-Clamped paper for controlling and balancing individual capacitor
Multilevel Inverter (DCMLI)/Neutral Point Clamped (NPC) Inverter, voltages and also balancing neutral point voltage with less
Equalizing Circuit, Bias Value (B), Sinusoidal Pulse Width Modulation THD.
(SPWM), Total Harmonic Distortion (THD).
II. NEUTRAL POINT CLAMPED INVERTER
I. INTRODUCTION NPC inverter can convert a single DC source to any
Numerous industrial applications need high power number of level AC output. With increase in level the AC
equipment in recent years. Multilevel inverter attracted output is nearly sinusoidal and also THD decreases.
researchers due to its advantages of offering better switch
utilization, high voltage and power ratings [1]-[4]. Diode S1 S5 S9
clamped multilevel inverter (DCMLI) is an attractive high
C1
voltage multilevel inverter due to its robustness. DCMLI is
also called Neutral Point Clamped (NPC) inverter. NPC V1
voltage source inverter (VSI) has many advantages over S2 S6 S10
D1 D2 D3
conventional two level VSI for high power applications.
O
i. The power rating increases and switches share less Vdc
load. Maximum voltage share by a switch in three
level is half of DC source voltage and one-fourth in
D1' D2' D3'
five level i.e. 1 th in m level NPC inverter[3]. S3 S7 S11
m−1
ii. Total Harmonic Distortion (THD) is very less V2
compared to conventional two level VSI. THD C2
S4 S8 S12
decreases with increase in level of NPC inverter.
On the other hand this topology has its disadvantages.
i. NPC inverter requires higher number of devices.
ii. The complexity of circuit is high and increases with Phase A Phase B Phase C
increase in level of the inverter. Fig. 1. Three level NPC inverter



 
    


       


In an m level inverter (m-1) number of DC link capacitors

and carrier wave forms. 2(m-1) switching devices and (m-
v AB
= vAO − vBO ; vBC = vBO − vCO ; vCA = vCO − vAO
…..(1)
1)*(m-2) diodes are required in each arm of the inverter. The
schematic diagram of NPC three-level inverter is shown in the
Fig. 1. III. NEUTRAL POINT VOLTAGE BALANCE USING SPWM
Each arm in three level inverter create three voltage SPWM modulation scheme is most widely used method to
generate gating signals. It is very simple and easy to
levels +vdc , 0, − vdc . The diodes used are called clamping
2 2 implement by using digital technique. In SPWM switching
diodes connected to midpoint of capacitors. Each capacitor pulses are generated by comparing a sinusoidal reference
will block a voltage of vdc where m is the level of the wave with vertically shifted triangular carrier waveforms. For
m −1 m level inverter (m-1) triangular carrier waveforms are
inverter. required to generate (m-1) level output voltage. All the carrier
Table I shows the switching states of three level inverter triangular waves have same frequency and amplitude. The
for phase A, For an output voltage +vdc upper two switches carrier wave frequency is very high compared to reference
2 wave frequency.
are ON i.e. S1 and S2 the lower switches are complimentary 5
pulse generation

of upper switches. When middle switches S2 and S3 are ON

the output voltage is zero as there is no capacitor connected to
these switches to share voltage. For an output voltage − vdc lower

A m p litu d e
2 0
switches S3 and S4 are ON.
TABLE I. Switching States of Three-Level Inverter for Phase A
S.NO. Arm switches Output Voltage
S1 S2 S3 S4 -5
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
1. 1 1 0 0 +v dc
Fig. 2(a).
Time (seconds)
SPWM scheme for NPC Three level inverter
2
2. 0 1 1 0 0
1
3. 0 0 1 1 −v dc
0.8
2
A m p lit u d e

0.6
In the same way switching states for five level inverter are
operated. 0.4

The possible pole voltages for each arm of three-level 0.2

inverter are: 0
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02

= ±v = ±v = ±v
Time (seconds)

v AO
dc
,0 ; v BO
dc
,0 ; v CO
dc
,0 Fig.2 (b). Pulses generated in the SPWM scheme
2 2 2
When reference wave is greater than carrier wave the
For five level NPC inverter: corresponding switch is ON. Here, when reference wave is
±v , ±v ±v , ±v ±v , ±v greater than upper carrier wave, S1 switch is ON and S3 is
v AO
= dc dc
,0 ; vBO = dc dc
,0 ; vCO = dc dc
,0 OFF. In contrast if reference wave is greater than lower carrier
4 2 4 2 4 2
wave, S2 is ON and S4 is OFF. In this scheme three reference
For seven level NPC inverter: sinusoidal waves each shifted with 120° are used to compare
level shifted carrier waves to generate gating signals. Fig. 2(a)
±v , ±v , ±v ,0 ; vBO = ±v , ±v , ±v ,0 ;
v AO
=
6
dc

4
dc

2
dc

6
dc

4
dc

2
dc
and Fig. 2(b) shows the control logic for SPWM scheme and
pulses generated respectively for an NPC three level inverter.
±v , ±v , ±v
v BO
=
6
dc

4
dc

2
dc
,0
Modulation index (MI) = Ar [4] (2)
Ac
For nine level NPC inverter:
Where,
±v , ±v , ±v , ±v ,0 ; A r - Reference signal amplitude, A c - carrier signal
v AO
=
8
dc

6
dc

4
dc

2
dc

amplitude.
±v , ±v , ±v , ±v ,0 ; The three phase reference voltages are expresses as:
vBO = 8
dc

6
dc

4
dc

2
dc

= ±v , ±v , ±v , ±v
V A = V m sin (Ȧt ) (3)
v dc dc dc dc
,0

( )
CO
8 6 4 2
From these pole voltages line to line voltages are obtained as V B = V m sin Ȧt − 120 0 (4)
in equation (1):

 

 
    


       


(
V C = V m sin Ȧt − 240 0 ) (5)
V m is the peak amplitude of reference wave and Ȧ is the
fundamental angular frequency (radian/sec).
The voltage difference of upper half and lower half
arm should be zero i.e. neutral point voltage should always
remains zero for stabilization. In Fig. 1, V1 and V2 are upper
half and lower half voltages with respect to neutral point.
Control technique proposed in [4] is improvised in this paper.
When neutral point voltage is positive means the upper half
voltage is greater than lower half voltage in a DC link. For
balancing the voltages, on time period of switches in lower
m level inverter each capacitor needs to block V dc voltage in
m −1
general. The NPC inverter with more than three level the
individual capacitor voltage is unbalanced as the time
progress, In an arm complete upper half voltage v dc is
2
blocked by top capacitor which is connected to positive
terminal of DC source voltage and complete lower half
voltage is blocked by lower capacitor connected to negative
terminal of DC voltage source. Schematic diagram of five
level NPC inverter is shown in fig 4(a).
S1

arm should be less than the on time period of upper switches C1 D1 S2

in an arm. Hence, whenever neutral point voltage becomes V1
unbalance it needs to shift reference wave in the same D2
S3
C2
direction. If neutral point voltage is positive then reference S4
wave is shifted in positive direction. If neutral point voltage is D3

negative then reference wave is shifted in negative direction. Vdc O

D1' S5
This is done by adding bias value to the reference wave. Table C3

III gives selection of bias value with respect to neutral point D2' S6
voltage, here when neutral point voltage is zero then no bias V2
C4 D3' S7
value is added.
TABLE II. Selection of the bias value S8

V1-V2 Bias Value

Phase A
Positive Positive
Fig. 4(a). Five level NPC inverter
Negative Negative
0 0
PWM SIGNALS C1
SC1
L1

SC3
INVERTER LOAD
DC1 C2
L3

V1-V2
Vdc
N

DC2 C3
L2
0,0.2,-0.2

LOGICAL
0,+ve,-ve + COMPARATOR
OPERATOR DC3

SC2 C4
Reference wave Carrier wave
Bias added based on
product output

Fig. 3. Control circuit for neutral point voltage balance
Fig.3 shows control circuit for neutral point voltage
balance. Upper and lower half capacitor voltage difference is
given to logical operator. The output of relational operator can
be positive, negative and zero. If this output is positive then
positive bias is added to reference wave. Here bias value
selected is 0.2 for balancing voltage variation If the output is
negative then negative bias is added (-0.2), else no change is
made to reference wave.
IV. DC LINK CAPACITOR BALANCE FOR NPC
INVERTER WITH MORE THAN THREE LEVEL
For higher level (more than three level) NPC inverter
SPWM scheme is effective for controlling neutral point
voltage. i.e. upper and lower half arm voltage balance can be
done but the individual capacitor balance is not possible. For
Fig. 4(b). Capacitor voltage balance control circuit diagram
As shown in Fig. 4(a), the four capacitors should block a
voltage of v dc each, but the capacitor C1 blocks + v dc and
4 2
lower most capacitor C4 blocks − v dc .The middle capacitors
2
C2 and C3 blocks almost zero voltage. This results in bad
quality voltage outputs. The switches are over rated hence
damage of equipment occurs which results in collapse of NPC
inverter.
This problem can be solved by balancing each capacitor
with its respective voltage. A control circuit is proposed in this
paper to balance individual capacitor voltage. Fig 4(b) shows
control circuit diagram for DC link capacitor balance.
Consider the upper half of an arm, whenever the upper



 
    


       


capacitor C1 blocks more than v dc voltage then the controller
4 be overloaded due to uneven voltage levels. This results in
switches on the switch SC1 to transfer the extra energy to L1.
When the capacitor C1 is balanced inductor L1 discharges its
energy to C2 through a diode DC1 and balances both the
capacitors to v dc . Same control circuit operation is applied to
4
lower half of the arm. Here whenever lower capacitor C4
blocks less than - v dc voltage, control circuit comes into
4
action and charges inductor L2. Now the whole upper half of
the arm and lower half of the arm of five-level NPC inverter
can be controlled through the application of same control
circuit. Therefore neutral point voltage is balanced. Here,
whenever upper arm capacitors voltage is greater than v dc
2 The DC source voltage of 400 V and DC link capacitors of
Voltage, the extra energy deviates through the switch SC3 and
charges inductor L3. After balancing upper arm voltage the
stored energy in L3 discharges to lower arm capacitors.
For NPC inverter with more than three level switches may
NPC inverter damage. Individual capacitor voltage control
circuit helps to maintain constant levels. Fig. 5 and Fig. 6
shows control circuit and flow chart for individual capacitor
control circuit for five level NPC inverter. This DC link
capacitor balance control works good For wind energy
systems, this individual capacitor balance circuit acts as a DC
filter and maintain constant input voltage to the inverter from
rectifier output.
V. SIMULATON RESULTS
The developed control strategy for neutral point voltage
balance and DC link capacitors voltage balance of NPC
inverter is implemented using MATLAB Simulink toolbox.
4940μF is used.
NPV without Neutral point voltage balance controller

voltage amplitude (volts)

50
In this way both upper and lower half capacitor voltages
are balanced and the difference between them is always zero 0

i.e. neutral point voltage is balanced. -50

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Time (seconds)
Three level pole voltage without Neutral point voltage balance controller
voltage amplitude (volts)
200

100

-100

-200
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35
Time (seconds)

Fig. 7. Neutral point voltage and pole voltages of three level NPC
inverter with SPWM scheme
NPV with Neutral point voltage balance controller
voltage am plitude

50
(volts)

-50
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (seconds)
pole voltages with Neutral point voltage balance controller
voltage am plitude

Fig. 5. Individual capacitor voltage balance control circuit diagram

200
(volts)

Start 0

-200
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35
Time (seconds)
Capacitor Voltage=x Line to line voltages with Neutral point voltage balance controller
voltage am plitude

400
200
(volts)

0
-200
X X > Vdc/4 -400
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35
Time (seconds)

Switch is ON and
Fig. 8. Neutral point voltage, pole and line-line voltages of three
X ” Vdc/4 level NPC inverter with SPWM scheme based on neutral
charges inductor
point voltage balance controller

Switch is OFF
Fig 7 and Fig 8 shows the unbalanced and balanced
and no control neutral point voltages, pole voltage and line voltage wave
circuit operation
forms. Fig 7 shows that neutral point voltage without control
scheme varies over a wide range i.e., +50 V to -50 V. Fig 8
End
shows that neutral point voltage variation in the range of
Fig. 6. flow chart for the individual capacitor voltage balance
+0.5V to -0.5V which shows improvement with pole and line-
control circuit diagram line voltage waveforms it is observed that developed strategy



 
    


       


for neutral point voltage balancing for NPC inverter is Pole voltages without balanced system

voltage amplitude (volts)

200
functioning effectively. 100
TABLE III. Neutral point voltages in three level SPWM based 0
DCMLI without and with NPV balance controller -100

S.NO LOAD NPV with NPV with sine PWM -200

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (seconds)
sine PWM scheme based
Seven level DC link capacitor voltages without balancing system

scheme neutral point voltage

voltage amplitude (volts)

200 C1
C2
150
balance controller C3
C4
100
C5
1. R = 10Ÿ, L = 2e-3H 12.22 -0.84 50 C6

2. R = 5Ÿ, L = 10*10e-12H 25.12 0.0122 0

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (seconds)

3. R = 8Ÿ, L = 10*10e-9H 17.23 -0.029 Fig. 11. Seven level NPC inverter pole voltages and DC link
4. R = 10Ÿ, L = 0.003H 28.02 -0.08 capacitor voltages without DC link capacitor voltage balance
controller.
It is seen from Table III the NPV with NPV balance controller Pole voltage with balancing system

is stabilized for different loads. It is observed that the neutral

voltage amplitude (volts)

200

point voltage variation is reduced by 90% with the proposed 100

technique. -100

-200
Pole voltages without DC link capacitor voltage balancing system
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35
voltage am p litud e (vo lts)

Time (seconds)
200 DC link capacitor voltages with balancing system

Voltage Amplitude (volts)

100
100 C1
C2
C3
0 50 C4
C5
-100 C6

-200 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (seconds)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (seconds)
Fig. 12. Seven level NPC inverter balanced pole voltages and DC link
Five level DC link capacitor voltages without balanced system
200 capacitor voltages with DC link capacitor voltage balance
vo ltag e am p litud e (vo lts)

C4
controller.
150 C2
Nine level Pole voltages without balancing system
C1
voltage amplitude (volts)

100 C3 200

100

50 0

-100
0 -200
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (seconds) Time (seconds)
DC link capacitor voltages without balancng system
300
Voltage Amplitude (volts)

Fig. 9. Five level NPC inverter unbalanced pole voltages and DC C1

200 C2
link capacitors voltages without DC link capacitor voltage C3
C4
balance controller 100
C5
0 C6
Pole voltages with balanced system C7
-100 C8
v o lta g e a m p litu d e (v o lts)

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

200 Time (seconds)

100
Fig. 13. Nine level NPC inverter pole voltages and DC link capacitor
0 voltages without DC link capacitor voltage balance
-100 controller.
Nine level Pole voltages with balancing system
-200
voltage amplitude (volts)

200
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 100
Time (seconds)
0
DC link capacitor voltages with balanced system
200 -100
v o lta g e a m p litu d e (v o lts)

C4 -200
150 C2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35
Time (seconds)
C1
DC link capacitor voltages with balancing system
100 C3 100
Voltage Amplitude (volts)

C1
C2
50 C3
50 C4
0 C5
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 C6
C7
Time (seconds)
0 C8
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time (seconds)
Fig. 10. Five level NPC inverter balanced pole voltages and DC link
Fig. 14. Nine level NPC inverter balanced pole voltages and DC link
capacitor voltages with DC link capacitor voltage balance
capacitors voltage without DC link capacitor voltage balance
controller.
controller.




 
    


       


TABLE IV. THD comparision of three level NPCI In capacitor voltage balance control circuit low value
of inductor is chosen for complete transfer of stored energy.
S.NO. Load %THD
With SPWM With SPWM
This results high currents in control circuit. If a high value of
scheme scheme based inductor is used to reduce current, the controller performance
NPV balance will degrade. A possible solution to this limitation is the use of
controller controller with a current limiter. Another limitation is the
1. R=10Ÿ 27.23 11.12 switches or diodes used in capacitor voltage balance control
2. R=10Ÿ, L=100e-3H 28.66 12.29 circuit should be of higher rating than the switches or devices
3. R=10Ÿ, L=100e-3H, 28.7 13.41
in the inverter.
C=2200e-6F

VI. CONCLUSIONS
TABLE V. THD comparision of five level, seven level and nine
level SPWM base NPC inverter with and without DC link capacitor From the discussions and simulations presented, the
voltage balance controller neutral point voltage balancing scheme for three level NPC
S.NO. Load %THD inverter is analyzed and simulation results are displayed with
better THD. In this paper stabilization of neutral point voltage
NPC Inverter without NPC Inverter with and balancing of individual capacitor voltages is achieved for
DC link capacitor DC link capacitor three level, five level, seven level and nine level NPC Inverter.
voltage balance voltage balance
There is a significant reduction in harmonic loss minimization
and effective capacitor voltage balancing is also achieved.
controller controller

ACKNOWLEDGMENT
Five Seven Nine Five Seven Nine
level level level level level level The authors thank the management of BHEL corporate R&D
to carry out the work and report the research results

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